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clean up for porting - move platform specific stuff into outer project

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This commit is contained in:
MightyPork
2018-07-07 23:02:58 +02:00
parent b8909fca06
commit 20639b77a6
35 changed files with 499 additions and 485 deletions
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FreeRTOSConfig.h
+6 -28
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@@ -90,6 +90,7 @@
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include <stdint.h>
#include "main.h"
#include "plat_config.h"
#include "plat_compat.h"
extern uint32_t SystemCoreClock;
#endif
@@ -134,34 +135,11 @@ to exclude the API function. */
///* Cortex-M specific definitions. */
#if defined(GEX_PLAT_F103_BLUEPILL) || defined(GEX_PLAT_F303_DISCOVERY) \
|| defined(GEX_PLAT_F407_DISCOVERY)
// This is for F103+
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
#define configPRIO_BITS 4
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#elif defined(STM32F072xB)
// This is for F072
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 3
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1
#define configPRIO_BITS 2
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#else
#error "BAD PLATFORM!!"
#endif
// These are defined in plat_compat.h:
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY PLAT_FREERTOS_LOWEST_INTERRUPT_PRIORITY
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY PLAT_FREERTOS_MAX_SYSCALL_INTERRUPT_PRIORITY
#define configPRIO_BITS PLAT_FREERTOS_PRIO_BITS
#define configUSE_PORT_OPTIMISED_TASK_SELECTION PLAT_FREERTOS_USE_PORT_OPTIMISED_TASK_SELECTION
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
USB/usbd_conf.c
+7 -6
View File
@@ -84,13 +84,14 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
__HAL_RCC_USB_CLK_ENABLE();
/* Peripheral interrupt init */
#if GEX_PLAT_F103_BLUEPILL
// TODO convert this to feature flags if possible - avoid tying to particular platforms
#if GEX_PLAT_F103
HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
#elif STM32F072xB
#elif GEX_PLAT_F072
HAL_NVIC_SetPriority(USB_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(USB_IRQn);
#elif GEX_PLAT_F303_DISCOVERY
#elif GEX_PLAT_F303
// Pins need to be configured here
/**USB GPIO Configuration
@@ -149,11 +150,11 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
__HAL_RCC_USB_CLK_DISABLE();
/* Peripheral interrupt Deinit*/
#if GEX_PLAT_F103_BLUEPILL
#if GEX_PLAT_F103
HAL_NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
#elif STM32F072xB
#elif GEX_PLAT_F072
HAL_NVIC_DisableIRQ(USB_IRQn);
#elif GEX_PLAT_F303_DISCOVERY
#elif GEX_PLAT_F303
HAL_NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn);
#else
#error "BAD PLATFORM"
comm/event_reports.h
+3 -3
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@@ -2,8 +2,8 @@
// Created by MightyPork on 2018/01/27.
//
#ifndef GEX_F072_EVENT_REPORTS_H
#define GEX_F072_EVENT_REPORTS_H
#ifndef GEX_CORE_EVENT_REPORTS_H
#define GEX_CORE_EVENT_REPORTS_H
#ifndef GEX_MESSAGES_H
#error "Include messages.h instead!"
@@ -31,4 +31,4 @@ void EventReport_Data(const uint8_t *buff, uint16_t len);
void EventReport_PB(PayloadBuilder *pb);
void EventReport_End(void);
#endif //GEX_F072_EVENT_REPORTS_H
#endif //GEX_CORE_EVENT_REPORTS_H
comm/iface_nordic.c
+3 -1
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@@ -2,6 +2,9 @@
// Created by MightyPork on 2018/04/06.
//
#include "platform.h"
#if SUPPORT_NRF
#include "iface_nordic.h"
#include "nrf_pins.h"
#include "resources.h"
@@ -11,7 +14,6 @@
#include "system_settings.h"
#include "utils/hexdump.h"
#if SUPPORT_NRF
extern osSemaphoreId semVcomTxReadyHandle;
comm/iface_nordic.h
+3 -4
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@@ -2,11 +2,10 @@
// Created by MightyPork on 2018/04/06.
//
#ifndef GEX_F072_IFACE_NORDIC_H
#define GEX_F072_IFACE_NORDIC_H
#ifndef GEX_CORE_IFACE_NORDIC_H
#define GEX_CORE_IFACE_NORDIC_H
#include "platform.h"
#if SUPPORT_NRF
void iface_nordic_claim_resources(void);
@@ -21,4 +20,4 @@ void iface_nordic_transmit(const uint8_t *buff, uint32_t len);
#endif // SUPPORT_NRF
#endif //GEX_F072_IFACE_NORDIC_H
#endif //GEX_CORE_IFACE_NORDIC_H
comm/iface_uart.h
+3 -3
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@@ -2,8 +2,8 @@
// Created by MightyPork on 2018/04/06.
//
#ifndef GEX_F072_IFACE_UART_H
#define GEX_F072_IFACE_UART_H
#ifndef GEX_CORE_IFACE_UART_H
#define GEX_CORE_IFACE_UART_H
#include "platform.h"
@@ -17,4 +17,4 @@ void iface_uart_claim_resources(void);
void iface_uart_transmit(const uint8_t *buff, uint32_t len);
#endif //GEX_F072_IFACE_UART_H
#endif //GEX_CORE_IFACE_UART_H
comm/iface_usb.h
+3 -3
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@@ -2,8 +2,8 @@
// Created by MightyPork on 2018/04/06.
//
#ifndef GEX_F072_IFACE_USB_H
#define GEX_F072_IFACE_USB_H
#ifndef GEX_CORE_IFACE_USB_H
#define GEX_CORE_IFACE_USB_H
#include "platform.h"
@@ -17,4 +17,4 @@ bool iface_usb_ready(void);
*/
void iface_usb_transmit(const uint8_t *buff, uint32_t len);
#endif //GEX_F072_IFACE_USB_H
#endif //GEX_CORE_IFACE_USB_H
comm/interfaces.h
+3 -3
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@@ -2,8 +2,8 @@
// Created by MightyPork on 2018/03/23.
//
#ifndef GEX_F072_COM_INTERFACES_H
#define GEX_F072_COM_INTERFACES_H
#ifndef GEX_CORE_COM_INTERFACES_H
#define GEX_CORE_COM_INTERFACES_H
#include "platform.h"
@@ -34,4 +34,4 @@ void com_release_resources_for_alt_transfers(void);
/** Flush the rx buffer */
void com_iface_flush_buffer(void);
#endif //GEX_F072_COM_INTERFACES_H
#endif //GEX_CORE_COM_INTERFACES_H
comm/msg_bulkread.h
+3 -3
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@@ -4,8 +4,8 @@
// Bulk read (providing data for bulk read by the PC)
//
#ifndef GEX_F072_MSG_BULKREAD_H
#define GEX_F072_MSG_BULKREAD_H
#ifndef GEX_CORE_MSG_BULKREAD_H
#define GEX_CORE_MSG_BULKREAD_H
#ifndef GEX_MESSAGES_H
#error "Include messages.h instead!"
@@ -45,4 +45,4 @@ struct bulk_read {
void bulkread_start(TinyFrame *tf, BulkRead *bulk);
#endif //GEX_F072_MSG_BULKREAD_H
#endif //GEX_CORE_MSG_BULKREAD_H
comm/msg_bulkwrite.h
+3 -3
View File
@@ -4,8 +4,8 @@
// Bulk write (receiving bulk write from the PC)
//
#ifndef GEX_F072_MSG_BULKWRITE_H
#define GEX_F072_MSG_BULKWRITE_H
#ifndef GEX_CORE_MSG_BULKWRITE_H
#define GEX_CORE_MSG_BULKWRITE_H
#ifndef GEX_MESSAGES_H
#error "Include messages.h instead!"
@@ -44,4 +44,4 @@ struct bulk_write {
void bulkwrite_start(TinyFrame *tf, BulkWrite *bulk);
#endif //GEX_F072_MSG_BULKWRITE_H
#endif //GEX_CORE_MSG_BULKWRITE_H
comm/msg_responses.h
+3 -3
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@@ -4,8 +4,8 @@
// Routines for sending TinyFrame responses.
//
#ifndef GEX_F072_MSG_RESPONSES_H
#define GEX_F072_MSG_RESPONSES_H
#ifndef GEX_CORE_MSG_RESPONSES_H
#define GEX_CORE_MSG_RESPONSES_H
#ifndef GEX_MESSAGES_H
#error "Include messages.h instead!"
@@ -109,4 +109,4 @@ void com_respond_u16(TF_ID frame_id, uint16_t d);
*/
void com_respond_u32(TF_ID frame_id, uint32_t d);
#endif //GEX_F072_MSG_RESPONSES_H
#endif //GEX_CORE_MSG_RESPONSES_H
comm/nrf.c
+4
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@@ -3,6 +3,8 @@
//
#include "platform.h"
#if SUPPORT_NRF
#include "nrf.h"
/**
@@ -545,3 +547,5 @@ bool NRF_Init(uint8_t pSpeed)
return true;
}
#endif
comm/nrf.h
+3 -5
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@@ -15,11 +15,9 @@
*
*/
#ifndef NORDIC_H_
#define NORDIC_H_
#include "platform.h"
#if SUPPORT_NRF
#include "resources.h"
#include "nrf_pins.h"
@@ -160,6 +158,6 @@ void NRF_EnablePipe(uint8_t pipenum);
*/
void NRF_DisablePipe(uint8_t pipenum);
#endif /* NORDIC_H_ */
#endif // SUPPORT_NRF
#endif //GEX_NRF_NRF_H
comm/nrf_pins.h
-75
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@@ -1,75 +0,0 @@
//
// Created by MightyPork on 2018/04/06.
//
#ifndef GEX_F072_NRF_PINS_H
#define GEX_F072_NRF_PINS_H
#include "platform.h"
#if defined(GEX_PLAT_F072_DISCOVERY) || defined(GEX_PLAT_F072_HUB)
// This config was used only for development when NRF was enabled for those platforms. It is normally disabled.
#define NRF_SPI SPI1
#define NRF_R_SPI R_SPI1
#define NRF_IRQ_Pin LL_GPIO_PIN_10
#define NRF_IRQ_GPIO_Port GPIOB
#define NRF_R_IRQ R_PB10
#define NRF_EXTI_LINENUM 10
#define NRF_SYSCFG_EXTI_PORT LL_SYSCFG_EXTI_PORTB
#define NRF_NSS_Pin LL_GPIO_PIN_11
#define NRF_NSS_GPIO_Port GPIOB
#define NRF_R_NSS R_PB11
#define NRF_CE_Pin LL_GPIO_PIN_12
#define NRF_CE_GPIO_Port GPIOB
#define NRF_R_CE R_PB12
#define NRF_RST_Pin LL_GPIO_PIN_13
#define NRF_RST_GPIO_Port GPIOB
#define NRF_R_RST R_PB13
#define NRF_R_SCK R_PA5
#define NRF_SCK_AF LL_GPIO_AF_0
#define NRF_R_MISO R_PA6
#define NRF_MISO_AF LL_GPIO_AF_0
#define NRF_R_MOSI R_PA7
#define NRF_MOSI_AF LL_GPIO_AF_0
#elif defined(GEX_PLAT_F072_ZERO)
#define NRF_SPI SPI2
#define NRF_R_SPI R_SPI2
#define NRF_IRQ_Pin LL_GPIO_PIN_15
#define NRF_IRQ_GPIO_Port GPIOC
#define NRF_R_IRQ R_PC15
#define NRF_EXTI_LINENUM 15
#define NRF_SYSCFG_EXTI_PORT LL_SYSCFG_EXTI_PORTC
#define NRF_NSS_Pin LL_GPIO_PIN_13
#define NRF_NSS_GPIO_Port GPIOC
#define NRF_R_NSS R_PC13
#define NRF_CE_Pin LL_GPIO_PIN_14
#define NRF_CE_GPIO_Port GPIOC
#define NRF_R_CE R_PC14
#define NRF_RST_Pin LL_GPIO_PIN_12
#define NRF_RST_GPIO_Port GPIOC
#define NRF_R_RST R_PC12
#define NRF_R_SCK R_PB13
#define NRF_SCK_AF LL_GPIO_AF_0
#define NRF_R_MISO R_PC2
#define NRF_MISO_AF LL_GPIO_AF_1
#define NRF_R_MOSI R_PC3
#define NRF_MOSI_AF LL_GPIO_AF_1
#else
#error "Missing NRF config for this platform."
#endif
#endif //GEX_F072_NRF_PINS_H
framework/rsc_enum.h
+3 -3
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@@ -4,8 +4,8 @@
// Enum of all defined resources
//
#ifndef GEX_F072_RSC_ENUM_H
#define GEX_F072_RSC_ENUM_H
#ifndef GEX_CORE_RSC_ENUM_H
#define GEX_CORE_RSC_ENUM_H
// X macro: Resource name,
#define XX_RESOURCES \
@@ -132,4 +132,4 @@ static inline void rscmap_free(ResourceMap *rscmap, Resource rsc)
#define RSC_CLAIM(rscmap, rsc) rscmap_claim(&rscmap, (rsc))
#define RSC_FREE(rscmap, rsc) rscmap_free(&rscmap, (rsc))
#endif //GEX_F072_RSC_ENUM_H
#endif //GEX_CORE_RSC_ENUM_H
framework/settings.c
+2 -1
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@@ -110,7 +110,7 @@ void settings_save(void)
erase.Banks = FLASH_BANK_1; // TODO ?????
#endif
#if defined(GEX_PLAT_F407_DISCOVERY)
#if GEX_PLAT_F407
// specialty for F4 with too much flash
erase.NbSectors = 1;
erase.Sector = SETTINGS_FLASH_SECTOR;
@@ -122,6 +122,7 @@ void settings_save(void)
erase.PageAddress = SETTINGS_FLASH_ADDR;
erase.TypeErase = FLASH_TYPEERASE_PAGES;
#endif
uint32_t pgerror = 0;
hst = HAL_FLASHEx_Erase(&erase, &pgerror);
assert_param(pgerror == 0xFFFFFFFFU);
gex.mk
+2 -1
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@@ -83,7 +83,8 @@ GEX_C_FILES = \
GexCore/USB/STM32_USB_Device_Library/Class/MSC_CDC/usbd_msc_cdc.c \
GexCore/USB/STM32_USB_Device_Library/Core/Src/usbd_core.c \
GexCore/USB/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \
GexCore/USB/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
GexCore/USB/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \
Src/platform_resources.c
GEX_C_INCLUDES = \
-IGexUnits \
platform/cfg_utils.h
+3 -3
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@@ -2,8 +2,8 @@
// Created by MightyPork on 2018/02/23.
//
#ifndef GEX_F072_CFG_UTILS_H
#define GEX_F072_CFG_UTILS_H
#ifndef GEX_CORE_CFG_UTILS_H
#define GEX_CORE_CFG_UTILS_H
#include "platform.h"
#include "rsc_enum.h"
@@ -162,4 +162,4 @@ static inline int32_t cfg_i32_parse(const char *value, bool *suc)
return (int32_t) avr_atoi(value);
}
#endif //GEX_F072_CFG_UTILS_H
#endif //GEX_CORE_CFG_UTILS_H
platform/debug_uart.c
-43
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@@ -5,54 +5,11 @@
#include "platform.h"
#include "framework/resources.h"
#include "debug_uart.h"
#include "plat_compat.h"
#include "hw_utils.h"
#include "framework/system_settings.h"
#if USE_DEBUG_UART
#define DEBUG_USART_BAUD 115200
#if GEX_PLAT_F072_DISCOVERY || GEX_PLAT_F072_HUB || GEX_PLAT_F072_ZERO
#define DEBUG_USART USART1
#define DEBUG_USART_RSC R_USART1
#define DEBUG_USART_PORT 'A'
#define DEBUG_USART_PIN 9
#define DEBUG_USART_AF 1
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#elif GEX_PLAT_F103_BLUEPILL
#define DEBUG_USART USART2
#define DEBUG_USART_RSC R_USART2
#define DEBUG_USART_PORT 'A'
#define DEBUG_USART_PIN 2
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#elif GEX_PLAT_F303_DISCOVERY
#define DEBUG_USART USART3
#define DEBUG_USART_RSC R_USART3
#define DEBUG_USART_PORT 'D'
#define DEBUG_USART_PIN 8
#define DEBUG_USART_AF 7
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#elif GEX_PLAT_F407_DISCOVERY
#define DEBUG_USART USART2
#define DEBUG_USART_RSC R_USART2
#define DEBUG_USART_PORT 'A'
#define DEBUG_USART_PIN 2
#define DEBUG_USART_AF 7
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#else
#error "BAD PLATFORM!"
#endif
static bool debug_uart_inited = false;
static bool debug_uart_preinited = false;
platform/irq_dispatcher.h
+3 -3
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@@ -4,8 +4,8 @@
// Provides a trampoline system for redirecting IRQ calls to assigned callbacks.
//
#ifndef GEX_F072_IRQ_DISPATCHER_H
#define GEX_F072_IRQ_DISPATCHER_H
#ifndef GEX_CORE_IRQ_DISPATCHER_H
#define GEX_CORE_IRQ_DISPATCHER_H
// Dummy peripherals for use with the
extern void * const EXTIS[16];
@@ -42,4 +42,4 @@ void irqd_attach(void *periph, IrqCallback callback, void *data);
*/
void* irqd_detach(void *periph, IrqCallback callback);
#endif //GEX_F072_IRQ_DISPATCHER_H
#endif //GEX_CORE_IRQ_DISPATCHER_H
platform/ll_extension.h
+3 -3
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@@ -2,8 +2,8 @@
// Created by MightyPork on 2018/02/04.
//
#ifndef GEX_F072_LL_EXTENSION_H
#define GEX_F072_LL_EXTENSION_H
#ifndef GEX_CORE_LL_EXTENSION_H
#define GEX_CORE_LL_EXTENSION_H
#include "platform.h"
@@ -57,4 +57,4 @@ static inline void LL_DMA_ClearFlags(DMA_TypeDef *DMAx, uint8_t channel)
}
#endif //GEX_F072_LL_EXTENSION_H
#endif //GEX_CORE_LL_EXTENSION_H
platform/lock_jumper.h
-2
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@@ -7,8 +7,6 @@
#ifndef GEX_LOCK_JUMPER_H
#define GEX_LOCK_JUMPER_H
#include "plat_compat.h"
/**
* Init the lock jumper subsystem
*/
platform/plat_config.h
+64
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@@ -0,0 +1,64 @@
//
// Created by MightyPork on 2018/07/07.
//
#ifndef GEX_CORE_PLAT_CONFIG_H
#define GEX_CORE_PLAT_CONFIG_H
#define VFS_DRIVE_NAME "GEX"
// -------- Priorities -------------
#define TSK_MAIN_PRIO osPriorityNormal
#define TSK_JOBS_PRIO osPriorityHigh
#define TSK_TIMERS_PRIO 4 // this must be in the 0-7 range
// -------- Static buffers ---------
// USB / VFS task stack size
#if DISABLE_MSC
#define TSK_STACK_MAIN 100 // without MSC the stack usage is significantly lower
#else
#define TSK_STACK_MAIN 160
#endif
// 180 is normally enough if not doing extensive debug logging
#define TSK_STACK_MSG 220 // TF message handler task stack size (all unit commands run on this thread)
#define TSK_STACK_IDLE 64 //configMINIMAL_STACK_SIZE
#define TSK_STACK_TIMERS 64 //configTIMER_TASK_STACK_DEPTH
#define PLAT_HEAP_SIZE 4096
#define BULK_READ_BUF_LEN 256 // Buffer for TF bulk reads
#define UNIT_TMP_LEN 256 // Buffer for internal unit operations
#define FLASH_SAVE_BUF_LEN 128 // Malloc'd buffer for saving to flash
#define MSG_QUE_SLOT_SIZE 64 // FIXME this should be possible to lower, but there's some bug with bulk transfer / INI parser
#define RX_QUE_CAPACITY 16 // TinyFrame rx queue size (64 bytes each)
#define TF_MAX_PAYLOAD_RX 512 // TF max Rx payload
#define TF_SENDBUF_LEN 512 // TF transmit buffer (can be less than a full frame)
#define TF_MAX_ID_LST 4 // Frame ID listener count
#define TF_MAX_TYPE_LST 6 // Frame Type listener count
#define TF_MAX_GEN_LST 1 // Generic listener count
#define USBD_MAX_STR_DESC_SIZ 64 // Descriptor conversion buffer (used for converting ASCII to UTF-16, must be 2x the size of the longest descriptor)
#define MSC_MEDIA_PACKET 512 // Mass storage sector size (packet)
#define INI_KEY_MAX 20 // Ini parser key buffer
#define INI_VALUE_MAX 30 // Ini parser value buffer
// -------- Stack buffers ----------
#define DBG_BUF_LEN 100 // Size of the snprintf buffer for debug messages
#define ERR_MSG_STR_LEN 64 // Error message buffer size
#define IWBUFFER_LEN 80 // Ini writer buffer for sprintf
// -------- Timeouts ------------
#define TF_PARSER_TIMEOUT_TICKS 100 // Timeout for receiving & parsing a frame
#define BULK_LST_TIMEOUT_MS 2000 // timeout for the bulk transaction to expire
#define MSG_QUE_POST_TIMEOUT 200 // Time to post to the messages / jobs queue
#endif //GEX_CORE_PLAT_CONFIG_H
platform/platform.c
+6 -208
View File
@@ -12,6 +12,8 @@
#include "units_manifest.h"
extern uint32_t plat_init_resources2(void);
// TODO split this and the plat_compat files to per-platform ones stored in the platform project
void plat_init_resources(void)
@@ -26,217 +28,16 @@ void plat_init_resources(void)
hw_periph_clock_enable(DMA2);
#endif
// --- Common unit drivers ---
#if HAVE_TEST_UNIT
ureg_add_type(&UNIT_TEST);
#endif
// EXTI are always available
rsc_free_range(NULL, R_EXTI0, R_EXTI15);
// --- platform specific resource releases and claims ---
#if defined(GEX_PLAT_F103_BLUEPILL)
// Platform STM32F103C8T6 Bluepill ($4 board from eBay)
// Units supported by the platform (known to work correctly)
// free all present resources
{
rsc_free_range(NULL, R_ADC1, R_ADC2);
rsc_free_range(NULL, R_I2C1, R_I2C2);
rsc_free_range(NULL, R_SPI1, R_SPI2);
rsc_free_range(NULL, R_TIM1, R_TIM4);
rsc_free_range(NULL, R_USART1, R_USART3);
rsc_free_range(NULL, R_PA0, R_PA15);
rsc_free_range(NULL, R_PB0, R_PB15);
rsc_free_range(NULL, R_PC13, R_PC15);
rsc_free_range(NULL, R_PD0, R_PD1);
}
// Claim resources not available due to board layout or internal usage
{
// HAL timebase
rv |= rsc_claim(&UNIT_SYSTEM, R_TIM1);
// HSE crystal
rv |= rsc_claim(&UNIT_SYSTEM, R_PD0);
rv |= rsc_claim(&UNIT_SYSTEM, R_PD1);
// SWD
rv |= rsc_claim(&UNIT_SYSTEM, R_PA13);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA14);
// USB
rv |= rsc_claim(&UNIT_SYSTEM, R_PA11);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA12);
// BOOT pin(s)
rv |= rsc_claim(&UNIT_SYSTEM, R_PB2); // BOOT1
}
#elif defined(STM32F072xB)
// Platform STM32F073RBT
// Additional GPIO ports
__HAL_RCC_GPIOF_CLK_ENABLE();
// Units supported by the platform (known to work correctly)
// - this is a macro created in the Makefile, registering all enabled units
UNITS_REGISTER_CMD
// Free all present resources
{
rsc_free(NULL, R_ADC1);
// rsc_free(NULL, R_CAN1);
// rsc_free_range(NULL, R_COMP1, R_COMP2);
rsc_free(NULL, R_DAC1);
// rsc_free(NULL, R_HDMI_CEC);
rsc_free(NULL, R_TSC);
rsc_free_range(NULL, R_I2C1, R_I2C2);
// rsc_free_range(NULL, R_I2S1, R_I2S2);
rsc_free_range(NULL, R_SPI1, R_SPI2);
rsc_free_range(NULL, R_TIM1, R_TIM3);
rsc_free_range(NULL, R_TIM6, R_TIM7);
rsc_free_range(NULL, R_TIM14, R_TIM17);
rsc_free_range(NULL, R_USART1, R_USART4);
rsc_free_range(NULL, R_DMA1_1, R_DMA1_7);
rsc_free_range(NULL, R_PA0, R_PA15);
rsc_free_range(NULL, R_PB0, R_PB15);
rsc_free_range(NULL, R_PC0, R_PC15);
rsc_free(NULL, R_PD2);
rsc_free_range(NULL, R_PF0, R_PF1);
}
// Claim resources not available due to board layout or internal usage
{
// HAL timebase
rv |= rsc_claim(&UNIT_SYSTEM, R_TIM17);
// HSE crystal
rv |= rsc_claim(&UNIT_SYSTEM, R_PF0);
#if PLAT_FULL_XTAL
rv |= rsc_claim(&UNIT_SYSTEM, R_PF1); // - not used in BYPASS mode
#endif
// SWD
// rv |= rsc_claim(&UNIT_SYSTEM, R_PA13);
// rv |= rsc_claim(&UNIT_SYSTEM, R_PA14);
// USB
rv |= rsc_claim(&UNIT_SYSTEM, R_PA11);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA12);
#if defined(GEX_PLAT_F072_ZERO)
// unconnected pins
rv |= rsc_claim_range(&UNIT_PLATFORM, R_PC0, R_PC1);
rv |= rsc_claim_range(&UNIT_PLATFORM, R_PC4, R_PC9);
#endif
}
#elif defined(GEX_PLAT_F303_DISCOVERY)
// Platform STM32F303VCT
// Additional GPIO ports
__HAL_RCC_GPIOF_CLK_ENABLE();
// Units supported by the platform (known to work correctly)
// ureg_add_type(&UNIT_XYZ);
// Free all present resources
{
rsc_free_range(NULL, R_ADC1, R_ADC4);
// rsc_free(NULL, R_CAN1);
// rsc_free_range(NULL, R_COMP1, R_COMP7);
// rsc_free(NULL, R_HDMI_CEC);
rsc_free(NULL, R_DAC1);
rsc_free_range(NULL, R_I2C1, R_I2C2);
rsc_free_range(NULL, R_I2S2, R_I2S3);
// rsc_free_range(NULL, R_OPAMP1, R_OPAMP4);
rsc_free_range(NULL, R_SPI1, R_SPI3);
rsc_free_range(NULL, R_TIM1, R_TIM4);
rsc_free_range(NULL, R_TIM6, R_TIM8);
rsc_free_range(NULL, R_TIM15, R_TIM17);
rsc_free(NULL, R_TSC);
rsc_free_range(NULL, R_USART1, R_USART5);
rsc_free_range(NULL, R_PA0, R_PA15);
rsc_free_range(NULL, R_PB0, R_PB15);
rsc_free_range(NULL, R_PC0, R_PC15);
rsc_free_range(NULL, R_PD0, R_PD15);
rsc_free_range(NULL, R_PE0, R_PE15);
rsc_free_range(NULL, R_PF0, R_PF2);
rsc_free(NULL, R_PF4);
rsc_free_range(NULL, R_PF9, R_PF10);
}
// Claim resources not available due to board layout or internal usage
{
// HAL timebase
rv |= rsc_claim(&UNIT_SYSTEM, R_TIM1);
// HSE crystal
rv |= rsc_claim(&UNIT_SYSTEM, R_PF0);
//rv |= rsc_claim(&UNIT_SYSTEM, R_PF1); // - not used in BYPASS mode
// SWD
rv |= rsc_claim(&UNIT_SYSTEM, R_PA13);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA14);
// USB
rv |= rsc_claim(&UNIT_SYSTEM, R_PA11);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA12);
// BOOT pin(s)
rv |= rsc_claim(&UNIT_SYSTEM, R_PB2); // BOOT1
}
#elif defined(GEX_PLAT_F407_DISCOVERY)
// Platform STM32F407VGT
// Additional GPIO ports
__HAL_RCC_GPIOF_CLK_ENABLE();
// Units supported by the platform (known to work correctly)
// ureg_add_type(&UNIT_XYZ);
// Free all present resources
{
rsc_free_range(NULL, R_ADC1, R_ADC3);
// rsc_free_range(NULL, R_CAN1, R_CAN2);
// rsc_free_range(NULL, R_COMP1, R_COMP7);
rsc_free(NULL, R_DAC1);
// rsc_free(NULL, R_DCMI);
// rsc_free(NULL, R_ETH);
// rsc_free(NULL, R_FSMC);
rsc_free_range(NULL, R_I2C1, R_I2C3);
rsc_free_range(NULL, R_I2S2, R_I2S3);
// rsc_free(NULL, R_SDIO);
rsc_free_range(NULL, R_SPI1, R_SPI3);
rsc_free_range(NULL, R_TIM1, R_TIM14);
rsc_free_range(NULL, R_USART1, R_USART3);
rsc_free(NULL, R_USART6);
rsc_free_range(NULL, R_PA0, R_PA15);
rsc_free_range(NULL, R_PB0, R_PB15);
rsc_free_range(NULL, R_PC0, R_PC15);
rsc_free_range(NULL, R_PD0, R_PD15);
rsc_free_range(NULL, R_PE0, R_PE15);
// also has 2 PH pins
// F407 appears to have fewer GPIOs than F303?
}
// Claim resources not available due to board layout or internal usage
{
// HAL timebase
rv |= rsc_claim(&UNIT_SYSTEM, R_TIM1);
// HSE crystal
// H0 and H1
// SWD
rv |= rsc_claim(&UNIT_SYSTEM, R_PA13);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA14);
// USB
rv |= rsc_claim(&UNIT_SYSTEM, R_PA11);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA12);
// BOOT pin(s)
rv |= rsc_claim(&UNIT_SYSTEM, R_PB2); // BOOT1
}
#else
#error "BAD PLATFORM!"
#endif
UNITS_REGISTER_CMD;
rv = plat_init_resources2();
assert_param(rv == 0);
}
@@ -250,13 +51,10 @@ void plat_usb_reconnect(void)
{
if (gActiveComport != COMPORT_USB) return;
// TODO add better reset methods available on different chips
// TODO add other reset methods available on different chips (e.g. externam FET)
USBD_LL_Reset(&hUsbDeviceFS);
#if defined(GEX_PLAT_F103_BLUEPILL)
// F103 doesn't have pull-up control
#else
#if PLAT_USB_PU_CTL
HAL_PCD_DevDisconnect(&hpcd_USB_FS);
osDelay(100);
HAL_PCD_DevConnect(&hpcd_USB_FS);
platform/platform.h
+7
View File
@@ -17,8 +17,15 @@
// FreeRTOS includes
#include <cmsis_os.h>
// platform-independent GEX config
#include "plat_config.h"
// platform-specific stuff (includes stm32 driver headers)
#include "plat_compat.h"
#define PLAT_AHB_HZ (PLAT_AHB_MHZ*1000000)
#define PLAT_APB1_HZ (PLAT_APB1_MHZ*1000000)
#define PLAT_APB2_HZ (PLAT_APB2_MHZ*1000000)
// assert_param, trap...
#include "stm32_assert.h"
// inIRQ etc
platform/timebase.h
+3 -3
View File
@@ -8,8 +8,8 @@
// and interrupts.
//
#ifndef GEX_F072_TIMEBASE_H
#define GEX_F072_TIMEBASE_H
#ifndef GEX_CORE_TIMEBASE_H
#define GEX_CORE_TIMEBASE_H
#include "platform.h"
@@ -58,4 +58,4 @@ static inline uint32_t PTIM_MicroDelayAlign(void)
return res;
}
#endif //GEX_F072_TIMEBASE_H
#endif //GEX_CORE_TIMEBASE_H
platform/watchdog.h
+3 -3
View File
@@ -2,8 +2,8 @@
// Created by MightyPork on 2018/02/27.
//
#ifndef GEX_F072_WATCHDOG_H
#define GEX_F072_WATCHDOG_H
#ifndef GEX_CORE_WATCHDOG_H
#define GEX_CORE_WATCHDOG_H
/**
* Initialize the application watchdog
@@ -29,4 +29,4 @@ void wd_resume(void);
*/
void wd_restart(void);
#endif //GEX_F072_WATCHDOG_H
#endif //GEX_CORE_WATCHDOG_H
tasks/task_msg.h
+3 -3
View File
@@ -5,8 +5,8 @@
// and TinyFrame message handling
//
#ifndef GEX_F072_TASK_MSG_H
#define GEX_F072_TASK_MSG_H
#ifndef GEX_CORE_TASK_MSG_H
#define GEX_CORE_TASK_MSG_H
#include "platform.h"
#include "sched_queue.h"
@@ -39,4 +39,4 @@ void rxQuePostMsg(uint8_t *buf, uint32_t len);
extern volatile uint32_t msgQueHighWaterMark;
#endif
#endif //GEX_F072_TASK_MSG_H
#endif //GEX_CORE_TASK_MSG_H
template/nrf_pins.h.txt
+41
View File
@@ -0,0 +1,41 @@
//
// Definition of nRF24L01+ pin mappings for the platform
// This file may be omitted if SUPPORT_NRF is not set in plat_compat.h
// See rsc_enum.h for the R_ resource constants
//
#ifndef GEX_NRF_PINS_H
#define GEX_NRF_PINS_H
#include "platform.h"
#include "rsc_enum.h"
#define NRF_SPI SPI2
#define NRF_R_SPI R_SPI2
#define NRF_IRQ_Pin LL_GPIO_PIN_15
#define NRF_IRQ_GPIO_Port GPIOC
#define NRF_R_IRQ R_PC15
#define NRF_EXTI_LINENUM 15
#define NRF_SYSCFG_EXTI_PORT LL_SYSCFG_EXTI_PORTC
#define NRF_NSS_Pin LL_GPIO_PIN_13
#define NRF_NSS_GPIO_Port GPIOC
#define NRF_R_NSS R_PC13
#define NRF_CE_Pin LL_GPIO_PIN_14
#define NRF_CE_GPIO_Port GPIOC
#define NRF_R_CE R_PC14
#define NRF_RST_Pin LL_GPIO_PIN_12
#define NRF_RST_GPIO_Port GPIOC
#define NRF_R_RST R_PC12
#define NRF_R_SCK R_PB13
#define NRF_SCK_AF LL_GPIO_AF_0
#define NRF_R_MISO R_PC2
#define NRF_MISO_AF LL_GPIO_AF_1
#define NRF_R_MOSI R_PC3
#define NRF_MOSI_AF LL_GPIO_AF_1
#endif //GEX_NRF_PINS_H
template/old/FreeRTOSConfig.plat.txt
+28
View File
@@ -0,0 +1,28 @@
#if defined(GEX_PLAT_F103_BLUEPILL) || defined(GEX_PLAT_F303_DISCOVERY) \
|| defined(GEX_PLAT_F407_DISCOVERY)
// This is for F103+
/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
#define configPRIO_BITS 4
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#elif defined(STM32F072xB)
// This is for F072
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 3
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1
#define configPRIO_BITS 2
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#else
#error "BAD PLATFORM!!"
#endif
template/old/debug_uart.h.txt
+41
View File
@@ -0,0 +1,41 @@
#define DEBUG_USART_BAUD 115200
#if GEX_PLAT_F072
#define DEBUG_USART USART1
#define DEBUG_USART_RSC R_USART1
#define DEBUG_USART_PORT 'A'
#define DEBUG_USART_PIN 9
#define DEBUG_USART_AF 1
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#elif GEX_PLAT_F103
#define DEBUG_USART USART2
#define DEBUG_USART_RSC R_USART2
#define DEBUG_USART_PORT 'A'
#define DEBUG_USART_PIN 2
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#elif GEX_PLAT_F303
#define DEBUG_USART USART3
#define DEBUG_USART_RSC R_USART3
#define DEBUG_USART_PORT 'D'
#define DEBUG_USART_PIN 8
#define DEBUG_USART_AF 7
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#elif GEX_PLAT_F407
#define DEBUG_USART USART2
#define DEBUG_USART_RSC R_USART2
#define DEBUG_USART_PORT 'A'
#define DEBUG_USART_PIN 2
#define DEBUG_USART_AF 7
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#else
#error "BAD PLATFORM!"
#endif
platform/plat_compat.h → template/old/plat_compat.h.txt
-69
View File
@@ -5,75 +5,6 @@
#ifndef GEX_PLAT_COMPAT_H
#define GEX_PLAT_COMPAT_H
#define VFS_DRIVE_NAME "GEX"
// -------- Priorities -------------
#define TSK_MAIN_PRIO osPriorityNormal
#define TSK_JOBS_PRIO osPriorityHigh
#define TSK_TIMERS_PRIO 4 // this must be in the 0-7 range
// -------- Static buffers ---------
// USB / VFS task stack size
#if DISABLE_MSC
#define TSK_STACK_MAIN 100 // without MSC the stack usage is significantly lower
#else
#define TSK_STACK_MAIN 160
#endif
// 180 is normally enough if not doing extensive debug logging
#define TSK_STACK_MSG 220 // TF message handler task stack size (all unit commands run on this thread)
#define TSK_STACK_IDLE 64 //configMINIMAL_STACK_SIZE
#define TSK_STACK_TIMERS 64 //configTIMER_TASK_STACK_DEPTH
#define PLAT_HEAP_SIZE 4096
#define BULK_READ_BUF_LEN 256 // Buffer for TF bulk reads
#define UNIT_TMP_LEN 256 // Buffer for internal unit operations
#define FLASH_SAVE_BUF_LEN 128 // Malloc'd buffer for saving to flash
#define MSG_QUE_SLOT_SIZE 64 // FIXME this should be possible to lower, but there's some bug with bulk transfer / INI parser
#define RX_QUE_CAPACITY 16 // TinyFrame rx queue size (64 bytes each)
#define TF_MAX_PAYLOAD_RX 512 // TF max Rx payload
#define TF_SENDBUF_LEN 512 // TF transmit buffer (can be less than a full frame)
#define TF_MAX_ID_LST 4 // Frame ID listener count
#define TF_MAX_TYPE_LST 6 // Frame Type listener count
#define TF_MAX_GEN_LST 1 // Generic listener count
#define USBD_MAX_STR_DESC_SIZ 64 // Descriptor conversion buffer (used for converting ASCII to UTF-16, must be 2x the size of the longest descriptor)
#define MSC_MEDIA_PACKET 512 // Mass storage sector size (packet)
#define INI_KEY_MAX 20 // Ini parser key buffer
#define INI_VALUE_MAX 30 // Ini parser value buffer
// -------- Stack buffers ----------
#define DBG_BUF_LEN 100 // Size of the snprintf buffer for debug messages
#define ERR_MSG_STR_LEN 64 // Error message buffer size
#define IWBUFFER_LEN 80 // Ini writer buffer for sprintf
// -------- Timeouts ------------
#define TF_PARSER_TIMEOUT_TICKS 100 // Timeout for receiving & parsing a frame
#define BULK_LST_TIMEOUT_MS 2000 // timeout for the bulk transaction to expire
#define MSG_QUE_POST_TIMEOUT 200 // Time to post to the messages / jobs queue
// -------- Platform specific includes and defines ---------
/// Feature flags:
// PLAT_FLASHBANKS - has the Banks field on the Flash config struct
// PLAT_NO_FLOATING_INPUTS - can't have digital inputs with no pull resistor
// PLAT_USB_PHYCLOCK - requires special config of phy clock for USB
// PLAT_USB_OTGFS - uses the USB OTG IP, needs different config code
// PLAT_LOCK_BTN - use a lock button instead of a lock jumper (push to toggle)
// PLAT_LOCK_1CLOSED - lock jumper is active (closed / button pressed) in logical 1
// PLAT_NO_AFNUM - legacy platform without numbered AF alternatives
// PLAT_FULL_XTAL - use two-wire xtal attachment
// SUPPORT_NRF
#if defined(GEX_PLAT_F103_BLUEPILL)
// platform name for the version string
template/old/plat_init.c.txt
+194
View File
@@ -0,0 +1,194 @@
#if defined(GEX_PLAT_F103_BLUEPILL)
// Platform STM32F103C8T6 Bluepill ($4 board from eBay)
// Units supported by the platform (known to work correctly)
// free all present resources
{
rsc_free_range(NULL, R_ADC1, R_ADC2);
rsc_free_range(NULL, R_I2C1, R_I2C2);
rsc_free_range(NULL, R_SPI1, R_SPI2);
rsc_free_range(NULL, R_TIM1, R_TIM4);
rsc_free_range(NULL, R_USART1, R_USART3);
rsc_free_range(NULL, R_PA0, R_PA15);
rsc_free_range(NULL, R_PB0, R_PB15);
rsc_free_range(NULL, R_PC13, R_PC15);
rsc_free_range(NULL, R_PD0, R_PD1);
}
// Claim resources not available due to board layout or internal usage
{
// HAL timebase
rv |= rsc_claim(&UNIT_SYSTEM, R_TIM1);
// HSE crystal
rv |= rsc_claim(&UNIT_SYSTEM, R_PD0);
rv |= rsc_claim(&UNIT_SYSTEM, R_PD1);
// SWD
rv |= rsc_claim(&UNIT_SYSTEM, R_PA13);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA14);
// USB
rv |= rsc_claim(&UNIT_SYSTEM, R_PA11);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA12);
// BOOT pin(s)
rv |= rsc_claim(&UNIT_SYSTEM, R_PB2); // BOOT1
}
#elif defined(STM32F072xB)
// Platform STM32F073RBT
// Free all present resources
{
rsc_free(NULL, R_ADC1);
// rsc_free(NULL, R_CAN1);
// rsc_free_range(NULL, R_COMP1, R_COMP2);
rsc_free(NULL, R_DAC1);
// rsc_free(NULL, R_HDMI_CEC);
rsc_free(NULL, R_TSC);
rsc_free_range(NULL, R_I2C1, R_I2C2);
// rsc_free_range(NULL, R_I2S1, R_I2S2);
rsc_free_range(NULL, R_SPI1, R_SPI2);
rsc_free_range(NULL, R_TIM1, R_TIM3);
rsc_free_range(NULL, R_TIM6, R_TIM7);
rsc_free_range(NULL, R_TIM14, R_TIM17);
rsc_free_range(NULL, R_USART1, R_USART4);
rsc_free_range(NULL, R_DMA1_1, R_DMA1_7);
rsc_free_range(NULL, R_PA0, R_PA15);
rsc_free_range(NULL, R_PB0, R_PB15);
rsc_free_range(NULL, R_PC0, R_PC15);
rsc_free(NULL, R_PD2);
rsc_free_range(NULL, R_PF0, R_PF1);
}
// Claim resources not available due to board layout or internal usage
{
// HAL timebase
rv |= rsc_claim(&UNIT_SYSTEM, R_TIM17);
// HSE crystal
rv |= rsc_claim(&UNIT_SYSTEM, R_PF0);
#if PLAT_FULL_XTAL
rv |= rsc_claim(&UNIT_SYSTEM, R_PF1); // - not used in BYPASS mode
#endif
// SWD
// rv |= rsc_claim(&UNIT_SYSTEM, R_PA13);
// rv |= rsc_claim(&UNIT_SYSTEM, R_PA14);
// USB
rv |= rsc_claim(&UNIT_SYSTEM, R_PA11);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA12);
#if defined(GEX_PLAT_F072_ZERO)
// unconnected pins
rv |= rsc_claim_range(&UNIT_PLATFORM, R_PC0, R_PC1);
rv |= rsc_claim_range(&UNIT_PLATFORM, R_PC4, R_PC9);
#endif
}
#elif defined(GEX_PLAT_F303_DISCOVERY)
// Platform STM32F303VCT
// Additional GPIO ports
__HAL_RCC_GPIOF_CLK_ENABLE();
// Units supported by the platform (known to work correctly)
// ureg_add_type(&UNIT_XYZ);
// Free all present resources
{
rsc_free_range(NULL, R_ADC1, R_ADC4);
// rsc_free(NULL, R_CAN1);
// rsc_free_range(NULL, R_COMP1, R_COMP7);
// rsc_free(NULL, R_HDMI_CEC);
rsc_free(NULL, R_DAC1);
rsc_free_range(NULL, R_I2C1, R_I2C2);
rsc_free_range(NULL, R_I2S2, R_I2S3);
// rsc_free_range(NULL, R_OPAMP1, R_OPAMP4);
rsc_free_range(NULL, R_SPI1, R_SPI3);
rsc_free_range(NULL, R_TIM1, R_TIM4);
rsc_free_range(NULL, R_TIM6, R_TIM8);
rsc_free_range(NULL, R_TIM15, R_TIM17);
rsc_free(NULL, R_TSC);
rsc_free_range(NULL, R_USART1, R_USART5);
rsc_free_range(NULL, R_PA0, R_PA15);
rsc_free_range(NULL, R_PB0, R_PB15);
rsc_free_range(NULL, R_PC0, R_PC15);
rsc_free_range(NULL, R_PD0, R_PD15);
rsc_free_range(NULL, R_PE0, R_PE15);
rsc_free_range(NULL, R_PF0, R_PF2);
rsc_free(NULL, R_PF4);
rsc_free_range(NULL, R_PF9, R_PF10);
}
// Claim resources not available due to board layout or internal usage
{
// HAL timebase
rv |= rsc_claim(&UNIT_SYSTEM, R_TIM1);
// HSE crystal
rv |= rsc_claim(&UNIT_SYSTEM, R_PF0);
//rv |= rsc_claim(&UNIT_SYSTEM, R_PF1); // - not used in BYPASS mode
// SWD
rv |= rsc_claim(&UNIT_SYSTEM, R_PA13);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA14);
// USB
rv |= rsc_claim(&UNIT_SYSTEM, R_PA11);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA12);
// BOOT pin(s)
rv |= rsc_claim(&UNIT_SYSTEM, R_PB2); // BOOT1
}
#elif defined(GEX_PLAT_F407_DISCOVERY)
// Platform STM32F407VGT
// Additional GPIO ports
__HAL_RCC_GPIOF_CLK_ENABLE();
// Units supported by the platform (known to work correctly)
// ureg_add_type(&UNIT_XYZ);
// Free all present resources
{
rsc_free_range(NULL, R_ADC1, R_ADC3);
// rsc_free_range(NULL, R_CAN1, R_CAN2);
// rsc_free_range(NULL, R_COMP1, R_COMP7);
rsc_free(NULL, R_DAC1);
// rsc_free(NULL, R_DCMI);
// rsc_free(NULL, R_ETH);
// rsc_free(NULL, R_FSMC);
rsc_free_range(NULL, R_I2C1, R_I2C3);
rsc_free_range(NULL, R_I2S2, R_I2S3);
// rsc_free(NULL, R_SDIO);
rsc_free_range(NULL, R_SPI1, R_SPI3);
rsc_free_range(NULL, R_TIM1, R_TIM14);
rsc_free_range(NULL, R_USART1, R_USART3);
rsc_free(NULL, R_USART6);
rsc_free_range(NULL, R_PA0, R_PA15);
rsc_free_range(NULL, R_PB0, R_PB15);
rsc_free_range(NULL, R_PC0, R_PC15);
rsc_free_range(NULL, R_PD0, R_PD15);
rsc_free_range(NULL, R_PE0, R_PE15);
// also has 2 PH pins
// F407 appears to have fewer GPIOs than F303?
}
// Claim resources not available due to board layout or internal usage
{
// HAL timebase
rv |= rsc_claim(&UNIT_SYSTEM, R_TIM1);
// HSE crystal
// H0 and H1
// SWD
rv |= rsc_claim(&UNIT_SYSTEM, R_PA13);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA14);
// USB
rv |= rsc_claim(&UNIT_SYSTEM, R_PA11);
rv |= rsc_claim(&UNIT_SYSTEM, R_PA12);
// BOOT pin(s)
rv |= rsc_claim(&UNIT_SYSTEM, R_PB2); // BOOT1
}
#else
#error "BAD PLATFORM!"
#endif
template/plat_compat.h.txt
+46
View File
@@ -0,0 +1,46 @@
#ifndef GEX_PLAT_COMPAT_H
#define GEX_PLAT_COMPAT_H
// string identifying the GEX board
#define GEX_PLATFORM "Discovery-XYZ"
#define GEX_PLAT_XYZ 1 // only with the MCU name
// GEX_PLAT_XYZ_BOARD is defined in build.mk to identify particular board layout
#define PLAT_AHB_MHZ 72
#define PLAT_APB1_MHZ 36
#include ... // all useful from the peripheral library (HAL / LL)
// in bytes
#define FLASH_SIZE (128*1024)
// in bytes
#define SETTINGS_BLOCK_SIZE (2*1024)
// address where the settings block starts
#define SETTINGS_FLASH_ADDR (0x08000000 + FLASH_SIZE - SETTINGS_BLOCK_SIZE)
#define PORTS_COUNT 5 // number of available GPIO ports A,B,C,D,E,F...
#define LOCK_JUMPER_PORT 'A'
#define LOCK_JUMPER_PIN 2
#define STATUS_LED_PORT 'A'
#define STATUS_LED_PIN 15
// Feature flags:
#define PLAT_FLASHBANKS 0 // has the Banks field on the Flash config struct
#define PLAT_NO_FLOATING_INPUTS 0 // can't have digital inputs with no pull resistor
#define PLAT_USB_PHYCLOCK 0 // requires special config of phy clock for USB
#define PLAT_USB_OTGFS 0 // uses the USB OTG IP, needs different config code
#define PLAT_LOCK_BTN 1 // use a lock button instead of a lock jumper (push to toggle)
#define PLAT_LOCK_1CLOSED 1 // lock jumper is active (closed / button pressed) in logical 1
#define PLAT_NO_AFNUM 0 // legacy platform without numbered AF alternatives
#define PLAT_FULL_XTAL 1 // use two-wire xtal attachment
#define PLAT_USB_PU_CTL 1 // platform has USB pullup control
// FreeRTOS config
#define PLAT_FREERTOS_LOWEST_INTERRUPT_PRIORITY 3
#define PLAT_FREERTOS_MAX_SYSCALL_INTERRUPT_PRIORITY 1
#define PLAT_FREERTOS_PRIO_BITS 2
#define PLAT_FREERTOS_USE_PORT_OPTIMISED_TASK_SELECTION 0
#endif //GEX_PLAT_COMPAT_H
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