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551 lines
16 KiB
551 lines
16 KiB
//
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// Created by MightyPork on 2018/04/02.
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//
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#include "platform.h"
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#if SUPPORT_NRF
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#include "nrf.h"
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/**
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* Read a register
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*
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* @param reg - register number (max 83)
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* @return register value
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*/
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static uint8_t NRF_ReadRegister(uint8_t reg);
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/**
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* Write a register
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*
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* @param reg - register number (max 83)
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* @param value - register value
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* @return status register value
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*/
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static uint8_t NRF_WriteRegister(uint8_t reg, uint8_t value);
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// Internal use
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static uint8_t NRF_WriteBuffer(uint8_t reg, const uint8_t *pBuf, uint8_t bytes);
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static uint8_t NRF_ReadBuffer(uint8_t reg, uint8_t *pBuf, uint8_t bytes);
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/**
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* Set TX address for next frame
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*
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* @param SendTo - addr
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*/
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static void NRF_SetTxAddress(uint8_t ToAddr);
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//----------------------------------------------------------
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/** Tight asm loop */
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#define __asm_loop(cycles) \
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do { \
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register uint32_t _count asm ("r4") = cycles; \
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asm volatile( \
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".syntax unified\n" \
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".thumb\n" \
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"0:" \
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"subs %0, #1\n" \
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"bne 0b\n" \
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: "+r" (_count)); \
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} while(0)
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// 12 for 72 MHz
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#define _delay_us(n) __asm_loop((n)*8)
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static inline void CE(bool level) {
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__asm_loop(1);
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if (level) LL_GPIO_SetOutputPin(NRF_CE_GPIO_Port, NRF_CE_Pin);
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else LL_GPIO_ResetOutputPin(NRF_CE_GPIO_Port, NRF_CE_Pin);
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__asm_loop(1);
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}
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static inline void NSS(bool level) {
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__asm_loop(1);
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if (level) LL_GPIO_SetOutputPin(NRF_NSS_GPIO_Port, NRF_NSS_Pin);
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else LL_GPIO_ResetOutputPin(NRF_NSS_GPIO_Port, NRF_NSS_Pin);
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__asm_loop(1);
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}
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static uint8_t spi(uint8_t tx) {
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while (! LL_SPI_IsActiveFlag_TXE(NRF_SPI));
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LL_SPI_TransmitData8(NRF_SPI, tx);
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while (! LL_SPI_IsActiveFlag_RXNE(NRF_SPI));
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return LL_SPI_ReceiveData8(NRF_SPI);
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}
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void NRF_Reset(bool enable_reset)
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{
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if (enable_reset) {
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// go HIGH - this closes the PMOS
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LL_GPIO_SetOutputPin(NRF_RST_GPIO_Port, NRF_RST_Pin);
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} else {
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// LOW - open PMOS, enable power
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LL_GPIO_ResetOutputPin(NRF_RST_GPIO_Port, NRF_RST_Pin);
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}
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}
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//-------
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/*
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* from: http://barefootelectronics.com/NRF24L01.aspx
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*/
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#define CMD_READ_REG 0x00 // Read command to register
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#define CMD_WRITE_REG 0x20 // Write command to register
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#define CMD_RD_RX_PLD 0x61 // Read RX payload register address
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#define CMD_WR_TX_PLD 0xA0 // Write TX payload register address
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#define CMD_FLUSH_TX 0xE1 // Flush TX register command
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#define CMD_FLUSH_RX 0xE2 // Flush RX register command
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#define CMD_REUSE_TX_PL 0xE3 // Reuse TX payload register command
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#define CMD_RD_RX_PL_WIDTH 0x60 // Read RX Payload Width
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#define CMD_WR_ACK_PLD 0xA8 // Write ACK payload for Pipe (Add pipe number 0-6)
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#define CMD_WR_TX_PLD_NK 0xB0 // Write ACK payload for not ack
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#define CMD_NOP 0xFF // No Operation, might be used to read status register
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// SPI(nRF24L01) registers(addresses)
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#define RG_CONFIG 0x00 // 'Config' register address
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#define RG_EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
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#define RG_EN_RXADDR 0x02 // 'Enabled RX addresses' register address
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#define RG_SETUP_AW 0x03 // 'Setup address width' register address
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#define RG_SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
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#define RG_RF_CH 0x05 // 'RF channel' register address
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#define RG_RF_SETUP 0x06 // 'RF setup' register address
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#define RG_STATUS 0x07 // 'Status' register address
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#define RG_OBSERVE_TX 0x08 // 'Observe TX' register address
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#define RG_CD 0x09 // 'Carrier Detect' register address
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#define RG_RX_ADDR_P0 0x0A // 'RX address pipe0' register address
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#define RG_RX_ADDR_P1 0x0B // 'RX address pipe1' register address
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#define RG_RX_ADDR_P2 0x0C // 'RX address pipe2' register address
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#define RG_RX_ADDR_P3 0x0D // 'RX address pipe3' register address
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#define RG_RX_ADDR_P4 0x0E // 'RX address pipe4' register address
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#define RG_RX_ADDR_P5 0x0F // 'RX address pipe5' register address
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#define RG_TX_ADDR 0x10 // 'TX address' register address
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#define RG_RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
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#define RG_RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
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#define RG_RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
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#define RG_RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
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#define RG_RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
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#define RG_RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
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#define RG_FIFO_STATUS 0x17 // 'FIFO Status Register' register address
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#define RG_DYNPD 0x1C // 'Enable dynamic payload length
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#define RG_FEATURE 0x1D // 'Feature register
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#define RD_STATUS_TX_FULL 0x01 // tx queue full
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#define RD_STATUS_RX_PNO 0x0E // pipe number of the received payload
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#define RD_STATUS_MAX_RT 0x10 // max retransmissions
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#define RD_STATUS_TX_DS 0x20 // data sent
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#define RD_STATUS_RX_DR 0x40 // data ready
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#define RD_CONFIG_PRIM_RX 0x01 // is primary receiver
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#define RD_CONFIG_PWR_UP 0x02 // power up
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#define RD_CONFIG_CRCO 0x04 // 2-byte CRC
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#define RD_CONFIG_EN_CRC 0x08 // enable CRC
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#define RD_CONFIG_DISABLE_IRQ_MAX_RT 0x10
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#define RD_CONFIG_DISABLE_IRQ_TX_DS 0x20
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#define RD_CONFIG_DISABLE_IRQ_RX_DR 0x40
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#define RD_FIFO_STATUS_RX_EMPTY 0x01
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#define RD_FIFO_STATUS_RX_FULL 0x02
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#define RD_FIFO_STATUS_TX_EMPTY 0x10
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#define RD_FIFO_STATUS_TX_FULL 0x20
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#define RD_FIFO_STATUS_TX_REUSE 0x40
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// Config register bits (excluding the bottom two that are changed dynamically)
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// enable only Rx IRQ
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#define ModeBits (RD_CONFIG_DISABLE_IRQ_MAX_RT | \
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RD_CONFIG_DISABLE_IRQ_TX_DS | \
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RD_CONFIG_EN_CRC | \
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RD_CONFIG_CRCO)
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static inline uint8_t CS(uint8_t hl)
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{
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if (hl == 1) {
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NSS(0);
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}
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else {
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NSS(1);
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}
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return hl;
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}
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#define CHIPSELECT for (uint8_t cs = CS(1); cs==1; cs = CS(0))
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// Base NRF address - byte 4 may be modified before writing to a pipe register,
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// the first 4 bytes are shared in the network. Master is always code 0.
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static uint8_t nrf_base_address[5];
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static uint8_t nrf_pipe_addr[6];
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static bool nrf_pipe_enabled[6];
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static uint8_t NRF_WriteRegister(uint8_t reg, uint8_t value)
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{
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uint8_t status = 0;
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CHIPSELECT {
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status = spi(CMD_WRITE_REG | reg);
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spi(value);
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}
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dbg_nrf("Wr[0x%02x] := 0x%02x", (int)reg, (int) value);
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uint8_t reg_val = 0;
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CHIPSELECT {
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spi(CMD_READ_REG | reg);
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reg_val = spi(0);
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}
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dbg_nrf(" verify 0x%02x", (int)reg_val);
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if (reg_val != value)
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dbg_nrf(" !!!");
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else
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dbg_nrf(" OK");
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return status;
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}
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static uint8_t NRF_ReadRegister(uint8_t reg)
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{
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uint8_t reg_val = 0;
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CHIPSELECT {
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spi(CMD_READ_REG | reg);
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reg_val = spi(0);
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}
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dbg_nrf("Rd[0x%02x] = 0x%02x", (int)reg, (int) reg_val);
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return reg_val;
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}
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static uint8_t NRF_ReadStatus(void)
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{
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uint8_t reg_val = 0;
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CHIPSELECT {
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reg_val = spi(CMD_NOP);
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}
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return reg_val;
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}
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static uint8_t NRF_WriteBuffer(uint8_t reg, const uint8_t *pBuf, uint8_t bytes)
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{
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uint8_t status = 0, i = 0;
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CHIPSELECT {
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status = spi(CMD_WRITE_REG | reg);
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for (i = 0; i < bytes; i++) {
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spi(*pBuf++);
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}
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}
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return status;
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}
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static uint8_t NRF_ReadBuffer(uint8_t reg, uint8_t *pBuf, uint8_t bytes)
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{
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uint8_t status = 0, i;
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CHIPSELECT {
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status = spi(CMD_READ_REG | reg);
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for (i = 0; i < bytes; i++) {
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pBuf[i] = spi(0);
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}
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}
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return status;
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}
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void NRF_SetBaseAddress(const uint8_t *Bytes4)
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{
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memcpy(nrf_base_address, Bytes4, 4);
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nrf_base_address[4] = 0;
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// write it to the two full-width address registers
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NRF_WriteBuffer(RG_RX_ADDR_P0, nrf_base_address, 5);
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nrf_base_address[4] = 1;// to be different
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NRF_WriteBuffer(RG_RX_ADDR_P1, nrf_base_address, 5);
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}
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void NRF_SetRxAddress(uint8_t pipenum, uint8_t AddrByte)
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{
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if (pipenum > 5) {
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dbg_nrf("!! bad pipe %d", pipenum);
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return;
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}
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nrf_base_address[4] = AddrByte;
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nrf_pipe_addr[pipenum] = AddrByte;
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dbg_nrf("Set Rx addr (pipe %d) = 0x%02x", (int)pipenum, AddrByte);
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if (pipenum == 0) {
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dbg_nrf("W ADDR_PA0: %02X-%02X-%02X-%02X-%02X", nrf_base_address[0], nrf_base_address[1], nrf_base_address[2], nrf_base_address[3], nrf_base_address[4]);
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NRF_WriteBuffer(RG_RX_ADDR_P0, nrf_base_address, 5);
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}
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else if (pipenum == 1) {
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dbg_nrf("W ADDR_PA1: %02X-%02X-%02X-%02X-%02X", nrf_base_address[0], nrf_base_address[1], nrf_base_address[2], nrf_base_address[3], nrf_base_address[4]);
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NRF_WriteBuffer(RG_RX_ADDR_P1, nrf_base_address, 5);
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}
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else {
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NRF_WriteRegister(RG_RX_ADDR_P2 + (pipenum - 2), AddrByte);
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}
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}
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bool NRF_AddPipe(uint8_t AddrByte, uint8_t *PipeNum)
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{
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for (uint8_t i = 0; i < 6; i++) {
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if(!nrf_pipe_enabled[i]) {
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NRF_SetRxAddress(i, AddrByte);
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*PipeNum = i;
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NRF_EnablePipe(i);
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return true;
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}
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}
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return false;
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}
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uint8_t NRF_PipeNum2Addr(uint8_t pipe_num)
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{
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if (pipe_num > 5) return 0; // fail
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return nrf_pipe_addr[pipe_num];
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}
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uint8_t NRF_Addr2PipeNum(uint8_t addr)
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{
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for (int i = 0; i < 6; i++) {
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if (nrf_pipe_addr[i] == addr) return (uint8_t) i;
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}
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return 0xFF;
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}
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void NRF_EnablePipe(uint8_t pipenum)
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{
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dbg_nrf("Enable pipe num %d", (int)pipenum);
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uint8_t enabled = NRF_ReadRegister(RG_EN_RXADDR);
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enabled |= 1 << pipenum;
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NRF_WriteRegister(RG_EN_RXADDR, enabled);
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nrf_pipe_enabled[pipenum] = 1;
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}
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void NRF_DisablePipe(uint8_t pipenum)
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{
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uint8_t enabled = NRF_ReadRegister(RG_EN_RXADDR);
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enabled &= ~(1 << pipenum);
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NRF_WriteRegister(RG_EN_RXADDR, enabled);
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nrf_pipe_enabled[pipenum] = 0;
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}
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static void NRF_SetTxAddress(uint8_t SendTo)
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{
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nrf_base_address[4] = SendTo;
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dbg_nrf("W Tx_ADDR + Rx0: %02X-%02X-%02X-%02X-%02X",
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nrf_base_address[0], nrf_base_address[1], nrf_base_address[2], nrf_base_address[3], nrf_base_address[4]);
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NRF_WriteBuffer(RG_TX_ADDR, nrf_base_address, 5);
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NRF_WriteBuffer(RG_RX_ADDR_P0, nrf_base_address, 5); // the ACK will come to pipe 0
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}
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void NRF_PowerDown(void)
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{
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dbg_nrf("PDn");
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CE(0);
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NRF_WriteRegister(RG_CONFIG, ModeBits);
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}
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void NRF_ModeTX(void)
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{
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dbg_nrf("Tx Mode");
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CE(0);
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uint8_t m = NRF_ReadRegister(RG_CONFIG);
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NRF_WriteRegister(RG_CONFIG, ModeBits | RD_CONFIG_PWR_UP);
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if ((m & RD_CONFIG_PWR_UP) == 0) {
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// switching on
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LL_mDelay(5);
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}
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}
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void NRF_ModeRX(void)
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{
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dbg_nrf("Rx Mode");
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NRF_WriteRegister(RG_CONFIG, ModeBits | RD_CONFIG_PWR_UP | RD_CONFIG_PRIM_RX);
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NRF_SetRxAddress(0, nrf_pipe_addr[0]); // set the P0 address - it was changed during Rx for ACK reception
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CE(1);
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//if ((m&2)==0) LL_mDelay()(5); You don't need to wait. Just nothing will come for 5ms or more
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}
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uint8_t NRF_IsModePowerDown(void)
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{
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uint8_t ret = 0;
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if ((NRF_ReadRegister(RG_CONFIG) & RD_CONFIG_PWR_UP) == 0) ret = 1;
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return ret;
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}
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uint8_t NRF_IsModeTX(void)
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{
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uint8_t m = NRF_ReadRegister(RG_CONFIG);
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if ((m & RD_CONFIG_PWR_UP) == 0) return 0; // OFF
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if ((m & RD_CONFIG_PRIM_RX) == 0) return 1;
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return 0;
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}
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uint8_t NRF_IsModeRx(void)
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{
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uint8_t m = NRF_ReadRegister(RG_CONFIG);
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if ((m & RD_CONFIG_PWR_UP) == 0) return 0; // OFF
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if ((m & RD_CONFIG_PRIM_RX) == 0) return 0;
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return 1;
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}
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void NRF_SetChannel(uint8_t Ch)
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{
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NRF_WriteRegister(RG_RF_CH, Ch);
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}
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uint8_t NRF_ReceivePacket(uint8_t *Packet, uint8_t *PipeNum)
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{
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uint8_t pw = 0, status;
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// if (!NRF_IsRxPacket()) {
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// dbg("rx queue empty");
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// return 0;
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// }
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// const uint8_t orig_conf = NRF_ReadRegister(RG_CONFIG);
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// CE(0); // quit Rx mode - go idle
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CHIPSELECT {
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status = spi(CMD_RD_RX_PL_WIDTH);
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pw = spi(0);
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}
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if (pw == 0) {
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dbg("empty pld");
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}
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if (pw > 32) {
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CHIPSELECT {
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spi(CMD_FLUSH_RX);
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}
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pw = 0;
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dbg("over 32");
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} else {
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// Read the reception pipe number
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*PipeNum = ((status & RD_STATUS_RX_PNO) >> 1);
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CHIPSELECT {
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spi(CMD_RD_RX_PLD);
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for (uint8_t i = 0; i < pw; i++) Packet[i] = spi(0);
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}
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}
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NRF_WriteRegister(RG_STATUS, RD_STATUS_RX_DR); // Clear the RX_DR interrupt
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// if ((orig_conf & RD_CONFIG_PWR_UP) == 0) {
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// dbg_nrf("going back PwrDn");
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// NRF_PowerDown();
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// }
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// else if ((orig_conf & RD_CONFIG_PRIM_RX) == RD_CONFIG_PRIM_RX) {
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// dbg_nrf("going back PwrUp+Rx");
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// NRF_ModeRX();
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// }
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// CE(1); // back to rx
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return pw;
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}
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bool NRF_IsRxPacket(void)
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{
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return 0 == (NRF_ReadRegister(RG_FIFO_STATUS) & RD_FIFO_STATUS_RX_EMPTY);
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// uint8_t ret = NRF_ReadRegister(RG_STATUS) & RD_STATUS_RX_DR;
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// return 0 != ret;
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}
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bool NRF_SendPacket(uint8_t PipeNum, const uint8_t *Packet, uint8_t Length)
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{
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if (!nrf_pipe_enabled[PipeNum]) {
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dbg_nrf("!! Pipe %d not enabled", PipeNum);
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return 0;
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}
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dbg_nrf("Will tx to addr %02x", nrf_pipe_addr[PipeNum]);
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const uint8_t orig_conf = NRF_ReadRegister(RG_CONFIG);
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CE(0);
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NRF_ModeTX(); // Make sure in TX mode
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NRF_SetTxAddress(nrf_pipe_addr[PipeNum]); // this sets the Tx addr and also pipe 0 addr for ACK
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|
|
CHIPSELECT {
|
|
spi(CMD_FLUSH_TX);
|
|
};
|
|
|
|
CHIPSELECT {
|
|
spi(CMD_WR_TX_PLD);
|
|
for (uint8_t i = 0; i < Length; i++) spi(Packet[i]);
|
|
};
|
|
|
|
// CE pulse
|
|
CE(1);
|
|
_delay_us(20); // At least 10 us
|
|
CE(0);
|
|
|
|
uint8_t st = 0;
|
|
while ((st & (RD_STATUS_MAX_RT|RD_STATUS_TX_DS)) == 0) {
|
|
st = NRF_ReadStatus(); // Packet acked or timed out
|
|
}
|
|
|
|
dbg_nrf("Send status: 0x%02x - MAX_RT %d, SENT %d", (int)st,
|
|
(st&RD_STATUS_MAX_RT) != 0, (st&RD_STATUS_TX_DS) != 0);
|
|
|
|
NRF_WriteRegister(RG_STATUS, st & (RD_STATUS_MAX_RT|RD_STATUS_TX_DS)); // Clear the bit
|
|
|
|
if ((orig_conf & RD_CONFIG_PWR_UP) == 0) {
|
|
dbg_nrf("going back PwrDn");
|
|
NRF_PowerDown();
|
|
}
|
|
else if ((orig_conf & RD_CONFIG_PRIM_RX) == RD_CONFIG_PRIM_RX) {
|
|
dbg_nrf("going back PwrUp+Rx");
|
|
NRF_ModeRX();
|
|
}
|
|
|
|
return 0 != (st & RD_STATUS_TX_DS); // success
|
|
}
|
|
|
|
bool NRF_Init(uint8_t pSpeed)
|
|
{
|
|
// Set the required output pins
|
|
NSS(1);
|
|
CE(0);
|
|
|
|
LL_mDelay(200);
|
|
|
|
for (int i = 0; i < 6; i++) {
|
|
nrf_pipe_addr[i] = 0;
|
|
nrf_pipe_enabled[i] = 0;
|
|
}
|
|
|
|
// this is a test if there's anything present
|
|
uint8_t awreg = NRF_ReadRegister(RG_SETUP_AW);
|
|
if (awreg == 0 || awreg > 3) return false;
|
|
|
|
// clear flags etc
|
|
NRF_PowerDown();
|
|
CHIPSELECT { spi(CMD_FLUSH_RX); }
|
|
CHIPSELECT { spi(CMD_FLUSH_TX); }
|
|
NRF_WriteRegister(RG_STATUS, 0x70);
|
|
|
|
NRF_WriteRegister(RG_CONFIG, ModeBits);
|
|
NRF_WriteRegister(RG_SETUP_AW, 0b11); // 5 byte addresses
|
|
|
|
NRF_WriteRegister(RG_EN_RXADDR, 0x01); // disable all, enable pipe 0 - this is required for shockburst, despite not being specified in the DS
|
|
|
|
NRF_WriteRegister(RG_SETUP_RETR, 0x18); // 8 retries
|
|
NRF_WriteRegister(RG_RF_CH, 2); // channel 2 NO HIGHER THAN 83 in USA!
|
|
|
|
NRF_WriteRegister(RG_RF_SETUP, pSpeed);
|
|
|
|
NRF_WriteRegister(RG_DYNPD, 0b111111); // Dynamic packet length
|
|
NRF_WriteRegister(RG_FEATURE, 0b100); // Enable dynamic payload, and no payload in the ack.
|
|
|
|
// for (int i = 0; i < 6; i++) {
|
|
// NRF_WriteRegister(RG_RX_PW_P0+i, 32); // Receive 32 byte packets - XXX this is probably not needed with dynamic length
|
|
// }
|
|
|
|
return true;
|
|
}
|
|
|
|
#endif
|
|
|