12 Commits (a44eb5f16ae618fdc550d52a9a64f6072c424a14)

Author	SHA1	Message	Date
Ondřej Hruška	a44eb5f16a	doc for all units	6 years ago
Ondřej Hruška	4930f14047	made usart rxbuf large again	6 years ago
Ondřej Hruška	5edbf1306f	removed the DMA timeout message	6 years ago
Ondřej Hruška	8272a36aee	Implemented unit timed tick and uart rx timeout	6 years ago
Ondřej Hruška	b3d1f95e7d	cleanup and added sync + async commands	6 years ago
Ondřej Hruška	5d12b23ceb	deleted old sync sending code	6 years ago
Ondřej Hruška	b5d2930e30	uart tx now pretty reliable, but msg queue sometimes seemingly gets corrupted (checksum mismatch)	6 years ago
Ondřej Hruška	77f794e94a	some debuggiong. Tx is not reliable and sometimes duplicates or loses bytes	6 years ago
Ondřej Hruška	2881c2ff2a	almost finished DMA reception	6 years ago
Ondřej Hruška	e2e4d91cf3	Added func for simple periph clock toggling without the horrible if jungle	6 years ago
Ondřej Hruška	ace2bd6357	switch to freeRtos malloc + improve malloc_safe utils, fixed memleak	6 years ago
Ondřej Hruška	d49081b190	basic work on uart	6 years ago
Ondřej Hruška	8852f9f8b4	enable all periph clocks by default on startup, added testing synchronous uart write command	6 years ago
Ondřej Hruška	29264540f7	added uart init (untested) and more config option	6 years ago
Ondřej Hruška	e88bf84ea1	basic usart skeleton	6 years ago