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@ -5,18 +5,18 @@ |
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* @version V1.0.4 |
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* @date 29-April-2016 |
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* @brief RCC HAL module driver. |
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* This file provides firmware functions to manage the following
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* This file provides firmware functions to manage the following |
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* functionalities of the Reset and Clock Control (RCC) peripheral: |
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* + Initialization and de-initialization functions |
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* + Peripheral Control functions |
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*
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@verbatim
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* |
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@verbatim |
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============================================================================== |
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##### RCC specific features ##### |
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============================================================================== |
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[..]
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[..] |
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After reset the device is running from Internal High Speed oscillator |
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(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
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(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, |
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and all peripherals are off except internal SRAM, Flash and JTAG. |
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(+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; |
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all peripherals mapped on these buses are running at HSI speed. |
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@ -26,22 +26,22 @@ |
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[..] Once the device started from reset, the user application has to: |
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(+) Configure the clock source to be used to drive the System clock |
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(if the application needs higher frequency/performance) |
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(+) Configure the System clock frequency and Flash settings
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(+) Configure the System clock frequency and Flash settings |
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(+) Configure the AHB and APB buses prescalers |
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(+) Enable the clock for the peripheral(s) to be used |
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(+) Configure the clock source(s) for peripherals whose clocks are not |
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derived from the System clock (I2S, RTC, ADC, USB OTG FS)
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derived from the System clock (I2S, RTC, ADC, USB OTG FS) |
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##### RCC Limitations ##### |
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============================================================================== |
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[..]
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A delay between an RCC peripheral clock enable and the effective peripheral
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enabling should be taken into account in order to manage the peripheral read/write
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[..] |
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A delay between an RCC peripheral clock enable and the effective peripheral |
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enabling should be taken into account in order to manage the peripheral read/write |
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from/to registers. |
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(+) This delay depends on the peripheral mapping. |
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(++) AHB & APB peripherals, 1 dummy read is necessary |
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[..]
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[..] |
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Workarounds: |
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(#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
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inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. |
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@ -74,9 +74,9 @@ |
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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******************************************************************************
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****************************************************************************** |
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*/ |
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f1xx_hal.h" |
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@ -131,10 +131,10 @@ |
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* @{ |
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*/ |
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/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions |
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* |
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@verbatim
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@verbatim |
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=============================================================================== |
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##### Initialization and de-initialization functions ##### |
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=============================================================================== |
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@ -152,19 +152,19 @@ |
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(#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or |
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through the PLL as System clock source. Can be used also as RTC clock source. |
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(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
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(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. |
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(#) PLL (clocked by HSI or HSE), featuring different output clocks: |
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(++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx) |
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(++) The second output is used to generate the clock for the USB OTG FS (48 MHz) |
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(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() |
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and if a HSE clock failure occurs(HSE used directly or through PLL as System
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and if a HSE clock failure occurs(HSE used directly or through PLL as System |
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clock source), the System clocks automatically switched to HSI and an interrupt |
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is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
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(Non-Maskable Interrupt) exception vector.
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is generated if enabled. The interrupt is linked to the Cortex-M3 NMI |
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(Non-Maskable Interrupt) exception vector. |
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(#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
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(#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, |
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HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x |
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[..] System, AHB and APB buses clocks configuration |
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@ -179,19 +179,19 @@ |
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-@- All the peripheral clocks are derived from the System clock (SYSCLK) except: |
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(+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock |
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divided by 128.
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divided by 128. |
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(+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz |
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to work correctly. This clock is derived of the main PLL through PLL Multiplier. |
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(+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK |
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(+@) IWDG clock which is always the LSI clock. |
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(#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz. |
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For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
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For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz. |
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Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. |
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@endverbatim |
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* @{ |
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*/ |
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/*
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Additional consideration on the SYSCLK based on Latency settings: |
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+-----------------------------------------------+ |
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@ -225,16 +225,16 @@ void HAL_RCC_DeInit(void) |
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/* Reset HSEON, CSSON, & PLLON bits */ |
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CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); |
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/* Reset HSEBYP bit */ |
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CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
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/* Reset CFGR register */ |
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CLEAR_REG(RCC->CFGR); |
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/* Set HSITRIM bits to the reset value */ |
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MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM))); |
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#if (defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)) |
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/* Reset CFGR2 register */ |
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CLEAR_REG(RCC->CFGR2); |
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@ -265,19 +265,19 @@ void HAL_RCC_DeInit(void) |
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HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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uint32_t tickstart = 0; |
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/* Check the parameters */ |
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assert_param(RCC_OscInitStruct != NULL); |
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assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); |
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/*------------------------------- HSE Configuration ------------------------*/
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/*------------------------------- HSE Configuration ------------------------*/ |
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if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); |
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/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ |
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if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
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if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) |
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|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) |
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{ |
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if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) |
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@ -289,14 +289,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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/* Set the new HSE configuration ---------------------------------------*/ |
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__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); |
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/* Check the HSE State */ |
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if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) |
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{ |
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/* Get Start Tick */ |
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tickstart = HAL_GetTick(); |
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/* Wait till HSE is ready */ |
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
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{ |
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@ -310,7 +310,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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/* Get Start Tick */ |
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tickstart = HAL_GetTick(); |
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/* Wait till HSE is disabled */ |
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) |
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{ |
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@ -322,15 +322,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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} |
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} |
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} |
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/*----------------------------- HSI Configuration --------------------------*/
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/*----------------------------- HSI Configuration --------------------------*/ |
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if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); |
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assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); |
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/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
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if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
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/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ |
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if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) |
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|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) |
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{ |
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/* When HSI is used as system clock it will not disabled */ |
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@ -352,10 +352,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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/* Enable the Internal High Speed oscillator (HSI). */ |
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__HAL_RCC_HSI_ENABLE(); |
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/* Get Start Tick */ |
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tickstart = HAL_GetTick(); |
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/* Wait till HSI is ready */ |
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
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{ |
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@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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return HAL_TIMEOUT; |
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} |
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} |
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/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ |
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__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); |
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} |
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@ -372,10 +372,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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/* Disable the Internal High Speed oscillator (HSI). */ |
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__HAL_RCC_HSI_DISABLE(); |
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/* Get Start Tick */ |
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tickstart = HAL_GetTick(); |
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/* Wait till HSI is disabled */ |
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) |
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{ |
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@ -387,22 +387,22 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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} |
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} |
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} |
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/*------------------------------ LSI Configuration -------------------------*/
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/*------------------------------ LSI Configuration -------------------------*/ |
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if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) |
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{ |
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/* Check the parameters */ |
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assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); |
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/* Check the LSI State */ |
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if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) |
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{ |
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/* Enable the Internal Low Speed oscillator (LSI). */ |
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__HAL_RCC_LSI_ENABLE(); |
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/* Get Start Tick */ |
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tickstart = HAL_GetTick(); |
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/* Wait till LSI is ready */
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/* Wait till LSI is ready */ |
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) |
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{ |
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if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) |
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@ -410,7 +410,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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return HAL_TIMEOUT; |
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} |
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} |
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/* To have a fully stabilized clock in the specified range, a software delay of 1ms
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/* To have a fully stabilized clock in the specified range, a software delay of 1ms
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should be added.*/ |
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HAL_Delay(1); |
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} |
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@ -418,11 +418,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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/* Disable the Internal Low Speed oscillator (LSI). */ |
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__HAL_RCC_LSI_DISABLE(); |
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/* Get Start Tick */ |
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tickstart = HAL_GetTick(); |
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/* Wait till LSI is disabled */
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/* Wait till LSI is disabled */ |
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) |
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{ |
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if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) |
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@ -432,7 +432,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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} |
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} |
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} |
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/*------------------------------ LSE Configuration -------------------------*/
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/*------------------------------ LSE Configuration -------------------------*/ |
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if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) |
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{ |
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/* Check the parameters */ |
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@ -440,10 +440,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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/* Enable Power Clock*/ |
|
|
|
|
__HAL_RCC_PWR_CLK_ENABLE(); |
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|
/* Enable write access to Backup domain */ |
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|
SET_BIT(PWR->CR, PWR_CR_DBP); |
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|
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|
|
/* Wait for Backup domain Write protection disable */ |
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|
tickstart = HAL_GetTick(); |
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|
@ -462,8 +462,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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|
{ |
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|
/* Get Start Tick */ |
|
|
|
|
tickstart = HAL_GetTick(); |
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|
/* Wait till LSE is ready */
|
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|
/* Wait till LSE is ready */ |
|
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|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
|
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|
{ |
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|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
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|
@ -476,8 +476,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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|
/* Get Start Tick */ |
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|
tickstart = HAL_GetTick(); |
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|
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|
|
/* Wait till LSE is disabled */
|
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|
/* Wait till LSE is disabled */ |
|
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|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) |
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|
{ |
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|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
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|
@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State)); |
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|
|
if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE) |
|
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|
|
{ |
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|
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
|
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|
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
|
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|
clock (i.e. it is used as PLL clock entry that is used as system clock). */ |
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|
if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
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(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
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@ -517,13 +517,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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|
return HAL_ERROR; |
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|
} |
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|
/* Disable the main PLL2. */ |
|
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|
|
__HAL_RCC_PLL2_DISABLE(); |
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|
/* Get Start Tick */ |
|
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|
|
tickstart = HAL_GetTick(); |
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|
|
/* Wait till PLL2 is disabled */ |
|
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|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) |
|
|
|
|
{ |
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|
|
@ -532,19 +532,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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|
return HAL_TIMEOUT; |
|
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|
} |
|
|
|
|
} |
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|
|
/* Configure the HSE prediv2 factor --------------------------------*/ |
|
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|
|
__HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value); |
|
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|
|
|
/* Configure the main PLL2 multiplication factors. */ |
|
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|
|
__HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL); |
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|
|
/* Enable the main PLL2. */ |
|
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|
|
__HAL_RCC_PLL2_ENABLE(); |
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|
|
|
/* Get Start Tick */ |
|
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|
|
tickstart = HAL_GetTick(); |
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|
|
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|
|
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|
|
/* Wait till PLL2 is ready */ |
|
|
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) |
|
|
|
|
{ |
|
|
|
@ -561,11 +561,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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|
|
/* Disable the main PLL2. */ |
|
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|
|
__HAL_RCC_PLL2_DISABLE(); |
|
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|
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|
|
|
|
|
|
|
/* Get Start Tick */ |
|
|
|
|
tickstart = HAL_GetTick(); |
|
|
|
|
|
|
|
|
|
/* Wait till PLL2 is disabled */
|
|
|
|
|
|
|
|
|
|
/* Wait till PLL2 is disabled */ |
|
|
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) |
|
|
|
|
{ |
|
|
|
|
if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) |
|
|
|
@ -585,19 +585,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
|
|
|
|
{ |
|
|
|
|
/* Check if the PLL is used as system clock or not */ |
|
|
|
|
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) |
|
|
|
|
{
|
|
|
|
|
{ |
|
|
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) |
|
|
|
|
{ |
|
|
|
|
/* Check the parameters */ |
|
|
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); |
|
|
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); |
|
|
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|
|
|
|
|
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|
|
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|
|
/* Disable the main PLL. */ |
|
|
|
|
__HAL_RCC_PLL_DISABLE(); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Get Start Tick */ |
|
|
|
|
tickstart = HAL_GetTick(); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Wait till PLL is disabled */ |
|
|
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
|
|
|
|
{ |
|
|
|
@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
|
|
|
|
assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue)); |
|
|
|
|
#if defined(RCC_CFGR2_PREDIV1SRC) |
|
|
|
|
assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source)); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Set PREDIV1 source */ |
|
|
|
|
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); |
|
|
|
|
#endif /* RCC_CFGR2_PREDIV1SRC */ |
|
|
|
@ -629,10 +629,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
|
|
|
|
RCC_OscInitStruct->PLL.PLLMUL); |
|
|
|
|
/* Enable the main PLL. */ |
|
|
|
|
__HAL_RCC_PLL_ENABLE(); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Get Start Tick */ |
|
|
|
|
tickstart = HAL_GetTick(); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Wait till PLL is ready */ |
|
|
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
|
|
|
|
{ |
|
|
|
@ -646,11 +646,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
|
|
|
|
{ |
|
|
|
|
/* Disable the main PLL. */ |
|
|
|
|
__HAL_RCC_PLL_DISABLE(); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Get Start Tick */ |
|
|
|
|
tickstart = HAL_GetTick(); |
|
|
|
|
|
|
|
|
|
/* Wait till PLL is disabled */
|
|
|
|
|
|
|
|
|
|
/* Wait till PLL is disabled */ |
|
|
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
|
|
|
|
{ |
|
|
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
|
|
|
@ -665,29 +665,29 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
|
|
|
|
return HAL_ERROR; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
return HAL_OK; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Initializes the CPU, AHB and APB buses clocks according to the specified
|
|
|
|
|
* @brief Initializes the CPU, AHB and APB buses clocks according to the specified |
|
|
|
|
* parameters in the RCC_ClkInitStruct. |
|
|
|
|
* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that |
|
|
|
|
* contains the configuration information for the RCC peripheral. |
|
|
|
|
* @param FLatency FLASH Latency
|
|
|
|
|
* @param FLatency FLASH Latency |
|
|
|
|
* The value of this parameter depend on device used within the same series |
|
|
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
|
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
|
|
|
|
* and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function |
|
|
|
|
* |
|
|
|
|
* @note The HSI is used (enabled by hardware) as system clock source after |
|
|
|
|
* start-up from Reset, wake-up from STOP and STANDBY mode, or in case |
|
|
|
|
* of failure of the HSE used directly or indirectly as system clock |
|
|
|
|
* (if the Clock Security System CSS is enabled). |
|
|
|
|
*
|
|
|
|
|
* |
|
|
|
|
* @note A switch from one clock source to another occurs only if the target |
|
|
|
|
* clock source is ready (clock stable after start-up delay or PLL locked).
|
|
|
|
|
* clock source is ready (clock stable after start-up delay or PLL locked). |
|
|
|
|
* If a clock source which is not yet ready is selected, the switch will |
|
|
|
|
* occur when the clock source will be ready.
|
|
|
|
|
* occur when the clock source will be ready. |
|
|
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is |
|
|
|
|
* currently used as system clock source. |
|
|
|
|
* @retval HAL status |
|
|
|
@ -695,23 +695,23 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
|
|
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) |
|
|
|
|
{ |
|
|
|
|
uint32_t tickstart = 0; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Check the parameters */ |
|
|
|
|
assert_param(RCC_ClkInitStruct != NULL); |
|
|
|
|
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); |
|
|
|
|
assert_param(IS_FLASH_LATENCY(FLatency)); |
|
|
|
|
|
|
|
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
|
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
|
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
|
|
|
must be correctly programmed according to the frequency of the CPU clock |
|
|
|
|
(HCLK) of the device. */ |
|
|
|
|
|
|
|
|
|
#if defined(FLASH_ACR_LATENCY) |
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */ |
|
|
|
|
if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) |
|
|
|
|
{
|
|
|
|
|
{ |
|
|
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ |
|
|
|
|
__HAL_FLASH_SET_LATENCY(FLatency); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
|
|
|
memory by reading the FLASH_ACR register */ |
|
|
|
|
if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) |
|
|
|
@ -728,15 +728,15 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui |
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/ |
|
|
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) |
|
|
|
|
{
|
|
|
|
|
{ |
|
|
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* HSE is selected as System Clock Source */ |
|
|
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
|
|
|
|
{ |
|
|
|
|
/* Check the HSE ready flag */
|
|
|
|
|
/* Check the HSE ready flag */ |
|
|
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
|
|
|
|
{ |
|
|
|
|
return HAL_ERROR; |
|
|
|
@ -745,7 +745,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui |
|
|
|
|
/* PLL is selected as System Clock Source */ |
|
|
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
|
|
|
|
{ |
|
|
|
|
/* Check the PLL ready flag */
|
|
|
|
|
/* Check the PLL ready flag */ |
|
|
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
|
|
|
|
{ |
|
|
|
|
return HAL_ERROR; |
|
|
|
@ -754,7 +754,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui |
|
|
|
|
/* HSI is selected as System Clock Source */ |
|
|
|
|
else |
|
|
|
|
{ |
|
|
|
|
/* Check the HSI ready flag */
|
|
|
|
|
/* Check the HSI ready flag */ |
|
|
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
|
|
|
|
{ |
|
|
|
|
return HAL_ERROR; |
|
|
|
@ -764,7 +764,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui |
|
|
|
|
|
|
|
|
|
/* Get Start Tick */ |
|
|
|
|
tickstart = HAL_GetTick(); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
|
|
|
|
{ |
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) |
|
|
|
@ -794,44 +794,44 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui |
|
|
|
|
return HAL_TIMEOUT; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
#if defined(FLASH_ACR_LATENCY) |
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */ |
|
|
|
|
if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) |
|
|
|
|
{
|
|
|
|
|
{ |
|
|
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ |
|
|
|
|
__HAL_FLASH_SET_LATENCY(FLatency); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
|
|
|
memory by reading the FLASH_ACR register */ |
|
|
|
|
if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) |
|
|
|
|
{ |
|
|
|
|
return HAL_ERROR; |
|
|
|
|
} |
|
|
|
|
}
|
|
|
|
|
} |
|
|
|
|
#endif /* FLASH_ACR_LATENCY */ |
|
|
|
|
|
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/ |
|
|
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) |
|
|
|
|
{ |
|
|
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); |
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
|
|
|
|
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/ |
|
|
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) |
|
|
|
|
{ |
|
|
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); |
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Update the SystemCoreClock global variable */ |
|
|
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; |
|
|
|
|
|
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/ |
|
|
|
|
HAL_InitTick (TICK_INT_PRIORITY); |
|
|
|
|
|
|
|
|
|
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return HAL_OK; |
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} |
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@ -842,12 +842,12 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui |
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/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
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* @brief RCC clocks control functions |
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* |
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@verbatim
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@verbatim |
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=============================================================================== |
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##### Peripheral Control functions ##### |
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===============================================================================
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=============================================================================== |
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[..] |
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This subsection provides a set of functions allowing to control the RCC Clocks
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This subsection provides a set of functions allowing to control the RCC Clocks |
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frequencies. |
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@endverbatim |
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@ -893,7 +893,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M |
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assert_param(IS_RCC_MCO(RCC_MCOx)); |
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assert_param(IS_RCC_MCODIV(RCC_MCODiv)); |
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assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); |
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/* Configure the MCO1 pin in alternate function mode */ |
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gpio.Mode = GPIO_MODE_AF_PP; |
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gpio.Speed = GPIO_SPEED_FREQ_HIGH; |
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@ -902,9 +902,9 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M |
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/* MCO1 Clock Enable */ |
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MCO1_CLK_ENABLE(); |
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HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); |
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/* Configure the MCO clock source */ |
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__HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); |
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} |
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@ -914,8 +914,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M |
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* @note If a failure is detected on the HSE oscillator clock, this oscillator |
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* is automatically disabled and an interrupt is generated to inform the |
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* software about the failure (Clock Security System Interrupt, CSSI), |
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* allowing the MCU to perform rescue operations. The CSSI is linked to
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* the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
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* allowing the MCU to perform rescue operations. The CSSI is linked to |
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* the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. |
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* @retval None |
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*/ |
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void HAL_RCC_EnableCSS(void) |
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@ -933,9 +933,9 @@ void HAL_RCC_DisableCSS(void) |
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} |
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/**
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* @brief Returns the SYSCLK frequency
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* @note The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* @brief Returns the SYSCLK frequency |
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* @note The system frequency computed by this function is not the real |
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* frequency in the chip. It is calculated based on the predefined |
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* constant and the selected clock source: |
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* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) |
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* @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE |
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@ -949,16 +949,16 @@ void HAL_RCC_DisableCSS(void) |
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real |
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* frequency of the crystal used. Otherwise, this function may |
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* have wrong result. |
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*
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* |
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* @note The result of this function could be not correct when using fractional |
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* value for HSE crystal. |
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*
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* @note This function can be used by the user application to compute the
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* |
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* @note This function can be used by the user application to compute the |
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* baud-rate for the communication peripherals or configure other parameters. |
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*
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* |
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* @note Each time SYSCLK changes, this function must be called to update the |
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* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. |
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*
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* |
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* @retval SYSCLK frequency |
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*/ |
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uint32_t HAL_RCC_GetSysClockFreq(void) |
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@ -980,9 +980,9 @@ uint32_t HAL_RCC_GetSysClockFreq(void) |
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#if defined(RCC_CFGR2_PREDIV1SRC) |
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uint32_t prediv2 = 0, pll2mul = 0; |
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#endif /*RCC_CFGR2_PREDIV1SRC*/ |
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tmpreg = RCC->CFGR; |
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/* Get SYSCLK source -------------------------------------------------------*/ |
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switch (tmpreg & RCC_CFGR_SWS) |
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{ |
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@ -1016,7 +1016,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) |
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/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ |
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pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul); |
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} |
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/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ |
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/* In this case need to divide pllclk by 2 */ |
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if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)]) |
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@ -1047,11 +1047,11 @@ uint32_t HAL_RCC_GetSysClockFreq(void) |
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} |
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/**
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* @brief Returns the HCLK frequency
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* @brief Returns the HCLK frequency |
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* @note Each time HCLK changes, this function must be called to update the |
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* right HCLK value. Otherwise, any configuration based on this function will be incorrect. |
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*
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* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
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* |
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* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
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* and updated within this function |
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* @retval HCLK frequency |
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*/ |
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@ -1061,7 +1061,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) |
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} |
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/**
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* @brief Returns the PCLK1 frequency
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* @brief Returns the PCLK1 frequency |
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* @note Each time PCLK1 changes, this function must be called to update the |
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* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. |
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* @retval PCLK1 frequency |
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@ -1070,10 +1070,10 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) |
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{ |
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/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ |
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return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]); |
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}
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} |
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/**
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* @brief Returns the PCLK2 frequency
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* @brief Returns the PCLK2 frequency |
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* @note Each time PCLK2 changes, this function must be called to update the |
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* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. |
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* @retval PCLK2 frequency |
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@ -1082,12 +1082,12 @@ uint32_t HAL_RCC_GetPCLK2Freq(void) |
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{ |
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/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ |
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return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]); |
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}
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} |
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/**
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* @brief Configures the RCC_OscInitStruct according to the internal
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* @brief Configures the RCC_OscInitStruct according to the internal |
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* RCC configuration registers. |
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* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
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* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that |
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* will be configured. |
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* @retval None |
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*/ |
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@ -1129,9 +1129,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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RCC_OscInitStruct->HSIState = RCC_HSI_OFF; |
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} |
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RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); |
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/* Get the LSE configuration -----------------------------------------------*/ |
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if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) |
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{ |
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@ -1145,7 +1145,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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RCC_OscInitStruct->LSEState = RCC_LSE_OFF; |
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} |
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/* Get the LSI configuration -----------------------------------------------*/ |
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if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) |
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{ |
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@ -1155,7 +1155,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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{ |
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RCC_OscInitStruct->LSIState = RCC_LSI_OFF; |
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} |
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/* Get the PLL configuration -----------------------------------------------*/ |
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if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) |
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@ -1184,9 +1184,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
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} |
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/**
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* @brief Get the RCC_ClkInitStruct according to the internal
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* @brief Get the RCC_ClkInitStruct according to the internal |
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* RCC configuration registers. |
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* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
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* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that |
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* contains the current clock configuration. |
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* @param pFLatency Pointer on the Flash Latency. |
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* @retval None |
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@ -1199,25 +1199,25 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF |
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/* Set all possible values for the Clock type parameter --------------------*/ |
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RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |
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/* Get the SYSCLK configuration --------------------------------------------*/
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/* Get the SYSCLK configuration --------------------------------------------*/ |
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RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); |
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/* Get the HCLK configuration ----------------------------------------------*/
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RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
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/* Get the APB1 configuration ----------------------------------------------*/
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RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
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/* Get the APB2 configuration ----------------------------------------------*/
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/* Get the HCLK configuration ----------------------------------------------*/ |
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RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); |
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/* Get the APB1 configuration ----------------------------------------------*/ |
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RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); |
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/* Get the APB2 configuration ----------------------------------------------*/ |
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RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); |
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#if defined(FLASH_ACR_LATENCY) |
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/* Get the Flash Wait State (Latency) configuration ------------------------*/
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*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
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/* Get the Flash Wait State (Latency) configuration ------------------------*/ |
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*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); |
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#else |
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/* For VALUE lines devices, only LATENCY_0 can be set*/ |
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*pFLatency = (uint32_t)FLASH_LATENCY_0;
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*pFLatency = (uint32_t)FLASH_LATENCY_0; |
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#endif |
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} |
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@ -1233,7 +1233,7 @@ void HAL_RCC_NMI_IRQHandler(void) |
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{ |
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/* RCC Clock Security System interrupt user callback */ |
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HAL_RCC_CSSCallback(); |
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/* Clear RCC CSS pending bit */ |
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__HAL_RCC_CLEAR_IT(RCC_IT_CSS); |
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} |
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@ -1247,7 +1247,7 @@ __weak void HAL_RCC_CSSCallback(void) |
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{ |
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_RCC_CSSCallback could be implemented in the user file |
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*/
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*/ |
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} |
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/**
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