15 Commits (5edbf1306f32be1bee53a4da6d66a97975c4b62c)

Author	SHA1	Message	Date
Ondřej Hruška	5edbf1306f	removed the DMA timeout message	7 years ago
Ondřej Hruška	8272a36aee	Implemented unit timed tick and uart rx timeout	7 years ago
Ondřej Hruška	b3d1f95e7d	cleanup and added sync + async commands	7 years ago
Ondřej Hruška	5d12b23ceb	deleted old sync sending code	7 years ago
Ondřej Hruška	b5d2930e30	uart tx now pretty reliable, but msg queue sometimes seemingly gets corrupted (checksum mismatch)	7 years ago
Ondřej Hruška	2d53fc29be	removed the alignment crap, left one length field byte and wraparound markers. Works except one mysterious lock-up	7 years ago
Ondřej Hruška	08b4010b13	uhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh	7 years ago
Ondřej Hruška	77f794e94a	some debuggiong. Tx is not reliable and sometimes duplicates or loses bytes	7 years ago
Ondřej Hruška	2881c2ff2a	almost finished DMA reception	7 years ago
Ondřej Hruška	e2e4d91cf3	Added func for simple periph clock toggling without the horrible if jungle	7 years ago
Ondřej Hruška	ace2bd6357	switch to freeRtos malloc + improve malloc_safe utils, fixed memleak	7 years ago
Ondřej Hruška	d49081b190	basic work on uart	7 years ago
Ondřej Hruška	8852f9f8b4	enable all periph clocks by default on startup, added testing synchronous uart write command	7 years ago
Ondřej Hruška	29264540f7	added uart init (untested) and more config option	7 years ago
Ondřej Hruška	e88bf84ea1	basic usart skeleton	7 years ago