commit
766cfdba06
GPG Key ID:
2C5FD5035250423D
@ -0,0 +1,92 @@ |
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//
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// Created by MightyPork on 2018/01/06.
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//
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#ifndef GEX_F072_RSC_ENUM_H |
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#define GEX_F072_RSC_ENUM_H |
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// X macro: Resource name,
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#define XX_RESOURCES \ |
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X(SPI1) X(SPI2) X(SPI3) \
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X(I2C1) X(I2C2) X(I2C3) \
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X(ADC1) X(ADC2) X(ADC3) X(ADC4) \
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X(DAC1) X(DAC2) \
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X(USART1) X(USART2) X(USART3) X(USART4) X(USART5) X(USART6) \
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X(TIM1) X(TIM2) X(TIM3) X(TIM4) X(TIM5) \
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X(TIM6) X(TIM7) X(TIM8) X(TIM9) X(TIM10) X(TIM11) X(TIM12) X(TIM13) X(TIM14) \
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X(TIM15) X(TIM16) X(TIM17) \
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X(DMA1) X(DMA2) |
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// Resources not used anywhere:
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// X(I2S1) X(I2S2) X(I2S3)
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// X(OPAMP1) X(OPAMP2) X(OPAMP3) X(OPAMP4)
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// X(CAN1) X(CAN2)
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// X(TSC)
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// X(DCMI)
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// X(ETH)
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// X(FSMC)
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// X(SDIO)
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// X(RNG) X(LCD)
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// X(HDMI_CEC)
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// X(COMP1) X(COMP2) X(COMP3) X(COMP4) X(COMP5) X(COMP6) X(COMP7)
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#define XX_RESOURCES_GPIO \ |
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X(PA0) X(PA1) X(PA2) X(PA3) X(PA4) X(PA5) X(PA6) X(PA7) \
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X(PA8) X(PA9) X(PA10) X(PA11) X(PA12) X(PA13) X(PA14) X(PA15) \
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X(PB0) X(PB1) X(PB2) X(PB3) X(PB4) X(PB5) X(PB6) X(PB7) \
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X(PB8) X(PB9) X(PB10) X(PB11) X(PB12) X(PB13) X(PB14) X(PB15) \
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X(PC0) X(PC1) X(PC2) X(PC3) X(PC4) X(PC5) X(PC6) X(PC7) \
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X(PC8) X(PC9) X(PC10) X(PC11) X(PC12) X(PC13) X(PC14) X(PC15) \
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X(PD0) X(PD1) X(PD2) X(PD3) X(PD4) X(PD5) X(PD6) X(PD7) \
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X(PD8) X(PD9) X(PD10) X(PD11) X(PD12) X(PD13) X(PD14) X(PD15) \
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X(PE0) X(PE1) X(PE2) X(PE3) X(PE4) X(PE5) X(PE6) X(PE7) \
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X(PE8) X(PE9) X(PE10) X(PE11) X(PE12) X(PE13) X(PE14) X(PE15) \
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X(PF0) X(PF1) X(PF2) X(PF3) X(PF4) X(PF5) X(PF6) X(PF7) \
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X(PF8) X(PF9) X(PF10) X(PF11) X(PF12) X(PF13) X(PF14) X(PF15) \
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// GPIOs are allocated whenever the pin is needed
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// (e.g. when used for SPI, the R_SPI resource as well as the corresponding R_GPIO resources must be claimed)
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// Peripheral blocks (IPs) - not all chips have all blocks, usually the 1 and 2 are present as a minimum, if any.
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// It doesn't really make sense to expose multiple instances of buses that support addressing
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// ADCs - some more advanced chips support differential input mode on some (not all!) inputs
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// Usually only one or two instances are present
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// DAC - often only one is present, or none.
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// UARTs
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// - 1 and 2 are present universally, 2 is connected to VCOM on Nucleo/Discovery boards, good for debug messages
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// 4 and 5 don't support synchronous mode.
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// Timers
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// - some support quadrature input, probably all support external clock / gating / clock-out/PWM generation
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// Not all chips have all timers and not all timers are equal.
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// DMA - Direct memory access lines - TODO split those to channels, they can be used separately
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// The resource registry will be pre-loaded with platform-specific config of which blocks are available - the rest will be "pre-claimed"
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// (i.e. unavailable to functional modules)
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typedef enum hw_resource Resource; |
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enum hw_resource { |
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#define X(res_name) R_##res_name, |
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XX_RESOURCES |
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XX_RESOURCES_GPIO |
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#undef X |
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R_NONE, |
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RESOURCE_COUNT = R_NONE, |
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}; |
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#define RSCMAP_LEN ((RESOURCE_COUNT/8)+1) |
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typedef uint8_t ResourceMap[RSCMAP_LEN]; |
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#define RSC_IS_FREE(rscmap, rsc) (0 == (rscmap[((rsc)>>3)&0xFF] & (1<<((rsc)&0x7)))) |
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#define RSC_IS_HELD(rscmap, rsc) (!RSC_IS_FREE(rscmap, rsc)) |
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#define RSC_CLAIM(rscmap, rsc) do { rscmap[((rsc)>>3)&0xFF] |= (1<<((rsc)&0x7)); } while(0) |
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#define RSC_FREE(rscmap, rsc) do { rscmap[((rsc)>>3)&0xFF] &= ~(1<<((rsc)&0x7)); } while(0) |
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#endif //GEX_F072_RSC_ENUM_H
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@ -0,0 +1,529 @@ |
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//
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// Created by MightyPork on 2018/01/02.
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//
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#include <framework/system_settings.h> |
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#include <stm32f072xb.h> |
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#include "comm/messages.h" |
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#include "unit_base.h" |
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#include "utils/avrlibc.h" |
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#include "unit_spi.h" |
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// SPI master
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/** Private data structure */ |
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struct priv { |
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uint8_t periph_num; //!< 1 or 2
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uint8_t remap; //!< SPI remap option
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uint16_t prescaller; //!< Clock prescaller, stored as the dividing factor
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bool cpol; //!< CPOL setting
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bool cpha; //!< CPHA setting
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bool tx_only; //!< If true, Enable only the MOSI line
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bool lsb_first; //!< Option to send LSB first
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char ssn_port_name; //!< SSN port
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uint16_t ssn_pins; //!< SSN pin mask
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SPI_TypeDef *periph; |
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GPIO_TypeDef *ssn_port; |
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}; |
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// ------------------------------------------------------------------------
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/** Load from a binary buffer stored in Flash */ |
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static void USPI_loadBinary(Unit *unit, PayloadParser *pp) |
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{ |
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struct priv *priv = unit->data; |
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uint8_t version = pp_u8(pp); |
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(void)version; |
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priv->periph_num = pp_u8(pp); |
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priv->prescaller = pp_u16(pp); |
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priv->remap = pp_u8(pp); |
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priv->cpol = pp_bool(pp); |
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priv->cpha = pp_bool(pp); |
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priv->tx_only = pp_bool(pp); |
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priv->lsb_first = pp_bool(pp); |
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priv->ssn_port_name = pp_char(pp); |
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priv->ssn_pins = pp_u16(pp); |
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} |
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/** Write to a binary buffer for storing in Flash */ |
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static void USPI_writeBinary(Unit *unit, PayloadBuilder *pb) |
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{ |
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struct priv *priv = unit->data; |
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pb_u8(pb, 0); // version
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pb_u8(pb, priv->periph_num); |
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pb_u16(pb, priv->prescaller); |
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pb_u8(pb, priv->remap); |
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pb_bool(pb, priv->cpol); |
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pb_bool(pb, priv->cpha); |
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pb_bool(pb, priv->tx_only); |
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pb_bool(pb, priv->lsb_first); |
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pb_char(pb, priv->ssn_port_name); |
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pb_u16(pb, priv->ssn_pins); |
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} |
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// ------------------------------------------------------------------------
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/** Parse a key-value pair from the INI file */ |
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static error_t USPI_loadIni(Unit *unit, const char *key, const char *value) |
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{ |
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bool suc = true; |
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struct priv *priv = unit->data; |
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if (streq(key, "device")) { |
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priv->periph_num = (uint8_t) avr_atoi(value); |
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} |
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else if (streq(key, "remap")) { |
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priv->remap = (uint8_t) avr_atoi(value); |
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} |
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else if (streq(key, "prescaller")) { |
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priv->prescaller = (uint16_t ) avr_atoi(value); |
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} |
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else if (streq(key, "cpol")) { |
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priv->cpol = (bool) avr_atoi(value); |
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} |
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else if (streq(key, "cpha")) { |
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priv->cpha = (bool) avr_atoi(value); |
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} |
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else if (streq(key, "tx-only")) { |
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priv->tx_only = str_parse_yn(value, &suc); |
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} |
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else if (streq(key, "lsb-first")) { |
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priv->lsb_first = str_parse_yn(value, &suc); |
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} |
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else if (streq(key, "port")) { |
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suc = parse_port(value, &priv->ssn_port_name); |
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} |
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else if (streq(key, "pins")) { |
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priv->ssn_pins = parse_pinmask(value, &suc); |
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} |
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else { |
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return E_BAD_KEY; |
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} |
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if (!suc) return E_BAD_VALUE; |
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return E_SUCCESS; |
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} |
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/** Generate INI file section for the unit */ |
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static void USPI_writeIni(Unit *unit, IniWriter *iw) |
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{ |
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struct priv *priv = unit->data; |
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iw_comment(iw, "Peripheral number (SPIx)"); |
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iw_entry(iw, "device", "%d", (int)priv->periph_num); |
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// TODO show a legend for peripherals and remaps
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iw_comment(iw, "Pin mappings (SCK,MISO,MOSI)"); |
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#if GEX_PLAT_F072_DISCOVERY |
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iw_comment(iw, " SPI1: (0) A5,A6,A7 (1) B3,B4,B5 (2) E13,E14,E15"); |
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iw_comment(iw, " SPI2: (0) B13,B14,B15 (1) D1,D3,D4"); |
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#elif GEX_PLAT_F103_BLUEPILL |
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#error "NO IMPL" |
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#elif GEX_PLAT_F303_DISCOVERY |
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#error "NO IMPL" |
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#elif GEX_PLAT_F407_DISCOVERY |
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#error "NO IMPL" |
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#else |
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#error "BAD PLATFORM!" |
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#endif |
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iw_entry(iw, "remap", "%d", (int)priv->remap); |
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iw_cmt_newline(iw); |
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iw_comment(iw, "Prescaller: 2,4,8,...,256"); |
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iw_entry(iw, "prescaller", "%d", (int)priv->prescaller); |
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iw_comment(iw, "Clock polarity: 0,1 (clock idle level)"); |
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iw_entry(iw, "cpol", "%d", (int)priv->cpol); |
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iw_comment(iw, "Clock phase: 0,1 (active edge, 0-first, 1-second)"); |
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iw_entry(iw, "cpha", "%d", (int)priv->cpha); |
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iw_comment(iw, "Transmit only, disable MISO"); |
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iw_entry(iw, "tx-only", str_yn(priv->tx_only)); |
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iw_comment(iw, "Use LSB-first bit order"); |
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iw_entry(iw, "lsb-first", str_yn(priv->lsb_first)); |
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iw_cmt_newline(iw); |
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iw_comment(iw, "SS port name"); |
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iw_entry(iw, "port", "%c", priv->ssn_port_name); |
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iw_comment(iw, "SS pins (comma separated, supports ranges)"); |
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iw_entry(iw, "pins", "%s", str_pinmask(priv->ssn_pins, unit_tmp512)); |
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} |
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// ------------------------------------------------------------------------
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/** Allocate data structure and set defaults */ |
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static error_t USPI_preInit(Unit *unit) |
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{ |
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bool suc = true; |
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struct priv *priv = unit->data = calloc_ck(1, sizeof(struct priv), &suc); |
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if (!suc) return E_OUT_OF_MEM; |
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// some defaults
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priv->periph_num = 1; |
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priv->prescaller = 64; |
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priv->remap = 0; |
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priv->cpol = 0; |
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priv->cpha = 0; |
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priv->tx_only = false; |
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priv->lsb_first = false; |
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priv->ssn_port_name = 'A'; |
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priv->ssn_pins = 0x0001; |
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return E_SUCCESS; |
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} |
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/** Finalize unit set-up */ |
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static error_t USPI_init(Unit *unit) |
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{ |
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bool suc = true; |
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struct priv *priv = unit->data; |
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if (!(priv->periph_num >= 1 && priv->periph_num <= 2)) { |
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dbg("!! Bad SPI periph"); |
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// XXX some chips have also SPI3
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return E_BAD_CONFIG; |
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} |
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// assign and claim the peripheral
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if (priv->periph_num == 1) { |
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TRY(rsc_claim(unit, R_SPI1)); |
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priv->periph = SPI1; |
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} |
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else if (priv->periph_num == 2) { |
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TRY(rsc_claim(unit, R_SPI2)); |
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priv->periph = SPI2; |
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} |
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// This is written for F072, other platforms will need adjustments
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// Configure SPI own pins (AF)
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char spi_portname; |
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uint8_t pin_miso; |
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uint8_t pin_mosi; |
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uint8_t pin_sck; |
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uint32_t af_spi; |
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// TODO
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#if GEX_PLAT_F072_DISCOVERY |
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// SPI1 - many options
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// sck, miso, mosi, af
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if (priv->periph_num == 1) { |
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// SPI1
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if (priv->remap == 0) { |
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spi_portname = 'A'; |
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af_spi = LL_GPIO_AF_0; |
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pin_sck = 5; |
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pin_miso = 6; |
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pin_mosi = 7; |
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} |
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else if (priv->remap == 1) { |
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spi_portname = 'B'; |
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af_spi = LL_GPIO_AF_0; |
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pin_sck = 3; |
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pin_miso = 4; |
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pin_mosi = 5; |
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} |
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else if (priv->remap == 2) { |
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// large packages only
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spi_portname = 'E'; |
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af_spi = LL_GPIO_AF_1; |
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pin_sck = 13; |
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pin_miso = 14; |
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pin_mosi = 15; |
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} |
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else { |
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return E_BAD_CONFIG; |
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} |
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} |
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else { |
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// SPI2
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if (priv->remap == 0) { |
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spi_portname = 'B'; |
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af_spi = LL_GPIO_AF_0; |
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pin_sck = 13; |
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pin_miso = 14; |
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pin_mosi = 15; |
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} |
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else if (priv->remap == 1) { |
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// NOTE: the's also a incomplete remap in PB and PC
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spi_portname = 'D'; |
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af_spi = LL_GPIO_AF_0; |
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pin_sck = 1; |
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pin_miso = 3; |
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pin_mosi = 4; |
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} |
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else { |
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return E_BAD_CONFIG; |
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} |
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} |
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#elif GEX_PLAT_F103_BLUEPILL |
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#error "NO IMPL" |
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#elif GEX_PLAT_F303_DISCOVERY |
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#error "NO IMPL" |
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#elif GEX_PLAT_F407_DISCOVERY |
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#error "NO IMPL" |
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#else |
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#error "BAD PLATFORM!" |
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#endif |
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// first, we have to claim the pins
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TRY(rsc_claim_pin(unit, spi_portname, pin_mosi)); |
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TRY(rsc_claim_pin(unit, spi_portname, pin_miso)); |
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TRY(rsc_claim_pin(unit, spi_portname, pin_sck)); |
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configure_gpio_alternate(spi_portname, pin_mosi, af_spi); |
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configure_gpio_alternate(spi_portname, pin_miso, af_spi); |
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configure_gpio_alternate(spi_portname, pin_sck, af_spi); |
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if (priv->periph_num == 1) { |
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__HAL_RCC_SPI1_CLK_ENABLE(); |
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} else { |
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__HAL_RCC_SPI2_CLK_ENABLE(); |
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} |
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// configure SSN GPIOs
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{ |
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// Claim all needed pins
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TRY(rsc_claim_gpios(unit, priv->ssn_port_name, priv->ssn_pins)); |
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TRY(configure_sparse_pins(priv->ssn_port_name, priv->ssn_pins, &priv->ssn_port, |
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LL_GPIO_MODE_OUTPUT, LL_GPIO_OUTPUT_PUSHPULL)); |
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// Set the initial state - all high
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priv->ssn_port->BSRR = priv->ssn_pins; |
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} |
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// Configure SPI - must be configured under reset
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LL_SPI_Disable(priv->periph); |
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{ |
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uint32_t presc = priv->prescaller; |
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uint32_t lz = __CLZ(presc); |
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if (lz < 23) lz = 23; |
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if (lz > 30) lz = 30; |
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presc = (32 - lz - 2); |
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LL_SPI_SetBaudRatePrescaler(priv->periph, (presc<<SPI_CR1_BR_Pos)&SPI_CR1_BR_Msk); |
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LL_SPI_SetClockPolarity(priv->periph, priv->cpol ? LL_SPI_POLARITY_HIGH : LL_SPI_POLARITY_LOW); |
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LL_SPI_SetClockPhase(priv->periph, priv->cpha ? LL_SPI_PHASE_1EDGE : LL_SPI_PHASE_2EDGE); |
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LL_SPI_SetTransferDirection(priv->periph, priv->tx_only ? LL_SPI_HALF_DUPLEX_TX : LL_SPI_FULL_DUPLEX); |
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LL_SPI_SetTransferBitOrder(priv->periph, priv->lsb_first ? LL_SPI_LSB_FIRST : LL_SPI_MSB_FIRST); |
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LL_SPI_SetNSSMode(priv->periph, LL_SPI_NSS_SOFT); |
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LL_SPI_SetDataWidth(priv->periph, LL_SPI_DATAWIDTH_8BIT); |
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LL_SPI_SetRxFIFOThreshold(priv->periph, LL_SPI_RX_FIFO_TH_QUARTER); // trigger RXNE on 1 byte
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LL_SPI_SetMode(priv->periph, LL_SPI_MODE_MASTER); |
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} |
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LL_SPI_Enable(priv->periph); |
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return E_SUCCESS; |
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} |
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/** Tear down the unit */ |
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static void USPI_deInit(Unit *unit) |
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{ |
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struct priv *priv = unit->data; |
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// de-init the pins & peripheral only if inited correctly
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if (unit->status == E_SUCCESS) { |
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assert_param(priv->periph); |
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LL_SPI_DeInit(priv->periph); |
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if (priv->periph_num == 1) { |
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__HAL_RCC_SPI1_CLK_DISABLE(); |
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} else { |
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__HAL_RCC_SPI2_CLK_DISABLE(); |
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} |
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} |
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// Release all resources
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rsc_teardown(unit); |
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// Free memory
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free(unit->data); |
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unit->data = NULL; |
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} |
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// ------------------------------------------------------------------------
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static error_t spi_wait_until_flag(struct priv *priv, uint32_t flag, bool stop_state) |
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{ |
||||
uint32_t t_start = HAL_GetTick(); |
||||
while (((priv->periph->SR & flag) != 0) != stop_state) { |
||||
if (HAL_GetTick() - t_start > 10) { |
||||
return E_HW_TIMEOUT; |
||||
} |
||||
} |
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
/**
|
||||
* Perform a low level SPI transfer |
||||
* |
||||
* @param priv - private object of the SPI unit |
||||
* @param request - request buffer |
||||
* @param response - response buffer |
||||
* @param req_len - request len |
||||
* @param resp_skip - response skip bytes |
||||
* @param resp_len - response len |
||||
* @return success |
||||
*/ |
||||
static error_t xfer_do(struct priv *priv, const uint8_t *request, |
||||
uint8_t *response, |
||||
uint32_t req_len, |
||||
uint32_t resp_skip, |
||||
uint32_t resp_len) |
||||
{ |
||||
// TODO this is slow, use DMA
|
||||
|
||||
if (response == NULL) resp_len = 0; |
||||
|
||||
// avoid skip causing stretch beyond tx window if nothing is to be read back
|
||||
if (resp_len == 0) resp_skip = 0; |
||||
|
||||
// in tx only mode, return zeros
|
||||
if (priv->tx_only && resp_len>0) { |
||||
memset(response, 0, resp_len); |
||||
} |
||||
|
||||
uint8_t tb; |
||||
uint32_t end = MAX(req_len, resp_len + resp_skip); |
||||
for (uint32_t i = 0; i < end; i++) { |
||||
if (i < req_len) tb = *request++; |
||||
else tb = 0; |
||||
|
||||
TRY(spi_wait_until_flag(priv, SPI_SR_TXE, true)); |
||||
LL_SPI_TransmitData8(priv->periph, tb); |
||||
|
||||
if (!priv->tx_only) { |
||||
TRY(spi_wait_until_flag(priv, SPI_SR_RXNE, true)); |
||||
uint8_t rb = LL_SPI_ReceiveData8(priv->periph); |
||||
|
||||
if (resp_skip > 0) resp_skip--; |
||||
else if (resp_len > 0) { |
||||
resp_len--; |
||||
*response++ = rb; |
||||
} |
||||
} |
||||
} |
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
error_t UU_SPI_Multicast(Unit *unit, uint16_t slaves, |
||||
const uint8_t *request, uint32_t req_len) |
||||
{ |
||||
struct priv *priv= unit->data; |
||||
uint16_t mask = port_spread(slaves, priv->ssn_pins); |
||||
priv->ssn_port->BRR = mask; |
||||
{ |
||||
TRY(xfer_do(priv, request, NULL, req_len, 0, 0)); |
||||
} |
||||
priv->ssn_port->BSRR = mask; |
||||
|
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
error_t UU_SPI_Write(Unit *unit, uint8_t slave_num, |
||||
const uint8_t *request, uint8_t *response, |
||||
uint32_t req_len, uint32_t resp_skip, uint32_t resp_len) |
||||
{ |
||||
struct priv *priv= unit->data; |
||||
|
||||
uint16_t mask = port_spread((uint16_t) (1 << slave_num), priv->ssn_pins); |
||||
priv->ssn_port->BRR = mask; |
||||
{ |
||||
TRY(xfer_do(priv, request, response, req_len, resp_len, resp_skip)); |
||||
} |
||||
priv->ssn_port->BSRR = mask; |
||||
|
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
|
||||
enum PinCmd_ { |
||||
CMD_QUERY = 0, |
||||
CMD_MULTICAST = 1, |
||||
}; |
||||
|
||||
/** Handle a request message */ |
||||
static error_t USPI_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, PayloadParser *pp) |
||||
{ |
||||
uint8_t slave; |
||||
uint16_t slaves; |
||||
uint16_t req_len; |
||||
uint16_t resp_skip; |
||||
uint16_t resp_len; |
||||
const uint8_t *bb; |
||||
|
||||
uint32_t len; |
||||
|
||||
switch (command) { |
||||
/** Write and read byte(s) - slave_num:u8, req_len:u16, resp_skip:u16, resp_len:u16, byte(s) */ |
||||
case CMD_QUERY: |
||||
slave = pp_u8(pp); |
||||
resp_skip = pp_u16(pp); |
||||
resp_len = pp_u16(pp); |
||||
|
||||
bb = pp_tail(pp, &len); |
||||
|
||||
TRY(UU_SPI_Write(unit, slave, |
||||
bb, (uint8_t *) unit_tmp512, |
||||
len, resp_skip, resp_len)); |
||||
|
||||
// no response if we aren't reading
|
||||
if (resp_len > 0) { |
||||
com_respond_buf(frame_id, MSG_SUCCESS, (uint8_t *) unit_tmp512, resp_len); |
||||
} |
||||
return E_SUCCESS; |
||||
|
||||
/** Write byte(s) to multiple slaves - slaves:u16, req_len:u16, byte(s) */ |
||||
case CMD_MULTICAST: |
||||
slaves = pp_u16(pp); |
||||
|
||||
bb = pp_tail(pp, &len); |
||||
|
||||
TRY(UU_SPI_Multicast(unit, slaves, bb, len)); |
||||
return E_SUCCESS; |
||||
|
||||
default: |
||||
return E_UNKNOWN_COMMAND; |
||||
} |
||||
} |
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
/** Unit template */ |
||||
const UnitDriver UNIT_SPI = { |
||||
.name = "SPI", |
||||
.description = "SPI master", |
||||
// Settings
|
||||
.preInit = USPI_preInit, |
||||
.cfgLoadBinary = USPI_loadBinary, |
||||
.cfgWriteBinary = USPI_writeBinary, |
||||
.cfgLoadIni = USPI_loadIni, |
||||
.cfgWriteIni = USPI_writeIni, |
||||
// Init
|
||||
.init = USPI_init, |
||||
.deInit = USPI_deInit, |
||||
// Function
|
||||
.handleRequest = USPI_handleRequest, |
||||
}; |
||||
@ -0,0 +1,63 @@ |
||||
//
|
||||
// Created by MightyPork on 2018/01/02.
|
||||
//
|
||||
|
||||
#ifndef GEX_F072_UNIT_SPI_H |
||||
#define GEX_F072_UNIT_SPI_H |
||||
|
||||
#include "unit.h" |
||||
|
||||
extern const UnitDriver UNIT_SPI; |
||||
|
||||
// Unit-to-Unit API
|
||||
|
||||
/**
|
||||
* Raw read/write via SPI. |
||||
* It's possible to simultaneously write and read, or skip bytes in either direction. |
||||
* |
||||
* Example scenarios: |
||||
* |
||||
* req 2, skip 2, read 3 |
||||
* |<-- req_len --->| |
||||
* [ write ][ write ] . . . . . . . . |
||||
* . . . . . . . . . [ read ][ read ][ read ] |
||||
* |<-- resp_skip ->|<------ resp_len ----->| |
||||
* |
||||
* req 2, skip 0, read 2 |
||||
* |<-- req_len --->| |
||||
* [ write ][ write ] |
||||
* [ read ][ read ] |
||||
* |<-- resp_len -->| |
||||
* |
||||
* @param unit - SPI unit |
||||
* @param slave_num - slave number (SS pin index, counted from least significant bit) |
||||
* @param request - request bytes buffer |
||||
* @param response - response bytes buffer |
||||
* @param req_len - number of bytes in the request. Will be right-padded with zeros. |
||||
* @param resp_skip - response bytes to discard before starting to capture them |
||||
* @param resp_len - number of bytes to capture, after discarding resp_skip received bytes |
||||
* @return success |
||||
*/ |
||||
error_t UU_SPI_Write(Unit *unit, uint8_t slave_num, |
||||
const uint8_t *request, |
||||
uint8_t *response, |
||||
uint32_t req_len, |
||||
uint32_t resp_skip, |
||||
uint32_t resp_len); |
||||
|
||||
/**
|
||||
* Write to multiple slaves at once. |
||||
* This is similar to UU_SPI_Write, but performs no read and works only if the device |
||||
* is configured as tx-only. |
||||
* |
||||
* @param unit - SPI unit |
||||
* @param slaves - bitmap of slaves to write (packed bits representing the SSN pins) |
||||
* @param request - request bytes buffer |
||||
* @param req_len - length of the request buffer |
||||
* @return success |
||||
*/ |
||||
error_t UU_SPI_Multicast(Unit *unit, uint16_t slaves, |
||||
const uint8_t *request, |
||||
uint32_t req_len); |
||||
|
||||
#endif //GEX_F072_UNIT_SPI_H
|
||||
Loading…
Reference in new issue