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@ -133,6 +133,12 @@ static uint8_t spi(uint8_t tx) { |
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#define RD_CONFIG_DISABLE_IRQ_TX_DS 0x20 |
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#define RD_CONFIG_DISABLE_IRQ_TX_DS 0x20 |
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#define RD_CONFIG_DISABLE_IRQ_RX_DR 0x40 |
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#define RD_CONFIG_DISABLE_IRQ_RX_DR 0x40 |
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#define RD_FIFO_STATUS_RX_EMPTY 0x01 |
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#define RD_FIFO_STATUS_RX_FULL 0x02 |
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#define RD_FIFO_STATUS_TX_EMPTY 0x10 |
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#define RD_FIFO_STATUS_TX_FULL 0x20 |
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#define RD_FIFO_STATUS_TX_REUSE 0x40 |
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// Config register bits (excluding the bottom two that are changed dynamically)
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// Config register bits (excluding the bottom two that are changed dynamically)
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// enable only Rx IRQ
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// enable only Rx IRQ
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#define ModeBits (RD_CONFIG_DISABLE_IRQ_MAX_RT | \ |
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#define ModeBits (RD_CONFIG_DISABLE_IRQ_MAX_RT | \ |
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@ -384,21 +390,29 @@ void NRF_SetChannel(uint8_t Ch) |
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uint8_t NRF_ReceivePacket(uint8_t *Packet, uint8_t *PipeNum) |
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uint8_t NRF_ReceivePacket(uint8_t *Packet, uint8_t *PipeNum) |
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{ |
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{ |
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uint8_t pw = 0, status; |
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uint8_t pw = 0, status; |
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if (!NRF_IsRxPacket()) return 0; |
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// if (!NRF_IsRxPacket()) {
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// dbg("rx queue empty");
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// return 0;
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// }
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const uint8_t orig_conf = NRF_ReadRegister(RG_CONFIG); |
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// const uint8_t orig_conf = NRF_ReadRegister(RG_CONFIG);
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CE(0); // quit Rx mode - go idle
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// CE(0); // quit Rx mode - go idle
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CHIPSELECT { |
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CHIPSELECT { |
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status = spi(CMD_RD_RX_PL_WIDTH); |
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status = spi(CMD_RD_RX_PL_WIDTH); |
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pw = spi(0); |
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pw = spi(0); |
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} |
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} |
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if (pw == 0) { |
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dbg("empty pld"); |
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} |
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if (pw > 32) { |
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if (pw > 32) { |
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CHIPSELECT { |
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CHIPSELECT { |
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spi(CMD_FLUSH_RX); |
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spi(CMD_FLUSH_RX); |
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} |
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} |
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pw = 0; |
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pw = 0; |
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dbg("over 32"); |
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} else { |
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} else { |
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// Read the reception pipe number
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// Read the reception pipe number
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*PipeNum = ((status & RD_STATUS_RX_PNO) >> 1); |
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*PipeNum = ((status & RD_STATUS_RX_PNO) >> 1); |
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@ -409,21 +423,23 @@ uint8_t NRF_ReceivePacket(uint8_t *Packet, uint8_t *PipeNum) |
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} |
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} |
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NRF_WriteRegister(RG_STATUS, RD_STATUS_RX_DR); // Clear the RX_DR interrupt
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NRF_WriteRegister(RG_STATUS, RD_STATUS_RX_DR); // Clear the RX_DR interrupt
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if ((orig_conf & RD_CONFIG_PWR_UP) == 0) { |
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// if ((orig_conf & RD_CONFIG_PWR_UP) == 0) {
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dbg_nrf("going back PwrDn"); |
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// dbg_nrf("going back PwrDn");
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NRF_PowerDown(); |
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// NRF_PowerDown();
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} |
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// }
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else if ((orig_conf & RD_CONFIG_PRIM_RX) == RD_CONFIG_PRIM_RX) { |
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// else if ((orig_conf & RD_CONFIG_PRIM_RX) == RD_CONFIG_PRIM_RX) {
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dbg_nrf("going back PwrUp+Rx"); |
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// dbg_nrf("going back PwrUp+Rx");
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NRF_ModeRX(); |
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// NRF_ModeRX();
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} |
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// }
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// CE(1); // back to rx
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return pw; |
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return pw; |
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} |
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} |
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bool NRF_IsRxPacket(void) |
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bool NRF_IsRxPacket(void) |
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{ |
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{ |
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uint8_t ret = NRF_ReadRegister(RG_STATUS) & RD_STATUS_RX_DR; |
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return 0 == (NRF_ReadRegister(RG_FIFO_STATUS) & RD_FIFO_STATUS_RX_EMPTY); |
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return 0 != ret; |
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// uint8_t ret = NRF_ReadRegister(RG_STATUS) & RD_STATUS_RX_DR;
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// return 0 != ret;
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} |
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} |
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bool NRF_SendPacket(uint8_t PipeNum, const uint8_t *Packet, uint8_t Length) |
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bool NRF_SendPacket(uint8_t PipeNum, const uint8_t *Packet, uint8_t Length) |
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