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stm32l100-asm-bootstrap
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Started moving stuff from INI_REGS to separate periph files. Cleaning.

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master
Ondřej Hruška 9 years ago
parent 2ba25d0f98
commit 0812f21fae
10 changed files with 745 additions and 669 deletions
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  1. 6
      .cproject
  2. 103
      lib/INI_BASE.s
  3. 240
      lib/INI_BITS_GPIO.s
  4. 142
      lib/INI_BITS_SCB.s
  5. 38
      lib/INI_BITS_SYSTICK.s
  6. 372
      lib/INI_GPIO.s
  7. 225
      lib/INI_REGS.s
  8. 199
      lib/INI_SCB.s
  9. 61
      lib/INI_SYSTICK.s
  10. 12
      main.asm

6
.cproject
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@ -13,7 +13,7 @@
<folderInfo id="0.1395987404." name="/" resourcePath="">
<toolChain errorParsers="" id="org.eclipse.cdt.build.core.prefbase.toolchain.201835191" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.201835191.1247016447" name=""/>
<builder autoBuildTarget="asm,s" cleanBuildTarget="clean" enableAutoBuild="true" enableCleanBuild="true" enabledIncrementalBuild="true" errorParsers="" id="org.eclipse.cdt.build.core.settings.default.builder.2008815367" incrementalBuildTarget="link" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="false" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
<builder autoBuildTarget="asm,s" cleanBuildTarget="clean" enableAutoBuild="true" enableCleanBuild="true" enabledIncrementalBuild="true" errorParsers="" id="org.eclipse.cdt.build.core.settings.default.builder.2008815367" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="false" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
<tool errorParsers="" id="org.eclipse.cdt.build.core.settings.holder.libs.1471334506" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
<tool errorParsers="" id="org.eclipse.cdt.build.core.settings.holder.917796934" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1343808760" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
@ -42,7 +42,9 @@
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Default"/>
<configuration configurationName="Default">
<resource resourceType="PROJECT" workspacePath="/STM32L100-asm-bootstrap"/>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>

103
lib/INI_BASE.s
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;********************************************************************************
; SOUBOR : INI_BASE.S
; AUTOR : Ondrej Hruska
; DATUM : 10/2015
; POPIS : Zakladni soubor knihovny. Musi byt includovat pred vsemi ostatnimi.
; Soubor definuje rozdeleni adresniho prostoru a adresy periferii.
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
FLASH_BASE EQU 0x08000000 ; FLASH base address in the alias region
SRAM_BASE EQU 0x20000000 ; SRAM base address in the alias region
PERIPH_BASE EQU 0x40000000 ; Peripheral base address in the alias region
SRAM_BB_BASE EQU (SRAM_BASE + 0x02000000) ; SRAM base address in the bit-band region
PERIPH_BB_BASE EQU (PERIPH_BASE + 0x02000000) ; Peripheral base address in the bit-band region
; ------------------------- System Config Blocks -----------------------------
_SCS_BASE EQU 0xE000E000 ; System Control Space base
_SCB EQU (_SCS_BASE + 0x0D00) ; System Control Block base
_NVIC EQU (_SCS_BASE + 0x0100) ; Nested Interrupt Vector Controller base
_OB EQU 0x1FF80000 ; FLASH Option Bytes base address
_AES EQU 0x50060000 ; Encryption module
_FSMC EQU 0xA0000000 ; External Memory Control base
_DBGMCU EQU 0xE0042000 ; Debug MCU registers base address
; ----------------------------- Peripherals ----------------------------------
; *** Peripheral bus bases ***
_APB1 EQU PERIPH_BASE ; Advanced Peripheral Bus 1 base
_APB2 EQU (PERIPH_BASE + 0x10000) ; Advanced Peripheral Bus 2 base
_AHB EQU (PERIPH_BASE + 0x20000) ; Advanced High-speed Bus base
; *** Peripheral Bus 1 devices ***
_TIM2 EQU (_APB1 + 0x0000) ; Timer bases
_TIM3 EQU (_APB1 + 0x0400)
_TIM4 EQU (_APB1 + 0x0800)
_TIM5 EQU (_APB1 + 0x0C00)
_TIM6 EQU (_APB1 + 0x1000)
_TIM7 EQU (_APB1 + 0x1400)
_LCD EQU (_APB1 + 0x2400) ; LCD controller base
_RTC EQU (_APB1 + 0x2800) ; RTC base
_WWDG EQU (_APB1 + 0x2C00) ; Window Watchdog base
_IWDG EQU (_APB1 + 0x3000) ; Independent Watchdog base
_SPI2 EQU (_APB1 + 0x3800) ; SPI base
_SPI3 EQU (_APB1 + 0x3C00)
_USART2 EQU (_APB1 + 0x4400) ; USART base
_USART3 EQU (_APB1 + 0x4800)
_UART4 EQU (_APB1 + 0x4C00) ; UART base (?)
_UART5 EQU (_APB1 + 0x5000)
_I2C1 EQU (_APB1 + 0x5400) ; I2C base
_I2C2 EQU (_APB1 + 0x5800)
_PWR EQU (_APB1 + 0x7000) ; Power Control block base
_DAC EQU (_APB1 + 0x7400) ; D/A config base
_COMP EQU (_APB1 + 0x7C00) ; Analog Comparator base
_RI EQU (_APB1 + 0x7C04) ; Routing Interface base (analog pin connections)
_OPAMP EQU (_APB1 + 0x7C5C) ; OpAmp config base
; *** Peripheral Bus 2 devices ***
_TIM9 EQU (_APB2 + 0x0800) ; Timer base
_TIM10 EQU (_APB2 + 0x0C00)
_TIM11 EQU (_APB2 + 0x1000)
_SYSCFG EQU (_APB2 + 0x0000) ; System config block base
_EXTI EQU (_APB2 + 0x0400) ; External interrupt settings base
_ADC1 EQU (_APB2 + 0x2400) ; A/D 1
_ADCC EQU (_APB2 + 0x2700) ; common A/D registers base
_SDIO EQU (_APB2 + 0x2C00) ; SD host
_SPI1 EQU (_APB2 + 0x3000) ; SPI
_USART1 EQU (_APB2 + 0x3800)
; *** High Speed Bus devices ***
_GPIO EQU (_AHB + 0x0000) ; GPIO block base
_CRC EQU (_AHB + 0x3000) ; CRC module base
_RCC EQU (_AHB + 0x3800) ; Reset and Clock Config base
_DMA1 EQU (_AHB + 0x6000) ; DMA control base
_DMA2 EQU (_AHB + 0x6400)
_FLASH EQU (_AHB + 0x3C00) ; FLASH control base
END

240
lib/INI_BITS_GPIO.s
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;********************************************************************************
; SOUBOR : INI_BITS_GPIO.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro GPIO (I/O brany)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; General Purpose IOs (GPIO)
;
;****************************************************************************
; Short pin masks. Valid for OTYPER, IDR and ODR.
GPIO0 EQU 0x00000001
GPIO1 EQU 0x00000002
GPIO2 EQU 0x00000004
GPIO3 EQU 0x00000008
GPIO4 EQU 0x00000010
GPIO5 EQU 0x00000020
GPIO6 EQU 0x00000040
GPIO7 EQU 0x00000080
GPIO8 EQU 0x00000100
GPIO9 EQU 0x00000200
GPIO10 EQU 0x00000400
GPIO11 EQU 0x00000800
GPIO12 EQU 0x00001000
GPIO13 EQU 0x00002000
GPIO14 EQU 0x00004000
GPIO15 EQU 0x00008000
; OTYPER pattern masks - use as (GPIO_OTYPER_6 & GPIO_OTYPER_OD)
GPIO_OTYPER_PP EQU 0x00000000
GPIO_OTYPER_OD EQU 0xFFFFFFFF
; For completenes, aliases also for OTYPER, ODR and IDR
GPIO_OTYPER_0 EQU 0x00000001
GPIO_OTYPER_1 EQU 0x00000002
GPIO_OTYPER_2 EQU 0x00000004
GPIO_OTYPER_3 EQU 0x00000008
GPIO_OTYPER_4 EQU 0x00000010
GPIO_OTYPER_5 EQU 0x00000020
GPIO_OTYPER_6 EQU 0x00000040
GPIO_OTYPER_7 EQU 0x00000080
GPIO_OTYPER_8 EQU 0x00000100
GPIO_OTYPER_9 EQU 0x00000200
GPIO_OTYPER_10 EQU 0x00000400
GPIO_OTYPER_11 EQU 0x00000800
GPIO_OTYPER_12 EQU 0x00001000
GPIO_OTYPER_13 EQU 0x00002000
GPIO_OTYPER_14 EQU 0x00004000
GPIO_OTYPER_15 EQU 0x00008000
GPIO_ODR_0 EQU 0x00000001
GPIO_ODR_1 EQU 0x00000002
GPIO_ODR_2 EQU 0x00000004
GPIO_ODR_3 EQU 0x00000008
GPIO_ODR_4 EQU 0x00000010
GPIO_ODR_5 EQU 0x00000020
GPIO_ODR_6 EQU 0x00000040
GPIO_ODR_7 EQU 0x00000080
GPIO_ODR_8 EQU 0x00000100
GPIO_ODR_9 EQU 0x00000200
GPIO_ODR_10 EQU 0x00000400
GPIO_ODR_11 EQU 0x00000800
GPIO_ODR_12 EQU 0x00001000
GPIO_ODR_13 EQU 0x00002000
GPIO_ODR_14 EQU 0x00004000
GPIO_ODR_15 EQU 0x00008000
GPIO_IDR_0 EQU 0x00000001
GPIO_IDR_1 EQU 0x00000002
GPIO_IDR_2 EQU 0x00000004
GPIO_IDR_3 EQU 0x00000008
GPIO_IDR_4 EQU 0x00000010
GPIO_IDR_5 EQU 0x00000020
GPIO_IDR_6 EQU 0x00000040
GPIO_IDR_7 EQU 0x00000080
GPIO_IDR_8 EQU 0x00000100
GPIO_IDR_9 EQU 0x00000200
GPIO_IDR_10 EQU 0x00000400
GPIO_IDR_11 EQU 0x00000800
GPIO_IDR_12 EQU 0x00001000
GPIO_IDR_13 EQU 0x00002000
GPIO_IDR_14 EQU 0x00004000
GPIO_IDR_15 EQU 0x00008000
;****************** Bit definition for GPIO_MODER register ****************
; pattern masks. Use as: (GPIO_MODER_0 & GPIO_MODER_OUTPUT)
GPIO_MODER_INPUT EQU 0x00000000
GPIO_MODER_OUTPUT EQU 0x55555555
GPIO_MODER_AF EQU 0xAAAAAAAA
GPIO_MODER_ANALOG EQU 0xFFFFFFFF
GPIO_MODER_0 EQU 0x00000003
GPIO_MODER_1 EQU 0x0000000C
GPIO_MODER_2 EQU 0x00000030
GPIO_MODER_3 EQU 0x000000C0
GPIO_MODER_4 EQU 0x00000300
GPIO_MODER_5 EQU 0x00000C00
GPIO_MODER_6 EQU 0x00003000
GPIO_MODER_7 EQU 0x0000C000
GPIO_MODER_8 EQU 0x00030000
GPIO_MODER_9 EQU 0x000C0000
GPIO_MODER_10 EQU 0x00300000
GPIO_MODER_11 EQU 0x00C00000
GPIO_MODER_12 EQU 0x03000000
GPIO_MODER_13 EQU 0x0C000000
GPIO_MODER_14 EQU 0x30000000
GPIO_MODER_15 EQU 0xC0000000
;****************** Bit definition for GPIO_OSPEEDR register **************
; pattern masks. Use as: (GPIO_OSPEEDR_2 & GPIO_OSPEEDR_LOW)
GPIO_OSPEEDR_LOW EQU 0x00000000
GPIO_OSPEEDR_MEDIUM EQU 0x55555555
GPIO_OSPEEDR_HIGH EQU 0xFFFFFFFF
GPIO_OSPEEDR_0 EQU (0x00000003)
GPIO_OSPEEDR_1 EQU (0x0000000C)
GPIO_OSPEEDR_2 EQU (0x00000030)
GPIO_OSPEEDR_3 EQU (0x000000C0)
GPIO_OSPEEDR_4 EQU (0x00000300)
GPIO_OSPEEDR_5 EQU (0x00000C00)
GPIO_OSPEEDR_6 EQU (0x00003000)
GPIO_OSPEEDR_7 EQU (0x0000C000)
GPIO_OSPEEDR_8 EQU (0x00030000)
GPIO_OSPEEDR_9 EQU (0x000C0000)
GPIO_OSPEEDR_10 EQU (0x00300000)
GPIO_OSPEEDR_11 EQU (0x00C00000)
GPIO_OSPEEDR_12 EQU (0x03000000)
GPIO_OSPEEDR_13 EQU (0x0C000000)
GPIO_OSPEEDR_14 EQU (0x30000000)
GPIO_OSPEEDR_15 EQU (0xC0000000)
;****************** Bit definition for GPIO_PUPDR register ****************
; pattern masks. Use as: (GPIO_PUPDR_6 & GPIO_PUPDR_UP)
GPIO_PUPDR_NONE EQU 0x00000000
GPIO_PUPDR_UP EQU 0x55555555
GPIO_PUPDR_DOWN EQU 0xAAAAAAAA
GPIO_PUPDR_0 EQU (0x00000003)
GPIO_PUPDR_1 EQU (0x0000000C)
GPIO_PUPDR_2 EQU (0x00000030)
GPIO_PUPDR_3 EQU (0x000000C0)
GPIO_PUPDR_4 EQU (0x00000300)
GPIO_PUPDR_5 EQU (0x00000C00)
GPIO_PUPDR_6 EQU (0x00003000)
GPIO_PUPDR_7 EQU (0x0000C000)
GPIO_PUPDR_8 EQU (0x00030000)
GPIO_PUPDR_9 EQU (0x000C0000)
GPIO_PUPDR_10 EQU (0x00300000)
GPIO_PUPDR_11 EQU (0x00C00000)
GPIO_PUPDR_12 EQU (0x03000000)
GPIO_PUPDR_13 EQU (0x0C000000)
GPIO_PUPDR_14 EQU (0x30000000)
GPIO_PUPDR_15 EQU (0xC0000000)
;****************** Bit definition for GPIO_BSRR register *****************
GPIO_BSRR_BS_0 EQU (0x00000001)
GPIO_BSRR_BS_1 EQU (0x00000002)
GPIO_BSRR_BS_2 EQU (0x00000004)
GPIO_BSRR_BS_3 EQU (0x00000008)
GPIO_BSRR_BS_4 EQU (0x00000010)
GPIO_BSRR_BS_5 EQU (0x00000020)
GPIO_BSRR_BS_6 EQU (0x00000040)
GPIO_BSRR_BS_7 EQU (0x00000080)
GPIO_BSRR_BS_8 EQU (0x00000100)
GPIO_BSRR_BS_9 EQU (0x00000200)
GPIO_BSRR_BS_10 EQU (0x00000400)
GPIO_BSRR_BS_11 EQU (0x00000800)
GPIO_BSRR_BS_12 EQU (0x00001000)
GPIO_BSRR_BS_13 EQU (0x00002000)
GPIO_BSRR_BS_14 EQU (0x00004000)
GPIO_BSRR_BS_15 EQU (0x00008000)
GPIO_BSRR_BR_0 EQU (0x00010000)
GPIO_BSRR_BR_1 EQU (0x00020000)
GPIO_BSRR_BR_2 EQU (0x00040000)
GPIO_BSRR_BR_3 EQU (0x00080000)
GPIO_BSRR_BR_4 EQU (0x00100000)
GPIO_BSRR_BR_5 EQU (0x00200000)
GPIO_BSRR_BR_6 EQU (0x00400000)
GPIO_BSRR_BR_7 EQU (0x00800000)
GPIO_BSRR_BR_8 EQU (0x01000000)
GPIO_BSRR_BR_9 EQU (0x02000000)
GPIO_BSRR_BR_10 EQU (0x04000000)
GPIO_BSRR_BR_11 EQU (0x08000000)
GPIO_BSRR_BR_12 EQU (0x10000000)
GPIO_BSRR_BR_13 EQU (0x20000000)
GPIO_BSRR_BR_14 EQU (0x40000000)
GPIO_BSRR_BR_15 EQU (0x80000000)
;****************** Bit definition for GPIO_LCKR register *****************
GPIO_LCKR_0 EQU (0x00000001)
GPIO_LCKR_1 EQU (0x00000002)
GPIO_LCKR_2 EQU (0x00000004)
GPIO_LCKR_3 EQU (0x00000008)
GPIO_LCKR_4 EQU (0x00000010)
GPIO_LCKR_5 EQU (0x00000020)
GPIO_LCKR_6 EQU (0x00000040)
GPIO_LCKR_7 EQU (0x00000080)
GPIO_LCKR_8 EQU (0x00000100)
GPIO_LCKR_9 EQU (0x00000200)
GPIO_LCKR_10 EQU (0x00000400)
GPIO_LCKR_11 EQU (0x00000800)
GPIO_LCKR_12 EQU (0x00001000)
GPIO_LCKR_13 EQU (0x00002000)
GPIO_LCKR_14 EQU (0x00004000)
GPIO_LCKR_15 EQU (0x00008000)
GPIO_LCKR_K EQU (0x00010000)
;****************** Bit definition for GPIO_AFRL register *****************
GPIO_AFRL_0 EQU (0x0000000F)
GPIO_AFRL_1 EQU (0x000000F0)
GPIO_AFRL_2 EQU (0x00000F00)
GPIO_AFRL_3 EQU (0x0000F000)
GPIO_AFRL_4 EQU (0x000F0000)
GPIO_AFRL_5 EQU (0x00F00000)
GPIO_AFRL_6 EQU (0x0F000000)
GPIO_AFRL_7 EQU (0xF0000000)
;****************** Bit definition for GPIO_AFRH register *****************
GPIO_AFRH_8 EQU (0x0000000F)
GPIO_AFRH_9 EQU (0x000000F0)
GPIO_AFRH_10 EQU (0x00000F00)
GPIO_AFRH_11 EQU (0x0000F000)
GPIO_AFRH_12 EQU (0x000F0000)
GPIO_AFRH_13 EQU (0x00F00000)
GPIO_AFRH_14 EQU (0x0F000000)
GPIO_AFRH_15 EQU (0xF0000000)
END

142
lib/INI_BITS_SCB.s
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;********************************************************************************
; SOUBOR : INI_BITS_SCB.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro SCB (ovladani systemu + hw info)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; System Control Block (SCB)
;
;****************************************************************************
;***************** Bit definition for SCB_CPUID register ******************
SCB_CPUID_REVISION EQU 0x0000000F ; Implementation defined revision number
SCB_CPUID_PARTNO EQU 0x0000FFF0 ; Number of processor within family
SCB_CPUID_Constant EQU 0x000F0000 ; Reads as 0x0F
SCB_CPUID_VARIANT EQU 0x00F00000 ; Implementation defined variant number
SCB_CPUID_IMPLEMENTER EQU 0xFF000000 ; Implementer code. ARM is 0x41
;****************** Bit definition for SCB_ICSR register ******************
SCB_ICSR_VECTACTIVE EQU 0x000001FF ; Active ISR number field
SCB_ICSR_RETTOBASE EQU 0x00000800 ; All active exceptions minus the IPSR_current_exception yields the empty set
SCB_ICSR_VECTPENDING EQU 0x003FF000 ; Pending ISR number field
SCB_ICSR_ISRPENDING EQU 0x00400000 ; Interrupt pending flag
SCB_ICSR_ISRPREEMPT EQU 0x00800000 ; It indicates that a pending interrupt becomes active in the next running cycle
SCB_ICSR_PENDSTCLR EQU 0x02000000 ; Clear pending SysTick bit
SCB_ICSR_PENDSTSET EQU 0x04000000 ; Set pending SysTick bit
SCB_ICSR_PENDSVCLR EQU 0x08000000 ; Clear pending pendSV bit
SCB_ICSR_PENDSVSET EQU 0x10000000 ; Set pending pendSV bit
SCB_ICSR_NMIPENDSET EQU 0x80000000 ; Set pending NMI bit
;****************** Bit definition for SCB_VTOR register ******************
SCB_VTOR_TBLOFF EQU 0x1FFFFF80 ; Vector table base offset field
SCB_VTOR_TBLBASE EQU 0x20000000 ; Table base in code(0) or RAM(1)
; ***************** Bit definition for SCB_AIRCR register ******************
SCB_AIRCR_VECTKEY EQU 0x05FA0000 ; Value required to enable write to this register
SCB_AIRCR_VECTRESET EQU 0x00000001 ; System Reset bit
SCB_AIRCR_VECTCLRACTIVE EQU 0x00000002 ; Clear active vector bit
SCB_AIRCR_SYSRESETREQ EQU 0x00000004 ; Requests chip control logic to generate a reset
SCB_AIRCR_PRIGROUP EQU 0x00000700 ; PRIGROUP[2:0] bits (Priority group)
SCB_AIRCR_PRIGROUP_0 EQU 0x00000100 ; Bit 0
SCB_AIRCR_PRIGROUP_1 EQU 0x00000200 ; Bit 1
SCB_AIRCR_PRIGROUP_2 EQU 0x00000400 ; Bit 2
; prority group configuration
SCB_AIRCR_PRIGROUP0 EQU 0x00000000 ; Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)
SCB_AIRCR_PRIGROUP1 EQU 0x00000100 ; Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)
SCB_AIRCR_PRIGROUP2 EQU 0x00000200 ; Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)
SCB_AIRCR_PRIGROUP3 EQU 0x00000300 ; Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)
SCB_AIRCR_PRIGROUP4 EQU 0x00000400 ; Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)
SCB_AIRCR_PRIGROUP5 EQU 0x00000500 ; Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)
SCB_AIRCR_PRIGROUP6 EQU 0x00000600 ; Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)
SCB_AIRCR_PRIGROUP7 EQU 0x00000700 ; Priority group=7 (no pre-emption priority, 8 bits of subpriority)
SCB_AIRCR_ENDIANESS EQU 0x00008000 ; Data endianness bit
SCB_AIRCR_VECTKEY EQU 0xFFFF0000 ; Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)
;****************** Bit definition for SCB_SCR register *******************
SCB_SCR_SLEEPONEXIT EQU 0x02 ; Sleep on exit bit
SCB_SCR_SLEEPDEEP EQU 0x04 ; Sleep deep bit
SCB_SCR_SEVONPEND EQU 0x10 ; Wake up from WFE
;******************* Bit definition for SCB_CCR register ******************
SCB_CCR_NONBASETHRDENA EQU 0x0001 ; Thread mode can be entered from any level in Handler mode by controlled return value
SCB_CCR_USERSETMPEND EQU 0x0002 ; Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception
SCB_CCR_UNALIGN_TRP EQU 0x0008 ; Trap for unaligned access
SCB_CCR_DIV_0_TRP EQU 0x0010 ; Trap on Divide by 0
SCB_CCR_BFHFNMIGN EQU 0x0100 ; Handlers running at priority -1 and -2
SCB_CCR_STKALIGN EQU 0x0200 ; On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned
;****************** Bit definition for SCB_SHPR register *******************
SCB_SHPR_PRI_N EQU 0x000000FF ; Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor
SCB_SHPR_PRI_N1 EQU 0x0000FF00 ; Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved
SCB_SHPR_PRI_N2 EQU 0x00FF0000 ; Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV
SCB_SHPR_PRI_N3 EQU 0xFF000000 ; Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick
;***************** Bit definition for SCB_SHCSR register ******************
SCB_SHCSR_MEMFAULTACT EQU 0x00000001 ; MemManage is active
SCB_SHCSR_BUSFAULTACT EQU 0x00000002 ; BusFault is active
SCB_SHCSR_USGFAULTACT EQU 0x00000008 ; UsageFault is active
SCB_SHCSR_SVCALLACT EQU 0x00000080 ; SVCall is active
SCB_SHCSR_MONITORACT EQU 0x00000100 ; Monitor is active
SCB_SHCSR_PENDSVACT EQU 0x00000400 ; PendSV is active
SCB_SHCSR_SYSTICKACT EQU 0x00000800 ; SysTick is active
SCB_SHCSR_USGFAULTPENDED EQU 0x00001000 ; Usage Fault is pended
SCB_SHCSR_MEMFAULTPENDED EQU 0x00002000 ; MemManage is pended
SCB_SHCSR_BUSFAULTPENDED EQU 0x00004000 ; Bus Fault is pended
SCB_SHCSR_SVCALLPENDED EQU 0x00008000 ; SVCall is pended
SCB_SHCSR_MEMFAULTENA EQU 0x00010000 ; MemManage enable
SCB_SHCSR_BUSFAULTENA EQU 0x00020000 ; Bus Fault enable
SCB_SHCSR_USGFAULTENA EQU 0x00040000 ; UsageFault enable
;****************** Bit definition for SCB_CFSR register ******************
; MFSR
SCB_CFSR_IACCVIOL EQU 0x00000001 ; Instruction access violation
SCB_CFSR_DACCVIOL EQU 0x00000002 ; Data access violation
SCB_CFSR_MUNSTKERR EQU 0x00000008 ; Unstacking error
SCB_CFSR_MSTKERR EQU 0x00000010 ; Stacking error
SCB_CFSR_MMARVALID EQU 0x00000080 ; Memory Manage Address Register address valid flag
; BFSR
SCB_CFSR_IBUSERR EQU 0x00000100 ; Instruction bus error flag
SCB_CFSR_PRECISERR EQU 0x00000200 ; Precise data bus error
SCB_CFSR_IMPRECISERR EQU 0x00000400 ; Imprecise data bus error
SCB_CFSR_UNSTKERR EQU 0x00000800 ; Unstacking error
SCB_CFSR_STKERR EQU 0x00001000 ; Stacking error
SCB_CFSR_BFARVALID EQU 0x00008000 ; Bus Fault Address Register address valid flag
; UFSR
SCB_CFSR_UNDEFINSTR EQU 0x00010000 ; The processor attempt to excecute an undefined instruction
SCB_CFSR_INVSTATE EQU 0x00020000 ; Invalid combination of EPSR and instruction
SCB_CFSR_INVPC EQU 0x00040000 ; Attempt to load EXC_RETURN into pc illegally
SCB_CFSR_NOCP EQU 0x00080000 ; Attempt to use a coprocessor instruction
SCB_CFSR_UNALIGNED EQU 0x01000000 ; Fault occurs when there is an attempt to make an unaligned memory access
SCB_CFSR_DIVBYZERO EQU 0x02000000 ; Fault occurs when SDIV or DIV instruction is used with a divisor of 0
;****************** Bit definition for SCB_HFSR register ******************
SCB_HFSR_VECTTBL EQU 0x00000002 ; Fault occures because of vector table read on exception processing
SCB_HFSR_FORCED EQU 0x40000000 ; Hard Fault activated when a configurable Fault was received and cannot activate
SCB_HFSR_DEBUGEVT EQU 0x80000000 ; Fault related to debug
;****************** Bit definition for SCB_DFSR register ******************
SCB_DFSR_HALTED EQU 0x01 ; Halt request flag
SCB_DFSR_BKPT EQU 0x02 ; BKPT flag
SCB_DFSR_DWTTRAP EQU 0x04 ; Data Watchpoint and Trace (DWT) flag
SCB_DFSR_VCATCH EQU 0x08 ; Vector catch flag
SCB_DFSR_EXTERNAL EQU 0x10 ; External debug request flag
;****************** Bit definition for SCB_MMFAR register *****************
SCB_MMFAR_ADDRESS EQU 0xFFFFFFFF ; Mem Manage fault address field
;****************** Bit definition for SCB_BFAR register ******************
SCB_BFAR_ADDRESS EQU 0xFFFFFFFF ; Bus fault address field
;****************** Bit definition for SCB_afsr register ******************
SCB_AFSR_IMPDEF EQU 0xFFFFFFFF ; Implementation defined
END

38
lib/INI_BITS_SYSTICK.s
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;********************************************************************************
; SOUBOR : INI_BITS_SYSTICK.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro SYSTICK (casovac pro RTOS)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; SystemTick (SysTick)
;
;****************************************************************************
;**************** Bit definition for SysTick_CSR register ****************
SysTick_CSR_ENABLE EQU 0x00000001 ; Counter enable
SysTick_CSR_TICKINT EQU 0x00000002 ; Enable interrupt when counter reaches zero
SysTick_CSR_CLKSOURCE EQU 0x00000004 ; Clock source (0 - external, 1 - core clock)
SysTick_CSR_CLKSOURCE_CORE EQU 0x00000004 ; Clock source - core clock
SysTick_CSR_CLKSOURCE_DIV8 EQU 0x00000000 ; Clock source - core clock / 8
SysTick_CSR_COUNTFLAG EQU 0x00010000 ; Count Flag (only if interrupt is disabled)
;**************** Bit definition for SysTick_LOAD register ****************
SysTick_RELOAD_MASK EQU 0x00FFFFFF ; Value to load into the SysTick Current Value Register when the counter reaches 0
;**************** Bit definition for SysTick_VAL register *****************
SysTick_VAL_MASK EQU 0x00FFFFFF ; Current value at the time the register is accessed
;**************** Bit definition for SysTick_CALIB register ***************
SysTick_CALIB_TENMS EQU 0x00FFFFFF ; Reload value to use for 10ms timing
SysTick_CALIB_SKEW EQU 0x40000000 ; Calibration value is not exactly 10 ms
SysTick_CALIB_NOREF EQU 0x80000000 ; The reference clock is not provided
END

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lib/INI_BB.s → lib/INI_GPIO.s
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@ -1,14 +1,370 @@
;********************************************************************************
; SOUBOR : INI_BB.S
; AUTOR : Ondrej Hruska
;****************************************************************************
; SOUBOR : INI_GPIO.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Adresy bit-bandingovych registru
;
; General Purpose IOs (GPIO)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
; ======================== GPIO BITS ===========================
;****************************************************************************
;****************************************************************************
;*
;* REGISTERS
;*
;****************************************************************************
_GPIOA EQU (_GPIO + 0x0000)
_GPIOB EQU (_GPIO + 0x0400)
_GPIOC EQU (_GPIO + 0x0800)
_GPIOD EQU (_GPIO + 0x0C00)
_GPIOE EQU (_GPIO + 0x1000)
_GPIOH EQU (_GPIO + 0x1400)
_GPIOF EQU (_GPIO + 0x1800)
_GPIOG EQU (_GPIO + 0x1C00)
GPIOA_MODER EQU (_GPIOA + 0x00) ; GPIOA pin mode register,
GPIOA_OTYPER EQU (_GPIOA + 0x04) ; GPIOA output type register,
GPIOA_OSPEEDR EQU (_GPIOA + 0x08) ; GPIOA output speed register,
GPIOA_PUPDR EQU (_GPIOA + 0x0C) ; GPIOA pull-up/pull-down register,
GPIOA_IDR EQU (_GPIOA + 0x10) ; GPIOA input data register,
GPIOA_ODR EQU (_GPIOA + 0x14) ; GPIOA output data register,
GPIOA_BSRR EQU (_GPIOA + 0x18) ; GPIOA bit set/reset register,
GPIOA_LCKR EQU (_GPIOA + 0x1C) ; GPIOA configuration lock register,
GPIOA_AFRL EQU (_GPIOA + 0x20) ; GPIOA alternate function low register,
GPIOA_AFRH EQU (_GPIOA + 0x24) ; GPIOA alternate function low register,
GPIOA_BRR EQU (_GPIOA + 0x28) ; GPIOA bit reset register,
GPIOB_MODER EQU (_GPIOB + 0x00) ; GPIOB pin mode register,
GPIOB_OTYPER EQU (_GPIOB + 0x04) ; GPIOB output type register,
GPIOB_OSPEEDR EQU (_GPIOB + 0x08) ; GPIOB output speed register,
GPIOB_PUPDR EQU (_GPIOB + 0x0C) ; GPIOB pull-up/pull-down register,
GPIOB_IDR EQU (_GPIOB + 0x10) ; GPIOB input data register,
GPIOB_ODR EQU (_GPIOB + 0x14) ; GPIOB output data register,
GPIOB_BSRR EQU (_GPIOB + 0x18) ; GPIOB bit set/reset register,
GPIOB_LCKR EQU (_GPIOB + 0x1C) ; GPIOB configuration lock register,
GPIOB_AFR EQU (_GPIOB + 0x20) ; GPIOB alternate function low register,
GPIOB_BRR EQU (_GPIOB + 0x28) ; GPIOB bit reset register,
GPIOC_MODER EQU (_GPIOC + 0x00) ; GPIOC pin mode register,
GPIOC_OTYPER EQU (_GPIOC + 0x04) ; GPIOC output type register,
GPIOC_OSPEEDR EQU (_GPIOC + 0x08) ; GPIOC output speed register,
GPIOC_PUPDR EQU (_GPIOC + 0x0C) ; GPIOC pull-up/pull-down register,
GPIOC_IDR EQU (_GPIOC + 0x10) ; GPIOC input data register,
GPIOC_ODR EQU (_GPIOC + 0x14) ; GPIOC output data register,
GPIOC_BSRR EQU (_GPIOC + 0x18) ; GPIOC bit set/reset register,
GPIOC_LCKR EQU (_GPIOC + 0x1C) ; GPIOC configuration lock register,
GPIOC_AFR EQU (_GPIOC + 0x20) ; GPIOC alternate function low register,
GPIOC_BRR EQU (_GPIOC + 0x28) ; GPIOC bit reset register,
GPIOD_MODER EQU (_GPIOD + 0x00) ; GPIOD pin mode register,
GPIOD_OTYPER EQU (_GPIOD + 0x04) ; GPIOD output type register,
GPIOD_OSPEEDR EQU (_GPIOD + 0x08) ; GPIOD output speed register,
GPIOD_PUPDR EQU (_GPIOD + 0x0C) ; GPIOD pull-up/pull-down register,
GPIOD_IDR EQU (_GPIOD + 0x10) ; GPIOD input data register,
GPIOD_ODR EQU (_GPIOD + 0x14) ; GPIOD output data register,
GPIOD_BSRR EQU (_GPIOD + 0x18) ; GPIOD bit set/reset register,
GPIOD_LCKR EQU (_GPIOD + 0x1C) ; GPIOD configuration lock register,
GPIOD_AFR EQU (_GPIOD + 0x20) ; GPIOD alternate function low register,
GPIOD_BRR EQU (_GPIOD + 0x28) ; GPIOD bit reset register,
GPIOE_MODER EQU (_GPIOE + 0x00) ; GPIOE pin mode register,
GPIOE_OTYPER EQU (_GPIOE + 0x04) ; GPIOE output type register,
GPIOE_OSPEEDR EQU (_GPIOE + 0x08) ; GPIOE output speed register,
GPIOE_PUPDR EQU (_GPIOE + 0x0C) ; GPIOE pull-up/pull-down register,
GPIOE_IDR EQU (_GPIOE + 0x10) ; GPIOE input data register,
GPIOE_ODR EQU (_GPIOE + 0x14) ; GPIOE output data register,
GPIOE_BSRR EQU (_GPIOE + 0x18) ; GPIOE bit set/reset register,
GPIOE_LCKR EQU (_GPIOE + 0x1C) ; GPIOE configuration lock register,
GPIOE_AFR EQU (_GPIOE + 0x20) ; GPIOE alternate function low register,
GPIOE_BRR EQU (_GPIOE + 0x28) ; GPIOE bit reset register,
GPIOF_MODER EQU (_GPIOF + 0x00) ; GPIOF pin mode register,
GPIOF_OTYPER EQU (_GPIOF + 0x04) ; GPIOF output type register,
GPIOF_OSPEEDR EQU (_GPIOF + 0x08) ; GPIOF output speed register,
GPIOF_PUPDR EQU (_GPIOF + 0x0C) ; GPIOF pull-up/pull-down register,
GPIOF_IDR EQU (_GPIOF + 0x10) ; GPIOF input data register,
GPIOF_ODR EQU (_GPIOF + 0x14) ; GPIOF output data register,
GPIOF_BSRR EQU (_GPIOF + 0x18) ; GPIOF bit set/reset register,
GPIOF_LCKR EQU (_GPIOF + 0x1C) ; GPIOF configuration lock register,
GPIOF_AFR EQU (_GPIOF + 0x20) ; GPIOF alternate function low register,
GPIOF_BRR EQU (_GPIOF + 0x28) ; GPIOF bit reset register,
GPIOG_MODER EQU (_GPIOG + 0x00) ; GPIOG pin mode register,
GPIOG_OTYPER EQU (_GPIOG + 0x04) ; GPIOG output type register,
GPIOG_OSPEEDR EQU (_GPIOG + 0x08) ; GPIOG output speed register,
GPIOG_PUPDR EQU (_GPIOG + 0x0C) ; GPIOG pull-up/pull-down register,
GPIOG_IDR EQU (_GPIOG + 0x10) ; GPIOG input data register,
GPIOG_ODR EQU (_GPIOG + 0x14) ; GPIOG output data register,
GPIOG_BSRR EQU (_GPIOG + 0x18) ; GPIOG bit set/reset register,
GPIOG_LCKR EQU (_GPIOG + 0x1C) ; GPIOG configuration lock register,
GPIOG_AFR EQU (_GPIOG + 0x20) ; GPIOG alternate function low register,
GPIOG_BRR EQU (_GPIOG + 0x28) ; GPIOG bit reset register,
GPIOH_MODER EQU (_GPIOH + 0x00) ; GPIOH pin mode register,
GPIOH_OTYPER EQU (_GPIOH + 0x04) ; GPIOH output type register,
GPIOH_OSPEEDR EQU (_GPIOH + 0x08) ; GPIOH output speed register,
GPIOH_PUPDR EQU (_GPIOH + 0x0C) ; GPIOH pull-up/pull-down register,
GPIOH_IDR EQU (_GPIOH + 0x10) ; GPIOH input data register,
GPIOH_ODR EQU (_GPIOH + 0x14) ; GPIOH output data register,
GPIOH_BSRR EQU (_GPIOH + 0x18) ; GPIOH bit set/reset register,
GPIOH_LCKR EQU (_GPIOH + 0x1C) ; GPIOH configuration lock register,
GPIOH_AFR EQU (_GPIOH + 0x20) ; GPIOH alternate function low register,
GPIOH_BRR EQU (_GPIOH + 0x28) ; GPIOH bit reset register,
;****************************************************************************
;*
;* BIT MASKS AND DEFINITIONS
;*
;****************************************************************************
; Short pin masks. Valid for OTYPER, IDR and ODR.
GPIO0 EQU 0x00000001
GPIO1 EQU 0x00000002
GPIO2 EQU 0x00000004
GPIO3 EQU 0x00000008
GPIO4 EQU 0x00000010
GPIO5 EQU 0x00000020
GPIO6 EQU 0x00000040
GPIO7 EQU 0x00000080
GPIO8 EQU 0x00000100
GPIO9 EQU 0x00000200
GPIO10 EQU 0x00000400
GPIO11 EQU 0x00000800
GPIO12 EQU 0x00001000
GPIO13 EQU 0x00002000
GPIO14 EQU 0x00004000
GPIO15 EQU 0x00008000
; OTYPER pattern masks - use as (GPIO_OTYPER_6 & GPIO_OTYPER_OD)
GPIO_OTYPER_PP EQU 0x00000000
GPIO_OTYPER_OD EQU 0xFFFFFFFF
; For completenes, aliases also for OTYPER, ODR and IDR
GPIO_OTYPER_0 EQU 0x00000001
GPIO_OTYPER_1 EQU 0x00000002
GPIO_OTYPER_2 EQU 0x00000004
GPIO_OTYPER_3 EQU 0x00000008
GPIO_OTYPER_4 EQU 0x00000010
GPIO_OTYPER_5 EQU 0x00000020
GPIO_OTYPER_6 EQU 0x00000040
GPIO_OTYPER_7 EQU 0x00000080
GPIO_OTYPER_8 EQU 0x00000100
GPIO_OTYPER_9 EQU 0x00000200
GPIO_OTYPER_10 EQU 0x00000400
GPIO_OTYPER_11 EQU 0x00000800
GPIO_OTYPER_12 EQU 0x00001000
GPIO_OTYPER_13 EQU 0x00002000
GPIO_OTYPER_14 EQU 0x00004000
GPIO_OTYPER_15 EQU 0x00008000
GPIO_ODR_0 EQU 0x00000001
GPIO_ODR_1 EQU 0x00000002
GPIO_ODR_2 EQU 0x00000004
GPIO_ODR_3 EQU 0x00000008
GPIO_ODR_4 EQU 0x00000010
GPIO_ODR_5 EQU 0x00000020
GPIO_ODR_6 EQU 0x00000040
GPIO_ODR_7 EQU 0x00000080
GPIO_ODR_8 EQU 0x00000100
GPIO_ODR_9 EQU 0x00000200
GPIO_ODR_10 EQU 0x00000400
GPIO_ODR_11 EQU 0x00000800
GPIO_ODR_12 EQU 0x00001000
GPIO_ODR_13 EQU 0x00002000
GPIO_ODR_14 EQU 0x00004000
GPIO_ODR_15 EQU 0x00008000
GPIO_IDR_0 EQU 0x00000001
GPIO_IDR_1 EQU 0x00000002
GPIO_IDR_2 EQU 0x00000004
GPIO_IDR_3 EQU 0x00000008
GPIO_IDR_4 EQU 0x00000010
GPIO_IDR_5 EQU 0x00000020
GPIO_IDR_6 EQU 0x00000040
GPIO_IDR_7 EQU 0x00000080
GPIO_IDR_8 EQU 0x00000100
GPIO_IDR_9 EQU 0x00000200
GPIO_IDR_10 EQU 0x00000400
GPIO_IDR_11 EQU 0x00000800
GPIO_IDR_12 EQU 0x00001000
GPIO_IDR_13 EQU 0x00002000
GPIO_IDR_14 EQU 0x00004000
GPIO_IDR_15 EQU 0x00008000
;****************** Bit definition for GPIO_MODER register ****************
; pattern masks. Use as: (GPIO_MODER_0 & GPIO_MODER_OUTPUT)
GPIO_MODER_INPUT EQU 0x00000000
GPIO_MODER_OUTPUT EQU 0x55555555
GPIO_MODER_AF EQU 0xAAAAAAAA
GPIO_MODER_ANALOG EQU 0xFFFFFFFF
GPIO_MODER_0 EQU 0x00000003
GPIO_MODER_1 EQU 0x0000000C
GPIO_MODER_2 EQU 0x00000030
GPIO_MODER_3 EQU 0x000000C0
GPIO_MODER_4 EQU 0x00000300
GPIO_MODER_5 EQU 0x00000C00
GPIO_MODER_6 EQU 0x00003000
GPIO_MODER_7 EQU 0x0000C000
GPIO_MODER_8 EQU 0x00030000
GPIO_MODER_9 EQU 0x000C0000
GPIO_MODER_10 EQU 0x00300000
GPIO_MODER_11 EQU 0x00C00000
GPIO_MODER_12 EQU 0x03000000
GPIO_MODER_13 EQU 0x0C000000
GPIO_MODER_14 EQU 0x30000000
GPIO_MODER_15 EQU 0xC0000000
;****************** Bit definition for GPIO_OSPEEDR register **************
; pattern masks. Use as: (GPIO_OSPEEDR_2 & GPIO_OSPEEDR_LOW)
GPIO_OSPEEDR_LOW EQU 0x00000000
GPIO_OSPEEDR_MEDIUM EQU 0x55555555
GPIO_OSPEEDR_HIGH EQU 0xFFFFFFFF
GPIO_OSPEEDR_0 EQU (0x00000003)
GPIO_OSPEEDR_1 EQU (0x0000000C)
GPIO_OSPEEDR_2 EQU (0x00000030)
GPIO_OSPEEDR_3 EQU (0x000000C0)
GPIO_OSPEEDR_4 EQU (0x00000300)
GPIO_OSPEEDR_5 EQU (0x00000C00)
GPIO_OSPEEDR_6 EQU (0x00003000)
GPIO_OSPEEDR_7 EQU (0x0000C000)
GPIO_OSPEEDR_8 EQU (0x00030000)
GPIO_OSPEEDR_9 EQU (0x000C0000)
GPIO_OSPEEDR_10 EQU (0x00300000)
GPIO_OSPEEDR_11 EQU (0x00C00000)
GPIO_OSPEEDR_12 EQU (0x03000000)
GPIO_OSPEEDR_13 EQU (0x0C000000)
GPIO_OSPEEDR_14 EQU (0x30000000)
GPIO_OSPEEDR_15 EQU (0xC0000000)
;****************** Bit definition for GPIO_PUPDR register ****************
; pattern masks. Use as: (GPIO_PUPDR_6 & GPIO_PUPDR_UP)
GPIO_PUPDR_NONE EQU 0x00000000
GPIO_PUPDR_UP EQU 0x55555555
GPIO_PUPDR_DOWN EQU 0xAAAAAAAA
GPIO_PUPDR_0 EQU (0x00000003)
GPIO_PUPDR_1 EQU (0x0000000C)
GPIO_PUPDR_2 EQU (0x00000030)
GPIO_PUPDR_3 EQU (0x000000C0)
GPIO_PUPDR_4 EQU (0x00000300)
GPIO_PUPDR_5 EQU (0x00000C00)
GPIO_PUPDR_6 EQU (0x00003000)
GPIO_PUPDR_7 EQU (0x0000C000)
GPIO_PUPDR_8 EQU (0x00030000)
GPIO_PUPDR_9 EQU (0x000C0000)
GPIO_PUPDR_10 EQU (0x00300000)
GPIO_PUPDR_11 EQU (0x00C00000)
GPIO_PUPDR_12 EQU (0x03000000)
GPIO_PUPDR_13 EQU (0x0C000000)
GPIO_PUPDR_14 EQU (0x30000000)
GPIO_PUPDR_15 EQU (0xC0000000)
;****************** Bit definition for GPIO_BSRR register *****************
GPIO_BSRR_BS_0 EQU (0x00000001)
GPIO_BSRR_BS_1 EQU (0x00000002)
GPIO_BSRR_BS_2 EQU (0x00000004)
GPIO_BSRR_BS_3 EQU (0x00000008)
GPIO_BSRR_BS_4 EQU (0x00000010)
GPIO_BSRR_BS_5 EQU (0x00000020)
GPIO_BSRR_BS_6 EQU (0x00000040)
GPIO_BSRR_BS_7 EQU (0x00000080)
GPIO_BSRR_BS_8 EQU (0x00000100)
GPIO_BSRR_BS_9 EQU (0x00000200)
GPIO_BSRR_BS_10 EQU (0x00000400)
GPIO_BSRR_BS_11 EQU (0x00000800)
GPIO_BSRR_BS_12 EQU (0x00001000)
GPIO_BSRR_BS_13 EQU (0x00002000)
GPIO_BSRR_BS_14 EQU (0x00004000)
GPIO_BSRR_BS_15 EQU (0x00008000)
GPIO_BSRR_BR_0 EQU (0x00010000)
GPIO_BSRR_BR_1 EQU (0x00020000)
GPIO_BSRR_BR_2 EQU (0x00040000)
GPIO_BSRR_BR_3 EQU (0x00080000)
GPIO_BSRR_BR_4 EQU (0x00100000)
GPIO_BSRR_BR_5 EQU (0x00200000)
GPIO_BSRR_BR_6 EQU (0x00400000)
GPIO_BSRR_BR_7 EQU (0x00800000)
GPIO_BSRR_BR_8 EQU (0x01000000)
GPIO_BSRR_BR_9 EQU (0x02000000)
GPIO_BSRR_BR_10 EQU (0x04000000)
GPIO_BSRR_BR_11 EQU (0x08000000)
GPIO_BSRR_BR_12 EQU (0x10000000)
GPIO_BSRR_BR_13 EQU (0x20000000)
GPIO_BSRR_BR_14 EQU (0x40000000)
GPIO_BSRR_BR_15 EQU (0x80000000)
;****************** Bit definition for GPIO_LCKR register *****************
GPIO_LCKR_0 EQU (0x00000001)
GPIO_LCKR_1 EQU (0x00000002)
GPIO_LCKR_2 EQU (0x00000004)
GPIO_LCKR_3 EQU (0x00000008)
GPIO_LCKR_4 EQU (0x00000010)
GPIO_LCKR_5 EQU (0x00000020)
GPIO_LCKR_6 EQU (0x00000040)
GPIO_LCKR_7 EQU (0x00000080)
GPIO_LCKR_8 EQU (0x00000100)
GPIO_LCKR_9 EQU (0x00000200)
GPIO_LCKR_10 EQU (0x00000400)
GPIO_LCKR_11 EQU (0x00000800)
GPIO_LCKR_12 EQU (0x00001000)
GPIO_LCKR_13 EQU (0x00002000)
GPIO_LCKR_14 EQU (0x00004000)
GPIO_LCKR_15 EQU (0x00008000)
GPIO_LCKR_K EQU (0x00010000)
;****************** Bit definition for GPIO_AFRL register *****************
GPIO_AFRL_0 EQU (0x0000000F)
GPIO_AFRL_1 EQU (0x000000F0)
GPIO_AFRL_2 EQU (0x00000F00)
GPIO_AFRL_3 EQU (0x0000F000)
GPIO_AFRL_4 EQU (0x000F0000)
GPIO_AFRL_5 EQU (0x00F00000)
GPIO_AFRL_6 EQU (0x0F000000)
GPIO_AFRL_7 EQU (0xF0000000)
;****************** Bit definition for GPIO_AFRH register *****************
GPIO_AFRH_8 EQU (0x0000000F)
GPIO_AFRH_9 EQU (0x000000F0)
GPIO_AFRH_10 EQU (0x00000F00)
GPIO_AFRH_11 EQU (0x0000F000)
GPIO_AFRH_12 EQU (0x000F0000)
GPIO_AFRH_13 EQU (0x00F00000)
GPIO_AFRH_14 EQU (0x0F000000)
GPIO_AFRH_15 EQU (0xF0000000)
;****************************************************************************
;*
;* BIT BANDING REGISTERS
;*
;****************************************************************************
; ---------------------- IDR ----------------------

225
lib/INI_REGS.s
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; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
FLASH_BASE EQU 0x08000000 ; FLASH base address in the alias region
SRAM_BASE EQU 0x20000000 ; SRAM base address in the alias region
PERIPH_BASE EQU 0x40000000 ; Peripheral base address in the alias region
; Value to add to region base to get bitband base
SRAM_BB_OFFSET EQU 0x02000000
PERIPH_BB_OFFSET EQU 0x02000000
SRAM_BB_BASE EQU (SRAM_BASE + SRAM_BB_OFFSET) ; SRAM base address in the bit-band region
PERIPH_BB_BASE EQU (PERIPH_BASE + PERIPH_BB_OFFSET) ; Peripheral base address in the bit-band region
; ------------------------- Peripheral Bases --------------------------
; *** System peripherals ***
_SCS_BASE EQU 0xE000E000 ; SCS Base Address
_SCB EQU (_SCS_BASE + 0x0D00) ; System Control Block
_NVIC EQU (_SCS_BASE + 0x0100) ; Nested Interrupt Vector Controller
; *** Special system preipherals ***
_OB EQU 0x1FF80000 ; FLASH Option Bytes base address
_AES EQU 0x50060000
_FSMC EQU 0xA0000000 ; FSMC registers base address
_DBGMCU EQU 0xE0042000 ; Debug MCU registers base address
; Bus base addresses
_APB1 EQU PERIPH_BASE
_APB2 EQU (PERIPH_BASE + 0x10000)
_AHB EQU (PERIPH_BASE + 0x20000)
; *** Peripheral Bus 1 ***
_TIM2 EQU (_APB1 + 0x0000)
_TIM3 EQU (_APB1 + 0x0400)
_TIM4 EQU (_APB1 + 0x0800)
_TIM5 EQU (_APB1 + 0x0C00)
_TIM6 EQU (_APB1 + 0x1000)
_TIM7 EQU (_APB1 + 0x1400)
_LCD EQU (_APB1 + 0x2400)
_RTC EQU (_APB1 + 0x2800)
_WWDG EQU (_APB1 + 0x2C00)
_IWDG EQU (_APB1 + 0x3000)
_SPI2 EQU (_APB1 + 0x3800)
_SPI3 EQU (_APB1 + 0x3C00)
_USART2 EQU (_APB1 + 0x4400)
_USART3 EQU (_APB1 + 0x4800)
_UART4 EQU (_APB1 + 0x4C00)
_UART5 EQU (_APB1 + 0x5000)
_I2C1 EQU (_APB1 + 0x5400)
_I2C2 EQU (_APB1 + 0x5800)
_PWR EQU (_APB1 + 0x7000)
_DAC EQU (_APB1 + 0x7400)
_COMP EQU (_APB1 + 0x7C00)
_RI EQU (_APB1 + 0x7C04)
_OPAMP EQU (_APB1 + 0x7C5C)
; *** Peripheral Bus 2 ***
_TIM9 EQU (_APB2 + 0x0800)
_TIM10 EQU (_APB2 + 0x0C00)
_TIM11 EQU (_APB2 + 0x1000)
_SYSCFG EQU (_APB2 + 0x0000)
_EXTI EQU (_APB2 + 0x0400)
_ADC1 EQU (_APB2 + 0x2400)
_ADCC EQU (_APB2 + 0x2700) ; common
_SDIO EQU (_APB2 + 0x2C00) ; SD host
_SPI1 EQU (_APB2 + 0x3000) ; SPI
_USART1 EQU (_APB2 + 0x3800)
; *** High Speed Bus ***
; GPIOs base
_GPIO EQU (_AHB + 0x0000)
_CRC EQU (_AHB + 0x3000)
_RCC EQU (_AHB + 0x3800)
; DMA channels base
_DMA1 EQU (_AHB + 0x6000)
_DMA2 EQU (_AHB + 0x6400)
_FLASH EQU (_AHB + 0x3C00)
; ----------------------- Peripherals ------------------------
; Special system control registers
SysTick_CSR EQU (_SCS_BASE + 0x010) ; (R/W) SysTick Control and Status Register
SysTick_RELOAD EQU (_SCS_BASE + 0x014) ; (R/W) SysTick Reload Value Register
SysTick_VAL EQU (_SCS_BASE + 0x018) ; (R/W) SysTick Current Value Register
SysTick_CALIB EQU (_SCS_BASE + 0x01C) ; (R/ ) SysTick Calibration Value Register
; SCB
SCB_ACTLR EQU (_SCS_BASE + 0x008) ; (R/W) ACTLR
SCB_CPUID EQU (_SCB + 0x000) ; (R/ ) CPUID Base Register
SCB_ICSR EQU (_SCB + 0x004) ; (R/W) Interrupt Control and State Register
SCB_VTOR EQU (_SCB + 0x008) ; (R/W) Vector Table Offset Register
SCB_AIRCR EQU (_SCB + 0x00C) ; (R/W) Application Interrupt and Reset Control Register
SCB_SCR EQU (_SCB + 0x010) ; (R/W) System Control Register
SCB_CCR EQU (_SCB + 0x014) ; (R/W) Configuration Control Register
SCB_SHPR1 EQU (_SCB + 0x018) ; (R/W) System Handler Priority Register 1 (4-7)
SCB_SHPR2 EQU (_SCB + 0x01C) ; (R/W) System Handler Priority Register 2 (8-11)
SCB_SHPR3 EQU (_SCB + 0x020) ; (R/W) System Handler Priority Register 3 (12-15)
SCB_SHCSR EQU (_SCB + 0x024) ; (R/W) System Handler Control and State Register
SCB_CFSR EQU (_SCB + 0x028) ; (R/W) Configurable Fault Status Register
SCB_HFSR EQU (_SCB + 0x02C) ; (R/W) HardFault Status Register
SCB_DFSR EQU (_SCB + 0x030) ; (R/W) Debug Fault Status Register
SCB_MMFAR EQU (_SCB + 0x034) ; (R/W) MemManage Fault Address Register
SCB_BFAR EQU (_SCB + 0x038) ; (R/W) BusFault Address Register
SCB_AFSR EQU (_SCB + 0x03C) ; (R/W) Auxiliary Fault Status Register
; skipped Feature Registers
SCB_CPACR EQU (_SCB + 0x088) ; (R/W) Coprocessor Access Control Register
; NVIC
@ -837,105 +711,6 @@ CRC_IDR EQU (_CRC + 0x04) ; CRC Independent data register,
CRC_CR EQU (_CRC + 0x08) ; CRC Control register,
; GPIO ports
_GPIOA EQU (_GPIO + 0x0000)
_GPIOB EQU (_GPIO + 0x0400)
_GPIOC EQU (_GPIO + 0x0800)
_GPIOD EQU (_GPIO + 0x0C00)
_GPIOE EQU (_GPIO + 0x1000)
_GPIOH EQU (_GPIO + 0x1400)
_GPIOF EQU (_GPIO + 0x1800)
_GPIOG EQU (_GPIO + 0x1C00)
GPIOA_MODER EQU (_GPIOA + 0x00) ; GPIOA pin mode register,
GPIOA_OTYPER EQU (_GPIOA + 0x04) ; GPIOA output type register,
GPIOA_OSPEEDR EQU (_GPIOA + 0x08) ; GPIOA output speed register,
GPIOA_PUPDR EQU (_GPIOA + 0x0C) ; GPIOA pull-up/pull-down register,
GPIOA_IDR EQU (_GPIOA + 0x10) ; GPIOA input data register,
GPIOA_ODR EQU (_GPIOA + 0x14) ; GPIOA output data register,
GPIOA_BSRR EQU (_GPIOA + 0x18) ; GPIOA bit set/reset register,
GPIOA_LCKR EQU (_GPIOA + 0x1C) ; GPIOA configuration lock register,
GPIOA_AFRL EQU (_GPIOA + 0x20) ; GPIOA alternate function low register,
GPIOA_AFRH EQU (_GPIOA + 0x24) ; GPIOA alternate function low register,
GPIOA_BRR EQU (_GPIOA + 0x28) ; GPIOA bit reset register,
GPIOB_MODER EQU (_GPIOB + 0x00) ; GPIOB pin mode register,
GPIOB_OTYPER EQU (_GPIOB + 0x04) ; GPIOB output type register,
GPIOB_OSPEEDR EQU (_GPIOB + 0x08) ; GPIOB output speed register,
GPIOB_PUPDR EQU (_GPIOB + 0x0C) ; GPIOB pull-up/pull-down register,
GPIOB_IDR EQU (_GPIOB + 0x10) ; GPIOB input data register,
GPIOB_ODR EQU (_GPIOB + 0x14) ; GPIOB output data register,
GPIOB_BSRR EQU (_GPIOB + 0x18) ; GPIOB bit set/reset register,
GPIOB_LCKR EQU (_GPIOB + 0x1C) ; GPIOB configuration lock register,
GPIOB_AFR EQU (_GPIOB + 0x20) ; GPIOB alternate function low register,
GPIOB_BRR EQU (_GPIOB + 0x28) ; GPIOB bit reset register,
GPIOC_MODER EQU (_GPIOC + 0x00) ; GPIOC pin mode register,
GPIOC_OTYPER EQU (_GPIOC + 0x04) ; GPIOC output type register,
GPIOC_OSPEEDR EQU (_GPIOC + 0x08) ; GPIOC output speed register,
GPIOC_PUPDR EQU (_GPIOC + 0x0C) ; GPIOC pull-up/pull-down register,
GPIOC_IDR EQU (_GPIOC + 0x10) ; GPIOC input data register,
GPIOC_ODR EQU (_GPIOC + 0x14) ; GPIOC output data register,
GPIOC_BSRR EQU (_GPIOC + 0x18) ; GPIOC bit set/reset register,
GPIOC_LCKR EQU (_GPIOC + 0x1C) ; GPIOC configuration lock register,
GPIOC_AFR EQU (_GPIOC + 0x20) ; GPIOC alternate function low register,
GPIOC_BRR EQU (_GPIOC + 0x28) ; GPIOC bit reset register,
GPIOD_MODER EQU (_GPIOD + 0x00) ; GPIOD pin mode register,
GPIOD_OTYPER EQU (_GPIOD + 0x04) ; GPIOD output type register,
GPIOD_OSPEEDR EQU (_GPIOD + 0x08) ; GPIOD output speed register,
GPIOD_PUPDR EQU (_GPIOD + 0x0C) ; GPIOD pull-up/pull-down register,
GPIOD_IDR EQU (_GPIOD + 0x10) ; GPIOD input data register,
GPIOD_ODR EQU (_GPIOD + 0x14) ; GPIOD output data register,
GPIOD_BSRR EQU (_GPIOD + 0x18) ; GPIOD bit set/reset register,
GPIOD_LCKR EQU (_GPIOD + 0x1C) ; GPIOD configuration lock register,
GPIOD_AFR EQU (_GPIOD + 0x20) ; GPIOD alternate function low register,
GPIOD_BRR EQU (_GPIOD + 0x28) ; GPIOD bit reset register,
GPIOE_MODER EQU (_GPIOE + 0x00) ; GPIOE pin mode register,
GPIOE_OTYPER EQU (_GPIOE + 0x04) ; GPIOE output type register,
GPIOE_OSPEEDR EQU (_GPIOE + 0x08) ; GPIOE output speed register,
GPIOE_PUPDR EQU (_GPIOE + 0x0C) ; GPIOE pull-up/pull-down register,
GPIOE_IDR EQU (_GPIOE + 0x10) ; GPIOE input data register,
GPIOE_ODR EQU (_GPIOE + 0x14) ; GPIOE output data register,
GPIOE_BSRR EQU (_GPIOE + 0x18) ; GPIOE bit set/reset register,
GPIOE_LCKR EQU (_GPIOE + 0x1C) ; GPIOE configuration lock register,
GPIOE_AFR EQU (_GPIOE + 0x20) ; GPIOE alternate function low register,
GPIOE_BRR EQU (_GPIOE + 0x28) ; GPIOE bit reset register,
GPIOF_MODER EQU (_GPIOF + 0x00) ; GPIOF pin mode register,
GPIOF_OTYPER EQU (_GPIOF + 0x04) ; GPIOF output type register,
GPIOF_OSPEEDR EQU (_GPIOF + 0x08) ; GPIOF output speed register,
GPIOF_PUPDR EQU (_GPIOF + 0x0C) ; GPIOF pull-up/pull-down register,
GPIOF_IDR EQU (_GPIOF + 0x10) ; GPIOF input data register,
GPIOF_ODR EQU (_GPIOF + 0x14) ; GPIOF output data register,
GPIOF_BSRR EQU (_GPIOF + 0x18) ; GPIOF bit set/reset register,
GPIOF_LCKR EQU (_GPIOF + 0x1C) ; GPIOF configuration lock register,
GPIOF_AFR EQU (_GPIOF + 0x20) ; GPIOF alternate function low register,
GPIOF_BRR EQU (_GPIOF + 0x28) ; GPIOF bit reset register,
GPIOG_MODER EQU (_GPIOG + 0x00) ; GPIOG pin mode register,
GPIOG_OTYPER EQU (_GPIOG + 0x04) ; GPIOG output type register,
GPIOG_OSPEEDR EQU (_GPIOG + 0x08) ; GPIOG output speed register,
GPIOG_PUPDR EQU (_GPIOG + 0x0C) ; GPIOG pull-up/pull-down register,
GPIOG_IDR EQU (_GPIOG + 0x10) ; GPIOG input data register,
GPIOG_ODR EQU (_GPIOG + 0x14) ; GPIOG output data register,
GPIOG_BSRR EQU (_GPIOG + 0x18) ; GPIOG bit set/reset register,
GPIOG_LCKR EQU (_GPIOG + 0x1C) ; GPIOG configuration lock register,
GPIOG_AFR EQU (_GPIOG + 0x20) ; GPIOG alternate function low register,
GPIOG_BRR EQU (_GPIOG + 0x28) ; GPIOG bit reset register,
GPIOH_MODER EQU (_GPIOH + 0x00) ; GPIOH pin mode register,
GPIOH_OTYPER EQU (_GPIOH + 0x04) ; GPIOH output type register,
GPIOH_OSPEEDR EQU (_GPIOH + 0x08) ; GPIOH output speed register,
GPIOH_PUPDR EQU (_GPIOH + 0x0C) ; GPIOH pull-up/pull-down register,
GPIOH_IDR EQU (_GPIOH + 0x10) ; GPIOH input data register,
GPIOH_ODR EQU (_GPIOH + 0x14) ; GPIOH output data register,
GPIOH_BSRR EQU (_GPIOH + 0x18) ; GPIOH bit set/reset register,
GPIOH_LCKR EQU (_GPIOH + 0x1C) ; GPIOH configuration lock register,
GPIOH_AFR EQU (_GPIOH + 0x20) ; GPIOH alternate function low register,
GPIOH_BRR EQU (_GPIOH + 0x28) ; GPIOH bit reset register,
; FLASH registers

199
lib/INI_SCB.s
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;****************************************************************************
; SOUBOR : INI_SCB.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; System Control Block (SCB)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;****************************************************************************
;****************************************************************************
;*
;* REGISTERS
;*
;****************************************************************************
SCB_CPUID EQU (_SCB + 0x000) ; (R/ ) CPUID Base Register
SCB_ICSR EQU (_SCB + 0x004) ; (R/W) Interrupt Control and State Register
SCB_VTOR EQU (_SCB + 0x008) ; (R/W) Vector Table Offset Register
SCB_AIRCR EQU (_SCB + 0x00C) ; (R/W) Application Interrupt and Reset Control Register
SCB_SCR EQU (_SCB + 0x010) ; (R/W) System Control Register
SCB_CCR EQU (_SCB + 0x014) ; (R/W) Configuration Control Register
SCB_SHPR1 EQU (_SCB + 0x018) ; (R/W) System Handler Priority Register 1 (4-7)
SCB_SHPR2 EQU (_SCB + 0x01C) ; (R/W) System Handler Priority Register 2 (8-11)
SCB_SHPR3 EQU (_SCB + 0x020) ; (R/W) System Handler Priority Register 3 (12-15)
SCB_SHCSR EQU (_SCB + 0x024) ; (R/W) System Handler Control and State Register
SCB_CFSR EQU (_SCB + 0x028) ; (R/W) Configurable Fault Status Register
SCB_HFSR EQU (_SCB + 0x02C) ; (R/W) HardFault Status Register
SCB_DFSR EQU (_SCB + 0x030) ; (R/W) Debug Fault Status Register
SCB_MMFAR EQU (_SCB + 0x034) ; (R/W) MemManage Fault Address Register
SCB_BFAR EQU (_SCB + 0x038) ; (R/W) BusFault Address Register
SCB_AFSR EQU (_SCB + 0x03C) ; (R/W) Auxiliary Fault Status Register
; skipped Feature Registers
SCB_CPACR EQU (_SCB + 0x088) ; (R/W) Coprocessor Access Control Register
;****************************************************************************
;*
;* BIT MASKS AND DEFINITIONS
;*
;****************************************************************************
;***************** Bit definition for SCB_CPUID register ******************
SCB_CPUID_REVISION EQU 0x0000000F ; Implementation defined revision number
SCB_CPUID_PARTNO EQU 0x0000FFF0 ; Number of processor within family
SCB_CPUID_Constant EQU 0x000F0000 ; Reads as 0x0F
SCB_CPUID_VARIANT EQU 0x00F00000 ; Implementation defined variant number
SCB_CPUID_IMPLEMENTER EQU 0xFF000000 ; Implementer code. ARM is 0x41
;****************** Bit definition for SCB_ICSR register ******************
SCB_ICSR_VECTACTIVE EQU 0x000001FF ; Active ISR number field
SCB_ICSR_RETTOBASE EQU 0x00000800 ; All active exceptions minus the IPSR_current_exception yields the empty set
SCB_ICSR_VECTPENDING EQU 0x003FF000 ; Pending ISR number field
SCB_ICSR_ISRPENDING EQU 0x00400000 ; Interrupt pending flag
SCB_ICSR_ISRPREEMPT EQU 0x00800000 ; It indicates that a pending interrupt becomes active in the next running cycle
SCB_ICSR_PENDSTCLR EQU 0x02000000 ; Clear pending SysTick bit
SCB_ICSR_PENDSTSET EQU 0x04000000 ; Set pending SysTick bit
SCB_ICSR_PENDSVCLR EQU 0x08000000 ; Clear pending pendSV bit
SCB_ICSR_PENDSVSET EQU 0x10000000 ; Set pending pendSV bit
SCB_ICSR_NMIPENDSET EQU 0x80000000 ; Set pending NMI bit
;****************** Bit definition for SCB_VTOR register ******************
SCB_VTOR_TBLOFF EQU 0x1FFFFF80 ; Vector table base offset field
SCB_VTOR_TBLBASE EQU 0x20000000 ; Table base in code(0) or RAM(1)
; ***************** Bit definition for SCB_AIRCR register ******************
SCB_AIRCR_VECTKEY EQU 0x05FA0000 ; Value required to enable write to this register
SCB_AIRCR_VECTRESET EQU 0x00000001 ; System Reset bit
SCB_AIRCR_VECTCLRACTIVE EQU 0x00000002 ; Clear active vector bit
SCB_AIRCR_SYSRESETREQ EQU 0x00000004 ; Requests chip control logic to generate a reset
SCB_AIRCR_PRIGROUP EQU 0x00000700 ; PRIGROUP[2:0] bits (Priority group)
SCB_AIRCR_PRIGROUP_0 EQU 0x00000100 ; Bit 0
SCB_AIRCR_PRIGROUP_1 EQU 0x00000200 ; Bit 1
SCB_AIRCR_PRIGROUP_2 EQU 0x00000400 ; Bit 2
; prority group configuration
SCB_AIRCR_PRIGROUP0 EQU 0x00000000 ; Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)
SCB_AIRCR_PRIGROUP1 EQU 0x00000100 ; Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)
SCB_AIRCR_PRIGROUP2 EQU 0x00000200 ; Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)
SCB_AIRCR_PRIGROUP3 EQU 0x00000300 ; Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)
SCB_AIRCR_PRIGROUP4 EQU 0x00000400 ; Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)
SCB_AIRCR_PRIGROUP5 EQU 0x00000500 ; Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)
SCB_AIRCR_PRIGROUP6 EQU 0x00000600 ; Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)
SCB_AIRCR_PRIGROUP7 EQU 0x00000700 ; Priority group=7 (no pre-emption priority, 8 bits of subpriority)
SCB_AIRCR_ENDIANESS EQU 0x00008000 ; Data endianness bit
SCB_AIRCR_VECTKEY EQU 0xFFFF0000 ; Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)
;****************** Bit definition for SCB_SCR register *******************
SCB_SCR_SLEEPONEXIT EQU 0x02 ; Sleep on exit bit
SCB_SCR_SLEEPDEEP EQU 0x04 ; Sleep deep bit
SCB_SCR_SEVONPEND EQU 0x10 ; Wake up from WFE
;******************* Bit definition for SCB_CCR register ******************
SCB_CCR_NONBASETHRDENA EQU 0x0001 ; Thread mode can be entered from any level in Handler mode by controlled return value
SCB_CCR_USERSETMPEND EQU 0x0002 ; Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception
SCB_CCR_UNALIGN_TRP EQU 0x0008 ; Trap for unaligned access
SCB_CCR_DIV_0_TRP EQU 0x0010 ; Trap on Divide by 0
SCB_CCR_BFHFNMIGN EQU 0x0100 ; Handlers running at priority -1 and -2
SCB_CCR_STKALIGN EQU 0x0200 ; On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned
;****************** Bit definition for SCB_SHPR register *******************
SCB_SHPR_PRI_N EQU 0x000000FF ; Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor
SCB_SHPR_PRI_N1 EQU 0x0000FF00 ; Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved
SCB_SHPR_PRI_N2 EQU 0x00FF0000 ; Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV
SCB_SHPR_PRI_N3 EQU 0xFF000000 ; Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick
;***************** Bit definition for SCB_SHCSR register ******************
SCB_SHCSR_MEMFAULTACT EQU 0x00000001 ; MemManage is active
SCB_SHCSR_BUSFAULTACT EQU 0x00000002 ; BusFault is active
SCB_SHCSR_USGFAULTACT EQU 0x00000008 ; UsageFault is active
SCB_SHCSR_SVCALLACT EQU 0x00000080 ; SVCall is active
SCB_SHCSR_MONITORACT EQU 0x00000100 ; Monitor is active
SCB_SHCSR_PENDSVACT EQU 0x00000400 ; PendSV is active
SCB_SHCSR_SYSTICKACT EQU 0x00000800 ; SysTick is active
SCB_SHCSR_USGFAULTPENDED EQU 0x00001000 ; Usage Fault is pended
SCB_SHCSR_MEMFAULTPENDED EQU 0x00002000 ; MemManage is pended
SCB_SHCSR_BUSFAULTPENDED EQU 0x00004000 ; Bus Fault is pended
SCB_SHCSR_SVCALLPENDED EQU 0x00008000 ; SVCall is pended
SCB_SHCSR_MEMFAULTENA EQU 0x00010000 ; MemManage enable
SCB_SHCSR_BUSFAULTENA EQU 0x00020000 ; Bus Fault enable
SCB_SHCSR_USGFAULTENA EQU 0x00040000 ; UsageFault enable
;****************** Bit definition for SCB_CFSR register ******************
; MFSR
SCB_CFSR_IACCVIOL EQU 0x00000001 ; Instruction access violation
SCB_CFSR_DACCVIOL EQU 0x00000002 ; Data access violation
SCB_CFSR_MUNSTKERR EQU 0x00000008 ; Unstacking error
SCB_CFSR_MSTKERR EQU 0x00000010 ; Stacking error
SCB_CFSR_MMARVALID EQU 0x00000080 ; Memory Manage Address Register address valid flag
; BFSR
SCB_CFSR_IBUSERR EQU 0x00000100 ; Instruction bus error flag
SCB_CFSR_PRECISERR EQU 0x00000200 ; Precise data bus error
SCB_CFSR_IMPRECISERR EQU 0x00000400 ; Imprecise data bus error
SCB_CFSR_UNSTKERR EQU 0x00000800 ; Unstacking error
SCB_CFSR_STKERR EQU 0x00001000 ; Stacking error
SCB_CFSR_BFARVALID EQU 0x00008000 ; Bus Fault Address Register address valid flag
; UFSR
SCB_CFSR_UNDEFINSTR EQU 0x00010000 ; The processor attempt to excecute an undefined instruction
SCB_CFSR_INVSTATE EQU 0x00020000 ; Invalid combination of EPSR and instruction
SCB_CFSR_INVPC EQU 0x00040000 ; Attempt to load EXC_RETURN into pc illegally
SCB_CFSR_NOCP EQU 0x00080000 ; Attempt to use a coprocessor instruction
SCB_CFSR_UNALIGNED EQU 0x01000000 ; Fault occurs when there is an attempt to make an unaligned memory access
SCB_CFSR_DIVBYZERO EQU 0x02000000 ; Fault occurs when SDIV or DIV instruction is used with a divisor of 0
;****************** Bit definition for SCB_HFSR register ******************
SCB_HFSR_VECTTBL EQU 0x00000002 ; Fault occures because of vector table read on exception processing
SCB_HFSR_FORCED EQU 0x40000000 ; Hard Fault activated when a configurable Fault was received and cannot activate
SCB_HFSR_DEBUGEVT EQU 0x80000000 ; Fault related to debug
;****************** Bit definition for SCB_DFSR register ******************
SCB_DFSR_HALTED EQU 0x01 ; Halt request flag
SCB_DFSR_BKPT EQU 0x02 ; BKPT flag
SCB_DFSR_DWTTRAP EQU 0x04 ; Data Watchpoint and Trace (DWT) flag
SCB_DFSR_VCATCH EQU 0x08 ; Vector catch flag
SCB_DFSR_EXTERNAL EQU 0x10 ; External debug request flag
;****************** Bit definition for SCB_MMFAR register *****************
SCB_MMFAR_ADDRESS EQU 0xFFFFFFFF ; Mem Manage fault address field
;****************** Bit definition for SCB_BFAR register ******************
SCB_BFAR_ADDRESS EQU 0xFFFFFFFF ; Bus fault address field
;****************** Bit definition for SCB_afsr register ******************
SCB_AFSR_IMPDEF EQU 0xFFFFFFFF ; Implementation defined
END

61
lib/INI_SYSTICK.s
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@ -0,0 +1,61 @@
;****************************************************************************
; SOUBOR : INI_SYSTICK.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
;
; System Timer (SysTick)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;****************************************************************************
;****************************************************************************
;*
;* REGISTERS
;*
;****************************************************************************
SysTick_CSR EQU (_SCS_BASE + 0x010) ; (R/W) SysTick Control and Status Register
SysTick_RELOAD EQU (_SCS_BASE + 0x014) ; (R/W) SysTick Reload Value Register
SysTick_VAL EQU (_SCS_BASE + 0x018) ; (R/W) SysTick Current Value Register
SysTick_CALIB EQU (_SCS_BASE + 0x01C) ; (R/ ) SysTick Calibration Value Register
;****************************************************************************
;*
;* BIT MASKS AND DEFINITIONS
;*
;****************************************************************************
;**************** Bit definition for SysTick_CSR register ****************
SysTick_CSR_ENABLE EQU 0x00000001 ; Counter enable
SysTick_CSR_TICKINT EQU 0x00000002 ; Enable interrupt when counter reaches zero
SysTick_CSR_CLKSOURCE EQU 0x00000004 ; Clock source (0 - external, 1 - core clock)
SysTick_CSR_CLKSOURCE_CORE EQU 0x00000004 ; Clock source - core clock
SysTick_CSR_CLKSOURCE_DIV8 EQU 0x00000000 ; Clock source - core clock / 8
SysTick_CSR_COUNTFLAG EQU 0x00010000 ; Count Flag (only if interrupt is disabled)
;**************** Bit definition for SysTick_LOAD register ****************
SysTick_RELOAD_MASK EQU 0x00FFFFFF ; Reload value used when the counter reaches 0
;**************** Bit definition for SysTick_VAL register *****************
SysTick_VAL_MASK EQU 0x00FFFFFF ; Current value at the time the register is accessed
;**************** Bit definition for SysTick_CALIB register ***************
SysTick_CALIB_TENMS EQU 0x00FFFFFF ; Reload value to use for 10ms timing
SysTick_CALIB_SKEW EQU 0x40000000 ; Calibration value is not exactly 10 ms
SysTick_CALIB_NOREF EQU 0x80000000 ; The reference clock is not provided
END

12
main.asm
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@ -15,14 +15,14 @@
;***************************************************************************************************
; Register addresses
GET lib/INI_REGS.s
GET lib/INI_BASE.s
GET lib/INI_REGS.s ;deprecated TODO remove when definitions moved to other files
; Bit presets
GET lib/INI_BITS_GPIO.s
GET lib/INI_BITS_RCC.s
GET lib/INI_BITS_FLASH.s
GET lib/INI_BITS_SYSTICK.s
GET lib/INI_BB.s
GET lib/INI_GPIO.s
GET lib/INI_SYSTICK.s
GET lib/INI_BITS_RCC.s ;legacy FIXME
GET lib/INI_BITS_FLASH.s ;legacy FIXME
;***************************************************************************************************

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