Browse Source

Started moving stuff from INI_REGS to separate periph files. Cleaning.

Ondřej Hruška 5 years ago
parent
commit
0812f21fae
10 changed files with 745 additions and 669 deletions
  1. 4 2
      .cproject
  2. 103 0
      lib/INI_BASE.s
  3. 0 240
      lib/INI_BITS_GPIO.s
  4. 0 142
      lib/INI_BITS_SCB.s
  5. 0 38
      lib/INI_BITS_SYSTICK.s
  6. 372 16
      lib/INI_GPIO.s
  7. 0 225
      lib/INI_REGS.s
  8. 199 0
      lib/INI_SCB.s
  9. 61 0
      lib/INI_SYSTICK.s
  10. 6 6
      main.asm

+ 4 - 2
.cproject View File

@@ -13,7 +13,7 @@
13 13
 					<folderInfo id="0.1395987404." name="/" resourcePath="">
14 14
 						<toolChain errorParsers="" id="org.eclipse.cdt.build.core.prefbase.toolchain.201835191" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
15 15
 							<targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.201835191.1247016447" name=""/>
16
-							<builder autoBuildTarget="asm,s" cleanBuildTarget="clean" enableAutoBuild="true" enableCleanBuild="true" enabledIncrementalBuild="true" errorParsers="" id="org.eclipse.cdt.build.core.settings.default.builder.2008815367" incrementalBuildTarget="link" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="false" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
16
+							<builder autoBuildTarget="asm,s" cleanBuildTarget="clean" enableAutoBuild="true" enableCleanBuild="true" enabledIncrementalBuild="true" errorParsers="" id="org.eclipse.cdt.build.core.settings.default.builder.2008815367" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="false" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
17 17
 							<tool errorParsers="" id="org.eclipse.cdt.build.core.settings.holder.libs.1471334506" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
18 18
 							<tool errorParsers="" id="org.eclipse.cdt.build.core.settings.holder.917796934" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
19 19
 								<inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1343808760" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
@@ -42,7 +42,9 @@
42 42
 	</storageModule>
43 43
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
44 44
 	<storageModule moduleId="refreshScope" versionNumber="2">
45
-		<configuration configurationName="Default"/>
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+		<configuration configurationName="Default">
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+			<resource resourceType="PROJECT" workspacePath="/STM32L100-asm-bootstrap"/>
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+		</configuration>
46 48
 	</storageModule>
47 49
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
48 50
 	<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>

+ 103 - 0
lib/INI_BASE.s View File

@@ -0,0 +1,103 @@
1
+;********************************************************************************
2
+; SOUBOR : INI_BASE.S
3
+; AUTOR  : Ondrej Hruska
4
+; DATUM  : 10/2015
5
+; POPIS  : Zakladni soubor knihovny. Musi byt includovat pred vsemi ostatnimi.
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+;          Soubor definuje rozdeleni adresniho prostoru a adresy periferii.
7
+;
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+; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
9
+;********************************************************************************
10
+
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+
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+FLASH_BASE         EQU  0x08000000                 ; FLASH base address in the alias region
13
+SRAM_BASE          EQU  0x20000000                 ; SRAM base address in the alias region
14
+PERIPH_BASE        EQU  0x40000000                 ; Peripheral base address in the alias region
15
+
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+SRAM_BB_BASE       EQU  (SRAM_BASE   + 0x02000000) ; SRAM base address in the bit-band region
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+PERIPH_BB_BASE     EQU  (PERIPH_BASE + 0x02000000) ; Peripheral base address in the bit-band region
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+
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+
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+; ------------------------- System Config Blocks -----------------------------
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+
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+_SCS_BASE          EQU  0xE000E000                 ; System Control Space base
23
+_SCB               EQU  (_SCS_BASE + 0x0D00)       ; System Control Block base
24
+_NVIC              EQU  (_SCS_BASE + 0x0100)       ; Nested Interrupt Vector Controller base
25
+_OB                EQU  0x1FF80000                 ; FLASH Option Bytes base address
26
+_AES               EQU  0x50060000                 ; Encryption module
27
+_FSMC              EQU  0xA0000000                 ; External Memory Control base
28
+_DBGMCU            EQU  0xE0042000                 ; Debug MCU registers base address
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+
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+
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+; ----------------------------- Peripherals ----------------------------------
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+
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+; *** Peripheral bus bases ***
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+_APB1              EQU   PERIPH_BASE               ; Advanced Peripheral Bus 1 base
35
+_APB2              EQU  (PERIPH_BASE + 0x10000)    ; Advanced Peripheral Bus 2 base
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+_AHB               EQU  (PERIPH_BASE + 0x20000)    ; Advanced High-speed Bus base
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+
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+; *** Peripheral Bus 1 devices ***
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+
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+_TIM2              EQU  (_APB1 + 0x0000)           ; Timer bases
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+_TIM3              EQU  (_APB1 + 0x0400)
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+_TIM4              EQU  (_APB1 + 0x0800)
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+_TIM5              EQU  (_APB1 + 0x0C00)
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+_TIM6              EQU  (_APB1 + 0x1000)
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+_TIM7              EQU  (_APB1 + 0x1400)
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+
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+_LCD               EQU  (_APB1 + 0x2400)           ; LCD controller base
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+_RTC               EQU  (_APB1 + 0x2800)           ; RTC base
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+
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+_WWDG              EQU  (_APB1 + 0x2C00)           ; Window Watchdog base
51
+_IWDG              EQU  (_APB1 + 0x3000)           ; Independent Watchdog base
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+
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+_SPI2              EQU  (_APB1 + 0x3800)           ; SPI base
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+_SPI3              EQU  (_APB1 + 0x3C00)
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+
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+_USART2            EQU  (_APB1 + 0x4400)           ; USART base
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+_USART3            EQU  (_APB1 + 0x4800)
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+
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+_UART4             EQU  (_APB1 + 0x4C00)           ; UART base (?)
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+_UART5             EQU  (_APB1 + 0x5000)
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+
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+_I2C1              EQU  (_APB1 + 0x5400)           ; I2C base
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+_I2C2              EQU  (_APB1 + 0x5800)
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+
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+_PWR               EQU  (_APB1 + 0x7000)           ; Power Control block base
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+_DAC               EQU  (_APB1 + 0x7400)           ; D/A config base
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+_COMP              EQU  (_APB1 + 0x7C00)           ; Analog Comparator base
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+_RI                EQU  (_APB1 + 0x7C04)           ; Routing Interface base (analog pin connections)
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+_OPAMP             EQU  (_APB1 + 0x7C5C)           ; OpAmp config base
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+
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+
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+; *** Peripheral Bus 2 devices ***
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+
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+_TIM9              EQU  (_APB2 + 0x0800)           ; Timer base
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+_TIM10             EQU  (_APB2 + 0x0C00)
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+_TIM11             EQU  (_APB2 + 0x1000)
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+
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+_SYSCFG            EQU  (_APB2 + 0x0000)           ; System config block base
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+_EXTI              EQU  (_APB2 + 0x0400)           ; External interrupt settings base
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+
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+_ADC1              EQU  (_APB2 + 0x2400)           ; A/D 1
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+_ADCC              EQU  (_APB2 + 0x2700)           ; common A/D registers base
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+
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+_SDIO              EQU  (_APB2 + 0x2C00)           ; SD host
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+_SPI1              EQU  (_APB2 + 0x3000)           ; SPI
86
+_USART1            EQU  (_APB2 + 0x3800)
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+
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+
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+
90
+; *** High Speed Bus devices ***
91
+
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+_GPIO              EQU  (_AHB + 0x0000)            ; GPIO block base
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+
94
+_CRC               EQU  (_AHB + 0x3000)            ; CRC module base
95
+_RCC               EQU  (_AHB + 0x3800)            ; Reset and Clock Config base
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+
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+_DMA1              EQU  (_AHB + 0x6000)            ; DMA control base
98
+_DMA2              EQU  (_AHB + 0x6400)
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+
100
+_FLASH             EQU  (_AHB + 0x3C00)            ; FLASH control base
101
+
102
+
103
+	END

+ 0 - 240
lib/INI_BITS_GPIO.s View File

@@ -1,240 +0,0 @@
1
-;********************************************************************************
2
-; SOUBOR : INI_BITS_GPIO.S
3
-; AUTOR  : Petr Dousa, Ondrej Hruska
4
-; DATUM  : 10/2015
5
-; POPIS  : Bitove masky ridicich registru pro GPIO (I/O brany)
6
-;
7
-; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
8
-;********************************************************************************
9
-
10
-
11
-;****************************************************************************
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-;
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-;                      General Purpose IOs (GPIO)
14
-;
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-;****************************************************************************
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-
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-; Short pin masks. Valid for OTYPER, IDR and ODR.
18
-GPIO0                   EQU  0x00000001
19
-GPIO1                   EQU  0x00000002
20
-GPIO2                   EQU  0x00000004
21
-GPIO3                   EQU  0x00000008
22
-GPIO4                   EQU  0x00000010
23
-GPIO5                   EQU  0x00000020
24
-GPIO6                   EQU  0x00000040
25
-GPIO7                   EQU  0x00000080
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-GPIO8                   EQU  0x00000100
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-GPIO9                   EQU  0x00000200
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-GPIO10                  EQU  0x00000400
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-GPIO11                  EQU  0x00000800
30
-GPIO12                  EQU  0x00001000
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-GPIO13                  EQU  0x00002000
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-GPIO14                  EQU  0x00004000
33
-GPIO15                  EQU  0x00008000
34
-
35
-; OTYPER pattern masks - use as (GPIO_OTYPER_6 & GPIO_OTYPER_OD)
36
-GPIO_OTYPER_PP          EQU  0x00000000
37
-GPIO_OTYPER_OD          EQU  0xFFFFFFFF
38
-
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-; For completenes, aliases also for OTYPER, ODR and IDR
40
-GPIO_OTYPER_0           EQU  0x00000001
41
-GPIO_OTYPER_1           EQU  0x00000002
42
-GPIO_OTYPER_2           EQU  0x00000004
43
-GPIO_OTYPER_3           EQU  0x00000008
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-GPIO_OTYPER_4           EQU  0x00000010
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-GPIO_OTYPER_5           EQU  0x00000020
46
-GPIO_OTYPER_6           EQU  0x00000040
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-GPIO_OTYPER_7           EQU  0x00000080
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-GPIO_OTYPER_8           EQU  0x00000100
49
-GPIO_OTYPER_9           EQU  0x00000200
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-GPIO_OTYPER_10          EQU  0x00000400
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-GPIO_OTYPER_11          EQU  0x00000800
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-GPIO_OTYPER_12          EQU  0x00001000
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-GPIO_OTYPER_13          EQU  0x00002000
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-GPIO_OTYPER_14          EQU  0x00004000
55
-GPIO_OTYPER_15          EQU  0x00008000
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-
57
-GPIO_ODR_0           EQU  0x00000001
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-GPIO_ODR_1           EQU  0x00000002
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-GPIO_ODR_2           EQU  0x00000004
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-GPIO_ODR_3           EQU  0x00000008
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-GPIO_ODR_4           EQU  0x00000010
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-GPIO_ODR_5           EQU  0x00000020
63
-GPIO_ODR_6           EQU  0x00000040
64
-GPIO_ODR_7           EQU  0x00000080
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-GPIO_ODR_8           EQU  0x00000100
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-GPIO_ODR_9           EQU  0x00000200
67
-GPIO_ODR_10          EQU  0x00000400
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-GPIO_ODR_11          EQU  0x00000800
69
-GPIO_ODR_12          EQU  0x00001000
70
-GPIO_ODR_13          EQU  0x00002000
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-GPIO_ODR_14          EQU  0x00004000
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-GPIO_ODR_15          EQU  0x00008000
73
-
74
-GPIO_IDR_0           EQU  0x00000001
75
-GPIO_IDR_1           EQU  0x00000002
76
-GPIO_IDR_2           EQU  0x00000004
77
-GPIO_IDR_3           EQU  0x00000008
78
-GPIO_IDR_4           EQU  0x00000010
79
-GPIO_IDR_5           EQU  0x00000020
80
-GPIO_IDR_6           EQU  0x00000040
81
-GPIO_IDR_7           EQU  0x00000080
82
-GPIO_IDR_8           EQU  0x00000100
83
-GPIO_IDR_9           EQU  0x00000200
84
-GPIO_IDR_10          EQU  0x00000400
85
-GPIO_IDR_11          EQU  0x00000800
86
-GPIO_IDR_12          EQU  0x00001000
87
-GPIO_IDR_13          EQU  0x00002000
88
-GPIO_IDR_14          EQU  0x00004000
89
-GPIO_IDR_15          EQU  0x00008000
90
-
91
-;******************  Bit definition for GPIO_MODER register  ****************
92
-
93
-; pattern masks. Use as: (GPIO_MODER_0 & GPIO_MODER_OUTPUT)
94
-GPIO_MODER_INPUT        EQU 0x00000000
95
-GPIO_MODER_OUTPUT       EQU 0x55555555
96
-GPIO_MODER_AF           EQU 0xAAAAAAAA
97
-GPIO_MODER_ANALOG       EQU 0xFFFFFFFF
98
-
99
-GPIO_MODER_0       EQU  0x00000003
100
-GPIO_MODER_1       EQU  0x0000000C
101
-GPIO_MODER_2       EQU  0x00000030
102
-GPIO_MODER_3       EQU  0x000000C0
103
-GPIO_MODER_4       EQU  0x00000300
104
-GPIO_MODER_5       EQU  0x00000C00
105
-GPIO_MODER_6       EQU  0x00003000
106
-GPIO_MODER_7       EQU  0x0000C000
107
-GPIO_MODER_8       EQU  0x00030000
108
-GPIO_MODER_9       EQU  0x000C0000
109
-GPIO_MODER_10      EQU  0x00300000
110
-GPIO_MODER_11      EQU  0x00C00000
111
-GPIO_MODER_12      EQU  0x03000000
112
-GPIO_MODER_13      EQU  0x0C000000
113
-GPIO_MODER_14      EQU  0x30000000
114
-GPIO_MODER_15      EQU  0xC0000000
115
-
116
-
117
-;******************  Bit definition for GPIO_OSPEEDR register  **************
118
-
119
-; pattern masks. Use as: (GPIO_OSPEEDR_2 & GPIO_OSPEEDR_LOW)
120
-GPIO_OSPEEDR_LOW          EQU 0x00000000
121
-GPIO_OSPEEDR_MEDIUM       EQU 0x55555555
122
-GPIO_OSPEEDR_HIGH         EQU 0xFFFFFFFF
123
-
124
-GPIO_OSPEEDR_0    EQU  (0x00000003)
125
-GPIO_OSPEEDR_1    EQU  (0x0000000C)
126
-GPIO_OSPEEDR_2    EQU  (0x00000030)
127
-GPIO_OSPEEDR_3    EQU  (0x000000C0)
128
-GPIO_OSPEEDR_4    EQU  (0x00000300)
129
-GPIO_OSPEEDR_5    EQU  (0x00000C00)
130
-GPIO_OSPEEDR_6    EQU  (0x00003000)
131
-GPIO_OSPEEDR_7    EQU  (0x0000C000)
132
-GPIO_OSPEEDR_8    EQU  (0x00030000)
133
-GPIO_OSPEEDR_9    EQU  (0x000C0000)
134
-GPIO_OSPEEDR_10   EQU  (0x00300000)
135
-GPIO_OSPEEDR_11   EQU  (0x00C00000)
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-GPIO_OSPEEDR_12   EQU  (0x03000000)
137
-GPIO_OSPEEDR_13   EQU  (0x0C000000)
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-GPIO_OSPEEDR_14   EQU  (0x30000000)
139
-GPIO_OSPEEDR_15   EQU  (0xC0000000)
140
-
141
-;******************  Bit definition for GPIO_PUPDR register  ****************
142
-
143
-; pattern masks. Use as: (GPIO_PUPDR_6 & GPIO_PUPDR_UP)
144
-GPIO_PUPDR_NONE        EQU 0x00000000
145
-GPIO_PUPDR_UP          EQU 0x55555555
146
-GPIO_PUPDR_DOWN        EQU 0xAAAAAAAA
147
-
148
-GPIO_PUPDR_0    EQU  (0x00000003)
149
-GPIO_PUPDR_1    EQU  (0x0000000C)
150
-GPIO_PUPDR_2    EQU  (0x00000030)
151
-GPIO_PUPDR_3    EQU  (0x000000C0)
152
-GPIO_PUPDR_4    EQU  (0x00000300)
153
-GPIO_PUPDR_5    EQU  (0x00000C00)
154
-GPIO_PUPDR_6    EQU  (0x00003000)
155
-GPIO_PUPDR_7    EQU  (0x0000C000)
156
-GPIO_PUPDR_8    EQU  (0x00030000)
157
-GPIO_PUPDR_9    EQU  (0x000C0000)
158
-GPIO_PUPDR_10   EQU  (0x00300000)
159
-GPIO_PUPDR_11   EQU  (0x00C00000)
160
-GPIO_PUPDR_12   EQU  (0x03000000)
161
-GPIO_PUPDR_13   EQU  (0x0C000000)
162
-GPIO_PUPDR_14   EQU  (0x30000000)
163
-GPIO_PUPDR_15   EQU  (0xC0000000)
164
-
165
-
166
-;******************  Bit definition for GPIO_BSRR register  *****************
167
-GPIO_BSRR_BS_0          EQU  (0x00000001)
168
-GPIO_BSRR_BS_1          EQU  (0x00000002)
169
-GPIO_BSRR_BS_2          EQU  (0x00000004)
170
-GPIO_BSRR_BS_3          EQU  (0x00000008)
171
-GPIO_BSRR_BS_4          EQU  (0x00000010)
172
-GPIO_BSRR_BS_5          EQU  (0x00000020)
173
-GPIO_BSRR_BS_6          EQU  (0x00000040)
174
-GPIO_BSRR_BS_7          EQU  (0x00000080)
175
-GPIO_BSRR_BS_8          EQU  (0x00000100)
176
-GPIO_BSRR_BS_9          EQU  (0x00000200)
177
-GPIO_BSRR_BS_10         EQU  (0x00000400)
178
-GPIO_BSRR_BS_11         EQU  (0x00000800)
179
-GPIO_BSRR_BS_12         EQU  (0x00001000)
180
-GPIO_BSRR_BS_13         EQU  (0x00002000)
181
-GPIO_BSRR_BS_14         EQU  (0x00004000)
182
-GPIO_BSRR_BS_15         EQU  (0x00008000)
183
-
184
-GPIO_BSRR_BR_0          EQU  (0x00010000)
185
-GPIO_BSRR_BR_1          EQU  (0x00020000)
186
-GPIO_BSRR_BR_2          EQU  (0x00040000)
187
-GPIO_BSRR_BR_3          EQU  (0x00080000)
188
-GPIO_BSRR_BR_4          EQU  (0x00100000)
189
-GPIO_BSRR_BR_5          EQU  (0x00200000)
190
-GPIO_BSRR_BR_6          EQU  (0x00400000)
191
-GPIO_BSRR_BR_7          EQU  (0x00800000)
192
-GPIO_BSRR_BR_8          EQU  (0x01000000)
193
-GPIO_BSRR_BR_9          EQU  (0x02000000)
194
-GPIO_BSRR_BR_10         EQU  (0x04000000)
195
-GPIO_BSRR_BR_11         EQU  (0x08000000)
196
-GPIO_BSRR_BR_12         EQU  (0x10000000)
197
-GPIO_BSRR_BR_13         EQU  (0x20000000)
198
-GPIO_BSRR_BR_14         EQU  (0x40000000)
199
-GPIO_BSRR_BR_15         EQU  (0x80000000)
200
-
201
-;******************  Bit definition for GPIO_LCKR register  *****************
202
-GPIO_LCKR_0          EQU  (0x00000001)
203
-GPIO_LCKR_1          EQU  (0x00000002)
204
-GPIO_LCKR_2          EQU  (0x00000004)
205
-GPIO_LCKR_3          EQU  (0x00000008)
206
-GPIO_LCKR_4          EQU  (0x00000010)
207
-GPIO_LCKR_5          EQU  (0x00000020)
208
-GPIO_LCKR_6          EQU  (0x00000040)
209
-GPIO_LCKR_7          EQU  (0x00000080)
210
-GPIO_LCKR_8          EQU  (0x00000100)
211
-GPIO_LCKR_9          EQU  (0x00000200)
212
-GPIO_LCKR_10         EQU  (0x00000400)
213
-GPIO_LCKR_11         EQU  (0x00000800)
214
-GPIO_LCKR_12         EQU  (0x00001000)
215
-GPIO_LCKR_13         EQU  (0x00002000)
216
-GPIO_LCKR_14         EQU  (0x00004000)
217
-GPIO_LCKR_15         EQU  (0x00008000)
218
-GPIO_LCKR_K          EQU  (0x00010000)
219
-
220
-;******************  Bit definition for GPIO_AFRL register  *****************
221
-GPIO_AFRL_0         EQU  (0x0000000F)
222
-GPIO_AFRL_1         EQU  (0x000000F0)
223
-GPIO_AFRL_2         EQU  (0x00000F00)
224
-GPIO_AFRL_3         EQU  (0x0000F000)
225
-GPIO_AFRL_4         EQU  (0x000F0000)
226
-GPIO_AFRL_5         EQU  (0x00F00000)
227
-GPIO_AFRL_6         EQU  (0x0F000000)
228
-GPIO_AFRL_7         EQU  (0xF0000000)
229
-
230
-;******************  Bit definition for GPIO_AFRH register  *****************
231
-GPIO_AFRH_8         EQU  (0x0000000F)
232
-GPIO_AFRH_9         EQU  (0x000000F0)
233
-GPIO_AFRH_10        EQU  (0x00000F00)
234
-GPIO_AFRH_11        EQU  (0x0000F000)
235
-GPIO_AFRH_12        EQU  (0x000F0000)
236
-GPIO_AFRH_13        EQU  (0x00F00000)
237
-GPIO_AFRH_14        EQU  (0x0F000000)
238
-GPIO_AFRH_15        EQU  (0xF0000000)
239
-
240
-	END

+ 0 - 142
lib/INI_BITS_SCB.s View File

@@ -1,142 +0,0 @@
1
-;********************************************************************************
2
-; SOUBOR : INI_BITS_SCB.S
3
-; AUTOR  : Petr Dousa, Ondrej Hruska
4
-; DATUM  : 10/2015
5
-; POPIS  : Bitove masky ridicich registru pro SCB (ovladani systemu + hw info)
6
-;
7
-; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
8
-;********************************************************************************
9
-
10
-
11
-;****************************************************************************
12
-;
13
-;                          System Control Block (SCB)
14
-;
15
-;****************************************************************************
16
-
17
-;*****************  Bit definition for SCB_CPUID register  ******************
18
-SCB_CPUID_REVISION               EQU  0x0000000F        ; Implementation defined revision number
19
-SCB_CPUID_PARTNO                 EQU  0x0000FFF0        ; Number of processor within family
20
-SCB_CPUID_Constant               EQU  0x000F0000        ; Reads as 0x0F
21
-SCB_CPUID_VARIANT                EQU  0x00F00000        ; Implementation defined variant number
22
-SCB_CPUID_IMPLEMENTER            EQU  0xFF000000        ; Implementer code. ARM is 0x41
23
-
24
-;******************  Bit definition for SCB_ICSR register  ******************
25
-SCB_ICSR_VECTACTIVE              EQU  0x000001FF        ; Active ISR number field
26
-SCB_ICSR_RETTOBASE               EQU  0x00000800        ; All active exceptions minus the IPSR_current_exception yields the empty set
27
-SCB_ICSR_VECTPENDING             EQU  0x003FF000        ; Pending ISR number field
28
-SCB_ICSR_ISRPENDING              EQU  0x00400000        ; Interrupt pending flag
29
-SCB_ICSR_ISRPREEMPT              EQU  0x00800000        ; It indicates that a pending interrupt becomes active in the next running cycle
30
-SCB_ICSR_PENDSTCLR               EQU  0x02000000        ; Clear pending SysTick bit
31
-SCB_ICSR_PENDSTSET               EQU  0x04000000        ; Set pending SysTick bit
32
-SCB_ICSR_PENDSVCLR               EQU  0x08000000        ; Clear pending pendSV bit
33
-SCB_ICSR_PENDSVSET               EQU  0x10000000        ; Set pending pendSV bit
34
-SCB_ICSR_NMIPENDSET              EQU  0x80000000        ; Set pending NMI bit
35
-
36
-;******************  Bit definition for SCB_VTOR register  ******************
37
-SCB_VTOR_TBLOFF                  EQU  0x1FFFFF80        ; Vector table base offset field
38
-SCB_VTOR_TBLBASE                 EQU  0x20000000        ; Table base in code(0) or RAM(1)
39
-
40
-; *****************  Bit definition for SCB_AIRCR register  ******************
41
-SCB_AIRCR_VECTKEY                EQU  0x05FA0000        ; Value required to enable write to this register
42
-SCB_AIRCR_VECTRESET              EQU  0x00000001        ; System Reset bit
43
-SCB_AIRCR_VECTCLRACTIVE          EQU  0x00000002        ; Clear active vector bit
44
-SCB_AIRCR_SYSRESETREQ            EQU  0x00000004        ; Requests chip control logic to generate a reset
45
-
46
-SCB_AIRCR_PRIGROUP               EQU  0x00000700        ; PRIGROUP[2:0] bits (Priority group)
47
-SCB_AIRCR_PRIGROUP_0             EQU  0x00000100        ; Bit 0
48
-SCB_AIRCR_PRIGROUP_1             EQU  0x00000200        ; Bit 1
49
-SCB_AIRCR_PRIGROUP_2             EQU  0x00000400        ; Bit 2
50
-
51
-; prority group configuration
52
-SCB_AIRCR_PRIGROUP0              EQU  0x00000000        ; Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)
53
-SCB_AIRCR_PRIGROUP1              EQU  0x00000100        ; Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)
54
-SCB_AIRCR_PRIGROUP2              EQU  0x00000200        ; Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)
55
-SCB_AIRCR_PRIGROUP3              EQU  0x00000300        ; Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)
56
-SCB_AIRCR_PRIGROUP4              EQU  0x00000400        ; Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)
57
-SCB_AIRCR_PRIGROUP5              EQU  0x00000500        ; Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)
58
-SCB_AIRCR_PRIGROUP6              EQU  0x00000600        ; Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)
59
-SCB_AIRCR_PRIGROUP7              EQU  0x00000700        ; Priority group=7 (no pre-emption priority, 8 bits of subpriority)
60
-
61
-SCB_AIRCR_ENDIANESS              EQU  0x00008000        ; Data endianness bit
62
-SCB_AIRCR_VECTKEY                EQU  0xFFFF0000        ; Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)
63
-
64
-;******************  Bit definition for SCB_SCR register  *******************
65
-SCB_SCR_SLEEPONEXIT              EQU  0x02               ; Sleep on exit bit
66
-SCB_SCR_SLEEPDEEP                EQU  0x04               ; Sleep deep bit
67
-SCB_SCR_SEVONPEND                EQU  0x10               ; Wake up from WFE
68
-
69
-;*******************  Bit definition for SCB_CCR register  ******************
70
-SCB_CCR_NONBASETHRDENA           EQU  0x0001            ; Thread mode can be entered from any level in Handler mode by controlled return value
71
-SCB_CCR_USERSETMPEND             EQU  0x0002            ; Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception
72
-SCB_CCR_UNALIGN_TRP              EQU  0x0008            ; Trap for unaligned access
73
-SCB_CCR_DIV_0_TRP                EQU  0x0010            ; Trap on Divide by 0
74
-SCB_CCR_BFHFNMIGN                EQU  0x0100            ; Handlers running at priority -1 and -2
75
-SCB_CCR_STKALIGN                 EQU  0x0200            ; On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned
76
-
77
-;******************  Bit definition for SCB_SHPR register *******************
78
-SCB_SHPR_PRI_N                   EQU  0x000000FF        ; Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor
79
-SCB_SHPR_PRI_N1                  EQU  0x0000FF00        ; Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved
80
-SCB_SHPR_PRI_N2                  EQU  0x00FF0000        ; Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV
81
-SCB_SHPR_PRI_N3                  EQU  0xFF000000        ; Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick
82
-
83
-;*****************  Bit definition for SCB_SHCSR register  ******************
84
-SCB_SHCSR_MEMFAULTACT            EQU  0x00000001        ; MemManage is active
85
-SCB_SHCSR_BUSFAULTACT            EQU  0x00000002        ; BusFault is active
86
-SCB_SHCSR_USGFAULTACT            EQU  0x00000008        ; UsageFault is active
87
-SCB_SHCSR_SVCALLACT              EQU  0x00000080        ; SVCall is active
88
-SCB_SHCSR_MONITORACT             EQU  0x00000100        ; Monitor is active
89
-SCB_SHCSR_PENDSVACT              EQU  0x00000400        ; PendSV is active
90
-SCB_SHCSR_SYSTICKACT             EQU  0x00000800        ; SysTick is active
91
-SCB_SHCSR_USGFAULTPENDED         EQU  0x00001000        ; Usage Fault is pended
92
-SCB_SHCSR_MEMFAULTPENDED         EQU  0x00002000        ; MemManage is pended
93
-SCB_SHCSR_BUSFAULTPENDED         EQU  0x00004000        ; Bus Fault is pended
94
-SCB_SHCSR_SVCALLPENDED           EQU  0x00008000        ; SVCall is pended
95
-SCB_SHCSR_MEMFAULTENA            EQU  0x00010000        ; MemManage enable
96
-SCB_SHCSR_BUSFAULTENA            EQU  0x00020000        ; Bus Fault enable
97
-SCB_SHCSR_USGFAULTENA            EQU  0x00040000        ; UsageFault enable
98
-
99
-;******************  Bit definition for SCB_CFSR register  ******************
100
-; MFSR
101
-SCB_CFSR_IACCVIOL                EQU  0x00000001        ; Instruction access violation
102
-SCB_CFSR_DACCVIOL                EQU  0x00000002        ; Data access violation
103
-SCB_CFSR_MUNSTKERR               EQU  0x00000008        ; Unstacking error
104
-SCB_CFSR_MSTKERR                 EQU  0x00000010        ; Stacking error
105
-SCB_CFSR_MMARVALID               EQU  0x00000080        ; Memory Manage Address Register address valid flag
106
-; BFSR
107
-SCB_CFSR_IBUSERR                 EQU  0x00000100        ; Instruction bus error flag
108
-SCB_CFSR_PRECISERR               EQU  0x00000200        ; Precise data bus error
109
-SCB_CFSR_IMPRECISERR             EQU  0x00000400        ; Imprecise data bus error
110
-SCB_CFSR_UNSTKERR                EQU  0x00000800        ; Unstacking error
111
-SCB_CFSR_STKERR                  EQU  0x00001000        ; Stacking error
112
-SCB_CFSR_BFARVALID               EQU  0x00008000        ; Bus Fault Address Register address valid flag
113
-; UFSR
114
-SCB_CFSR_UNDEFINSTR              EQU  0x00010000        ; The processor attempt to excecute an undefined instruction
115
-SCB_CFSR_INVSTATE                EQU  0x00020000        ; Invalid combination of EPSR and instruction
116
-SCB_CFSR_INVPC                   EQU  0x00040000        ; Attempt to load EXC_RETURN into pc illegally
117
-SCB_CFSR_NOCP                    EQU  0x00080000        ; Attempt to use a coprocessor instruction
118
-SCB_CFSR_UNALIGNED               EQU  0x01000000        ; Fault occurs when there is an attempt to make an unaligned memory access
119
-SCB_CFSR_DIVBYZERO               EQU  0x02000000        ; Fault occurs when SDIV or DIV instruction is used with a divisor of 0
120
-
121
-;******************  Bit definition for SCB_HFSR register  ******************
122
-SCB_HFSR_VECTTBL                 EQU  0x00000002        ; Fault occures because of vector table read on exception processing
123
-SCB_HFSR_FORCED                  EQU  0x40000000        ; Hard Fault activated when a configurable Fault was received and cannot activate
124
-SCB_HFSR_DEBUGEVT                EQU  0x80000000        ; Fault related to debug
125
-
126
-;******************  Bit definition for SCB_DFSR register  ******************
127
-SCB_DFSR_HALTED                  EQU  0x01               ; Halt request flag
128
-SCB_DFSR_BKPT                    EQU  0x02               ; BKPT flag
129
-SCB_DFSR_DWTTRAP                 EQU  0x04               ; Data Watchpoint and Trace (DWT) flag
130
-SCB_DFSR_VCATCH                  EQU  0x08               ; Vector catch flag
131
-SCB_DFSR_EXTERNAL                EQU  0x10               ; External debug request flag
132
-
133
-;******************  Bit definition for SCB_MMFAR register  *****************
134
-SCB_MMFAR_ADDRESS                EQU  0xFFFFFFFF        ; Mem Manage fault address field
135
-
136
-;******************  Bit definition for SCB_BFAR register  ******************
137
-SCB_BFAR_ADDRESS                 EQU  0xFFFFFFFF        ; Bus fault address field
138
-
139
-;******************  Bit definition for SCB_afsr register  ******************
140
-SCB_AFSR_IMPDEF                  EQU  0xFFFFFFFF        ; Implementation defined
141
-
142
-	END

+ 0 - 38
lib/INI_BITS_SYSTICK.s View File

@@ -1,38 +0,0 @@
1
-;********************************************************************************
2
-; SOUBOR : INI_BITS_SYSTICK.S
3
-; AUTOR  : Petr Dousa, Ondrej Hruska
4
-; DATUM  : 10/2015
5
-; POPIS  : Bitove masky ridicich registru pro SYSTICK (casovac pro RTOS)
6
-;
7
-; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
8
-;********************************************************************************
9
-
10
-
11
-;****************************************************************************
12
-;
13
-;                        SystemTick (SysTick)
14
-;
15
-;****************************************************************************
16
-
17
-;****************  Bit definition for SysTick_CSR register  ****************
18
-SysTick_CSR_ENABLE              EQU  0x00000001        ; Counter enable
19
-SysTick_CSR_TICKINT             EQU  0x00000002        ; Enable interrupt when counter reaches zero
20
-SysTick_CSR_CLKSOURCE           EQU  0x00000004        ; Clock source (0 - external, 1 - core clock)
21
-
22
-SysTick_CSR_CLKSOURCE_CORE      EQU  0x00000004        ; Clock source - core clock
23
-SysTick_CSR_CLKSOURCE_DIV8      EQU  0x00000000        ; Clock source - core clock / 8
24
-
25
-SysTick_CSR_COUNTFLAG           EQU  0x00010000        ; Count Flag (only if interrupt is disabled)
26
-
27
-;****************  Bit definition for SysTick_LOAD register  ****************
28
-SysTick_RELOAD_MASK               EQU  0x00FFFFFF        ; Value to load into the SysTick Current Value Register when the counter reaches 0
29
-
30
-;****************  Bit definition for SysTick_VAL register  *****************
31
-SysTick_VAL_MASK                EQU  0x00FFFFFF        ; Current value at the time the register is accessed
32
-
33
-;****************  Bit definition for SysTick_CALIB register  ***************
34
-SysTick_CALIB_TENMS             EQU  0x00FFFFFF        ; Reload value to use for 10ms timing
35
-SysTick_CALIB_SKEW              EQU  0x40000000        ; Calibration value is not exactly 10 ms
36
-SysTick_CALIB_NOREF             EQU  0x80000000        ; The reference clock is not provided
37
-
38
-	END

lib/INI_BB.s → lib/INI_GPIO.s View File

@@ -1,14 +1,370 @@
1
-;********************************************************************************
2
-; SOUBOR : INI_BB.S
3
-; AUTOR  : Ondrej Hruska
1
+;****************************************************************************
2
+; SOUBOR : INI_GPIO.S
3
+; AUTOR  : Petr Dousa, Ondrej Hruska
4 4
 ; DATUM  : 10/2015
5
-; POPIS  : Adresy bit-bandingovych registru
5
+;
6
+;                        General Purpose IOs (GPIO)
6 7
 ;
7 8
 ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
8
-;********************************************************************************
9
-
10
-
11
-; ======================== GPIO BITS ===========================
9
+;****************************************************************************
10
+
11
+
12
+;****************************************************************************
13
+;*
14
+;*                               REGISTERS
15
+;*
16
+;****************************************************************************
17
+
18
+
19
+_GPIOA           EQU  (_GPIO + 0x0000)
20
+_GPIOB           EQU  (_GPIO + 0x0400)
21
+_GPIOC           EQU  (_GPIO + 0x0800)
22
+_GPIOD           EQU  (_GPIO + 0x0C00)
23
+_GPIOE           EQU  (_GPIO + 0x1000)
24
+_GPIOH           EQU  (_GPIO + 0x1400)
25
+_GPIOF           EQU  (_GPIO + 0x1800)
26
+_GPIOG           EQU  (_GPIO + 0x1C00)
27
+
28
+GPIOA_MODER      EQU  (_GPIOA + 0x00)              ; GPIOA pin mode register,
29
+GPIOA_OTYPER     EQU  (_GPIOA + 0x04)              ; GPIOA output type register,
30
+GPIOA_OSPEEDR    EQU  (_GPIOA + 0x08)              ; GPIOA output speed register,
31
+GPIOA_PUPDR      EQU  (_GPIOA + 0x0C)              ; GPIOA pull-up/pull-down register,
32
+GPIOA_IDR        EQU  (_GPIOA + 0x10)              ; GPIOA input data register,
33
+GPIOA_ODR        EQU  (_GPIOA + 0x14)              ; GPIOA output data register,
34
+GPIOA_BSRR       EQU  (_GPIOA + 0x18)              ; GPIOA bit set/reset register,
35
+GPIOA_LCKR       EQU  (_GPIOA + 0x1C)              ; GPIOA configuration lock register,
36
+GPIOA_AFRL       EQU  (_GPIOA + 0x20)              ; GPIOA alternate function low register,
37
+GPIOA_AFRH       EQU  (_GPIOA + 0x24)              ; GPIOA alternate function low register,
38
+GPIOA_BRR        EQU  (_GPIOA + 0x28)              ; GPIOA bit reset register,
39
+
40
+GPIOB_MODER      EQU  (_GPIOB + 0x00)              ; GPIOB pin mode register,
41
+GPIOB_OTYPER     EQU  (_GPIOB + 0x04)              ; GPIOB output type register,
42
+GPIOB_OSPEEDR    EQU  (_GPIOB + 0x08)              ; GPIOB output speed register,
43
+GPIOB_PUPDR      EQU  (_GPIOB + 0x0C)              ; GPIOB pull-up/pull-down register,
44
+GPIOB_IDR        EQU  (_GPIOB + 0x10)              ; GPIOB input data register,
45
+GPIOB_ODR        EQU  (_GPIOB + 0x14)              ; GPIOB output data register,
46
+GPIOB_BSRR       EQU  (_GPIOB + 0x18)              ; GPIOB bit set/reset register,
47
+GPIOB_LCKR       EQU  (_GPIOB + 0x1C)              ; GPIOB configuration lock register,
48
+GPIOB_AFR        EQU  (_GPIOB + 0x20)              ; GPIOB alternate function low register,
49
+GPIOB_BRR        EQU  (_GPIOB + 0x28)              ; GPIOB bit reset register,
50
+
51
+GPIOC_MODER      EQU  (_GPIOC + 0x00)              ; GPIOC pin mode register,
52
+GPIOC_OTYPER     EQU  (_GPIOC + 0x04)              ; GPIOC output type register,
53
+GPIOC_OSPEEDR    EQU  (_GPIOC + 0x08)              ; GPIOC output speed register,
54
+GPIOC_PUPDR      EQU  (_GPIOC + 0x0C)              ; GPIOC pull-up/pull-down register,
55
+GPIOC_IDR        EQU  (_GPIOC + 0x10)              ; GPIOC input data register,
56
+GPIOC_ODR        EQU  (_GPIOC + 0x14)              ; GPIOC output data register,
57
+GPIOC_BSRR       EQU  (_GPIOC + 0x18)              ; GPIOC bit set/reset register,
58
+GPIOC_LCKR       EQU  (_GPIOC + 0x1C)              ; GPIOC configuration lock register,
59
+GPIOC_AFR        EQU  (_GPIOC + 0x20)              ; GPIOC alternate function low register,
60
+GPIOC_BRR        EQU  (_GPIOC + 0x28)              ; GPIOC bit reset register,
61
+
62
+GPIOD_MODER      EQU  (_GPIOD + 0x00)              ; GPIOD pin mode register,
63
+GPIOD_OTYPER     EQU  (_GPIOD + 0x04)              ; GPIOD output type register,
64
+GPIOD_OSPEEDR    EQU  (_GPIOD + 0x08)              ; GPIOD output speed register,
65
+GPIOD_PUPDR      EQU  (_GPIOD + 0x0C)              ; GPIOD pull-up/pull-down register,
66
+GPIOD_IDR        EQU  (_GPIOD + 0x10)              ; GPIOD input data register,
67
+GPIOD_ODR        EQU  (_GPIOD + 0x14)              ; GPIOD output data register,
68
+GPIOD_BSRR       EQU  (_GPIOD + 0x18)              ; GPIOD bit set/reset register,
69
+GPIOD_LCKR       EQU  (_GPIOD + 0x1C)              ; GPIOD configuration lock register,
70
+GPIOD_AFR        EQU  (_GPIOD + 0x20)              ; GPIOD alternate function low register,
71
+GPIOD_BRR        EQU  (_GPIOD + 0x28)              ; GPIOD bit reset register,
72
+
73
+GPIOE_MODER      EQU  (_GPIOE + 0x00)              ; GPIOE pin mode register,
74
+GPIOE_OTYPER     EQU  (_GPIOE + 0x04)              ; GPIOE output type register,
75
+GPIOE_OSPEEDR    EQU  (_GPIOE + 0x08)              ; GPIOE output speed register,
76
+GPIOE_PUPDR      EQU  (_GPIOE + 0x0C)              ; GPIOE pull-up/pull-down register,
77
+GPIOE_IDR        EQU  (_GPIOE + 0x10)              ; GPIOE input data register,
78
+GPIOE_ODR        EQU  (_GPIOE + 0x14)              ; GPIOE output data register,
79
+GPIOE_BSRR       EQU  (_GPIOE + 0x18)              ; GPIOE bit set/reset register,
80
+GPIOE_LCKR       EQU  (_GPIOE + 0x1C)              ; GPIOE configuration lock register,
81
+GPIOE_AFR        EQU  (_GPIOE + 0x20)              ; GPIOE alternate function low register,
82
+GPIOE_BRR        EQU  (_GPIOE + 0x28)              ; GPIOE bit reset register,
83
+
84
+GPIOF_MODER      EQU  (_GPIOF + 0x00)              ; GPIOF pin mode register,
85
+GPIOF_OTYPER     EQU  (_GPIOF + 0x04)              ; GPIOF output type register,
86
+GPIOF_OSPEEDR    EQU  (_GPIOF + 0x08)              ; GPIOF output speed register,
87
+GPIOF_PUPDR      EQU  (_GPIOF + 0x0C)              ; GPIOF pull-up/pull-down register,
88
+GPIOF_IDR        EQU  (_GPIOF + 0x10)              ; GPIOF input data register,
89
+GPIOF_ODR        EQU  (_GPIOF + 0x14)              ; GPIOF output data register,
90
+GPIOF_BSRR       EQU  (_GPIOF + 0x18)              ; GPIOF bit set/reset register,
91
+GPIOF_LCKR       EQU  (_GPIOF + 0x1C)              ; GPIOF configuration lock register,
92
+GPIOF_AFR        EQU  (_GPIOF + 0x20)              ; GPIOF alternate function low register,
93
+GPIOF_BRR        EQU  (_GPIOF + 0x28)              ; GPIOF bit reset register,
94
+
95
+GPIOG_MODER      EQU  (_GPIOG + 0x00)              ; GPIOG pin mode register,
96
+GPIOG_OTYPER     EQU  (_GPIOG + 0x04)              ; GPIOG output type register,
97
+GPIOG_OSPEEDR    EQU  (_GPIOG + 0x08)              ; GPIOG output speed register,
98
+GPIOG_PUPDR      EQU  (_GPIOG + 0x0C)              ; GPIOG pull-up/pull-down register,
99
+GPIOG_IDR        EQU  (_GPIOG + 0x10)              ; GPIOG input data register,
100
+GPIOG_ODR        EQU  (_GPIOG + 0x14)              ; GPIOG output data register,
101
+GPIOG_BSRR       EQU  (_GPIOG + 0x18)              ; GPIOG bit set/reset register,
102
+GPIOG_LCKR       EQU  (_GPIOG + 0x1C)              ; GPIOG configuration lock register,
103
+GPIOG_AFR        EQU  (_GPIOG + 0x20)              ; GPIOG alternate function low register,
104
+GPIOG_BRR        EQU  (_GPIOG + 0x28)              ; GPIOG bit reset register,
105
+
106
+GPIOH_MODER      EQU  (_GPIOH + 0x00)              ; GPIOH pin mode register,
107
+GPIOH_OTYPER     EQU  (_GPIOH + 0x04)              ; GPIOH output type register,
108
+GPIOH_OSPEEDR    EQU  (_GPIOH + 0x08)              ; GPIOH output speed register,
109
+GPIOH_PUPDR      EQU  (_GPIOH + 0x0C)              ; GPIOH pull-up/pull-down register,
110
+GPIOH_IDR        EQU  (_GPIOH + 0x10)              ; GPIOH input data register,
111
+GPIOH_ODR        EQU  (_GPIOH + 0x14)              ; GPIOH output data register,
112
+GPIOH_BSRR       EQU  (_GPIOH + 0x18)              ; GPIOH bit set/reset register,
113
+GPIOH_LCKR       EQU  (_GPIOH + 0x1C)              ; GPIOH configuration lock register,
114
+GPIOH_AFR        EQU  (_GPIOH + 0x20)              ; GPIOH alternate function low register,
115
+GPIOH_BRR        EQU  (_GPIOH + 0x28)              ; GPIOH bit reset register,
116
+
117
+
118
+
119
+;****************************************************************************
120
+;*
121
+;*                        BIT MASKS AND DEFINITIONS
122
+;*
123
+;****************************************************************************
124
+
125
+
126
+; Short pin masks. Valid for OTYPER, IDR and ODR.
127
+
128
+GPIO0                   EQU  0x00000001
129
+GPIO1                   EQU  0x00000002
130
+GPIO2                   EQU  0x00000004
131
+GPIO3                   EQU  0x00000008
132
+GPIO4                   EQU  0x00000010
133
+GPIO5                   EQU  0x00000020
134
+GPIO6                   EQU  0x00000040
135
+GPIO7                   EQU  0x00000080
136
+GPIO8                   EQU  0x00000100
137
+GPIO9                   EQU  0x00000200
138
+GPIO10                  EQU  0x00000400
139
+GPIO11                  EQU  0x00000800
140
+GPIO12                  EQU  0x00001000
141
+GPIO13                  EQU  0x00002000
142
+GPIO14                  EQU  0x00004000
143
+GPIO15                  EQU  0x00008000
144
+
145
+; OTYPER pattern masks - use as (GPIO_OTYPER_6 & GPIO_OTYPER_OD)
146
+
147
+GPIO_OTYPER_PP          EQU  0x00000000
148
+GPIO_OTYPER_OD          EQU  0xFFFFFFFF
149
+
150
+; For completenes, aliases also for OTYPER, ODR and IDR
151
+
152
+GPIO_OTYPER_0           EQU  0x00000001
153
+GPIO_OTYPER_1           EQU  0x00000002
154
+GPIO_OTYPER_2           EQU  0x00000004
155
+GPIO_OTYPER_3           EQU  0x00000008
156
+GPIO_OTYPER_4           EQU  0x00000010
157
+GPIO_OTYPER_5           EQU  0x00000020
158
+GPIO_OTYPER_6           EQU  0x00000040
159
+GPIO_OTYPER_7           EQU  0x00000080
160
+GPIO_OTYPER_8           EQU  0x00000100
161
+GPIO_OTYPER_9           EQU  0x00000200
162
+GPIO_OTYPER_10          EQU  0x00000400
163
+GPIO_OTYPER_11          EQU  0x00000800
164
+GPIO_OTYPER_12          EQU  0x00001000
165
+GPIO_OTYPER_13          EQU  0x00002000
166
+GPIO_OTYPER_14          EQU  0x00004000
167
+GPIO_OTYPER_15          EQU  0x00008000
168
+
169
+GPIO_ODR_0           EQU  0x00000001
170
+GPIO_ODR_1           EQU  0x00000002
171
+GPIO_ODR_2           EQU  0x00000004
172
+GPIO_ODR_3           EQU  0x00000008
173
+GPIO_ODR_4           EQU  0x00000010
174
+GPIO_ODR_5           EQU  0x00000020
175
+GPIO_ODR_6           EQU  0x00000040
176
+GPIO_ODR_7           EQU  0x00000080
177
+GPIO_ODR_8           EQU  0x00000100
178
+GPIO_ODR_9           EQU  0x00000200
179
+GPIO_ODR_10          EQU  0x00000400
180
+GPIO_ODR_11          EQU  0x00000800
181
+GPIO_ODR_12          EQU  0x00001000
182
+GPIO_ODR_13          EQU  0x00002000
183
+GPIO_ODR_14          EQU  0x00004000
184
+GPIO_ODR_15          EQU  0x00008000
185
+
186
+GPIO_IDR_0           EQU  0x00000001
187
+GPIO_IDR_1           EQU  0x00000002
188
+GPIO_IDR_2           EQU  0x00000004
189
+GPIO_IDR_3           EQU  0x00000008
190
+GPIO_IDR_4           EQU  0x00000010
191
+GPIO_IDR_5           EQU  0x00000020
192
+GPIO_IDR_6           EQU  0x00000040
193
+GPIO_IDR_7           EQU  0x00000080
194
+GPIO_IDR_8           EQU  0x00000100
195
+GPIO_IDR_9           EQU  0x00000200
196
+GPIO_IDR_10          EQU  0x00000400
197
+GPIO_IDR_11          EQU  0x00000800
198
+GPIO_IDR_12          EQU  0x00001000
199
+GPIO_IDR_13          EQU  0x00002000
200
+GPIO_IDR_14          EQU  0x00004000
201
+GPIO_IDR_15          EQU  0x00008000
202
+
203
+
204
+;******************  Bit definition for GPIO_MODER register  ****************
205
+
206
+; pattern masks. Use as: (GPIO_MODER_0 & GPIO_MODER_OUTPUT)
207
+GPIO_MODER_INPUT        EQU 0x00000000
208
+GPIO_MODER_OUTPUT       EQU 0x55555555
209
+GPIO_MODER_AF           EQU 0xAAAAAAAA
210
+GPIO_MODER_ANALOG       EQU 0xFFFFFFFF
211
+
212
+GPIO_MODER_0       EQU  0x00000003
213
+GPIO_MODER_1       EQU  0x0000000C
214
+GPIO_MODER_2       EQU  0x00000030
215
+GPIO_MODER_3       EQU  0x000000C0
216
+GPIO_MODER_4       EQU  0x00000300
217
+GPIO_MODER_5       EQU  0x00000C00
218
+GPIO_MODER_6       EQU  0x00003000
219
+GPIO_MODER_7       EQU  0x0000C000
220
+GPIO_MODER_8       EQU  0x00030000
221
+GPIO_MODER_9       EQU  0x000C0000
222
+GPIO_MODER_10      EQU  0x00300000
223
+GPIO_MODER_11      EQU  0x00C00000
224
+GPIO_MODER_12      EQU  0x03000000
225
+GPIO_MODER_13      EQU  0x0C000000
226
+GPIO_MODER_14      EQU  0x30000000
227
+GPIO_MODER_15      EQU  0xC0000000
228
+
229
+
230
+;******************  Bit definition for GPIO_OSPEEDR register  **************
231
+
232
+; pattern masks. Use as: (GPIO_OSPEEDR_2 & GPIO_OSPEEDR_LOW)
233
+GPIO_OSPEEDR_LOW          EQU 0x00000000
234
+GPIO_OSPEEDR_MEDIUM       EQU 0x55555555
235
+GPIO_OSPEEDR_HIGH         EQU 0xFFFFFFFF
236
+
237
+GPIO_OSPEEDR_0    EQU  (0x00000003)
238
+GPIO_OSPEEDR_1    EQU  (0x0000000C)
239
+GPIO_OSPEEDR_2    EQU  (0x00000030)
240
+GPIO_OSPEEDR_3    EQU  (0x000000C0)
241
+GPIO_OSPEEDR_4    EQU  (0x00000300)
242
+GPIO_OSPEEDR_5    EQU  (0x00000C00)
243
+GPIO_OSPEEDR_6    EQU  (0x00003000)
244
+GPIO_OSPEEDR_7    EQU  (0x0000C000)
245
+GPIO_OSPEEDR_8    EQU  (0x00030000)
246
+GPIO_OSPEEDR_9    EQU  (0x000C0000)
247
+GPIO_OSPEEDR_10   EQU  (0x00300000)
248
+GPIO_OSPEEDR_11   EQU  (0x00C00000)
249
+GPIO_OSPEEDR_12   EQU  (0x03000000)
250
+GPIO_OSPEEDR_13   EQU  (0x0C000000)
251
+GPIO_OSPEEDR_14   EQU  (0x30000000)
252
+GPIO_OSPEEDR_15   EQU  (0xC0000000)
253
+
254
+
255
+;******************  Bit definition for GPIO_PUPDR register  ****************
256
+
257
+; pattern masks. Use as: (GPIO_PUPDR_6 & GPIO_PUPDR_UP)
258
+GPIO_PUPDR_NONE        EQU 0x00000000
259
+GPIO_PUPDR_UP          EQU 0x55555555
260
+GPIO_PUPDR_DOWN        EQU 0xAAAAAAAA
261
+
262
+GPIO_PUPDR_0    EQU  (0x00000003)
263
+GPIO_PUPDR_1    EQU  (0x0000000C)
264
+GPIO_PUPDR_2    EQU  (0x00000030)
265
+GPIO_PUPDR_3    EQU  (0x000000C0)
266
+GPIO_PUPDR_4    EQU  (0x00000300)
267
+GPIO_PUPDR_5    EQU  (0x00000C00)
268
+GPIO_PUPDR_6    EQU  (0x00003000)
269
+GPIO_PUPDR_7    EQU  (0x0000C000)
270
+GPIO_PUPDR_8    EQU  (0x00030000)
271
+GPIO_PUPDR_9    EQU  (0x000C0000)
272
+GPIO_PUPDR_10   EQU  (0x00300000)
273
+GPIO_PUPDR_11   EQU  (0x00C00000)
274
+GPIO_PUPDR_12   EQU  (0x03000000)
275
+GPIO_PUPDR_13   EQU  (0x0C000000)
276
+GPIO_PUPDR_14   EQU  (0x30000000)
277
+GPIO_PUPDR_15   EQU  (0xC0000000)
278
+
279
+
280
+;******************  Bit definition for GPIO_BSRR register  *****************
281
+
282
+GPIO_BSRR_BS_0          EQU  (0x00000001)
283
+GPIO_BSRR_BS_1          EQU  (0x00000002)
284
+GPIO_BSRR_BS_2          EQU  (0x00000004)
285
+GPIO_BSRR_BS_3          EQU  (0x00000008)
286
+GPIO_BSRR_BS_4          EQU  (0x00000010)
287
+GPIO_BSRR_BS_5          EQU  (0x00000020)
288
+GPIO_BSRR_BS_6          EQU  (0x00000040)
289
+GPIO_BSRR_BS_7          EQU  (0x00000080)
290
+GPIO_BSRR_BS_8          EQU  (0x00000100)
291
+GPIO_BSRR_BS_9          EQU  (0x00000200)
292
+GPIO_BSRR_BS_10         EQU  (0x00000400)
293
+GPIO_BSRR_BS_11         EQU  (0x00000800)
294
+GPIO_BSRR_BS_12         EQU  (0x00001000)
295
+GPIO_BSRR_BS_13         EQU  (0x00002000)
296
+GPIO_BSRR_BS_14         EQU  (0x00004000)
297
+GPIO_BSRR_BS_15         EQU  (0x00008000)
298
+
299
+GPIO_BSRR_BR_0          EQU  (0x00010000)
300
+GPIO_BSRR_BR_1          EQU  (0x00020000)
301
+GPIO_BSRR_BR_2          EQU  (0x00040000)
302
+GPIO_BSRR_BR_3          EQU  (0x00080000)
303
+GPIO_BSRR_BR_4          EQU  (0x00100000)
304
+GPIO_BSRR_BR_5          EQU  (0x00200000)
305
+GPIO_BSRR_BR_6          EQU  (0x00400000)
306
+GPIO_BSRR_BR_7          EQU  (0x00800000)
307
+GPIO_BSRR_BR_8          EQU  (0x01000000)
308
+GPIO_BSRR_BR_9          EQU  (0x02000000)
309
+GPIO_BSRR_BR_10         EQU  (0x04000000)
310
+GPIO_BSRR_BR_11         EQU  (0x08000000)
311
+GPIO_BSRR_BR_12         EQU  (0x10000000)
312
+GPIO_BSRR_BR_13         EQU  (0x20000000)
313
+GPIO_BSRR_BR_14         EQU  (0x40000000)
314
+GPIO_BSRR_BR_15         EQU  (0x80000000)
315
+
316
+
317
+;******************  Bit definition for GPIO_LCKR register  *****************
318
+
319
+GPIO_LCKR_0          EQU  (0x00000001)
320
+GPIO_LCKR_1          EQU  (0x00000002)
321
+GPIO_LCKR_2          EQU  (0x00000004)
322
+GPIO_LCKR_3          EQU  (0x00000008)
323
+GPIO_LCKR_4          EQU  (0x00000010)
324
+GPIO_LCKR_5          EQU  (0x00000020)
325
+GPIO_LCKR_6          EQU  (0x00000040)
326
+GPIO_LCKR_7          EQU  (0x00000080)
327
+GPIO_LCKR_8          EQU  (0x00000100)
328
+GPIO_LCKR_9          EQU  (0x00000200)
329
+GPIO_LCKR_10         EQU  (0x00000400)
330
+GPIO_LCKR_11         EQU  (0x00000800)
331
+GPIO_LCKR_12         EQU  (0x00001000)
332
+GPIO_LCKR_13         EQU  (0x00002000)
333
+GPIO_LCKR_14         EQU  (0x00004000)
334
+GPIO_LCKR_15         EQU  (0x00008000)
335
+GPIO_LCKR_K          EQU  (0x00010000)
336
+
337
+
338
+;******************  Bit definition for GPIO_AFRL register  *****************
339
+
340
+GPIO_AFRL_0         EQU  (0x0000000F)
341
+GPIO_AFRL_1         EQU  (0x000000F0)
342
+GPIO_AFRL_2         EQU  (0x00000F00)
343
+GPIO_AFRL_3         EQU  (0x0000F000)
344
+GPIO_AFRL_4         EQU  (0x000F0000)
345
+GPIO_AFRL_5         EQU  (0x00F00000)
346
+GPIO_AFRL_6         EQU  (0x0F000000)
347
+GPIO_AFRL_7         EQU  (0xF0000000)
348
+
349
+
350
+;******************  Bit definition for GPIO_AFRH register  *****************
351
+
352
+GPIO_AFRH_8         EQU  (0x0000000F)
353
+GPIO_AFRH_9         EQU  (0x000000F0)
354
+GPIO_AFRH_10        EQU  (0x00000F00)
355
+GPIO_AFRH_11        EQU  (0x0000F000)
356
+GPIO_AFRH_12        EQU  (0x000F0000)
357
+GPIO_AFRH_13        EQU  (0x00F00000)
358
+GPIO_AFRH_14        EQU  (0x0F000000)
359
+GPIO_AFRH_15        EQU  (0xF0000000)
360
+
361
+
362
+
363
+;****************************************************************************
364
+;*
365
+;*                         BIT BANDING REGISTERS
366
+;*
367
+;****************************************************************************
12 368
 
13 369
 ; ---------------------- IDR ----------------------
14 370
 
@@ -374,7 +730,7 @@ BB_GPIOA_LCKR_12        EQU  _BB_GPIOA_LCKR + (4 * 12)
374 730
 BB_GPIOA_LCKR_13        EQU  _BB_GPIOA_LCKR + (4 * 13)
375 731
 BB_GPIOA_LCKR_14        EQU  _BB_GPIOA_LCKR + (4 * 14)
376 732
 BB_GPIOA_LCKR_15        EQU  _BB_GPIOA_LCKR + (4 * 15)
377
-BB_GPIOA_LCKR_K         EQU  _BB_GPIOA_LCKR + (4 * 16) ; Lock key bit
733
+BB_GPIOA_LCKR_K         EQU  _BB_GPIOA_LCKR + (4 * 16); Lock key bit
378 734
 
379 735
 
380 736
 ; LCKR B
@@ -396,7 +752,7 @@ BB_GPIOB_LCKR_12        EQU  _BB_GPIOB_LCKR + (4 * 12)
396 752
 BB_GPIOB_LCKR_13        EQU  _BB_GPIOB_LCKR + (4 * 13)
397 753
 BB_GPIOB_LCKR_14        EQU  _BB_GPIOB_LCKR + (4 * 14)
398 754
 BB_GPIOB_LCKR_15        EQU  _BB_GPIOB_LCKR + (4 * 15)
399
-BB_GPIOB_LCKR_K         EQU  _BB_GPIOB_LCKR + (4 * 16) ; Lock key bit
755
+BB_GPIOB_LCKR_K         EQU  _BB_GPIOB_LCKR + (4 * 16); Lock key bit
400 756
 
401 757
 
402 758
 ; LCKR C
@@ -418,7 +774,7 @@ BB_GPIOC_LCKR_12        EQU  _BB_GPIOC_LCKR + (4 * 12)
418 774
 BB_GPIOC_LCKR_13        EQU  _BB_GPIOC_LCKR + (4 * 13)
419 775
 BB_GPIOC_LCKR_14        EQU  _BB_GPIOC_LCKR + (4 * 14)
420 776
 BB_GPIOC_LCKR_15        EQU  _BB_GPIOC_LCKR + (4 * 15)
421
-BB_GPIOC_LCKR_K         EQU  _BB_GPIOC_LCKR + (4 * 16) ; Lock key bit
777
+BB_GPIOC_LCKR_K         EQU  _BB_GPIOC_LCKR + (4 * 16); Lock key bit
422 778
 
423 779
 
424 780
 ; LCKR D
@@ -440,7 +796,7 @@ BB_GPIOD_LCKR_12        EQU  _BB_GPIOD_LCKR + (4 * 12)
440 796
 BB_GPIOD_LCKR_13        EQU  _BB_GPIOD_LCKR + (4 * 13)
441 797
 BB_GPIOD_LCKR_14        EQU  _BB_GPIOD_LCKR + (4 * 14)
442 798
 BB_GPIOD_LCKR_15        EQU  _BB_GPIOD_LCKR + (4 * 15)
443
-BB_GPIOD_LCKR_K         EQU  _BB_GPIOD_LCKR + (4 * 16) ; Lock key bit
799
+BB_GPIOD_LCKR_K         EQU  _BB_GPIOD_LCKR + (4 * 16); Lock key bit
444 800
 
445 801
 
446 802
 ; LCKR E
@@ -462,7 +818,7 @@ BB_GPIOE_LCKR_12        EQU  _BB_GPIOE_LCKR + (4 * 12)
462 818
 BB_GPIOE_LCKR_13        EQU  _BB_GPIOE_LCKR + (4 * 13)
463 819
 BB_GPIOE_LCKR_14        EQU  _BB_GPIOE_LCKR + (4 * 14)
464 820
 BB_GPIOE_LCKR_15        EQU  _BB_GPIOE_LCKR + (4 * 15)
465
-BB_GPIOE_LCKR_K         EQU  _BB_GPIOE_LCKR + (4 * 16) ; Lock key bit
821
+BB_GPIOE_LCKR_K         EQU  _BB_GPIOE_LCKR + (4 * 16); Lock key bit
466 822
 
467 823
 
468 824
 ; LCKR F
@@ -484,7 +840,7 @@ BB_GPIOF_LCKR_12        EQU  _BB_GPIOF_LCKR + (4 * 12)
484 840
 BB_GPIOF_LCKR_13        EQU  _BB_GPIOF_LCKR + (4 * 13)
485 841
 BB_GPIOF_LCKR_14        EQU  _BB_GPIOF_LCKR + (4 * 14)
486 842
 BB_GPIOF_LCKR_15        EQU  _BB_GPIOF_LCKR + (4 * 15)
487
-BB_GPIOF_LCKR_K         EQU  _BB_GPIOF_LCKR + (4 * 16) ; Lock key bit
843
+BB_GPIOF_LCKR_K         EQU  _BB_GPIOF_LCKR + (4 * 16); Lock key bit
488 844
 
489 845
 
490 846
 ; LCKR G
@@ -506,7 +862,7 @@ BB_GPIOG_LCKR_12        EQU  _BB_GPIOG_LCKR + (4 * 12)
506 862
 BB_GPIOG_LCKR_13        EQU  _BB_GPIOG_LCKR + (4 * 13)
507 863
 BB_GPIOG_LCKR_14        EQU  _BB_GPIOG_LCKR + (4 * 14)
508 864
 BB_GPIOG_LCKR_15        EQU  _BB_GPIOG_LCKR + (4 * 15)
509
-BB_GPIOG_LCKR_K         EQU  _BB_GPIOG_LCKR + (4 * 16) ; Lock key bit
865
+BB_GPIOG_LCKR_K         EQU  _BB_GPIOG_LCKR + (4 * 16); Lock key bit
510 866
 
511 867
 
512 868
 ; LCKR H
@@ -528,6 +884,6 @@ BB_GPIOH_LCKR_12        EQU  _BB_GPIOH_LCKR + (4 * 12)
528 884
 BB_GPIOH_LCKR_13        EQU  _BB_GPIOH_LCKR + (4 * 13)
529 885
 BB_GPIOH_LCKR_14        EQU  _BB_GPIOH_LCKR + (4 * 14)
530 886
 BB_GPIOH_LCKR_15        EQU  _BB_GPIOH_LCKR + (4 * 15)
531
-BB_GPIOH_LCKR_K         EQU  _BB_GPIOH_LCKR + (4 * 16) ; Lock key bit
887
+BB_GPIOH_LCKR_K         EQU  _BB_GPIOH_LCKR + (4 * 16); Lock key bit
532 888
 
533 889
 	END

+ 0 - 225
lib/INI_REGS.s View File

@@ -7,138 +7,12 @@
7 7
 ; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
8 8
 ;********************************************************************************
9 9
 
10
-
11
-FLASH_BASE         EQU  0x08000000 ; FLASH base address in the alias region
12
-SRAM_BASE          EQU  0x20000000 ; SRAM base address in the alias region
13
-PERIPH_BASE        EQU  0x40000000 ; Peripheral base address in the alias region
14
-
15
-; Value to add to region base to get bitband base
16
-SRAM_BB_OFFSET     EQU  0x02000000
17
-PERIPH_BB_OFFSET   EQU  0x02000000
18
-
19
-SRAM_BB_BASE       EQU  (SRAM_BASE   + SRAM_BB_OFFSET)   ; SRAM base address in the bit-band region
20
-PERIPH_BB_BASE     EQU  (PERIPH_BASE + PERIPH_BB_OFFSET) ; Peripheral base address in the bit-band region
21
-
22
-
23
-; ------------------------- Peripheral Bases --------------------------
24
-
25
-; *** System peripherals ***
26
-
27
-_SCS_BASE          EQU  0xE000E000         ; SCS Base Address
28
-_SCB               EQU  (_SCS_BASE + 0x0D00)  ; System Control Block
29
-_NVIC              EQU  (_SCS_BASE +  0x0100) ; Nested Interrupt Vector Controller
30
-
31
-
32
-; *** Special system preipherals ***
33
-
34
-_OB              EQU  0x1FF80000 ; FLASH Option Bytes base address
35
-_AES             EQU  0x50060000
36
-_FSMC            EQU  0xA0000000 ; FSMC registers base address
37
-_DBGMCU          EQU  0xE0042000 ; Debug MCU registers base address
38
-
39
-
40
-
41
-; Bus base addresses
42
-_APB1          EQU   PERIPH_BASE
43
-_APB2          EQU  (PERIPH_BASE + 0x10000)
44
-_AHB           EQU  (PERIPH_BASE + 0x20000)
45
-
46
-; *** Peripheral Bus 1 ***
47
-
48
-_TIM2          EQU  (_APB1 + 0x0000)
49
-_TIM3          EQU  (_APB1 + 0x0400)
50
-_TIM4          EQU  (_APB1 + 0x0800)
51
-_TIM5          EQU  (_APB1 + 0x0C00)
52
-_TIM6          EQU  (_APB1 + 0x1000)
53
-_TIM7          EQU  (_APB1 + 0x1400)
54
-
55
-_LCD           EQU  (_APB1 + 0x2400)
56
-_RTC           EQU  (_APB1 + 0x2800)
57
-_WWDG          EQU  (_APB1 + 0x2C00)
58
-_IWDG          EQU  (_APB1 + 0x3000)
59
-
60
-_SPI2          EQU  (_APB1 + 0x3800)
61
-_SPI3          EQU  (_APB1 + 0x3C00)
62
-
63
-_USART2        EQU  (_APB1 + 0x4400)
64
-_USART3        EQU  (_APB1 + 0x4800)
65
-
66
-_UART4         EQU  (_APB1 + 0x4C00)
67
-_UART5         EQU  (_APB1 + 0x5000)
68
-
69
-_I2C1          EQU  (_APB1 + 0x5400)
70
-_I2C2          EQU  (_APB1 + 0x5800)
71
-
72
-_PWR           EQU  (_APB1 + 0x7000)
73
-_DAC           EQU  (_APB1 + 0x7400)
74
-_COMP          EQU  (_APB1 + 0x7C00)
75
-_RI            EQU  (_APB1 + 0x7C04)
76
-_OPAMP         EQU  (_APB1 + 0x7C5C)
77
-
78
-
79
-; *** Peripheral Bus 2 ***
80
-
81
-_TIM9          EQU  (_APB2 + 0x0800)
82
-_TIM10         EQU  (_APB2 + 0x0C00)
83
-_TIM11         EQU  (_APB2 + 0x1000)
84
-
85
-_SYSCFG        EQU  (_APB2 + 0x0000)
86
-_EXTI          EQU  (_APB2 + 0x0400)
87
-_ADC1          EQU  (_APB2 + 0x2400)
88
-_ADCC          EQU  (_APB2 + 0x2700) ; common
89
-_SDIO          EQU  (_APB2 + 0x2C00) ; SD host
90
-_SPI1          EQU  (_APB2 + 0x3000) ; SPI
91
-_USART1        EQU  (_APB2 + 0x3800)
92
-
93
-
94
-
95
-; *** High Speed Bus ***
96
-
97
-; GPIOs base
98
-_GPIO              EQU  (_AHB + 0x0000)
99
-
100
-_CRC               EQU  (_AHB + 0x3000)
101
-_RCC               EQU  (_AHB + 0x3800)
102
-
103
-
104
-; DMA channels base
105
-_DMA1              EQU  (_AHB + 0x6000)
106
-_DMA2              EQU  (_AHB + 0x6400)
107
-
108
-_FLASH             EQU  (_AHB + 0x3C00)
109
-
110
-
111 10
 ; ----------------------- Peripherals ------------------------
112 11
 
113 12
 ; Special system control registers
114 13
 
115
-SysTick_CSR        EQU  (_SCS_BASE + 0x010) ; (R/W) SysTick Control and Status Register
116
-SysTick_RELOAD     EQU  (_SCS_BASE + 0x014) ; (R/W) SysTick Reload Value Register
117
-SysTick_VAL        EQU  (_SCS_BASE + 0x018) ; (R/W) SysTick Current Value Register
118
-SysTick_CALIB      EQU  (_SCS_BASE + 0x01C) ; (R/ ) SysTick Calibration Value Register
119
-
120 14
 ; SCB
121 15
 
122
-SCB_ACTLR          EQU  (_SCS_BASE + 0x008) ; (R/W) ACTLR
123
-SCB_CPUID          EQU  (_SCB + 0x000) ; (R/ )  CPUID Base Register
124
-SCB_ICSR           EQU  (_SCB + 0x004) ; (R/W)  Interrupt Control and State Register
125
-SCB_VTOR           EQU  (_SCB + 0x008) ; (R/W)  Vector Table Offset Register
126
-SCB_AIRCR          EQU  (_SCB + 0x00C) ; (R/W)  Application Interrupt and Reset Control Register
127
-SCB_SCR            EQU  (_SCB + 0x010) ; (R/W)  System Control Register
128
-SCB_CCR            EQU  (_SCB + 0x014) ; (R/W)  Configuration Control Register
129
-SCB_SHPR1          EQU  (_SCB + 0x018) ; (R/W)  System Handler Priority Register 1 (4-7)
130
-SCB_SHPR2          EQU  (_SCB + 0x01C) ; (R/W)  System Handler Priority Register 2 (8-11)
131
-SCB_SHPR3          EQU  (_SCB + 0x020) ; (R/W)  System Handler Priority Register 3 (12-15)
132
-SCB_SHCSR          EQU  (_SCB + 0x024) ; (R/W)  System Handler Control and State Register
133
-SCB_CFSR           EQU  (_SCB + 0x028) ; (R/W)  Configurable Fault Status Register
134
-SCB_HFSR           EQU  (_SCB + 0x02C) ; (R/W)  HardFault Status Register
135
-SCB_DFSR           EQU  (_SCB + 0x030) ; (R/W)  Debug Fault Status Register
136
-SCB_MMFAR          EQU  (_SCB + 0x034) ; (R/W)  MemManage Fault Address Register
137
-SCB_BFAR           EQU  (_SCB + 0x038) ; (R/W)  BusFault Address Register
138
-SCB_AFSR           EQU  (_SCB + 0x03C) ; (R/W)  Auxiliary Fault Status Register
139
-; skipped Feature Registers
140
-SCB_CPACR          EQU  (_SCB + 0x088) ; (R/W)  Coprocessor Access Control Register
141
-
142 16
 
143 17
 ; NVIC
144 18
 
@@ -837,105 +711,6 @@ CRC_IDR          EQU  (_CRC + 0x04) ; CRC Independent data register,
837 711
 CRC_CR           EQU  (_CRC + 0x08) ; CRC Control register,
838 712
 
839 713
 
840
-; GPIO ports
841
-
842
-_GPIOA           EQU  (_GPIO + 0x0000)
843
-_GPIOB           EQU  (_GPIO + 0x0400)
844
-_GPIOC           EQU  (_GPIO + 0x0800)
845
-_GPIOD           EQU  (_GPIO + 0x0C00)
846
-_GPIOE           EQU  (_GPIO + 0x1000)
847
-_GPIOH           EQU  (_GPIO + 0x1400)
848
-_GPIOF           EQU  (_GPIO + 0x1800)
849
-_GPIOG           EQU  (_GPIO + 0x1C00)
850
-
851
-GPIOA_MODER      EQU  (_GPIOA + 0x00) ; GPIOA pin mode register,
852
-GPIOA_OTYPER     EQU  (_GPIOA + 0x04) ; GPIOA output type register,
853
-GPIOA_OSPEEDR    EQU  (_GPIOA + 0x08) ; GPIOA output speed register,
854
-GPIOA_PUPDR      EQU  (_GPIOA + 0x0C) ; GPIOA pull-up/pull-down register,
855
-GPIOA_IDR        EQU  (_GPIOA + 0x10) ; GPIOA input data register,
856
-GPIOA_ODR        EQU  (_GPIOA + 0x14) ; GPIOA output data register,
857
-GPIOA_BSRR       EQU  (_GPIOA + 0x18) ; GPIOA bit set/reset register,
858
-GPIOA_LCKR       EQU  (_GPIOA + 0x1C) ; GPIOA configuration lock register,
859
-GPIOA_AFRL       EQU  (_GPIOA + 0x20) ; GPIOA alternate function low register,
860
-GPIOA_AFRH       EQU  (_GPIOA + 0x24) ; GPIOA alternate function low register,
861
-GPIOA_BRR        EQU  (_GPIOA + 0x28) ; GPIOA bit reset register,
862
-
863
-GPIOB_MODER      EQU  (_GPIOB + 0x00) ; GPIOB pin mode register,
864
-GPIOB_OTYPER     EQU  (_GPIOB + 0x04) ; GPIOB output type register,
865
-GPIOB_OSPEEDR    EQU  (_GPIOB + 0x08) ; GPIOB output speed register,
866
-GPIOB_PUPDR      EQU  (_GPIOB + 0x0C) ; GPIOB pull-up/pull-down register,
867
-GPIOB_IDR        EQU  (_GPIOB + 0x10) ; GPIOB input data register,
868
-GPIOB_ODR        EQU  (_GPIOB + 0x14) ; GPIOB output data register,
869
-GPIOB_BSRR       EQU  (_GPIOB + 0x18) ; GPIOB bit set/reset register,
870
-GPIOB_LCKR       EQU  (_GPIOB + 0x1C) ; GPIOB configuration lock register,
871
-GPIOB_AFR        EQU  (_GPIOB + 0x20) ; GPIOB alternate function low register,
872
-GPIOB_BRR        EQU  (_GPIOB + 0x28) ; GPIOB bit reset register,
873
-
874
-GPIOC_MODER      EQU  (_GPIOC + 0x00) ; GPIOC pin mode register,
875
-GPIOC_OTYPER     EQU  (_GPIOC + 0x04) ; GPIOC output type register,
876
-GPIOC_OSPEEDR    EQU  (_GPIOC + 0x08) ; GPIOC output speed register,
877
-GPIOC_PUPDR      EQU  (_GPIOC + 0x0C) ; GPIOC pull-up/pull-down register,
878
-GPIOC_IDR        EQU  (_GPIOC + 0x10) ; GPIOC input data register,
879
-GPIOC_ODR        EQU  (_GPIOC + 0x14) ; GPIOC output data register,
880
-GPIOC_BSRR       EQU  (_GPIOC + 0x18) ; GPIOC bit set/reset register,
881
-GPIOC_LCKR       EQU  (_GPIOC + 0x1C) ; GPIOC configuration lock register,
882
-GPIOC_AFR        EQU  (_GPIOC + 0x20) ; GPIOC alternate function low register,
883
-GPIOC_BRR        EQU  (_GPIOC + 0x28) ; GPIOC bit reset register,
884
-
885
-GPIOD_MODER      EQU  (_GPIOD + 0x00) ; GPIOD pin mode register,
886
-GPIOD_OTYPER     EQU  (_GPIOD + 0x04) ; GPIOD output type register,
887
-GPIOD_OSPEEDR    EQU  (_GPIOD + 0x08) ; GPIOD output speed register,
888
-GPIOD_PUPDR      EQU  (_GPIOD + 0x0C) ; GPIOD pull-up/pull-down register,
889
-GPIOD_IDR        EQU  (_GPIOD + 0x10) ; GPIOD input data register,
890
-GPIOD_ODR        EQU  (_GPIOD + 0x14) ; GPIOD output data register,
891
-GPIOD_BSRR       EQU  (_GPIOD + 0x18) ; GPIOD bit set/reset register,
892
-GPIOD_LCKR       EQU  (_GPIOD + 0x1C) ; GPIOD configuration lock register,
893
-GPIOD_AFR        EQU  (_GPIOD + 0x20) ; GPIOD alternate function low register,
894
-GPIOD_BRR        EQU  (_GPIOD + 0x28) ; GPIOD bit reset register,
895
-
896
-GPIOE_MODER      EQU  (_GPIOE + 0x00) ; GPIOE pin mode register,
897
-GPIOE_OTYPER     EQU  (_GPIOE + 0x04) ; GPIOE output type register,
898
-GPIOE_OSPEEDR    EQU  (_GPIOE + 0x08) ; GPIOE output speed register,
899
-GPIOE_PUPDR      EQU  (_GPIOE + 0x0C) ; GPIOE pull-up/pull-down register,
900
-GPIOE_IDR        EQU  (_GPIOE + 0x10) ; GPIOE input data register,
901
-GPIOE_ODR        EQU  (_GPIOE + 0x14) ; GPIOE output data register,
902
-GPIOE_BSRR       EQU  (_GPIOE + 0x18) ; GPIOE bit set/reset register,
903
-GPIOE_LCKR       EQU  (_GPIOE + 0x1C) ; GPIOE configuration lock register,
904
-GPIOE_AFR        EQU  (_GPIOE + 0x20) ; GPIOE alternate function low register,
905
-GPIOE_BRR        EQU  (_GPIOE + 0x28) ; GPIOE bit reset register,
906
-
907
-GPIOF_MODER      EQU  (_GPIOF + 0x00) ; GPIOF pin mode register,
908
-GPIOF_OTYPER     EQU  (_GPIOF + 0x04) ; GPIOF output type register,
909
-GPIOF_OSPEEDR    EQU  (_GPIOF + 0x08) ; GPIOF output speed register,
910
-GPIOF_PUPDR      EQU  (_GPIOF + 0x0C) ; GPIOF pull-up/pull-down register,
911
-GPIOF_IDR        EQU  (_GPIOF + 0x10) ; GPIOF input data register,
912
-GPIOF_ODR        EQU  (_GPIOF + 0x14) ; GPIOF output data register,
913
-GPIOF_BSRR       EQU  (_GPIOF + 0x18) ; GPIOF bit set/reset register,
914
-GPIOF_LCKR       EQU  (_GPIOF + 0x1C) ; GPIOF configuration lock register,
915
-GPIOF_AFR        EQU  (_GPIOF + 0x20) ; GPIOF alternate function low register,
916
-GPIOF_BRR        EQU  (_GPIOF + 0x28) ; GPIOF bit reset register,
917
-
918
-GPIOG_MODER      EQU  (_GPIOG + 0x00) ; GPIOG pin mode register,
919
-GPIOG_OTYPER     EQU  (_GPIOG + 0x04) ; GPIOG output type register,
920
-GPIOG_OSPEEDR    EQU  (_GPIOG + 0x08) ; GPIOG output speed register,
921
-GPIOG_PUPDR      EQU  (_GPIOG + 0x0C) ; GPIOG pull-up/pull-down register,
922
-GPIOG_IDR        EQU  (_GPIOG + 0x10) ; GPIOG input data register,
923
-GPIOG_ODR        EQU  (_GPIOG + 0x14) ; GPIOG output data register,
924
-GPIOG_BSRR       EQU  (_GPIOG + 0x18) ; GPIOG bit set/reset register,
925
-GPIOG_LCKR       EQU  (_GPIOG + 0x1C) ; GPIOG configuration lock register,
926
-GPIOG_AFR        EQU  (_GPIOG + 0x20) ; GPIOG alternate function low register,
927
-GPIOG_BRR        EQU  (_GPIOG + 0x28) ; GPIOG bit reset register,
928
-
929
-GPIOH_MODER      EQU  (_GPIOH + 0x00) ; GPIOH pin mode register,
930
-GPIOH_OTYPER     EQU  (_GPIOH + 0x04) ; GPIOH output type register,
931
-GPIOH_OSPEEDR    EQU  (_GPIOH + 0x08) ; GPIOH output speed register,
932
-GPIOH_PUPDR      EQU  (_GPIOH + 0x0C) ; GPIOH pull-up/pull-down register,
933
-GPIOH_IDR        EQU  (_GPIOH + 0x10) ; GPIOH input data register,
934
-GPIOH_ODR        EQU  (_GPIOH + 0x14) ; GPIOH output data register,
935
-GPIOH_BSRR       EQU  (_GPIOH + 0x18) ; GPIOH bit set/reset register,
936
-GPIOH_LCKR       EQU  (_GPIOH + 0x1C) ; GPIOH configuration lock register,
937
-GPIOH_AFR        EQU  (_GPIOH + 0x20) ; GPIOH alternate function low register,
938
-GPIOH_BRR        EQU  (_GPIOH + 0x28) ; GPIOH bit reset register,
939 714
 
940 715
 
941 716
 ; FLASH registers

+ 199 - 0
lib/INI_SCB.s View File

@@ -0,0 +1,199 @@
1
+;****************************************************************************
2
+; SOUBOR : INI_SCB.S
3
+; AUTOR  : Petr Dousa, Ondrej Hruska
4
+; DATUM  : 10/2015
5
+
6
+;                          System Control Block (SCB)
7
+;
8
+; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
9
+;****************************************************************************
10
+
11
+
12
+;****************************************************************************
13
+;*
14
+;*                               REGISTERS
15
+;*
16
+;****************************************************************************
17
+
18
+
19
+SCB_CPUID          EQU  (_SCB + 0x000)             ; (R/ )  CPUID Base Register
20
+SCB_ICSR           EQU  (_SCB + 0x004)             ; (R/W)  Interrupt Control and State Register
21
+SCB_VTOR           EQU  (_SCB + 0x008)             ; (R/W)  Vector Table Offset Register
22
+SCB_AIRCR          EQU  (_SCB + 0x00C)             ; (R/W)  Application Interrupt and Reset Control Register
23
+SCB_SCR            EQU  (_SCB + 0x010)             ; (R/W)  System Control Register
24
+SCB_CCR            EQU  (_SCB + 0x014)             ; (R/W)  Configuration Control Register
25
+SCB_SHPR1          EQU  (_SCB + 0x018)             ; (R/W)  System Handler Priority Register 1 (4-7)
26
+SCB_SHPR2          EQU  (_SCB + 0x01C)             ; (R/W)  System Handler Priority Register 2 (8-11)
27
+SCB_SHPR3          EQU  (_SCB + 0x020)             ; (R/W)  System Handler Priority Register 3 (12-15)
28
+SCB_SHCSR          EQU  (_SCB + 0x024)             ; (R/W)  System Handler Control and State Register
29
+SCB_CFSR           EQU  (_SCB + 0x028)             ; (R/W)  Configurable Fault Status Register
30
+SCB_HFSR           EQU  (_SCB + 0x02C)             ; (R/W)  HardFault Status Register
31
+SCB_DFSR           EQU  (_SCB + 0x030)             ; (R/W)  Debug Fault Status Register
32
+SCB_MMFAR          EQU  (_SCB + 0x034)             ; (R/W)  MemManage Fault Address Register
33
+SCB_BFAR           EQU  (_SCB + 0x038)             ; (R/W)  BusFault Address Register
34
+SCB_AFSR           EQU  (_SCB + 0x03C)             ; (R/W)  Auxiliary Fault Status Register
35
+; skipped Feature Registers
36
+SCB_CPACR          EQU  (_SCB + 0x088)             ; (R/W)  Coprocessor Access Control Register
37
+
38
+
39
+
40
+;****************************************************************************
41
+;*
42
+;*                       BIT MASKS AND DEFINITIONS
43
+;*
44
+;****************************************************************************
45
+
46
+
47
+;*****************  Bit definition for SCB_CPUID register  ******************
48
+
49
+SCB_CPUID_REVISION               EQU  0x0000000F   ; Implementation defined revision number
50
+SCB_CPUID_PARTNO                 EQU  0x0000FFF0   ; Number of processor within family
51
+SCB_CPUID_Constant               EQU  0x000F0000   ; Reads as 0x0F
52
+SCB_CPUID_VARIANT                EQU  0x00F00000   ; Implementation defined variant number
53
+SCB_CPUID_IMPLEMENTER            EQU  0xFF000000   ; Implementer code. ARM is 0x41
54
+
55
+
56
+;******************  Bit definition for SCB_ICSR register  ******************
57
+
58
+SCB_ICSR_VECTACTIVE              EQU  0x000001FF   ; Active ISR number field
59
+SCB_ICSR_RETTOBASE               EQU  0x00000800   ; All active exceptions minus the IPSR_current_exception yields the empty set
60
+SCB_ICSR_VECTPENDING             EQU  0x003FF000   ; Pending ISR number field
61
+SCB_ICSR_ISRPENDING              EQU  0x00400000   ; Interrupt pending flag
62
+SCB_ICSR_ISRPREEMPT              EQU  0x00800000   ; It indicates that a pending interrupt becomes active in the next running cycle
63
+SCB_ICSR_PENDSTCLR               EQU  0x02000000   ; Clear pending SysTick bit
64
+SCB_ICSR_PENDSTSET               EQU  0x04000000   ; Set pending SysTick bit
65
+SCB_ICSR_PENDSVCLR               EQU  0x08000000   ; Clear pending pendSV bit
66
+SCB_ICSR_PENDSVSET               EQU  0x10000000   ; Set pending pendSV bit
67
+SCB_ICSR_NMIPENDSET              EQU  0x80000000   ; Set pending NMI bit
68
+
69
+
70
+;******************  Bit definition for SCB_VTOR register  ******************
71
+
72
+SCB_VTOR_TBLOFF                  EQU  0x1FFFFF80   ; Vector table base offset field
73
+SCB_VTOR_TBLBASE                 EQU  0x20000000   ; Table base in code(0) or RAM(1)
74
+
75
+
76
+; *****************  Bit definition for SCB_AIRCR register  ******************
77
+
78
+SCB_AIRCR_VECTKEY                EQU  0x05FA0000   ; Value required to enable write to this register
79
+SCB_AIRCR_VECTRESET              EQU  0x00000001   ; System Reset bit
80
+SCB_AIRCR_VECTCLRACTIVE          EQU  0x00000002   ; Clear active vector bit
81
+SCB_AIRCR_SYSRESETREQ            EQU  0x00000004   ; Requests chip control logic to generate a reset
82
+
83
+SCB_AIRCR_PRIGROUP               EQU  0x00000700   ; PRIGROUP[2:0] bits (Priority group)
84
+SCB_AIRCR_PRIGROUP_0             EQU  0x00000100   ; Bit 0
85
+SCB_AIRCR_PRIGROUP_1             EQU  0x00000200   ; Bit 1
86
+SCB_AIRCR_PRIGROUP_2             EQU  0x00000400   ; Bit 2
87
+
88
+; prority group configuration
89
+SCB_AIRCR_PRIGROUP0              EQU  0x00000000   ; Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)
90
+SCB_AIRCR_PRIGROUP1              EQU  0x00000100   ; Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)
91
+SCB_AIRCR_PRIGROUP2              EQU  0x00000200   ; Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)
92
+SCB_AIRCR_PRIGROUP3              EQU  0x00000300   ; Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)
93
+SCB_AIRCR_PRIGROUP4              EQU  0x00000400   ; Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)
94
+SCB_AIRCR_PRIGROUP5              EQU  0x00000500   ; Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)
95
+SCB_AIRCR_PRIGROUP6              EQU  0x00000600   ; Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)
96
+SCB_AIRCR_PRIGROUP7              EQU  0x00000700   ; Priority group=7 (no pre-emption priority, 8 bits of subpriority)
97
+
98
+SCB_AIRCR_ENDIANESS              EQU  0x00008000   ; Data endianness bit
99
+SCB_AIRCR_VECTKEY                EQU  0xFFFF0000   ; Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)
100
+
101
+
102
+;******************  Bit definition for SCB_SCR register  *******************
103
+
104
+SCB_SCR_SLEEPONEXIT              EQU  0x02         ; Sleep on exit bit
105
+SCB_SCR_SLEEPDEEP                EQU  0x04         ; Sleep deep bit
106
+SCB_SCR_SEVONPEND                EQU  0x10         ; Wake up from WFE
107
+
108
+
109
+;*******************  Bit definition for SCB_CCR register  ******************
110
+
111
+SCB_CCR_NONBASETHRDENA           EQU  0x0001       ; Thread mode can be entered from any level in Handler mode by controlled return value
112
+SCB_CCR_USERSETMPEND             EQU  0x0002       ; Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception
113
+SCB_CCR_UNALIGN_TRP              EQU  0x0008       ; Trap for unaligned access
114
+SCB_CCR_DIV_0_TRP                EQU  0x0010       ; Trap on Divide by 0
115
+SCB_CCR_BFHFNMIGN                EQU  0x0100       ; Handlers running at priority -1 and -2
116
+SCB_CCR_STKALIGN                 EQU  0x0200       ; On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned
117
+
118
+
119
+;******************  Bit definition for SCB_SHPR register *******************
120
+
121
+SCB_SHPR_PRI_N                   EQU  0x000000FF   ; Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor
122
+SCB_SHPR_PRI_N1                  EQU  0x0000FF00   ; Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved
123
+SCB_SHPR_PRI_N2                  EQU  0x00FF0000   ; Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV
124
+SCB_SHPR_PRI_N3                  EQU  0xFF000000   ; Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick
125
+
126
+
127
+;*****************  Bit definition for SCB_SHCSR register  ******************
128
+
129
+SCB_SHCSR_MEMFAULTACT            EQU  0x00000001   ; MemManage is active
130
+SCB_SHCSR_BUSFAULTACT            EQU  0x00000002   ; BusFault is active
131
+SCB_SHCSR_USGFAULTACT            EQU  0x00000008   ; UsageFault is active
132
+SCB_SHCSR_SVCALLACT              EQU  0x00000080   ; SVCall is active
133
+SCB_SHCSR_MONITORACT             EQU  0x00000100   ; Monitor is active
134
+SCB_SHCSR_PENDSVACT              EQU  0x00000400   ; PendSV is active
135
+SCB_SHCSR_SYSTICKACT             EQU  0x00000800   ; SysTick is active
136
+SCB_SHCSR_USGFAULTPENDED         EQU  0x00001000   ; Usage Fault is pended
137
+SCB_SHCSR_MEMFAULTPENDED         EQU  0x00002000   ; MemManage is pended
138
+SCB_SHCSR_BUSFAULTPENDED         EQU  0x00004000   ; Bus Fault is pended
139
+SCB_SHCSR_SVCALLPENDED           EQU  0x00008000   ; SVCall is pended
140
+SCB_SHCSR_MEMFAULTENA            EQU  0x00010000   ; MemManage enable
141
+SCB_SHCSR_BUSFAULTENA            EQU  0x00020000   ; Bus Fault enable
142
+SCB_SHCSR_USGFAULTENA            EQU  0x00040000   ; UsageFault enable
143
+
144
+
145
+;******************  Bit definition for SCB_CFSR register  ******************
146
+
147
+; MFSR
148
+SCB_CFSR_IACCVIOL                EQU  0x00000001   ; Instruction access violation
149
+SCB_CFSR_DACCVIOL                EQU  0x00000002   ; Data access violation
150
+SCB_CFSR_MUNSTKERR               EQU  0x00000008   ; Unstacking error
151
+SCB_CFSR_MSTKERR                 EQU  0x00000010   ; Stacking error
152
+SCB_CFSR_MMARVALID               EQU  0x00000080   ; Memory Manage Address Register address valid flag
153
+; BFSR
154
+SCB_CFSR_IBUSERR                 EQU  0x00000100   ; Instruction bus error flag
155
+SCB_CFSR_PRECISERR               EQU  0x00000200   ; Precise data bus error
156
+SCB_CFSR_IMPRECISERR             EQU  0x00000400   ; Imprecise data bus error
157
+SCB_CFSR_UNSTKERR                EQU  0x00000800   ; Unstacking error
158
+SCB_CFSR_STKERR                  EQU  0x00001000   ; Stacking error
159
+SCB_CFSR_BFARVALID               EQU  0x00008000   ; Bus Fault Address Register address valid flag
160
+; UFSR
161
+SCB_CFSR_UNDEFINSTR              EQU  0x00010000   ; The processor attempt to excecute an undefined instruction
162
+SCB_CFSR_INVSTATE                EQU  0x00020000   ; Invalid combination of EPSR and instruction
163
+SCB_CFSR_INVPC                   EQU  0x00040000   ; Attempt to load EXC_RETURN into pc illegally
164
+SCB_CFSR_NOCP                    EQU  0x00080000   ; Attempt to use a coprocessor instruction
165
+SCB_CFSR_UNALIGNED               EQU  0x01000000   ; Fault occurs when there is an attempt to make an unaligned memory access
166
+SCB_CFSR_DIVBYZERO               EQU  0x02000000   ; Fault occurs when SDIV or DIV instruction is used with a divisor of 0
167
+
168
+
169
+;******************  Bit definition for SCB_HFSR register  ******************
170
+
171
+SCB_HFSR_VECTTBL                 EQU  0x00000002   ; Fault occures because of vector table read on exception processing
172
+SCB_HFSR_FORCED                  EQU  0x40000000   ; Hard Fault activated when a configurable Fault was received and cannot activate
173
+SCB_HFSR_DEBUGEVT                EQU  0x80000000   ; Fault related to debug
174
+
175
+
176
+;******************  Bit definition for SCB_DFSR register  ******************
177
+
178
+SCB_DFSR_HALTED                  EQU  0x01         ; Halt request flag
179
+SCB_DFSR_BKPT                    EQU  0x02         ; BKPT flag
180
+SCB_DFSR_DWTTRAP                 EQU  0x04         ; Data Watchpoint and Trace (DWT) flag
181
+SCB_DFSR_VCATCH                  EQU  0x08         ; Vector catch flag
182
+SCB_DFSR_EXTERNAL                EQU  0x10         ; External debug request flag
183
+
184
+
185
+;******************  Bit definition for SCB_MMFAR register  *****************
186
+
187
+SCB_MMFAR_ADDRESS                EQU  0xFFFFFFFF   ; Mem Manage fault address field
188
+
189
+
190
+;******************  Bit definition for SCB_BFAR register  ******************
191
+
192
+SCB_BFAR_ADDRESS                 EQU  0xFFFFFFFF   ; Bus fault address field
193
+
194
+
195
+;******************  Bit definition for SCB_afsr register  ******************
196
+
197
+SCB_AFSR_IMPDEF                  EQU  0xFFFFFFFF   ; Implementation defined
198
+
199
+	END

+ 61 - 0
lib/INI_SYSTICK.s View File

@@ -0,0 +1,61 @@
1
+;****************************************************************************
2
+; SOUBOR : INI_SYSTICK.S
3
+; AUTOR  : Petr Dousa, Ondrej Hruska
4
+; DATUM  : 10/2015
5
+;
6
+;                           System Timer (SysTick)
7
+;
8
+; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
9
+;****************************************************************************
10
+
11
+
12
+;****************************************************************************
13
+;*
14
+;*                               REGISTERS
15
+;*
16
+;****************************************************************************
17
+
18
+
19
+SysTick_CSR        EQU  (_SCS_BASE + 0x010)        ; (R/W) SysTick Control and Status Register
20
+SysTick_RELOAD     EQU  (_SCS_BASE + 0x014)        ; (R/W) SysTick Reload Value Register
21
+SysTick_VAL        EQU  (_SCS_BASE + 0x018)        ; (R/W) SysTick Current Value Register
22
+SysTick_CALIB      EQU  (_SCS_BASE + 0x01C)        ; (R/ ) SysTick Calibration Value Register
23
+
24
+
25
+
26
+;****************************************************************************
27
+;*
28
+;*                       BIT MASKS AND DEFINITIONS
29
+;*
30
+;****************************************************************************
31
+
32
+
33
+;****************  Bit definition for SysTick_CSR register  ****************
34
+
35
+SysTick_CSR_ENABLE              EQU  0x00000001    ; Counter enable
36
+SysTick_CSR_TICKINT             EQU  0x00000002    ; Enable interrupt when counter reaches zero
37
+SysTick_CSR_CLKSOURCE           EQU  0x00000004    ; Clock source (0 - external, 1 - core clock)
38
+
39
+SysTick_CSR_CLKSOURCE_CORE      EQU  0x00000004    ; Clock source - core clock
40
+SysTick_CSR_CLKSOURCE_DIV8      EQU  0x00000000    ; Clock source - core clock / 8
41
+
42
+SysTick_CSR_COUNTFLAG           EQU  0x00010000    ; Count Flag (only if interrupt is disabled)
43
+
44
+
45
+;****************  Bit definition for SysTick_LOAD register  ****************
46
+
47
+SysTick_RELOAD_MASK             EQU  0x00FFFFFF    ; Reload value used when the counter reaches 0
48
+
49
+
50
+;****************  Bit definition for SysTick_VAL register  *****************
51
+
52
+SysTick_VAL_MASK                EQU  0x00FFFFFF    ; Current value at the time the register is accessed
53
+
54
+
55
+;****************  Bit definition for SysTick_CALIB register  ***************
56
+
57
+SysTick_CALIB_TENMS             EQU  0x00FFFFFF    ; Reload value to use for 10ms timing
58
+SysTick_CALIB_SKEW              EQU  0x40000000    ; Calibration value is not exactly 10 ms
59
+SysTick_CALIB_NOREF             EQU  0x80000000    ; The reference clock is not provided
60
+
61
+	END

+ 6 - 6
main.asm View File

@@ -15,14 +15,14 @@
15 15
 ;***************************************************************************************************
16 16
 
17 17
 		; Register addresses
18
-		GET		lib/INI_REGS.s
18
+		GET		lib/INI_BASE.s
19
+		GET		lib/INI_REGS.s                     ;deprecated TODO remove when definitions moved to other files
19 20
 
20 21
 		; Bit presets
21
-		GET		lib/INI_BITS_GPIO.s
22
-		GET		lib/INI_BITS_RCC.s
23
-		GET		lib/INI_BITS_FLASH.s
24
-		GET		lib/INI_BITS_SYSTICK.s
25
-		GET		lib/INI_BB.s
22
+		GET		lib/INI_GPIO.s
23
+		GET		lib/INI_SYSTICK.s
24
+		GET		lib/INI_BITS_RCC.s                 ;legacy FIXME
25
+		GET		lib/INI_BITS_FLASH.s               ;legacy FIXME
26 26
 
27 27
 
28 28
 ;***************************************************************************************************