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;********************************************************************************
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; SOUBOR : INI_AES.S
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; AUTOR : Petr Dousa, Ondrej Hruska
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; DATUM : 10/2015
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; POPIS : Bitove masky ridicich registru pro AES (crypto);
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; ! Modul je pouze v STM32L162 !
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;
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; Advanced Encryption Standard (AES)
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;
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; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
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;********************************************************************************
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;****************************************************************************
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;*
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;* REGISTERS
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;*
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;****************************************************************************
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; AES crypto module
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AES_CR EQU (_AES + 0x00) ; AES control register,
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AES_SR EQU (_AES + 0x04) ; AES status register,
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AES_DINR_REG EQU (_AES + 0x08) ; AES data input register,
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AES_DOUTR_REG EQU (_AES + 0x0C) ; AES data output register,
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AES_KEYR0_REG EQU (_AES + 0x10) ; AES key register 0,
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AES_KEYR1_REG EQU (_AES + 0x14) ; AES key register 1,
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AES_KEYR2_REG EQU (_AES + 0x18) ; AES key register 2,
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AES_KEYR3_REG EQU (_AES + 0x1C) ; AES key register 3,
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AES_IVR0_REG EQU (_AES + 0x20) ; AES initialization vector register 0,
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AES_IVR1_REG EQU (_AES + 0x24) ; AES initialization vector register 1,
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AES_IVR2_REG EQU (_AES + 0x28) ; AES initialization vector register 2,
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AES_IVR3_REG EQU (_AES + 0x2C) ; AES initialization vector register 3,
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;****************************************************************************
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;*
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;* BIT MASKS AND DEFINITIONS
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;*
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;****************************************************************************
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;****************** Bit definition for AES_CR register ********************
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AES_CR_EN EQU 0x00000001 ; AES Enable
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AES_CR_DATATYPE EQU 0x00000006 ; Data type selection
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AES_CR_DATATYPE_0 EQU 0x00000002 ; Bit 0
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AES_CR_DATATYPE_1 EQU 0x00000004 ; Bit 1
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AES_CR_MODE EQU 0x00000018 ; AES Mode Of Operation
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AES_CR_MODE_0 EQU 0x00000008 ; Bit 0
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AES_CR_MODE_1 EQU 0x00000010 ; Bit 1
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AES_CR_CHMOD EQU 0x00000060 ; AES Chaining Mode
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AES_CR_CHMOD_0 EQU 0x00000020 ; Bit 0
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AES_CR_CHMOD_1 EQU 0x00000040 ; Bit 1
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AES_CR_CCFC EQU 0x00000080 ; Computation Complete Flag Clear
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AES_CR_ERRC EQU 0x00000100 ; Error Clear
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AES_CR_CCIE EQU 0x00000200 ; Computation Complete Interrupt Enable
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AES_CR_ERRIE EQU 0x00000400 ; Error Interrupt Enable
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AES_CR_DMAINEN EQU 0x00000800 ; DMA ENable managing the data input phase
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AES_CR_DMAOUTEN EQU 0x00001000 ; DMA Enable managing the data output phase
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;****************** Bit definition for AES_SR register ********************
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AES_SR_CCF EQU 0x00000001 ; Computation Complete Flag
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AES_SR_RDERR EQU 0x00000002 ; Read Error Flag
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AES_SR_WRERR EQU 0x00000004 ; Write Error Flag
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;****************** Bit definition for AES_DINR register ******************
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AES_DINR EQU 0x0000FFFF ; AES Data Input Register
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;****************** Bit definition for AES_DOUTR register *****************
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AES_DOUTR EQU 0x0000FFFF ; AES Data Output Register
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;****************** Bit definition for AES_KEYR0 register *****************
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AES_KEYR0 EQU 0x0000FFFF ; AES Key Register 0
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;****************** Bit definition for AES_KEYR1 register *****************
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AES_KEYR1 EQU 0x0000FFFF ; AES Key Register 1
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;****************** Bit definition for AES_KEYR2 register *****************
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AES_KEYR2 EQU 0x0000FFFF ; AES Key Register 2
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;****************** Bit definition for AES_KEYR3 register *****************
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AES_KEYR3 EQU 0x0000FFFF ; AES Key Register 3
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;****************** Bit definition for AES_IVR0 register ******************
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AES_IVR0 EQU 0x0000FFFF ; AES Initialization Vector Register 0
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;****************** Bit definition for AES_IVR1 register ******************
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AES_IVR1 EQU 0x0000FFFF ; AES Initialization Vector Register 1
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;****************** Bit definition for AES_IVR2 register ******************
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AES_IVR2 EQU 0x0000FFFF ; AES Initialization Vector Register 2
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;****************** Bit definition for AES_IVR3 register ******************
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AES_IVR3 EQU 0x0000FFFF ; AES Initialization Vector Register 3
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END
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