Source import

master
Ondřej Hruška 9 years ago
parent 86e41d4d68
commit c9a76d6da1
  1. 24
      .gitignore
  2. 7
      LICENSE
  3. 122
      Makefile
  4. 89
      README.md
  5. 533
      lib/INI_BB.s
  6. 554
      lib/INI_BITS_ADC.s
  7. 75
      lib/INI_BITS_AES.s
  8. 51
      lib/INI_BITS_COMP.s
  9. 26
      lib/INI_BITS_CRC.s
  10. 104
      lib/INI_BITS_DAC.s
  11. 68
      lib/INI_BITS_DBGMCU.s
  12. 311
      lib/INI_BITS_DMA.s
  13. 173
      lib/INI_BITS_EXTI.s
  14. 82
      lib/INI_BITS_FLASH.s
  15. 413
      lib/INI_BITS_FSMC.s
  16. 240
      lib/INI_BITS_GPIO.s
  17. 106
      lib/INI_BITS_I2C.s
  18. 33
      lib/INI_BITS_IWDG.s
  19. 79
      lib/INI_BITS_LCD.s
  20. 240
      lib/INI_BITS_NVIC.s
  21. 62
      lib/INI_BITS_OPAMP.s
  22. 60
      lib/INI_BITS_PWR.s
  23. 361
      lib/INI_BITS_RCC.s
  24. 529
      lib/INI_BITS_RI.s
  25. 429
      lib/INI_BITS_RTC.s
  26. 142
      lib/INI_BITS_SCB.s
  27. 170
      lib/INI_BITS_SDIO.s
  28. 96
      lib/INI_BITS_SPI.s
  29. 231
      lib/INI_BITS_SYSCFG.s
  30. 38
      lib/INI_BITS_SYSTICK.s
  31. 266
      lib/INI_BITS_TIM.s
  32. 95
      lib/INI_BITS_USART.s
  33. 679
      lib/INI_BITS_USB.s
  34. 48
      lib/INI_BITS_WWDG.s
  35. 1002
      lib/INI_REGS.s
  36. 257
      main.asm
  37. 355
      startup_stm32l100xc.s

24
.gitignore vendored

@ -0,0 +1,24 @@
# Temporary files
*.bak
*.lnp
*.iex
*.hex
*.elf
*.axf
*.htm
*.lnp
*.lst
*.plg
*.tra
*.o
*.map
*.d
*.dep
*.disasm
*.bin
# Backup files
*.bak
*~

@ -1,6 +1,11 @@
The MIT License (MIT)
Copyright (c) 2015 MightyPork-arm
Contributors:
Copyright (c) 2010 Michal Tomáš - část vzorového programu
Copyright (c) 2015 Petr Douša - základ knihovny dle CMSIS
Copyright (c) 2015 Ondřej Hruška - doplnění knihovny, Makefile
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal

@ -0,0 +1,122 @@
#####################################################################################
# File config
#####################################################################################
main_file = main.asm
startup_file = startup_stm32l100xc.s
lib_dir = lib/
#####################################################################################
# ASSEMBLER CONFIG
#####################################################################################
ASOPTS = --cpu Cortex-M3 --apcs interwork
# Add library to include path
ASOPTS += -I$(lib_dir)
# Debug flags
ifeq ($(G), 1)
ASOPTS += -g
endif
#####################################################################################
# LINKER CONFIG
#####################################################################################
LDOPTS = --cpu Cortex-M3 --strict
LDOPTS += --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000
LDOPTS += --entry Reset_Handler --first __Vectors
# Debug flags
ifneq ($(G), 1)
LDOPTS += --no_debug
endif
# Verbose flags (run make V=1)
ifeq ($(V), 1)
LDOPTS += --summary_stderr --map --xref --callgraph --symbols
LDOPTS += --info summarysizes,sizes,totals,unused,veneers
endif
#####################################################################################
# EXTERNAL PROGRAM NAMES
#####################################################################################
# armlink, armasm, fromelf - exe files in Wine directory (with Keil installed)
# Example launcher for Keil exe programs:
#
# #!/bin/bash
# WINEDEBUG=fixme-all wine ~/.wine/drive_c/Keil_v5/ARM/ARMCC_505u2/bin/armasm.exe $@
LD = WINEDEBUG=fixme-all wine ~/.wine/drive_c/Keil_v5/ARM/ARMCC_505u2/bin/armlink.exe
AS = WINEDEBUG=fixme-all wine ~/.wine/drive_c/Keil_v5/ARM/ARMCC_505u2/bin/armasm.exe
FROMELF = WINEDEBUG=fixme-all wine ~/.wine/drive_c/Keil_v5/ARM/ARMCC_505u2/bin/fromelf.exe
OBJDUMP = arm-none-eabi-objdump
STFLASH = st-flash
RM = rm
# --- END OF CONFIG ---
main_base = $(basename $(main_file))
startup_base = $(basename $(startup_file))
.PHONY: all build clean flash hex disasm
all: build
# Link object files to AXF file
output.axf: $(main_base).o $(startup_base).o
@echo -e "\e[0;33mLinking object files to $@\e[0m"
@$(LD) $(LDOPTS) --output $@ "$(main_base).o" "$(startup_base).o"
# Get BIN image file from AXF file
%.bin: %.axf
@echo -e "\e[0;33mConverting $< to $@\e[0m"
@$(FROMELF) --bincombined --output $@ $<
# Get Intel Hex file from AXF file
%.hex: %.axf
@echo -e "\e[0;33mConverting $< to $@\e[0m"
@$(FROMELF) --i32combined --output $@ $<
# Get Object file from Assembler source file
$(main_base).o: $(main_file)
@echo -e "\e[0;32mCompiling $< to $@\e[0m"
@$(AS) $(ASOPTS) --list $(main_base).lst -o $@ --depend $(main_base).d $<
$(startup_base).o: $(startup_file)
@echo -e "\e[0;32mCompiling $< to $@\e[0m"
@$(AS) $(ASOPTS) --list $(startup_base).lst -o $@ --depend $(startup_base).d $<
# Get binary image (compile and link)
build: output.bin
# Get hex image (compile and link)
hex: output.hex
# Run through assembler (checks for errors)
asm: $(main_base).o
# Run through linker
link: output.axf
# Flash using st-link
flash: output.bin
@echo -e "\e[0;96mWriting image to device via ST-Link\e[0m"
@$(STFLASH) write "output.bin" 0x8000000
@echo -e "\e[0;96mWrite OK!\e[0m"
disasm: output.axf
@echo -e "\e[0;33mDisassembling $< to output.disasm\e[0m"
@$(OBJDUMP) -d $< > output.disasm
# Remove temporary files
clean:
@echo -e "\e[0;32mRemoving temporary files\e[0m"
$(RM) -f *.bak *.lnp *.iex *.hex *.elf *.axf *.htm *.lnp *.lst *.plg *.tra *.o *.map *.d *.dep *.disasm *.bin

@ -0,0 +1,89 @@
# Keil (5) MDK-ARM projekt pro STM32L100 Discovery
Projekt je vyvíjen na *Katedře měření ČVUT FEL v Praze* a bude sloužit pro předmět [NVS][nvs] (příp. [MMP][mmp]).
- Ukázkový program je založený na starším kódu © Michal Tomáš, 2010.
- Základ knihovny a projektu © Petr Douša, 2015.
- Další úpravy knihovny, Makefile © Ondřej Hruška, 2015.
Kód je volně šiřitelný za podmínky zachování hlaviček souborů.
## Popis projektu
Jedná se o knihovnu definic adres registrů a bitů dle CMSIS a datasheetů spolu s ukázkovým programem,
který knihovnu využívá (a demonstruje nastavení RCC a pinů).
## Cílový hardware
Projekt je určen pro procesor **STM32L100RC** v kitu **STM32L100 Discovery**, který se připojí přes USB.
## Knihovna
Assemblerová knihovna sestává ze sady souborů ve složce `lib/` a startup scriptu `startup_stm32l100xc.s` (ten pochází
z instalace Keilu, dle hlavičky je přímo od ST).
Soubor `INI_REGS.s` obsahuje definice adres registrů, soubory `INI_BITS_*.s` pak bitové masky a hodnoty
jednotlivých registrů.
Soubor `INI_BB.s` poskutuje adresy pro bit-banding.
Soubory ze složky `lib/` je nutné naincludovat do hlavního programu, např.
```asm
; Register addresses
GET lib/INI_REGS.s
GET lib/INI_BB.s ; Must be included *after* INI_REGS!
; Bit presets
GET lib/INI_BITS_GPIO.s
GET lib/INI_BITS_RCC.s
GET lib/INI_BITS_FLASH.s
```
## Formátování
Soubory jsou formátovány se šířkou tabulátoru 4 znaky, komentáře jsou anglicky nebo bez diakritiky.
Soubory mají Windowsové konce řádků, aby nebyl problém s Keilem (a většina lidí to bude používat pod Windows).
## Jak s projektem pracovat
### Windows - Keil MDK-ARM
Projekt je primárně určen pro **µVision MDK-ARM v.5**, asm soubory fungují i ve verzi 4 (ale projekt bude potřeba upravit).
Keil je primárně pro Windows, pod Wine funguje, ale nedokáže přistupovat na ST-Link.
Ve Vitualboxu funguje včetne ST-Linku, ovšem pouze s verzí 2.
### Linux
Kompilace a nahrávání probíhá pomocí Makefile v projektu.
Napřed je potřeba nainstalovat následující software:
1. Pomocí `wine` nainstalovat Keil (do `~/.wine`) - z jeho složky se berou binutils a assembler, nejde je přesunout kvůli
licenčním souborům. Teoreticky by mohlo jít použít linuxové verze, pokud zjistíte jak nastavit, aby používaly licenční
soubory z Keilu (omezení na 32 kB).
2. Pro plnou funkčnost se hodí doinstalovat `arm-none-eabi-binutils`, ale není nutné - jen pro `make disasm`
3. Dále je potřeba nainstalovat `stlink` pro komunikaci s deskou, linuxová verze je volně dostupná.
*Tip:* Uživatelé ArchLinuxu vše najdou v oficiálních repozitářích.
#### V čem editovat
Jako editor lze použít Keil pod wine, libovolný textový editor nebo ARMovské IDE DS-5 Community Edition - bohužel nedovoluje
nic kompilovat, ale má dobru podporu pro assembler a kontextovou nápovědu.
[nvs]: http://measure.feld.cvut.cz/vyuka/predmety/A4B38NVS
[mmp]: http://measure.feld.cvut.cz/vyuka/predmety/A3B38MMP

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;********************************************************************************
; SOUBOR : INI_BB.S
; AUTOR : Ondrej Hruska
; DATUM : 10/2015
; POPIS : Adresy bit-bandingovych registru
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
; ======================== GPIO BITS ===========================
; ---------------------- IDR ----------------------
; IDR A
_BB_GPIOA_IDR EQU PERIPH_BB_BASE + (GPIOA_IDR - PERIPH_BASE) * 32
BB_GPIOA_IDR_0 EQU _BB_GPIOA_IDR + (4 * 0)
BB_GPIOA_IDR_1 EQU _BB_GPIOA_IDR + (4 * 1)
BB_GPIOA_IDR_2 EQU _BB_GPIOA_IDR + (4 * 2)
BB_GPIOA_IDR_3 EQU _BB_GPIOA_IDR + (4 * 3)
BB_GPIOA_IDR_4 EQU _BB_GPIOA_IDR + (4 * 4)
BB_GPIOA_IDR_5 EQU _BB_GPIOA_IDR + (4 * 5)
BB_GPIOA_IDR_6 EQU _BB_GPIOA_IDR + (4 * 6)
BB_GPIOA_IDR_7 EQU _BB_GPIOA_IDR + (4 * 7)
BB_GPIOA_IDR_8 EQU _BB_GPIOA_IDR + (4 * 8)
BB_GPIOA_IDR_9 EQU _BB_GPIOA_IDR + (4 * 9)
BB_GPIOA_IDR_10 EQU _BB_GPIOA_IDR + (4 * 10)
BB_GPIOA_IDR_11 EQU _BB_GPIOA_IDR + (4 * 11)
BB_GPIOA_IDR_12 EQU _BB_GPIOA_IDR + (4 * 12)
BB_GPIOA_IDR_13 EQU _BB_GPIOA_IDR + (4 * 13)
BB_GPIOA_IDR_14 EQU _BB_GPIOA_IDR + (4 * 14)
BB_GPIOA_IDR_15 EQU _BB_GPIOA_IDR + (4 * 15)
; IDR B
_BB_GPIOB_IDR EQU PERIPH_BB_BASE + (GPIOB_IDR - PERIPH_BASE) * 32
BB_GPIOB_IDR_0 EQU _BB_GPIOB_IDR + (4 * 0)
BB_GPIOB_IDR_1 EQU _BB_GPIOB_IDR + (4 * 1)
BB_GPIOB_IDR_2 EQU _BB_GPIOB_IDR + (4 * 2)
BB_GPIOB_IDR_3 EQU _BB_GPIOB_IDR + (4 * 3)
BB_GPIOB_IDR_4 EQU _BB_GPIOB_IDR + (4 * 4)
BB_GPIOB_IDR_5 EQU _BB_GPIOB_IDR + (4 * 5)
BB_GPIOB_IDR_6 EQU _BB_GPIOB_IDR + (4 * 6)
BB_GPIOB_IDR_7 EQU _BB_GPIOB_IDR + (4 * 7)
BB_GPIOB_IDR_8 EQU _BB_GPIOB_IDR + (4 * 8)
BB_GPIOB_IDR_9 EQU _BB_GPIOB_IDR + (4 * 9)
BB_GPIOB_IDR_10 EQU _BB_GPIOB_IDR + (4 * 10)
BB_GPIOB_IDR_11 EQU _BB_GPIOB_IDR + (4 * 11)
BB_GPIOB_IDR_12 EQU _BB_GPIOB_IDR + (4 * 12)
BB_GPIOB_IDR_13 EQU _BB_GPIOB_IDR + (4 * 13)
BB_GPIOB_IDR_14 EQU _BB_GPIOB_IDR + (4 * 14)
BB_GPIOB_IDR_15 EQU _BB_GPIOB_IDR + (4 * 15)
; IDR C
_BB_GPIOC_IDR EQU PERIPH_BB_BASE + (GPIOC_IDR - PERIPH_BASE) * 32
BB_GPIOC_IDR_0 EQU _BB_GPIOC_IDR + (4 * 0)
BB_GPIOC_IDR_1 EQU _BB_GPIOC_IDR + (4 * 1)
BB_GPIOC_IDR_2 EQU _BB_GPIOC_IDR + (4 * 2)
BB_GPIOC_IDR_3 EQU _BB_GPIOC_IDR + (4 * 3)
BB_GPIOC_IDR_4 EQU _BB_GPIOC_IDR + (4 * 4)
BB_GPIOC_IDR_5 EQU _BB_GPIOC_IDR + (4 * 5)
BB_GPIOC_IDR_6 EQU _BB_GPIOC_IDR + (4 * 6)
BB_GPIOC_IDR_7 EQU _BB_GPIOC_IDR + (4 * 7)
BB_GPIOC_IDR_8 EQU _BB_GPIOC_IDR + (4 * 8)
BB_GPIOC_IDR_9 EQU _BB_GPIOC_IDR + (4 * 9)
BB_GPIOC_IDR_10 EQU _BB_GPIOC_IDR + (4 * 10)
BB_GPIOC_IDR_11 EQU _BB_GPIOC_IDR + (4 * 11)
BB_GPIOC_IDR_12 EQU _BB_GPIOC_IDR + (4 * 12)
BB_GPIOC_IDR_13 EQU _BB_GPIOC_IDR + (4 * 13)
BB_GPIOC_IDR_14 EQU _BB_GPIOC_IDR + (4 * 14)
BB_GPIOC_IDR_15 EQU _BB_GPIOC_IDR + (4 * 15)
; IDR D
_BB_GPIOD_IDR EQU PERIPH_BB_BASE + (GPIOD_IDR - PERIPH_BASE) * 32
BB_GPIOD_IDR_0 EQU _BB_GPIOD_IDR + (4 * 0)
BB_GPIOD_IDR_1 EQU _BB_GPIOD_IDR + (4 * 1)
BB_GPIOD_IDR_2 EQU _BB_GPIOD_IDR + (4 * 2)
BB_GPIOD_IDR_3 EQU _BB_GPIOD_IDR + (4 * 3)
BB_GPIOD_IDR_4 EQU _BB_GPIOD_IDR + (4 * 4)
BB_GPIOD_IDR_5 EQU _BB_GPIOD_IDR + (4 * 5)
BB_GPIOD_IDR_6 EQU _BB_GPIOD_IDR + (4 * 6)
BB_GPIOD_IDR_7 EQU _BB_GPIOD_IDR + (4 * 7)
BB_GPIOD_IDR_8 EQU _BB_GPIOD_IDR + (4 * 8)
BB_GPIOD_IDR_9 EQU _BB_GPIOD_IDR + (4 * 9)
BB_GPIOD_IDR_10 EQU _BB_GPIOD_IDR + (4 * 10)
BB_GPIOD_IDR_11 EQU _BB_GPIOD_IDR + (4 * 11)
BB_GPIOD_IDR_12 EQU _BB_GPIOD_IDR + (4 * 12)
BB_GPIOD_IDR_13 EQU _BB_GPIOD_IDR + (4 * 13)
BB_GPIOD_IDR_14 EQU _BB_GPIOD_IDR + (4 * 14)
BB_GPIOD_IDR_15 EQU _BB_GPIOD_IDR + (4 * 15)
; IDR E
_BB_GPIOE_IDR EQU PERIPH_BB_BASE + (GPIOE_IDR - PERIPH_BASE) * 32
BB_GPIOE_IDR_0 EQU _BB_GPIOE_IDR + (4 * 0)
BB_GPIOE_IDR_1 EQU _BB_GPIOE_IDR + (4 * 1)
BB_GPIOE_IDR_2 EQU _BB_GPIOE_IDR + (4 * 2)
BB_GPIOE_IDR_3 EQU _BB_GPIOE_IDR + (4 * 3)
BB_GPIOE_IDR_4 EQU _BB_GPIOE_IDR + (4 * 4)
BB_GPIOE_IDR_5 EQU _BB_GPIOE_IDR + (4 * 5)
BB_GPIOE_IDR_6 EQU _BB_GPIOE_IDR + (4 * 6)
BB_GPIOE_IDR_7 EQU _BB_GPIOE_IDR + (4 * 7)
BB_GPIOE_IDR_8 EQU _BB_GPIOE_IDR + (4 * 8)
BB_GPIOE_IDR_9 EQU _BB_GPIOE_IDR + (4 * 9)
BB_GPIOE_IDR_10 EQU _BB_GPIOE_IDR + (4 * 10)
BB_GPIOE_IDR_11 EQU _BB_GPIOE_IDR + (4 * 11)
BB_GPIOE_IDR_12 EQU _BB_GPIOE_IDR + (4 * 12)
BB_GPIOE_IDR_13 EQU _BB_GPIOE_IDR + (4 * 13)
BB_GPIOE_IDR_14 EQU _BB_GPIOE_IDR + (4 * 14)
BB_GPIOE_IDR_15 EQU _BB_GPIOE_IDR + (4 * 15)
; IDR F
_BB_GPIOF_IDR EQU PERIPH_BB_BASE + (GPIOF_IDR - PERIPH_BASE) * 32
BB_GPIOF_IDR_0 EQU _BB_GPIOF_IDR + (4 * 0)
BB_GPIOF_IDR_1 EQU _BB_GPIOF_IDR + (4 * 1)
BB_GPIOF_IDR_2 EQU _BB_GPIOF_IDR + (4 * 2)
BB_GPIOF_IDR_3 EQU _BB_GPIOF_IDR + (4 * 3)
BB_GPIOF_IDR_4 EQU _BB_GPIOF_IDR + (4 * 4)
BB_GPIOF_IDR_5 EQU _BB_GPIOF_IDR + (4 * 5)
BB_GPIOF_IDR_6 EQU _BB_GPIOF_IDR + (4 * 6)
BB_GPIOF_IDR_7 EQU _BB_GPIOF_IDR + (4 * 7)
BB_GPIOF_IDR_8 EQU _BB_GPIOF_IDR + (4 * 8)
BB_GPIOF_IDR_9 EQU _BB_GPIOF_IDR + (4 * 9)
BB_GPIOF_IDR_10 EQU _BB_GPIOF_IDR + (4 * 10)
BB_GPIOF_IDR_11 EQU _BB_GPIOF_IDR + (4 * 11)
BB_GPIOF_IDR_12 EQU _BB_GPIOF_IDR + (4 * 12)
BB_GPIOF_IDR_13 EQU _BB_GPIOF_IDR + (4 * 13)
BB_GPIOF_IDR_14 EQU _BB_GPIOF_IDR + (4 * 14)
BB_GPIOF_IDR_15 EQU _BB_GPIOF_IDR + (4 * 15)
; IDR G
_BB_GPIOG_IDR EQU PERIPH_BB_BASE + (GPIOG_IDR - PERIPH_BASE) * 32
BB_GPIOG_IDR_0 EQU _BB_GPIOG_IDR + (4 * 0)
BB_GPIOG_IDR_1 EQU _BB_GPIOG_IDR + (4 * 1)
BB_GPIOG_IDR_2 EQU _BB_GPIOG_IDR + (4 * 2)
BB_GPIOG_IDR_3 EQU _BB_GPIOG_IDR + (4 * 3)
BB_GPIOG_IDR_4 EQU _BB_GPIOG_IDR + (4 * 4)
BB_GPIOG_IDR_5 EQU _BB_GPIOG_IDR + (4 * 5)
BB_GPIOG_IDR_6 EQU _BB_GPIOG_IDR + (4 * 6)
BB_GPIOG_IDR_7 EQU _BB_GPIOG_IDR + (4 * 7)
BB_GPIOG_IDR_8 EQU _BB_GPIOG_IDR + (4 * 8)
BB_GPIOG_IDR_9 EQU _BB_GPIOG_IDR + (4 * 9)
BB_GPIOG_IDR_10 EQU _BB_GPIOG_IDR + (4 * 10)
BB_GPIOG_IDR_11 EQU _BB_GPIOG_IDR + (4 * 11)
BB_GPIOG_IDR_12 EQU _BB_GPIOG_IDR + (4 * 12)
BB_GPIOG_IDR_13 EQU _BB_GPIOG_IDR + (4 * 13)
BB_GPIOG_IDR_14 EQU _BB_GPIOG_IDR + (4 * 14)
BB_GPIOG_IDR_15 EQU _BB_GPIOG_IDR + (4 * 15)
; IDR H
_BB_GPIOH_IDR EQU PERIPH_BB_BASE + (GPIOH_IDR - PERIPH_BASE) * 32
BB_GPIOH_IDR_0 EQU _BB_GPIOH_IDR + (4 * 0)
BB_GPIOH_IDR_1 EQU _BB_GPIOH_IDR + (4 * 1)
BB_GPIOH_IDR_2 EQU _BB_GPIOH_IDR + (4 * 2)
BB_GPIOH_IDR_3 EQU _BB_GPIOH_IDR + (4 * 3)
BB_GPIOH_IDR_4 EQU _BB_GPIOH_IDR + (4 * 4)
BB_GPIOH_IDR_5 EQU _BB_GPIOH_IDR + (4 * 5)
BB_GPIOH_IDR_6 EQU _BB_GPIOH_IDR + (4 * 6)
BB_GPIOH_IDR_7 EQU _BB_GPIOH_IDR + (4 * 7)
BB_GPIOH_IDR_8 EQU _BB_GPIOH_IDR + (4 * 8)
BB_GPIOH_IDR_9 EQU _BB_GPIOH_IDR + (4 * 9)
BB_GPIOH_IDR_10 EQU _BB_GPIOH_IDR + (4 * 10)
BB_GPIOH_IDR_11 EQU _BB_GPIOH_IDR + (4 * 11)
BB_GPIOH_IDR_12 EQU _BB_GPIOH_IDR + (4 * 12)
BB_GPIOH_IDR_13 EQU _BB_GPIOH_IDR + (4 * 13)
BB_GPIOH_IDR_14 EQU _BB_GPIOH_IDR + (4 * 14)
BB_GPIOH_IDR_15 EQU _BB_GPIOH_IDR + (4 * 15)
; ------------------ ODR ---------------------
; ODR A
_BB_GPIOA_ODR EQU PERIPH_BB_BASE + (GPIOA_ODR - PERIPH_BASE) * 32
BB_GPIOA_ODR_0 EQU _BB_GPIOA_ODR + (4 * 0)
BB_GPIOA_ODR_1 EQU _BB_GPIOA_ODR + (4 * 1)
BB_GPIOA_ODR_2 EQU _BB_GPIOA_ODR + (4 * 2)
BB_GPIOA_ODR_3 EQU _BB_GPIOA_ODR + (4 * 3)
BB_GPIOA_ODR_4 EQU _BB_GPIOA_ODR + (4 * 4)
BB_GPIOA_ODR_5 EQU _BB_GPIOA_ODR + (4 * 5)
BB_GPIOA_ODR_6 EQU _BB_GPIOA_ODR + (4 * 6)
BB_GPIOA_ODR_7 EQU _BB_GPIOA_ODR + (4 * 7)
BB_GPIOA_ODR_8 EQU _BB_GPIOA_ODR + (4 * 8)
BB_GPIOA_ODR_9 EQU _BB_GPIOA_ODR + (4 * 9)
BB_GPIOA_ODR_10 EQU _BB_GPIOA_ODR + (4 * 10)
BB_GPIOA_ODR_11 EQU _BB_GPIOA_ODR + (4 * 11)
BB_GPIOA_ODR_12 EQU _BB_GPIOA_ODR + (4 * 12)
BB_GPIOA_ODR_13 EQU _BB_GPIOA_ODR + (4 * 13)
BB_GPIOA_ODR_14 EQU _BB_GPIOA_ODR + (4 * 14)
BB_GPIOA_ODR_15 EQU _BB_GPIOA_ODR + (4 * 15)
; ODR B
_BB_GPIOB_ODR EQU PERIPH_BB_BASE + (GPIOB_ODR - PERIPH_BASE) * 32
BB_GPIOB_ODR_0 EQU _BB_GPIOB_ODR + (4 * 0)
BB_GPIOB_ODR_1 EQU _BB_GPIOB_ODR + (4 * 1)
BB_GPIOB_ODR_2 EQU _BB_GPIOB_ODR + (4 * 2)
BB_GPIOB_ODR_3 EQU _BB_GPIOB_ODR + (4 * 3)
BB_GPIOB_ODR_4 EQU _BB_GPIOB_ODR + (4 * 4)
BB_GPIOB_ODR_5 EQU _BB_GPIOB_ODR + (4 * 5)
BB_GPIOB_ODR_6 EQU _BB_GPIOB_ODR + (4 * 6)
BB_GPIOB_ODR_7 EQU _BB_GPIOB_ODR + (4 * 7)
BB_GPIOB_ODR_8 EQU _BB_GPIOB_ODR + (4 * 8)
BB_GPIOB_ODR_9 EQU _BB_GPIOB_ODR + (4 * 9)
BB_GPIOB_ODR_10 EQU _BB_GPIOB_ODR + (4 * 10)
BB_GPIOB_ODR_11 EQU _BB_GPIOB_ODR + (4 * 11)
BB_GPIOB_ODR_12 EQU _BB_GPIOB_ODR + (4 * 12)
BB_GPIOB_ODR_13 EQU _BB_GPIOB_ODR + (4 * 13)
BB_GPIOB_ODR_14 EQU _BB_GPIOB_ODR + (4 * 14)
BB_GPIOB_ODR_15 EQU _BB_GPIOB_ODR + (4 * 15)
; ODR C
_BB_GPIOC_ODR EQU PERIPH_BB_BASE + (GPIOC_ODR - PERIPH_BASE) * 32
BB_GPIOC_ODR_0 EQU _BB_GPIOC_ODR + (4 * 0)
BB_GPIOC_ODR_1 EQU _BB_GPIOC_ODR + (4 * 1)
BB_GPIOC_ODR_2 EQU _BB_GPIOC_ODR + (4 * 2)
BB_GPIOC_ODR_3 EQU _BB_GPIOC_ODR + (4 * 3)
BB_GPIOC_ODR_4 EQU _BB_GPIOC_ODR + (4 * 4)
BB_GPIOC_ODR_5 EQU _BB_GPIOC_ODR + (4 * 5)
BB_GPIOC_ODR_6 EQU _BB_GPIOC_ODR + (4 * 6)
BB_GPIOC_ODR_7 EQU _BB_GPIOC_ODR + (4 * 7)
BB_GPIOC_ODR_8 EQU _BB_GPIOC_ODR + (4 * 8)
BB_GPIOC_ODR_9 EQU _BB_GPIOC_ODR + (4 * 9)
BB_GPIOC_ODR_10 EQU _BB_GPIOC_ODR + (4 * 10)
BB_GPIOC_ODR_11 EQU _BB_GPIOC_ODR + (4 * 11)
BB_GPIOC_ODR_12 EQU _BB_GPIOC_ODR + (4 * 12)
BB_GPIOC_ODR_13 EQU _BB_GPIOC_ODR + (4 * 13)
BB_GPIOC_ODR_14 EQU _BB_GPIOC_ODR + (4 * 14)
BB_GPIOC_ODR_15 EQU _BB_GPIOC_ODR + (4 * 15)
; ODR D
_BB_GPIOD_ODR EQU PERIPH_BB_BASE + (GPIOD_ODR - PERIPH_BASE) * 32
BB_GPIOD_ODR_0 EQU _BB_GPIOD_ODR + (4 * 0)
BB_GPIOD_ODR_1 EQU _BB_GPIOD_ODR + (4 * 1)
BB_GPIOD_ODR_2 EQU _BB_GPIOD_ODR + (4 * 2)
BB_GPIOD_ODR_3 EQU _BB_GPIOD_ODR + (4 * 3)
BB_GPIOD_ODR_4 EQU _BB_GPIOD_ODR + (4 * 4)
BB_GPIOD_ODR_5 EQU _BB_GPIOD_ODR + (4 * 5)
BB_GPIOD_ODR_6 EQU _BB_GPIOD_ODR + (4 * 6)
BB_GPIOD_ODR_7 EQU _BB_GPIOD_ODR + (4 * 7)
BB_GPIOD_ODR_8 EQU _BB_GPIOD_ODR + (4 * 8)
BB_GPIOD_ODR_9 EQU _BB_GPIOD_ODR + (4 * 9)
BB_GPIOD_ODR_10 EQU _BB_GPIOD_ODR + (4 * 10)
BB_GPIOD_ODR_11 EQU _BB_GPIOD_ODR + (4 * 11)
BB_GPIOD_ODR_12 EQU _BB_GPIOD_ODR + (4 * 12)
BB_GPIOD_ODR_13 EQU _BB_GPIOD_ODR + (4 * 13)
BB_GPIOD_ODR_14 EQU _BB_GPIOD_ODR + (4 * 14)
BB_GPIOD_ODR_15 EQU _BB_GPIOD_ODR + (4 * 15)
; ODR E
_BB_GPIOE_ODR EQU PERIPH_BB_BASE + (GPIOE_ODR - PERIPH_BASE) * 32
BB_GPIOE_ODR_0 EQU _BB_GPIOE_ODR + (4 * 0)
BB_GPIOE_ODR_1 EQU _BB_GPIOE_ODR + (4 * 1)
BB_GPIOE_ODR_2 EQU _BB_GPIOE_ODR + (4 * 2)
BB_GPIOE_ODR_3 EQU _BB_GPIOE_ODR + (4 * 3)
BB_GPIOE_ODR_4 EQU _BB_GPIOE_ODR + (4 * 4)
BB_GPIOE_ODR_5 EQU _BB_GPIOE_ODR + (4 * 5)
BB_GPIOE_ODR_6 EQU _BB_GPIOE_ODR + (4 * 6)
BB_GPIOE_ODR_7 EQU _BB_GPIOE_ODR + (4 * 7)
BB_GPIOE_ODR_8 EQU _BB_GPIOE_ODR + (4 * 8)
BB_GPIOE_ODR_9 EQU _BB_GPIOE_ODR + (4 * 9)
BB_GPIOE_ODR_10 EQU _BB_GPIOE_ODR + (4 * 10)
BB_GPIOE_ODR_11 EQU _BB_GPIOE_ODR + (4 * 11)
BB_GPIOE_ODR_12 EQU _BB_GPIOE_ODR + (4 * 12)
BB_GPIOE_ODR_13 EQU _BB_GPIOE_ODR + (4 * 13)
BB_GPIOE_ODR_14 EQU _BB_GPIOE_ODR + (4 * 14)
BB_GPIOE_ODR_15 EQU _BB_GPIOE_ODR + (4 * 15)
; ODR F
_BB_GPIOF_ODR EQU PERIPH_BB_BASE + (GPIOF_ODR - PERIPH_BASE) * 32
BB_GPIOF_ODR_0 EQU _BB_GPIOF_ODR + (4 * 0)
BB_GPIOF_ODR_1 EQU _BB_GPIOF_ODR + (4 * 1)
BB_GPIOF_ODR_2 EQU _BB_GPIOF_ODR + (4 * 2)
BB_GPIOF_ODR_3 EQU _BB_GPIOF_ODR + (4 * 3)
BB_GPIOF_ODR_4 EQU _BB_GPIOF_ODR + (4 * 4)
BB_GPIOF_ODR_5 EQU _BB_GPIOF_ODR + (4 * 5)
BB_GPIOF_ODR_6 EQU _BB_GPIOF_ODR + (4 * 6)
BB_GPIOF_ODR_7 EQU _BB_GPIOF_ODR + (4 * 7)
BB_GPIOF_ODR_8 EQU _BB_GPIOF_ODR + (4 * 8)
BB_GPIOF_ODR_9 EQU _BB_GPIOF_ODR + (4 * 9)
BB_GPIOF_ODR_10 EQU _BB_GPIOF_ODR + (4 * 10)
BB_GPIOF_ODR_11 EQU _BB_GPIOF_ODR + (4 * 11)
BB_GPIOF_ODR_12 EQU _BB_GPIOF_ODR + (4 * 12)
BB_GPIOF_ODR_13 EQU _BB_GPIOF_ODR + (4 * 13)
BB_GPIOF_ODR_14 EQU _BB_GPIOF_ODR + (4 * 14)
BB_GPIOF_ODR_15 EQU _BB_GPIOF_ODR + (4 * 15)
; ODR G
_BB_GPIOG_ODR EQU PERIPH_BB_BASE + (GPIOG_ODR - PERIPH_BASE) * 32
BB_GPIOG_ODR_0 EQU _BB_GPIOG_ODR + (4 * 0)
BB_GPIOG_ODR_1 EQU _BB_GPIOG_ODR + (4 * 1)
BB_GPIOG_ODR_2 EQU _BB_GPIOG_ODR + (4 * 2)
BB_GPIOG_ODR_3 EQU _BB_GPIOG_ODR + (4 * 3)
BB_GPIOG_ODR_4 EQU _BB_GPIOG_ODR + (4 * 4)
BB_GPIOG_ODR_5 EQU _BB_GPIOG_ODR + (4 * 5)
BB_GPIOG_ODR_6 EQU _BB_GPIOG_ODR + (4 * 6)
BB_GPIOG_ODR_7 EQU _BB_GPIOG_ODR + (4 * 7)
BB_GPIOG_ODR_8 EQU _BB_GPIOG_ODR + (4 * 8)
BB_GPIOG_ODR_9 EQU _BB_GPIOG_ODR + (4 * 9)
BB_GPIOG_ODR_10 EQU _BB_GPIOG_ODR + (4 * 10)
BB_GPIOG_ODR_11 EQU _BB_GPIOG_ODR + (4 * 11)
BB_GPIOG_ODR_12 EQU _BB_GPIOG_ODR + (4 * 12)
BB_GPIOG_ODR_13 EQU _BB_GPIOG_ODR + (4 * 13)
BB_GPIOG_ODR_14 EQU _BB_GPIOG_ODR + (4 * 14)
BB_GPIOG_ODR_15 EQU _BB_GPIOG_ODR + (4 * 15)
; ODR H
_BB_GPIOH_ODR EQU PERIPH_BB_BASE + (GPIOH_ODR - PERIPH_BASE) * 32
BB_GPIOH_ODR_0 EQU _BB_GPIOH_ODR + (4 * 0)
BB_GPIOH_ODR_1 EQU _BB_GPIOH_ODR + (4 * 1)
BB_GPIOH_ODR_2 EQU _BB_GPIOH_ODR + (4 * 2)
BB_GPIOH_ODR_3 EQU _BB_GPIOH_ODR + (4 * 3)
BB_GPIOH_ODR_4 EQU _BB_GPIOH_ODR + (4 * 4)
BB_GPIOH_ODR_5 EQU _BB_GPIOH_ODR + (4 * 5)
BB_GPIOH_ODR_6 EQU _BB_GPIOH_ODR + (4 * 6)
BB_GPIOH_ODR_7 EQU _BB_GPIOH_ODR + (4 * 7)
BB_GPIOH_ODR_8 EQU _BB_GPIOH_ODR + (4 * 8)
BB_GPIOH_ODR_9 EQU _BB_GPIOH_ODR + (4 * 9)
BB_GPIOH_ODR_10 EQU _BB_GPIOH_ODR + (4 * 10)
BB_GPIOH_ODR_11 EQU _BB_GPIOH_ODR + (4 * 11)
BB_GPIOH_ODR_12 EQU _BB_GPIOH_ODR + (4 * 12)
BB_GPIOH_ODR_13 EQU _BB_GPIOH_ODR + (4 * 13)
BB_GPIOH_ODR_14 EQU _BB_GPIOH_ODR + (4 * 14)
BB_GPIOH_ODR_15 EQU _BB_GPIOH_ODR + (4 * 15)
; ---------------------- LCKR ---------------------------
; LCKR A
_BB_GPIOA_LCKR EQU PERIPH_BB_BASE + (GPIOA_LCKR - PERIPH_BASE) * 32
BB_GPIOA_LCKR_0 EQU _BB_GPIOA_LCKR + (4 * 0)
BB_GPIOA_LCKR_1 EQU _BB_GPIOA_LCKR + (4 * 1)
BB_GPIOA_LCKR_2 EQU _BB_GPIOA_LCKR + (4 * 2)
BB_GPIOA_LCKR_3 EQU _BB_GPIOA_LCKR + (4 * 3)
BB_GPIOA_LCKR_4 EQU _BB_GPIOA_LCKR + (4 * 4)
BB_GPIOA_LCKR_5 EQU _BB_GPIOA_LCKR + (4 * 5)
BB_GPIOA_LCKR_6 EQU _BB_GPIOA_LCKR + (4 * 6)
BB_GPIOA_LCKR_7 EQU _BB_GPIOA_LCKR + (4 * 7)
BB_GPIOA_LCKR_8 EQU _BB_GPIOA_LCKR + (4 * 8)
BB_GPIOA_LCKR_9 EQU _BB_GPIOA_LCKR + (4 * 9)
BB_GPIOA_LCKR_10 EQU _BB_GPIOA_LCKR + (4 * 10)
BB_GPIOA_LCKR_11 EQU _BB_GPIOA_LCKR + (4 * 11)
BB_GPIOA_LCKR_12 EQU _BB_GPIOA_LCKR + (4 * 12)
BB_GPIOA_LCKR_13 EQU _BB_GPIOA_LCKR + (4 * 13)
BB_GPIOA_LCKR_14 EQU _BB_GPIOA_LCKR + (4 * 14)
BB_GPIOA_LCKR_15 EQU _BB_GPIOA_LCKR + (4 * 15)
BB_GPIOA_LCKR_K EQU _BB_GPIOA_LCKR + (4 * 16) ; Lock key bit
; LCKR B
_BB_GPIOB_LCKR EQU PERIPH_BB_BASE + (GPIOB_LCKR - PERIPH_BASE) * 32
BB_GPIOB_LCKR_0 EQU _BB_GPIOB_LCKR + (4 * 0)
BB_GPIOB_LCKR_1 EQU _BB_GPIOB_LCKR + (4 * 1)
BB_GPIOB_LCKR_2 EQU _BB_GPIOB_LCKR + (4 * 2)
BB_GPIOB_LCKR_3 EQU _BB_GPIOB_LCKR + (4 * 3)
BB_GPIOB_LCKR_4 EQU _BB_GPIOB_LCKR + (4 * 4)
BB_GPIOB_LCKR_5 EQU _BB_GPIOB_LCKR + (4 * 5)
BB_GPIOB_LCKR_6 EQU _BB_GPIOB_LCKR + (4 * 6)
BB_GPIOB_LCKR_7 EQU _BB_GPIOB_LCKR + (4 * 7)
BB_GPIOB_LCKR_8 EQU _BB_GPIOB_LCKR + (4 * 8)
BB_GPIOB_LCKR_9 EQU _BB_GPIOB_LCKR + (4 * 9)
BB_GPIOB_LCKR_10 EQU _BB_GPIOB_LCKR + (4 * 10)
BB_GPIOB_LCKR_11 EQU _BB_GPIOB_LCKR + (4 * 11)
BB_GPIOB_LCKR_12 EQU _BB_GPIOB_LCKR + (4 * 12)
BB_GPIOB_LCKR_13 EQU _BB_GPIOB_LCKR + (4 * 13)
BB_GPIOB_LCKR_14 EQU _BB_GPIOB_LCKR + (4 * 14)
BB_GPIOB_LCKR_15 EQU _BB_GPIOB_LCKR + (4 * 15)
BB_GPIOB_LCKR_K EQU _BB_GPIOB_LCKR + (4 * 16) ; Lock key bit
; LCKR C
_BB_GPIOC_LCKR EQU PERIPH_BB_BASE + (GPIOC_LCKR - PERIPH_BASE) * 32
BB_GPIOC_LCKR_0 EQU _BB_GPIOC_LCKR + (4 * 0)
BB_GPIOC_LCKR_1 EQU _BB_GPIOC_LCKR + (4 * 1)
BB_GPIOC_LCKR_2 EQU _BB_GPIOC_LCKR + (4 * 2)
BB_GPIOC_LCKR_3 EQU _BB_GPIOC_LCKR + (4 * 3)
BB_GPIOC_LCKR_4 EQU _BB_GPIOC_LCKR + (4 * 4)
BB_GPIOC_LCKR_5 EQU _BB_GPIOC_LCKR + (4 * 5)
BB_GPIOC_LCKR_6 EQU _BB_GPIOC_LCKR + (4 * 6)
BB_GPIOC_LCKR_7 EQU _BB_GPIOC_LCKR + (4 * 7)
BB_GPIOC_LCKR_8 EQU _BB_GPIOC_LCKR + (4 * 8)
BB_GPIOC_LCKR_9 EQU _BB_GPIOC_LCKR + (4 * 9)
BB_GPIOC_LCKR_10 EQU _BB_GPIOC_LCKR + (4 * 10)
BB_GPIOC_LCKR_11 EQU _BB_GPIOC_LCKR + (4 * 11)
BB_GPIOC_LCKR_12 EQU _BB_GPIOC_LCKR + (4 * 12)
BB_GPIOC_LCKR_13 EQU _BB_GPIOC_LCKR + (4 * 13)
BB_GPIOC_LCKR_14 EQU _BB_GPIOC_LCKR + (4 * 14)
BB_GPIOC_LCKR_15 EQU _BB_GPIOC_LCKR + (4 * 15)
BB_GPIOC_LCKR_K EQU _BB_GPIOC_LCKR + (4 * 16) ; Lock key bit
; LCKR D
_BB_GPIOD_LCKR EQU PERIPH_BB_BASE + (GPIOD_LCKR - PERIPH_BASE) * 32
BB_GPIOD_LCKR_0 EQU _BB_GPIOD_LCKR + (4 * 0)
BB_GPIOD_LCKR_1 EQU _BB_GPIOD_LCKR + (4 * 1)
BB_GPIOD_LCKR_2 EQU _BB_GPIOD_LCKR + (4 * 2)
BB_GPIOD_LCKR_3 EQU _BB_GPIOD_LCKR + (4 * 3)
BB_GPIOD_LCKR_4 EQU _BB_GPIOD_LCKR + (4 * 4)
BB_GPIOD_LCKR_5 EQU _BB_GPIOD_LCKR + (4 * 5)
BB_GPIOD_LCKR_6 EQU _BB_GPIOD_LCKR + (4 * 6)
BB_GPIOD_LCKR_7 EQU _BB_GPIOD_LCKR + (4 * 7)
BB_GPIOD_LCKR_8 EQU _BB_GPIOD_LCKR + (4 * 8)
BB_GPIOD_LCKR_9 EQU _BB_GPIOD_LCKR + (4 * 9)
BB_GPIOD_LCKR_10 EQU _BB_GPIOD_LCKR + (4 * 10)
BB_GPIOD_LCKR_11 EQU _BB_GPIOD_LCKR + (4 * 11)
BB_GPIOD_LCKR_12 EQU _BB_GPIOD_LCKR + (4 * 12)
BB_GPIOD_LCKR_13 EQU _BB_GPIOD_LCKR + (4 * 13)
BB_GPIOD_LCKR_14 EQU _BB_GPIOD_LCKR + (4 * 14)
BB_GPIOD_LCKR_15 EQU _BB_GPIOD_LCKR + (4 * 15)
BB_GPIOD_LCKR_K EQU _BB_GPIOD_LCKR + (4 * 16) ; Lock key bit
; LCKR E
_BB_GPIOE_LCKR EQU PERIPH_BB_BASE + (GPIOE_LCKR - PERIPH_BASE) * 32
BB_GPIOE_LCKR_0 EQU _BB_GPIOE_LCKR + (4 * 0)
BB_GPIOE_LCKR_1 EQU _BB_GPIOE_LCKR + (4 * 1)
BB_GPIOE_LCKR_2 EQU _BB_GPIOE_LCKR + (4 * 2)
BB_GPIOE_LCKR_3 EQU _BB_GPIOE_LCKR + (4 * 3)
BB_GPIOE_LCKR_4 EQU _BB_GPIOE_LCKR + (4 * 4)
BB_GPIOE_LCKR_5 EQU _BB_GPIOE_LCKR + (4 * 5)
BB_GPIOE_LCKR_6 EQU _BB_GPIOE_LCKR + (4 * 6)
BB_GPIOE_LCKR_7 EQU _BB_GPIOE_LCKR + (4 * 7)
BB_GPIOE_LCKR_8 EQU _BB_GPIOE_LCKR + (4 * 8)
BB_GPIOE_LCKR_9 EQU _BB_GPIOE_LCKR + (4 * 9)
BB_GPIOE_LCKR_10 EQU _BB_GPIOE_LCKR + (4 * 10)
BB_GPIOE_LCKR_11 EQU _BB_GPIOE_LCKR + (4 * 11)
BB_GPIOE_LCKR_12 EQU _BB_GPIOE_LCKR + (4 * 12)
BB_GPIOE_LCKR_13 EQU _BB_GPIOE_LCKR + (4 * 13)
BB_GPIOE_LCKR_14 EQU _BB_GPIOE_LCKR + (4 * 14)
BB_GPIOE_LCKR_15 EQU _BB_GPIOE_LCKR + (4 * 15)
BB_GPIOE_LCKR_K EQU _BB_GPIOE_LCKR + (4 * 16) ; Lock key bit
; LCKR F
_BB_GPIOF_LCKR EQU PERIPH_BB_BASE + (GPIOF_LCKR - PERIPH_BASE) * 32
BB_GPIOF_LCKR_0 EQU _BB_GPIOF_LCKR + (4 * 0)
BB_GPIOF_LCKR_1 EQU _BB_GPIOF_LCKR + (4 * 1)
BB_GPIOF_LCKR_2 EQU _BB_GPIOF_LCKR + (4 * 2)
BB_GPIOF_LCKR_3 EQU _BB_GPIOF_LCKR + (4 * 3)
BB_GPIOF_LCKR_4 EQU _BB_GPIOF_LCKR + (4 * 4)
BB_GPIOF_LCKR_5 EQU _BB_GPIOF_LCKR + (4 * 5)
BB_GPIOF_LCKR_6 EQU _BB_GPIOF_LCKR + (4 * 6)
BB_GPIOF_LCKR_7 EQU _BB_GPIOF_LCKR + (4 * 7)
BB_GPIOF_LCKR_8 EQU _BB_GPIOF_LCKR + (4 * 8)
BB_GPIOF_LCKR_9 EQU _BB_GPIOF_LCKR + (4 * 9)
BB_GPIOF_LCKR_10 EQU _BB_GPIOF_LCKR + (4 * 10)
BB_GPIOF_LCKR_11 EQU _BB_GPIOF_LCKR + (4 * 11)
BB_GPIOF_LCKR_12 EQU _BB_GPIOF_LCKR + (4 * 12)
BB_GPIOF_LCKR_13 EQU _BB_GPIOF_LCKR + (4 * 13)
BB_GPIOF_LCKR_14 EQU _BB_GPIOF_LCKR + (4 * 14)
BB_GPIOF_LCKR_15 EQU _BB_GPIOF_LCKR + (4 * 15)
BB_GPIOF_LCKR_K EQU _BB_GPIOF_LCKR + (4 * 16) ; Lock key bit
; LCKR G
_BB_GPIOG_LCKR EQU PERIPH_BB_BASE + (GPIOG_LCKR - PERIPH_BASE) * 32
BB_GPIOG_LCKR_0 EQU _BB_GPIOG_LCKR + (4 * 0)
BB_GPIOG_LCKR_1 EQU _BB_GPIOG_LCKR + (4 * 1)
BB_GPIOG_LCKR_2 EQU _BB_GPIOG_LCKR + (4 * 2)
BB_GPIOG_LCKR_3 EQU _BB_GPIOG_LCKR + (4 * 3)
BB_GPIOG_LCKR_4 EQU _BB_GPIOG_LCKR + (4 * 4)
BB_GPIOG_LCKR_5 EQU _BB_GPIOG_LCKR + (4 * 5)
BB_GPIOG_LCKR_6 EQU _BB_GPIOG_LCKR + (4 * 6)
BB_GPIOG_LCKR_7 EQU _BB_GPIOG_LCKR + (4 * 7)
BB_GPIOG_LCKR_8 EQU _BB_GPIOG_LCKR + (4 * 8)
BB_GPIOG_LCKR_9 EQU _BB_GPIOG_LCKR + (4 * 9)
BB_GPIOG_LCKR_10 EQU _BB_GPIOG_LCKR + (4 * 10)
BB_GPIOG_LCKR_11 EQU _BB_GPIOG_LCKR + (4 * 11)
BB_GPIOG_LCKR_12 EQU _BB_GPIOG_LCKR + (4 * 12)
BB_GPIOG_LCKR_13 EQU _BB_GPIOG_LCKR + (4 * 13)
BB_GPIOG_LCKR_14 EQU _BB_GPIOG_LCKR + (4 * 14)
BB_GPIOG_LCKR_15 EQU _BB_GPIOG_LCKR + (4 * 15)
BB_GPIOG_LCKR_K EQU _BB_GPIOG_LCKR + (4 * 16) ; Lock key bit
; LCKR H
_BB_GPIOH_LCKR EQU PERIPH_BB_BASE + (GPIOH_LCKR - PERIPH_BASE) * 32
BB_GPIOH_LCKR_0 EQU _BB_GPIOH_LCKR + (4 * 0)
BB_GPIOH_LCKR_1 EQU _BB_GPIOH_LCKR + (4 * 1)
BB_GPIOH_LCKR_2 EQU _BB_GPIOH_LCKR + (4 * 2)
BB_GPIOH_LCKR_3 EQU _BB_GPIOH_LCKR + (4 * 3)
BB_GPIOH_LCKR_4 EQU _BB_GPIOH_LCKR + (4 * 4)
BB_GPIOH_LCKR_5 EQU _BB_GPIOH_LCKR + (4 * 5)
BB_GPIOH_LCKR_6 EQU _BB_GPIOH_LCKR + (4 * 6)
BB_GPIOH_LCKR_7 EQU _BB_GPIOH_LCKR + (4 * 7)
BB_GPIOH_LCKR_8 EQU _BB_GPIOH_LCKR + (4 * 8)
BB_GPIOH_LCKR_9 EQU _BB_GPIOH_LCKR + (4 * 9)
BB_GPIOH_LCKR_10 EQU _BB_GPIOH_LCKR + (4 * 10)
BB_GPIOH_LCKR_11 EQU _BB_GPIOH_LCKR + (4 * 11)
BB_GPIOH_LCKR_12 EQU _BB_GPIOH_LCKR + (4 * 12)
BB_GPIOH_LCKR_13 EQU _BB_GPIOH_LCKR + (4 * 13)
BB_GPIOH_LCKR_14 EQU _BB_GPIOH_LCKR + (4 * 14)
BB_GPIOH_LCKR_15 EQU _BB_GPIOH_LCKR + (4 * 15)
BB_GPIOH_LCKR_K EQU _BB_GPIOH_LCKR + (4 * 16) ; Lock key bit
END

@ -0,0 +1,554 @@
;********************************************************************************
; SOUBOR : INI_BITS_ADC.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro ADC
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Analog to Digital Converter (ADC)
;
;****************************************************************************
;******************* Bit definition for ADC_SR register *******************
ADC_SR_AWD EQU 0x00000001 ; Analog watchdog flag
ADC_SR_EOC EQU 0x00000002 ; End of conversion
ADC_SR_JEOC EQU 0x00000004 ; Injected channel end of conversion
ADC_SR_JSTRT EQU 0x00000008 ; Injected channel Start flag
ADC_SR_STRT EQU 0x00000010 ; Regular channel Start flag
ADC_SR_OVR EQU 0x00000020 ; Overrun flag
ADC_SR_ADONS EQU 0x00000040 ; ADC ON status
ADC_SR_RCNR EQU 0x00000100 ; Regular channel not ready flag
ADC_SR_JCNR EQU 0x00000200 ; Injected channel not ready flag
;****************** Bit definition for ADC_CR1 register *******************
ADC_CR1_AWDCH EQU 0x0000001F ; AWDCH[4:0] bits (Analog watchdog channel select bits)
ADC_CR1_AWDCH_0 EQU 0x00000001 ; Bit 0
ADC_CR1_AWDCH_1 EQU 0x00000002 ; Bit 1
ADC_CR1_AWDCH_2 EQU 0x00000004 ; Bit 2
ADC_CR1_AWDCH_3 EQU 0x00000008 ; Bit 3
ADC_CR1_AWDCH_4 EQU 0x00000010 ; Bit 4
ADC_CR1_EOCIE EQU 0x00000020 ; Interrupt enable for EOC
ADC_CR1_AWDIE EQU 0x00000040 ; Analog Watchdog interrupt enable
ADC_CR1_JEOCIE EQU 0x00000080 ; Interrupt enable for injected channels
ADC_CR1_SCAN EQU 0x00000100 ; Scan mode
ADC_CR1_AWDSGL EQU 0x00000200 ; Enable the watchdog on a single channel in scan mode
ADC_CR1_JAUTO EQU 0x00000400 ; Automatic injected group conversion
ADC_CR1_DISCEN EQU 0x00000800 ; Discontinuous mode on regular channels
ADC_CR1_JDISCEN EQU 0x00001000 ; Discontinuous mode on injected channels
ADC_CR1_DISCNUM EQU 0x0000E000 ; DISCNUM[2:0] bits (Discontinuous mode channel count)
ADC_CR1_DISCNUM_0 EQU 0x00002000 ; Bit 0
ADC_CR1_DISCNUM_1 EQU 0x00004000 ; Bit 1
ADC_CR1_DISCNUM_2 EQU 0x00008000 ; Bit 2
ADC_CR1_PDD EQU 0x00010000 ; Power Down during Delay phase
ADC_CR1_PDI EQU 0x00020000 ; Power Down during Idle phase
ADC_CR1_JAWDEN EQU 0x00400000 ; Analog watchdog enable on injected channels
ADC_CR1_AWDEN EQU 0x00800000 ; Analog watchdog enable on regular channels
ADC_CR1_RES EQU 0x03000000 ; RES[1:0] bits (Resolution)
ADC_CR1_RES_0 EQU 0x01000000 ; Bit 0
ADC_CR1_RES_1 EQU 0x02000000 ; Bit 1
ADC_CR1_OVRIE EQU 0x04000000 ; Overrun interrupt enable
;****************** Bit definition for ADC_CR2 register *******************
ADC_CR2_ADON EQU 0x00000001 ; A/D Converter ON / OFF
ADC_CR2_CONT EQU 0x00000002 ; Continuous Conversion
ADC_CR2_CFG EQU 0x00000004 ; ADC Configuration
ADC_CR2_DELS EQU 0x00000070 ; DELS[2:0] bits (Delay selection)
ADC_CR2_DELS_0 EQU 0x00000010 ; Bit 0
ADC_CR2_DELS_1 EQU 0x00000020 ; Bit 1
ADC_CR2_DELS_2 EQU 0x00000040 ; Bit 2
ADC_CR2_DMA EQU 0x00000100 ; Direct Memory access mode
ADC_CR2_DDS EQU 0x00000200 ; DMA disable selection (Single ADC)
ADC_CR2_EOCS EQU 0x00000400 ; End of conversion selection
ADC_CR2_ALIGN EQU 0x00000800 ; Data Alignment
ADC_CR2_JEXTSEL EQU 0x000F0000 ; JEXTSEL[3:0] bits (External event select for injected group)
ADC_CR2_JEXTSEL_0 EQU 0x00010000 ; Bit 0
ADC_CR2_JEXTSEL_1 EQU 0x00020000 ; Bit 1
ADC_CR2_JEXTSEL_2 EQU 0x00040000 ; Bit 2
ADC_CR2_JEXTSEL_3 EQU 0x00080000 ; Bit 3
ADC_CR2_JEXTEN EQU 0x00300000 ; JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels)
ADC_CR2_JEXTEN_0 EQU 0x00100000 ; Bit 0
ADC_CR2_JEXTEN_1 EQU 0x00200000 ; Bit 1
ADC_CR2_JSWSTART EQU 0x00400000 ; Start Conversion of injected channels
ADC_CR2_EXTSEL EQU 0x0F000000 ; EXTSEL[3:0] bits (External Event Select for regular group)
ADC_CR2_EXTSEL_0 EQU 0x01000000 ; Bit 0
ADC_CR2_EXTSEL_1 EQU 0x02000000 ; Bit 1
ADC_CR2_EXTSEL_2 EQU 0x04000000 ; Bit 2
ADC_CR2_EXTSEL_3 EQU 0x08000000 ; Bit 3
ADC_CR2_EXTEN EQU 0x30000000 ; EXTEN[1:0] bits (External Trigger Conversion mode for regular channels)
ADC_CR2_EXTEN_0 EQU 0x10000000 ; Bit 0
ADC_CR2_EXTEN_1 EQU 0x20000000 ; Bit 1
ADC_CR2_SWSTART EQU 0x40000000 ; Start Conversion of regular channels
;***************** Bit definition for ADC_SMPR1 register ******************
ADC_SMPR1_SMP20 EQU 0x00000007 ; SMP20[2:0] bits (Channel 20 Sample time selection)
ADC_SMPR1_SMP20_0 EQU 0x00000001 ; Bit 0
ADC_SMPR1_SMP20_1 EQU 0x00000002 ; Bit 1
ADC_SMPR1_SMP20_2 EQU 0x00000004 ; Bit 2
ADC_SMPR1_SMP21 EQU 0x00000038 ; SMP21[2:0] bits (Channel 21 Sample time selection)
ADC_SMPR1_SMP21_0 EQU 0x00000008 ; Bit 0
ADC_SMPR1_SMP21_1 EQU 0x00000010 ; Bit 1
ADC_SMPR1_SMP21_2 EQU 0x00000020 ; Bit 2
ADC_SMPR1_SMP22 EQU 0x000001C0 ; SMP22[2:0] bits (Channel 22 Sample time selection)
ADC_SMPR1_SMP22_0 EQU 0x00000040 ; Bit 0
ADC_SMPR1_SMP22_1 EQU 0x00000080 ; Bit 1
ADC_SMPR1_SMP22_2 EQU 0x00000100 ; Bit 2
ADC_SMPR1_SMP23 EQU 0x00000E00 ; SMP23[2:0] bits (Channel 23 Sample time selection)
ADC_SMPR1_SMP23_0 EQU 0x00000200 ; Bit 0
ADC_SMPR1_SMP23_1 EQU 0x00000400 ; Bit 1
ADC_SMPR1_SMP23_2 EQU 0x00000800 ; Bit 2
ADC_SMPR1_SMP24 EQU 0x00007000 ; SMP24[2:0] bits (Channel 24 Sample time selection)
ADC_SMPR1_SMP24_0 EQU 0x00001000 ; Bit 0
ADC_SMPR1_SMP24_1 EQU 0x00002000 ; Bit 1
ADC_SMPR1_SMP24_2 EQU 0x00004000 ; Bit 2
ADC_SMPR1_SMP25 EQU 0x00038000 ; SMP25[2:0] bits (Channel 25 Sample time selection)
ADC_SMPR1_SMP25_0 EQU 0x00008000 ; Bit 0
ADC_SMPR1_SMP25_1 EQU 0x00010000 ; Bit 1
ADC_SMPR1_SMP25_2 EQU 0x00020000 ; Bit 2
ADC_SMPR1_SMP26 EQU 0x001C0000 ; SMP26[2:0] bits (Channel 26 Sample time selection)
ADC_SMPR1_SMP26_0 EQU 0x00040000 ; Bit 0
ADC_SMPR1_SMP26_1 EQU 0x00080000 ; Bit 1
ADC_SMPR1_SMP26_2 EQU 0x00100000 ; Bit 2
ADC_SMPR1_SMP27 EQU 0x00E00000 ; SMP27[2:0] bits (Channel 27 Sample time selection)
ADC_SMPR1_SMP27_0 EQU 0x00200000 ; Bit 0
ADC_SMPR1_SMP27_1 EQU 0x00400000 ; Bit 1
ADC_SMPR1_SMP27_2 EQU 0x00800000 ; Bit 2
ADC_SMPR1_SMP28 EQU 0x07000000 ; SMP28[2:0] bits (Channel 28 Sample time selection)
ADC_SMPR1_SMP28_0 EQU 0x01000000 ; Bit 0
ADC_SMPR1_SMP28_1 EQU 0x02000000 ; Bit 1
ADC_SMPR1_SMP28_2 EQU 0x04000000 ; Bit 2
ADC_SMPR1_SMP29 EQU 0x38000000 ; SMP29[2:0] bits (Channel 29 Sample time selection)
ADC_SMPR1_SMP29_0 EQU 0x08000000 ; Bit 0
ADC_SMPR1_SMP29_1 EQU 0x10000000 ; Bit 1
ADC_SMPR1_SMP29_2 EQU 0x20000000 ; Bit 2
;***************** Bit definition for ADC_SMPR2 register ******************
ADC_SMPR2_SMP10 EQU 0x00000007 ; SMP10[2:0] bits (Channel 10 Sample time selection)
ADC_SMPR2_SMP10_0 EQU 0x00000001 ; Bit 0
ADC_SMPR2_SMP10_1 EQU 0x00000002 ; Bit 1
ADC_SMPR2_SMP10_2 EQU 0x00000004 ; Bit 2
ADC_SMPR2_SMP11 EQU 0x00000038 ; SMP11[2:0] bits (Channel 11 Sample time selection)
ADC_SMPR2_SMP11_0 EQU 0x00000008 ; Bit 0
ADC_SMPR2_SMP11_1 EQU 0x00000010 ; Bit 1
ADC_SMPR2_SMP11_2 EQU 0x00000020 ; Bit 2
ADC_SMPR2_SMP12 EQU 0x000001C0 ; SMP12[2:0] bits (Channel 12 Sample time selection)
ADC_SMPR2_SMP12_0 EQU 0x00000040 ; Bit 0
ADC_SMPR2_SMP12_1 EQU 0x00000080 ; Bit 1
ADC_SMPR2_SMP12_2 EQU 0x00000100 ; Bit 2
ADC_SMPR2_SMP13 EQU 0x00000E00 ; SMP13[2:0] bits (Channel 13 Sample time selection)
ADC_SMPR2_SMP13_0 EQU 0x00000200 ; Bit 0
ADC_SMPR2_SMP13_1 EQU 0x00000400 ; Bit 1
ADC_SMPR2_SMP13_2 EQU 0x00000800 ; Bit 2
ADC_SMPR2_SMP14 EQU 0x00007000 ; SMP14[2:0] bits (Channel 14 Sample time selection)
ADC_SMPR2_SMP14_0 EQU 0x00001000 ; Bit 0
ADC_SMPR2_SMP14_1 EQU 0x00002000 ; Bit 1
ADC_SMPR2_SMP14_2 EQU 0x00004000 ; Bit 2
ADC_SMPR2_SMP15 EQU 0x00038000 ; SMP15[2:0] bits (Channel 5 Sample time selection)
ADC_SMPR2_SMP15_0 EQU 0x00008000 ; Bit 0
ADC_SMPR2_SMP15_1 EQU 0x00010000 ; Bit 1
ADC_SMPR2_SMP15_2 EQU 0x00020000 ; Bit 2
ADC_SMPR2_SMP16 EQU 0x001C0000 ; SMP16[2:0] bits (Channel 16 Sample time selection)
ADC_SMPR2_SMP16_0 EQU 0x00040000 ; Bit 0
ADC_SMPR2_SMP16_1 EQU 0x00080000 ; Bit 1
ADC_SMPR2_SMP16_2 EQU 0x00100000 ; Bit 2
ADC_SMPR2_SMP17 EQU 0x00E00000 ; SMP17[2:0] bits (Channel 17 Sample time selection)
ADC_SMPR2_SMP17_0 EQU 0x00200000 ; Bit 0
ADC_SMPR2_SMP17_1 EQU 0x00400000 ; Bit 1
ADC_SMPR2_SMP17_2 EQU 0x00800000 ; Bit 2
ADC_SMPR2_SMP18 EQU 0x07000000 ; SMP18[2:0] bits (Channel 18 Sample time selection)
ADC_SMPR2_SMP18_0 EQU 0x01000000 ; Bit 0
ADC_SMPR2_SMP18_1 EQU 0x02000000 ; Bit 1
ADC_SMPR2_SMP18_2 EQU 0x04000000 ; Bit 2
ADC_SMPR2_SMP19 EQU 0x38000000 ; SMP19[2:0] bits (Channel 19 Sample time selection)
ADC_SMPR2_SMP19_0 EQU 0x08000000 ; Bit 0
ADC_SMPR2_SMP19_1 EQU 0x10000000 ; Bit 1
ADC_SMPR2_SMP19_2 EQU 0x20000000 ; Bit 2
;***************** Bit definition for ADC_SMPR3 register ******************
ADC_SMPR3_SMP0 EQU 0x00000007 ; SMP0[2:0] bits (Channel 0 Sample time selection)
ADC_SMPR3_SMP0_0 EQU 0x00000001 ; Bit 0
ADC_SMPR3_SMP0_1 EQU 0x00000002 ; Bit 1
ADC_SMPR3_SMP0_2 EQU 0x00000004 ; Bit 2
ADC_SMPR3_SMP1 EQU 0x00000038 ; SMP1[2:0] bits (Channel 1 Sample time selection)
ADC_SMPR3_SMP1_0 EQU 0x00000008 ; Bit 0
ADC_SMPR3_SMP1_1 EQU 0x00000010 ; Bit 1
ADC_SMPR3_SMP1_2 EQU 0x00000020 ; Bit 2
ADC_SMPR3_SMP2 EQU 0x000001C0 ; SMP2[2:0] bits (Channel 2 Sample time selection)
ADC_SMPR3_SMP2_0 EQU 0x00000040 ; Bit 0
ADC_SMPR3_SMP2_1 EQU 0x00000080 ; Bit 1
ADC_SMPR3_SMP2_2 EQU 0x00000100 ; Bit 2
ADC_SMPR3_SMP3 EQU 0x00000E00 ; SMP3[2:0] bits (Channel 3 Sample time selection)
ADC_SMPR3_SMP3_0 EQU 0x00000200 ; Bit 0
ADC_SMPR3_SMP3_1 EQU 0x00000400 ; Bit 1
ADC_SMPR3_SMP3_2 EQU 0x00000800 ; Bit 2
ADC_SMPR3_SMP4 EQU 0x00007000 ; SMP4[2:0] bits (Channel 4 Sample time selection)
ADC_SMPR3_SMP4_0 EQU 0x00001000 ; Bit 0
ADC_SMPR3_SMP4_1 EQU 0x00002000 ; Bit 1
ADC_SMPR3_SMP4_2 EQU 0x00004000 ; Bit 2
ADC_SMPR3_SMP5 EQU 0x00038000 ; SMP5[2:0] bits (Channel 5 Sample time selection)
ADC_SMPR3_SMP5_0 EQU 0x00008000 ; Bit 0
ADC_SMPR3_SMP5_1 EQU 0x00010000 ; Bit 1
ADC_SMPR3_SMP5_2 EQU 0x00020000 ; Bit 2
ADC_SMPR3_SMP6 EQU 0x001C0000 ; SMP6[2:0] bits (Channel 6 Sample time selection)
ADC_SMPR3_SMP6_0 EQU 0x00040000 ; Bit 0
ADC_SMPR3_SMP6_1 EQU 0x00080000 ; Bit 1
ADC_SMPR3_SMP6_2 EQU 0x00100000 ; Bit 2
ADC_SMPR3_SMP7 EQU 0x00E00000 ; SMP7[2:0] bits (Channel 7 Sample time selection)
ADC_SMPR3_SMP7_0 EQU 0x00200000 ; Bit 0
ADC_SMPR3_SMP7_1 EQU 0x00400000 ; Bit 1
ADC_SMPR3_SMP7_2 EQU 0x00800000 ; Bit 2
ADC_SMPR3_SMP8 EQU 0x07000000 ; SMP8[2:0] bits (Channel 8 Sample time selection)
ADC_SMPR3_SMP8_0 EQU 0x01000000 ; Bit 0
ADC_SMPR3_SMP8_1 EQU 0x02000000 ; Bit 1
ADC_SMPR3_SMP8_2 EQU 0x04000000 ; Bit 2
ADC_SMPR3_SMP9 EQU 0x38000000 ; SMP9[2:0] bits (Channel 9 Sample time selection)
ADC_SMPR3_SMP9_0 EQU 0x08000000 ; Bit 0
ADC_SMPR3_SMP9_1 EQU 0x10000000 ; Bit 1
ADC_SMPR3_SMP9_2 EQU 0x20000000 ; Bit 2
;***************** Bit definition for ADC_JOFR1 register ******************
ADC_JOFR1_JOFFSET1 EQU 0x00000FFF ; Data offset for injected channel 1
;***************** Bit definition for ADC_JOFR2 register ******************
ADC_JOFR2_JOFFSET2 EQU 0x00000FFF ; Data offset for injected channel 2
;***************** Bit definition for ADC_JOFR3 register ******************
ADC_JOFR3_JOFFSET3 EQU 0x00000FFF ; Data offset for injected channel 3
;***************** Bit definition for ADC_JOFR4 register ******************
ADC_JOFR4_JOFFSET4 EQU 0x00000FFF ; Data offset for injected channel 4
;****************** Bit definition for ADC_HTR register *******************
ADC_HTR_HT EQU 0x00000FFF ; Analog watchdog high threshold
;****************** Bit definition for ADC_LTR register *******************
ADC_LTR_LT EQU 0x00000FFF ; Analog watchdog low threshold
;****************** Bit definition for ADC_SQR1 register ******************
ADC_SQR1_L EQU 0x00F00000 ; L[3:0] bits (Regular channel sequence length)
ADC_SQR1_L_0 EQU 0x00100000 ; Bit 0
ADC_SQR1_L_1 EQU 0x00200000 ; Bit 1
ADC_SQR1_L_2 EQU 0x00400000 ; Bit 2
ADC_SQR1_L_3 EQU 0x00800000 ; Bit 3
ADC_SQR1_SQ28 EQU 0x000F8000 ; SQ28[4:0] bits (25th conversion in regular sequence)
ADC_SQR1_SQ28_0 EQU 0x00008000 ; Bit 0
ADC_SQR1_SQ28_1 EQU 0x00010000 ; Bit 1
ADC_SQR1_SQ28_2 EQU 0x00020000 ; Bit 2
ADC_SQR1_SQ28_3 EQU 0x00040000 ; Bit 3
ADC_SQR1_SQ28_4 EQU 0x00080000 ; Bit 4
ADC_SQR1_SQ27 EQU 0x00007C00 ; SQ27[4:0] bits (27th conversion in regular sequence)
ADC_SQR1_SQ27_0 EQU 0x00000400 ; Bit 0
ADC_SQR1_SQ27_1 EQU 0x00000800 ; Bit 1
ADC_SQR1_SQ27_2 EQU 0x00001000 ; Bit 2
ADC_SQR1_SQ27_3 EQU 0x00002000 ; Bit 3
ADC_SQR1_SQ27_4 EQU 0x00004000 ; Bit 4
ADC_SQR1_SQ26 EQU 0x000003E0 ; SQ26[4:0] bits (26th conversion in regular sequence)
ADC_SQR1_SQ26_0 EQU 0x00000020 ; Bit 0
ADC_SQR1_SQ26_1 EQU 0x00000040 ; Bit 1
ADC_SQR1_SQ26_2 EQU 0x00000080 ; Bit 2
ADC_SQR1_SQ26_3 EQU 0x00000100 ; Bit 3
ADC_SQR1_SQ26_4 EQU 0x00000200 ; Bit 4
ADC_SQR1_SQ25 EQU 0x0000001F ; SQ25[4:0] bits (25th conversion in regular sequence)
ADC_SQR1_SQ25_0 EQU 0x00000001 ; Bit 0
ADC_SQR1_SQ25_1 EQU 0x00000002 ; Bit 1
ADC_SQR1_SQ25_2 EQU 0x00000004 ; Bit 2
ADC_SQR1_SQ25_3 EQU 0x00000008 ; Bit 3
ADC_SQR1_SQ25_4 EQU 0x00000010 ; Bit 4
;****************** Bit definition for ADC_SQR2 register ******************
ADC_SQR2_SQ19 EQU 0x0000001F ; SQ19[4:0] bits (19th conversion in regular sequence)
ADC_SQR2_SQ19_0 EQU 0x00000001 ; Bit 0
ADC_SQR2_SQ19_1 EQU 0x00000002 ; Bit 1
ADC_SQR2_SQ19_2 EQU 0x00000004 ; Bit 2
ADC_SQR2_SQ19_3 EQU 0x00000008 ; Bit 3
ADC_SQR2_SQ19_4 EQU 0x00000010 ; Bit 4
ADC_SQR2_SQ20 EQU 0x000003E0 ; SQ20[4:0] bits (20th conversion in regular sequence)
ADC_SQR2_SQ20_0 EQU 0x00000020 ; Bit 0
ADC_SQR2_SQ20_1 EQU 0x00000040 ; Bit 1
ADC_SQR2_SQ20_2 EQU 0x00000080 ; Bit 2
ADC_SQR2_SQ20_3 EQU 0x00000100 ; Bit 3
ADC_SQR2_SQ20_4 EQU 0x00000200 ; Bit 4
ADC_SQR2_SQ21 EQU 0x00007C00 ; SQ21[4:0] bits (21th conversion in regular sequence)
ADC_SQR2_SQ21_0 EQU 0x00000400 ; Bit 0
ADC_SQR2_SQ21_1 EQU 0x00000800 ; Bit 1
ADC_SQR2_SQ21_2 EQU 0x00001000 ; Bit 2
ADC_SQR2_SQ21_3 EQU 0x00002000 ; Bit 3
ADC_SQR2_SQ21_4 EQU 0x00004000 ; Bit 4
ADC_SQR2_SQ22 EQU 0x000F8000 ; SQ22[4:0] bits (22th conversion in regular sequence)
ADC_SQR2_SQ22_0 EQU 0x00008000 ; Bit 0
ADC_SQR2_SQ22_1 EQU 0x00010000 ; Bit 1
ADC_SQR2_SQ22_2 EQU 0x00020000 ; Bit 2
ADC_SQR2_SQ22_3 EQU 0x00040000 ; Bit 3
ADC_SQR2_SQ22_4 EQU 0x00080000 ; Bit 4
ADC_SQR2_SQ23 EQU 0x01F00000 ; SQ23[4:0] bits (23th conversion in regular sequence)
ADC_SQR2_SQ23_0 EQU 0x00100000 ; Bit 0
ADC_SQR2_SQ23_1 EQU 0x00200000 ; Bit 1
ADC_SQR2_SQ23_2 EQU 0x00400000 ; Bit 2
ADC_SQR2_SQ23_3 EQU 0x00800000 ; Bit 3
ADC_SQR2_SQ23_4 EQU 0x01000000 ; Bit 4
ADC_SQR2_SQ24 EQU 0x3E000000 ; SQ24[4:0] bits (24th conversion in regular sequence)
ADC_SQR2_SQ24_0 EQU 0x02000000 ; Bit 0
ADC_SQR2_SQ24_1 EQU 0x04000000 ; Bit 1
ADC_SQR2_SQ24_2 EQU 0x08000000 ; Bit 2
ADC_SQR2_SQ24_3 EQU 0x10000000 ; Bit 3
ADC_SQR2_SQ24_4 EQU 0x20000000 ; Bit 4
;****************** Bit definition for ADC_SQR3 register ******************
ADC_SQR3_SQ13 EQU 0x0000001F ; SQ13[4:0] bits (13th conversion in regular sequence)
ADC_SQR3_SQ13_0 EQU 0x00000001 ; Bit 0
ADC_SQR3_SQ13_1 EQU 0x00000002 ; Bit 1
ADC_SQR3_SQ13_2 EQU 0x00000004 ; Bit 2
ADC_SQR3_SQ13_3 EQU 0x00000008 ; Bit 3
ADC_SQR3_SQ13_4 EQU 0x00000010 ; Bit 4
ADC_SQR3_SQ14 EQU 0x000003E0 ; SQ14[4:0] bits (14th conversion in regular sequence)
ADC_SQR3_SQ14_0 EQU 0x00000020 ; Bit 0
ADC_SQR3_SQ14_1 EQU 0x00000040 ; Bit 1
ADC_SQR3_SQ14_2 EQU 0x00000080 ; Bit 2
ADC_SQR3_SQ14_3 EQU 0x00000100 ; Bit 3
ADC_SQR3_SQ14_4 EQU 0x00000200 ; Bit 4
ADC_SQR3_SQ15 EQU 0x00007C00 ; SQ15[4:0] bits (15th conversion in regular sequence)
ADC_SQR3_SQ15_0 EQU 0x00000400 ; Bit 0
ADC_SQR3_SQ15_1 EQU 0x00000800 ; Bit 1
ADC_SQR3_SQ15_2 EQU 0x00001000 ; Bit 2
ADC_SQR3_SQ15_3 EQU 0x00002000 ; Bit 3
ADC_SQR3_SQ15_4 EQU 0x00004000 ; Bit 4
ADC_SQR3_SQ16 EQU 0x000F8000 ; SQ16[4:0] bits (16th conversion in regular sequence)
ADC_SQR3_SQ16_0 EQU 0x00008000 ; Bit 0
ADC_SQR3_SQ16_1 EQU 0x00010000 ; Bit 1
ADC_SQR3_SQ16_2 EQU 0x00020000 ; Bit 2
ADC_SQR3_SQ16_3 EQU 0x00040000 ; Bit 3
ADC_SQR3_SQ16_4 EQU 0x00080000 ; Bit 4
ADC_SQR3_SQ17 EQU 0x01F00000 ; SQ17[4:0] bits (17th conversion in regular sequence)
ADC_SQR3_SQ17_0 EQU 0x00100000 ; Bit 0
ADC_SQR3_SQ17_1 EQU 0x00200000 ; Bit 1
ADC_SQR3_SQ17_2 EQU 0x00400000 ; Bit 2
ADC_SQR3_SQ17_3 EQU 0x00800000 ; Bit 3
ADC_SQR3_SQ17_4 EQU 0x01000000 ; Bit 4
ADC_SQR3_SQ18 EQU 0x3E000000 ; SQ18[4:0] bits (18th conversion in regular sequence)
ADC_SQR3_SQ18_0 EQU 0x02000000 ; Bit 0
ADC_SQR3_SQ18_1 EQU 0x04000000 ; Bit 1
ADC_SQR3_SQ18_2 EQU 0x08000000 ; Bit 2
ADC_SQR3_SQ18_3 EQU 0x10000000 ; Bit 3
ADC_SQR3_SQ18_4 EQU 0x20000000 ; Bit 4
;****************** Bit definition for ADC_SQR4 register ******************
ADC_SQR4_SQ7 EQU 0x0000001F ; SQ7[4:0] bits (7th conversion in regular sequence)
ADC_SQR4_SQ7_0 EQU 0x00000001 ; Bit 0
ADC_SQR4_SQ7_1 EQU 0x00000002 ; Bit 1
ADC_SQR4_SQ7_2 EQU 0x00000004 ; Bit 2
ADC_SQR4_SQ7_3 EQU 0x00000008 ; Bit 3
ADC_SQR4_SQ7_4 EQU 0x00000010 ; Bit 4
ADC_SQR4_SQ8 EQU 0x000003E0 ; SQ8[4:0] bits (8th conversion in regular sequence)
ADC_SQR4_SQ8_0 EQU 0x00000020 ; Bit 0
ADC_SQR4_SQ8_1 EQU 0x00000040 ; Bit 1
ADC_SQR4_SQ8_2 EQU 0x00000080 ; Bit 2
ADC_SQR4_SQ8_3 EQU 0x00000100 ; Bit 3
ADC_SQR4_SQ8_4 EQU 0x00000200 ; Bit 4
ADC_SQR4_SQ9 EQU 0x00007C00 ; SQ9[4:0] bits (9th conversion in regular sequence)
ADC_SQR4_SQ9_0 EQU 0x00000400 ; Bit 0
ADC_SQR4_SQ9_1 EQU 0x00000800 ; Bit 1
ADC_SQR4_SQ9_2 EQU 0x00001000 ; Bit 2
ADC_SQR4_SQ9_3 EQU 0x00002000 ; Bit 3
ADC_SQR4_SQ9_4 EQU 0x00004000 ; Bit 4
ADC_SQR4_SQ10 EQU 0x000F8000 ; SQ10[4:0] bits (10th conversion in regular sequence)
ADC_SQR4_SQ10_0 EQU 0x00008000 ; Bit 0
ADC_SQR4_SQ10_1 EQU 0x00010000 ; Bit 1
ADC_SQR4_SQ10_2 EQU 0x00020000 ; Bit 2
ADC_SQR4_SQ10_3 EQU 0x00040000 ; Bit 3
ADC_SQR4_SQ10_4 EQU 0x00080000 ; Bit 4
ADC_SQR4_SQ11 EQU 0x01F00000 ; SQ11[4:0] bits (11th conversion in regular sequence)
ADC_SQR4_SQ11_0 EQU 0x00100000 ; Bit 0
ADC_SQR4_SQ11_1 EQU 0x00200000 ; Bit 1
ADC_SQR4_SQ11_2 EQU 0x00400000 ; Bit 2
ADC_SQR4_SQ11_3 EQU 0x00800000 ; Bit 3
ADC_SQR4_SQ11_4 EQU 0x01000000 ; Bit 4
ADC_SQR4_SQ12 EQU 0x3E000000 ; SQ12[4:0] bits (12th conversion in regular sequence)
ADC_SQR4_SQ12_0 EQU 0x02000000 ; Bit 0
ADC_SQR4_SQ12_1 EQU 0x04000000 ; Bit 1
ADC_SQR4_SQ12_2 EQU 0x08000000 ; Bit 2
ADC_SQR4_SQ12_3 EQU 0x10000000 ; Bit 3
ADC_SQR4_SQ12_4 EQU 0x20000000 ; Bit 4
;****************** Bit definition for ADC_SQR5 register ******************
ADC_SQR5_SQ1 EQU 0x0000001F ; SQ1[4:0] bits (1st conversion in regular sequence)
ADC_SQR5_SQ1_0 EQU 0x00000001 ; Bit 0
ADC_SQR5_SQ1_1 EQU 0x00000002 ; Bit 1
ADC_SQR5_SQ1_2 EQU 0x00000004 ; Bit 2
ADC_SQR5_SQ1_3 EQU 0x00000008 ; Bit 3
ADC_SQR5_SQ1_4 EQU 0x00000010 ; Bit 4
ADC_SQR5_SQ2 EQU 0x000003E0 ; SQ2[4:0] bits (2nd conversion in regular sequence)
ADC_SQR5_SQ2_0 EQU 0x00000020 ; Bit 0
ADC_SQR5_SQ2_1 EQU 0x00000040 ; Bit 1
ADC_SQR5_SQ2_2 EQU 0x00000080 ; Bit 2
ADC_SQR5_SQ2_3 EQU 0x00000100 ; Bit 3
ADC_SQR5_SQ2_4 EQU 0x00000200 ; Bit 4
ADC_SQR5_SQ3 EQU 0x00007C00 ; SQ3[4:0] bits (3rd conversion in regular sequence)
ADC_SQR5_SQ3_0 EQU 0x00000400 ; Bit 0
ADC_SQR5_SQ3_1 EQU 0x00000800 ; Bit 1
ADC_SQR5_SQ3_2 EQU 0x00001000 ; Bit 2
ADC_SQR5_SQ3_3 EQU 0x00002000 ; Bit 3
ADC_SQR5_SQ3_4 EQU 0x00004000 ; Bit 4
ADC_SQR5_SQ4 EQU 0x000F8000 ; SQ4[4:0] bits (4th conversion in regular sequence)
ADC_SQR5_SQ4_0 EQU 0x00008000 ; Bit 0
ADC_SQR5_SQ4_1 EQU 0x00010000 ; Bit 1
ADC_SQR5_SQ4_2 EQU 0x00020000 ; Bit 2
ADC_SQR5_SQ4_3 EQU 0x00040000 ; Bit 3
ADC_SQR5_SQ4_4 EQU 0x00080000 ; Bit 4
ADC_SQR5_SQ5 EQU 0x01F00000 ; SQ5[4:0] bits (5th conversion in regular sequence)
ADC_SQR5_SQ5_0 EQU 0x00100000 ; Bit 0
ADC_SQR5_SQ5_1 EQU 0x00200000 ; Bit 1
ADC_SQR5_SQ5_2 EQU 0x00400000 ; Bit 2
ADC_SQR5_SQ5_3 EQU 0x00800000 ; Bit 3
ADC_SQR5_SQ5_4 EQU 0x01000000 ; Bit 4
ADC_SQR5_SQ6 EQU 0x3E000000 ; SQ6[4:0] bits (6th conversion in regular sequence)
ADC_SQR5_SQ6_0 EQU 0x02000000 ; Bit 0
ADC_SQR5_SQ6_1 EQU 0x04000000 ; Bit 1
ADC_SQR5_SQ6_2 EQU 0x08000000 ; Bit 2
ADC_SQR5_SQ6_3 EQU 0x10000000 ; Bit 3
ADC_SQR5_SQ6_4 EQU 0x20000000 ; Bit 4
;****************** Bit definition for ADC_JSQR register ******************
ADC_JSQR_JSQ1 EQU 0x0000001F ; JSQ1[4:0] bits (1st conversion in injected sequence)
ADC_JSQR_JSQ1_0 EQU 0x00000001 ; Bit 0
ADC_JSQR_JSQ1_1 EQU 0x00000002 ; Bit 1
ADC_JSQR_JSQ1_2 EQU 0x00000004 ; Bit 2
ADC_JSQR_JSQ1_3 EQU 0x00000008 ; Bit 3
ADC_JSQR_JSQ1_4 EQU 0x00000010 ; Bit 4
ADC_JSQR_JSQ2 EQU 0x000003E0 ; JSQ2[4:0] bits (2nd conversion in injected sequence)
ADC_JSQR_JSQ2_0 EQU 0x00000020 ; Bit 0
ADC_JSQR_JSQ2_1 EQU 0x00000040 ; Bit 1
ADC_JSQR_JSQ2_2 EQU 0x00000080 ; Bit 2
ADC_JSQR_JSQ2_3 EQU 0x00000100 ; Bit 3
ADC_JSQR_JSQ2_4 EQU 0x00000200 ; Bit 4
ADC_JSQR_JSQ3 EQU 0x00007C00 ; JSQ3[4:0] bits (3rd conversion in injected sequence)
ADC_JSQR_JSQ3_0 EQU 0x00000400 ; Bit 0
ADC_JSQR_JSQ3_1 EQU 0x00000800 ; Bit 1
ADC_JSQR_JSQ3_2 EQU 0x00001000 ; Bit 2
ADC_JSQR_JSQ3_3 EQU 0x00002000 ; Bit 3
ADC_JSQR_JSQ3_4 EQU 0x00004000 ; Bit 4
ADC_JSQR_JSQ4 EQU 0x000F8000 ; JSQ4[4:0] bits (4th conversion in injected sequence)
ADC_JSQR_JSQ4_0 EQU 0x00008000 ; Bit 0
ADC_JSQR_JSQ4_1 EQU 0x00010000 ; Bit 1
ADC_JSQR_JSQ4_2 EQU 0x00020000 ; Bit 2
ADC_JSQR_JSQ4_3 EQU 0x00040000 ; Bit 3
ADC_JSQR_JSQ4_4 EQU 0x00080000 ; Bit 4
ADC_JSQR_JL EQU 0x00300000 ; JL[1:0] bits (Injected Sequence length)
ADC_JSQR_JL_0 EQU 0x00100000 ; Bit 0
ADC_JSQR_JL_1 EQU 0x00200000 ; Bit 1
;****************** Bit definition for ADC_JDR1 register ******************
ADC_JDR1_JDATA EQU 0x0000FFFF ; Injected data
;****************** Bit definition for ADC_JDR2 register ******************
ADC_JDR2_JDATA EQU 0x0000FFFF ; Injected data
;****************** Bit definition for ADC_JDR3 register ******************
ADC_JDR3_JDATA EQU 0x0000FFFF ; Injected data
;****************** Bit definition for ADC_JDR4 register ******************
ADC_JDR4_JDATA EQU 0x0000FFFF ; Injected data
;******************* Bit definition for ADC_DR register *******************
ADC_DR_DATA EQU 0x0000FFFF ; Regular data
;***************** Bit definition for ADC_SMPR0 register ******************
ADC_SMPR3_SMP30 EQU 0x00000007 ; SMP30[2:0] bits (Channel 30 Sample time selection)
ADC_SMPR3_SMP30_0 EQU 0x00000001 ; Bit 0
ADC_SMPR3_SMP30_1 EQU 0x00000002 ; Bit 1
ADC_SMPR3_SMP30_2 EQU 0x00000004 ; Bit 2
ADC_SMPR3_SMP31 EQU 0x00000038 ; SMP31[2:0] bits (Channel 31 Sample time selection)
ADC_SMPR3_SMP31_0 EQU 0x00000008 ; Bit 0
ADC_SMPR3_SMP31_1 EQU 0x00000010 ; Bit 1
ADC_SMPR3_SMP31_2 EQU 0x00000020 ; Bit 2
;****************** Bit definition for ADC_CSR register *******************
ADC_CSR_AWD1 EQU 0x00000001 ; ADC1 Analog watchdog flag
ADC_CSR_EOC1 EQU 0x00000002 ; ADC1 End of conversion
ADC_CSR_JEOC1 EQU 0x00000004 ; ADC1 Injected channel end of conversion
ADC_CSR_JSTRT1 EQU 0x00000008 ; ADC1 Injected channel Start flag
ADC_CSR_STRT1 EQU 0x00000010 ; ADC1 Regular channel Start flag
ADC_CSR_OVR1 EQU 0x00000020 ; ADC1 overrun flag
ADC_CSR_ADONS1 EQU 0x00000040 ; ADON status of ADC1
;****************** Bit definition for ADC_CCR register *******************
ADC_CCR_ADCPRE EQU 0x00030000 ; ADC prescaler
ADC_CCR_ADCPRE_0 EQU 0x00010000 ; Bit 0
ADC_CCR_ADCPRE_1 EQU 0x00020000 ; Bit 1
ADC_CCR_TSVREFE EQU 0x00800000 ; Temperature Sensor and VREFINT Enable
END

@ -0,0 +1,75 @@
;********************************************************************************
; SOUBOR : INI_BITS_AES.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro AES (crypto)
;
; ! Modul je pouze v STM32L162 !
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Advanced Encryption Standard (AES)
;
;****************************************************************************
;****************** Bit definition for AES_CR register ********************
AES_CR_EN EQU 0x00000001 ; AES Enable
AES_CR_DATATYPE EQU 0x00000006 ; Data type selection
AES_CR_DATATYPE_0 EQU 0x00000002 ; Bit 0
AES_CR_DATATYPE_1 EQU 0x00000004 ; Bit 1
AES_CR_MODE EQU 0x00000018 ; AES Mode Of Operation
AES_CR_MODE_0 EQU 0x00000008 ; Bit 0
AES_CR_MODE_1 EQU 0x00000010 ; Bit 1
AES_CR_CHMOD EQU 0x00000060 ; AES Chaining Mode
AES_CR_CHMOD_0 EQU 0x00000020 ; Bit 0
AES_CR_CHMOD_1 EQU 0x00000040 ; Bit 1
AES_CR_CCFC EQU 0x00000080 ; Computation Complete Flag Clear
AES_CR_ERRC EQU 0x00000100 ; Error Clear
AES_CR_CCIE EQU 0x00000200 ; Computation Complete Interrupt Enable
AES_CR_ERRIE EQU 0x00000400 ; Error Interrupt Enable
AES_CR_DMAINEN EQU 0x00000800 ; DMA ENable managing the data input phase
AES_CR_DMAOUTEN EQU 0x00001000 ; DMA Enable managing the data output phase
;****************** Bit definition for AES_SR register ********************
AES_SR_CCF EQU 0x00000001 ; Computation Complete Flag
AES_SR_RDERR EQU 0x00000002 ; Read Error Flag
AES_SR_WRERR EQU 0x00000004 ; Write Error Flag
;****************** Bit definition for AES_DINR register ******************
AES_DINR EQU 0x0000FFFF ; AES Data Input Register
;****************** Bit definition for AES_DOUTR register *****************
AES_DOUTR EQU 0x0000FFFF ; AES Data Output Register
;****************** Bit definition for AES_KEYR0 register *****************
AES_KEYR0 EQU 0x0000FFFF ; AES Key Register 0
;****************** Bit definition for AES_KEYR1 register *****************
AES_KEYR1 EQU 0x0000FFFF ; AES Key Register 1
;****************** Bit definition for AES_KEYR2 register *****************
AES_KEYR2 EQU 0x0000FFFF ; AES Key Register 2
;****************** Bit definition for AES_KEYR3 register *****************
AES_KEYR3 EQU 0x0000FFFF ; AES Key Register 3
;****************** Bit definition for AES_IVR0 register ******************
AES_IVR0 EQU 0x0000FFFF ; AES Initialization Vector Register 0
;****************** Bit definition for AES_IVR1 register ******************
AES_IVR1 EQU 0x0000FFFF ; AES Initialization Vector Register 1
;****************** Bit definition for AES_IVR2 register ******************
AES_IVR2 EQU 0x0000FFFF ; AES Initialization Vector Register 2
;****************** Bit definition for AES_IVR3 register ******************
AES_IVR3 EQU 0x0000FFFF ; AES Initialization Vector Register 3
END

@ -0,0 +1,51 @@
;********************************************************************************
; SOUBOR : INI_BITS_COMP.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro COMP (analogovy komparator)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Analog Comparators (COMP)
;
;****************************************************************************
;***************** Bit definition for COMP_CSR register *******************
COMP_CSR_10KPU EQU 0x00000001 ; 10K pull-up resistor
COMP_CSR_400KPU EQU 0x00000002 ; 400K pull-up resistor
COMP_CSR_10KPD EQU 0x00000004 ; 10K pull-down resistor
COMP_CSR_400KPD EQU 0x00000008 ; 400K pull-down resistor
COMP_CSR_CMP1EN EQU 0x00000010 ; Comparator 1 enable
COMP_CSR_SW1 EQU 0x00000020 ; SW1 analog switch enable
COMP_CSR_CMP1OUT EQU 0x00000080 ; Comparator 1 output
COMP_CSR_SPEED EQU 0x00001000 ; Comparator 2 speed
COMP_CSR_CMP2OUT EQU 0x00002000 ; Comparator 2 ouput
COMP_CSR_VREFOUTEN EQU 0x00010000 ; Comparator Vref Enable
COMP_CSR_WNDWE EQU 0x00020000 ; Window mode enable
COMP_CSR_INSEL EQU 0x001C0000 ; INSEL[2:0] Inversion input Selection
COMP_CSR_INSEL_0 EQU 0x00040000 ; Bit 0
COMP_CSR_INSEL_1 EQU 0x00080000 ; Bit 1
COMP_CSR_INSEL_2 EQU 0x00100000 ; Bit 2
COMP_CSR_OUTSEL EQU 0x00E00000 ; OUTSEL[2:0] comparator 2 output redirection
COMP_CSR_OUTSEL_0 EQU 0x00200000 ; Bit 0
COMP_CSR_OUTSEL_1 EQU 0x00400000 ; Bit 1
COMP_CSR_OUTSEL_2 EQU 0x00800000 ; Bit 2
COMP_CSR_FCH3 EQU 0x04000000 ; Bit 26
COMP_CSR_FCH8 EQU 0x08000000 ; Bit 27
COMP_CSR_RCH13 EQU 0x10000000 ; Bit 28
COMP_CSR_CAIE EQU 0x20000000 ; Bit 29
COMP_CSR_CAIF EQU 0x40000000 ; Bit 30
COMP_CSR_TSUSP EQU 0x80000000 ; Bit 31
END

@ -0,0 +1,26 @@
;********************************************************************************
; SOUBOR : INI_BITS_CRC.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro CRC (checksum generator)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; CRC calculation unit (CRC)
;
;****************************************************************************
;****************** Bit definition for CRC_DR register ********************
CRC_DR_DR EQU 0xFFFFFFFF ; Data register bits
;****************** Bit definition for CRC_IDR register *******************
CRC_IDR_IDR EQU 0xFF ; General-purpose 8-bit data register bits
;******************* Bit definition for CRC_CR register *******************
CRC_CR_RESET EQU 0x00000001 ; RESET bit
END

@ -0,0 +1,104 @@
;********************************************************************************
; SOUBOR : INI_BITS_DAC.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro DAC (digitalne-analogovy prevodnik)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Digital to Analog Converter (DAC)
;
;****************************************************************************
;******************* Bit definition for DAC_CR register *******************
DAC_CR_EN1 EQU 0x00000001 ; DAC channel1 enable
DAC_CR_BOFF1 EQU 0x00000002 ; DAC channel1 output buffer disable
DAC_CR_TEN1 EQU 0x00000004 ; DAC channel1 Trigger enable
DAC_CR_TSEL1 EQU 0x00000038 ; TSEL1[2:0] (DAC channel1 Trigger selection)
DAC_CR_TSEL1_0 EQU 0x00000008 ; Bit 0
DAC_CR_TSEL1_1 EQU 0x00000010 ; Bit 1
DAC_CR_TSEL1_2 EQU 0x00000020 ; Bit 2
DAC_CR_WAVE1 EQU 0x000000C0 ; WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
DAC_CR_WAVE1_0 EQU 0x00000040 ; Bit 0
DAC_CR_WAVE1_1 EQU 0x00000080 ; Bit 1
DAC_CR_MAMP1 EQU 0x00000F00 ; MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
DAC_CR_MAMP1_0 EQU 0x00000100 ; Bit 0
DAC_CR_MAMP1_1 EQU 0x00000200 ; Bit 1
DAC_CR_MAMP1_2 EQU 0x00000400 ; Bit 2
DAC_CR_MAMP1_3 EQU 0x00000800 ; Bit 3
DAC_CR_DMAEN1 EQU 0x00001000 ; DAC channel1 DMA enable
DAC_CR_DMAUDRIE1 EQU 0x00002000 ; DAC channel1 DMA underrun interrupt enable
DAC_CR_EN2 EQU 0x00010000 ; DAC channel2 enable
DAC_CR_BOFF2 EQU 0x00020000 ; DAC channel2 output buffer disable
DAC_CR_TEN2 EQU 0x00040000 ; DAC channel2 Trigger enable
DAC_CR_TSEL2 EQU 0x00380000 ; TSEL2[2:0] (DAC channel2 Trigger selection)
DAC_CR_TSEL2_0 EQU 0x00080000 ; Bit 0
DAC_CR_TSEL2_1 EQU 0x00100000 ; Bit 1
DAC_CR_TSEL2_2 EQU 0x00200000 ; Bit 2
DAC_CR_WAVE2 EQU 0x00C00000 ; WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)
DAC_CR_WAVE2_0 EQU 0x00400000 ; Bit 0
DAC_CR_WAVE2_1 EQU 0x00800000 ; Bit 1
DAC_CR_MAMP2 EQU 0x0F000000 ; MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)
DAC_CR_MAMP2_0 EQU 0x01000000 ; Bit 0
DAC_CR_MAMP2_1 EQU 0x02000000 ; Bit 1
DAC_CR_MAMP2_2 EQU 0x04000000 ; Bit 2
DAC_CR_MAMP2_3 EQU 0x08000000 ; Bit 3
DAC_CR_DMAEN2 EQU 0x10000000 ; DAC channel2 DMA enabled
DAC_CR_DMAUDRIE2 EQU 0x20000000 ; DAC channel2 DMA underrun interrupt enable
;**************** Bit definition for DAC_SWTRIGR register *****************
DAC_SWTRIGR_SWTRIG1 EQU 0x01 ; DAC channel1 software trigger
DAC_SWTRIGR_SWTRIG2 EQU 0x02 ; DAC channel2 software trigger
;**************** Bit definition for DAC_DHR12R1 register *****************
DAC_DHR12R1_DACC1DHR EQU 0x0FFF ; DAC channel1 12-bit Right aligned data
;**************** Bit definition for DAC_DHR12L1 register *****************
DAC_DHR12L1_DACC1DHR EQU 0xFFF0 ; DAC channel1 12-bit Left aligned data
;***************** Bit definition for DAC_DHR8R1 register *****************
DAC_DHR8R1_DACC1DHR EQU 0xFF ; DAC channel1 8-bit Right aligned data
;**************** Bit definition for DAC_DHR12R2 register *****************
DAC_DHR12R2_DACC2DHR EQU 0x0FFF ; DAC channel2 12-bit Right aligned data
;**************** Bit definition for DAC_DHR12L2 register *****************
DAC_DHR12L2_DACC2DHR EQU 0xFFF0 ; DAC channel2 12-bit Left aligned data
;***************** Bit definition for DAC_DHR8R2 register *****************
DAC_DHR8R2_DACC2DHR EQU 0xFF ; DAC channel2 8-bit Right aligned data
;**************** Bit definition for DAC_DHR12RD register *****************
DAC_DHR12RD_DACC1DHR EQU 0x00000FFF ; DAC channel1 12-bit Right aligned data
DAC_DHR12RD_DACC2DHR EQU 0x0FFF0000 ; DAC channel2 12-bit Right aligned data
;**************** Bit definition for DAC_DHR12LD register *****************
DAC_DHR12LD_DACC1DHR EQU 0x0000FFF0 ; DAC channel1 12-bit Left aligned data
DAC_DHR12LD_DACC2DHR EQU 0xFFF00000 ; DAC channel2 12-bit Left aligned data
;***************** Bit definition for DAC_DHR8RD register *****************
DAC_DHR8RD_DACC1DHR EQU 0x00FF ; DAC channel1 8-bit Right aligned data
DAC_DHR8RD_DACC2DHR EQU 0xFF00 ; DAC channel2 8-bit Right aligned data
;****************** Bit definition for DAC_DOR1 register ******************
DAC_DOR1_DACC1DOR EQU 0x0FFF ; DAC channel1 data output
;****************** Bit definition for DAC_DOR2 register ******************
DAC_DOR2_DACC2DOR EQU 0x0FFF ; DAC channel2 data output
;******************* Bit definition for DAC_SR register *******************
DAC_SR_DMAUDR1 EQU 0x00002000 ; DAC channel1 DMA underrun flag
DAC_SR_DMAUDR2 EQU 0x20000000 ; DAC channel2 DMA underrun flag
END

@ -0,0 +1,68 @@
;********************************************************************************
; SOUBOR : INI_BITS_DBGMCU.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro DBGMCU (Debug MCU control)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Debug MCU (DBGMCU)
;
;****************************************************************************
;*************** Bit definition for DBGMCU_IDCODE register ****************
DBGMCU_IDCODE_DEV_ID EQU 0x00000FFF ; Device Identifier
DBGMCU_IDCODE_REV_ID EQU 0xFFFF0000 ; REV_ID[15:0] bits (Revision Identifier)
DBGMCU_IDCODE_REV_ID_0 EQU 0x00010000 ; Bit 0
DBGMCU_IDCODE_REV_ID_1 EQU 0x00020000 ; Bit 1
DBGMCU_IDCODE_REV_ID_2 EQU 0x00040000 ; Bit 2
DBGMCU_IDCODE_REV_ID_3 EQU 0x00080000 ; Bit 3
DBGMCU_IDCODE_REV_ID_4 EQU 0x00100000 ; Bit 4
DBGMCU_IDCODE_REV_ID_5 EQU 0x00200000 ; Bit 5
DBGMCU_IDCODE_REV_ID_6 EQU 0x00400000 ; Bit 6
DBGMCU_IDCODE_REV_ID_7 EQU 0x00800000 ; Bit 7
DBGMCU_IDCODE_REV_ID_8 EQU 0x01000000 ; Bit 8
DBGMCU_IDCODE_REV_ID_9 EQU 0x02000000 ; Bit 9
DBGMCU_IDCODE_REV_ID_10 EQU 0x04000000 ; Bit 10
DBGMCU_IDCODE_REV_ID_11 EQU 0x08000000 ; Bit 11
DBGMCU_IDCODE_REV_ID_12 EQU 0x10000000 ; Bit 12
DBGMCU_IDCODE_REV_ID_13 EQU 0x20000000 ; Bit 13
DBGMCU_IDCODE_REV_ID_14 EQU 0x40000000 ; Bit 14
DBGMCU_IDCODE_REV_ID_15 EQU 0x80000000 ; Bit 15
;***************** Bit definition for DBGMCU_CR register ******************
DBGMCU_CR_DBG_SLEEP EQU 0x00000001 ; Debug Sleep Mode
DBGMCU_CR_DBG_STOP EQU 0x00000002 ; Debug Stop Mode
DBGMCU_CR_DBG_STANDBY EQU 0x00000004 ; Debug Standby mode
DBGMCU_CR_TRACE_IOEN EQU 0x00000020 ; Trace Pin Assignment Control
DBGMCU_CR_TRACE_MODE EQU 0x000000C0 ; TRACE_MODE[1:0] bits (Trace Pin Assignment Control)
DBGMCU_CR_TRACE_MODE_0 EQU 0x00000040 ; Bit 0
DBGMCU_CR_TRACE_MODE_1 EQU 0x00000080 ; Bit 1
;***************** Bit definition for DBGMCU_APB1_FZ register *************
DBGMCU_APB1_FZ_DBG_TIM2_STOP EQU 0x00000001 ; TIM2 counter stopped when core is halted
DBGMCU_APB1_FZ_DBG_TIM3_STOP EQU 0x00000002 ; TIM3 counter stopped when core is halted
DBGMCU_APB1_FZ_DBG_TIM4_STOP EQU 0x00000004 ; TIM4 counter stopped when core is halted
DBGMCU_APB1_FZ_DBG_TIM5_STOP EQU 0x00000008 ; TIM5 counter stopped when core is halted
DBGMCU_APB1_FZ_DBG_TIM6_STOP EQU 0x00000010 ; TIM6 counter stopped when core is halted
DBGMCU_APB1_FZ_DBG_TIM7_STOP EQU 0x00000020 ; TIM7 counter stopped when core is halted
DBGMCU_APB1_FZ_DBG_RTC_STOP EQU 0x00000400 ; RTC Counter stopped when Core is halted
DBGMCU_APB1_FZ_DBG_WWDG_STOP EQU 0x00000800 ; Debug Window Watchdog stopped when Core is halted
DBGMCU_APB1_FZ_DBG_IWDG_STOP EQU 0x00001000 ; Debug Independent Watchdog stopped when Core is halted
DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT EQU 0x00200000 ; SMBUS timeout mode stopped when Core is halted
DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT EQU 0x00400000 ; SMBUS timeout mode stopped when Core is halted
;***************** Bit definition for DBGMCU_APB2_FZ register *************
DBGMCU_APB2_FZ_DBG_TIM9_STOP EQU 0x00000004 ; TIM9 counter stopped when core is halted
DBGMCU_APB2_FZ_DBG_TIM10_STOP EQU 0x00000008 ; TIM10 counter stopped when core is halted
DBGMCU_APB2_FZ_DBG_TIM11_STOP EQU 0x00000010 ; TIM11 counter stopped when core is halted
END

@ -0,0 +1,311 @@
;********************************************************************************
; SOUBOR : INI_BITS_DMA.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro DMA (Direct memory access)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; DMA Controller (DMA)
;
;****************************************************************************
;****************** Bit definition for DMA_ISR register *******************
DMA_ISR_GIF1 EQU 0x00000001 ; Channel 1 Global interrupt flag
DMA_ISR_TCIF1 EQU 0x00000002 ; Channel 1 Transfer Complete flag
DMA_ISR_HTIF1 EQU 0x00000004 ; Channel 1 Half Transfer flag
DMA_ISR_TEIF1 EQU 0x00000008 ; Channel 1 Transfer Error flag
DMA_ISR_GIF2 EQU 0x00000010 ; Channel 2 Global interrupt flag
DMA_ISR_TCIF2 EQU 0x00000020 ; Channel 2 Transfer Complete flag
DMA_ISR_HTIF2 EQU 0x00000040 ; Channel 2 Half Transfer flag
DMA_ISR_TEIF2 EQU 0x00000080 ; Channel 2 Transfer Error flag
DMA_ISR_GIF3 EQU 0x00000100 ; Channel 3 Global interrupt flag
DMA_ISR_TCIF3 EQU 0x00000200 ; Channel 3 Transfer Complete flag
DMA_ISR_HTIF3 EQU 0x00000400 ; Channel 3 Half Transfer flag
DMA_ISR_TEIF3 EQU 0x00000800 ; Channel 3 Transfer Error flag
DMA_ISR_GIF4 EQU 0x00001000 ; Channel 4 Global interrupt flag
DMA_ISR_TCIF4 EQU 0x00002000 ; Channel 4 Transfer Complete flag
DMA_ISR_HTIF4 EQU 0x00004000 ; Channel 4 Half Transfer flag
DMA_ISR_TEIF4 EQU 0x00008000 ; Channel 4 Transfer Error flag
DMA_ISR_GIF5 EQU 0x00010000 ; Channel 5 Global interrupt flag
DMA_ISR_TCIF5 EQU 0x00020000 ; Channel 5 Transfer Complete flag
DMA_ISR_HTIF5 EQU 0x00040000 ; Channel 5 Half Transfer flag
DMA_ISR_TEIF5 EQU 0x00080000 ; Channel 5 Transfer Error flag
DMA_ISR_GIF6 EQU 0x00100000 ; Channel 6 Global interrupt flag
DMA_ISR_TCIF6 EQU 0x00200000 ; Channel 6 Transfer Complete flag
DMA_ISR_HTIF6 EQU 0x00400000 ; Channel 6 Half Transfer flag
DMA_ISR_TEIF6 EQU 0x00800000 ; Channel 6 Transfer Error flag
DMA_ISR_GIF7 EQU 0x01000000 ; Channel 7 Global interrupt flag
DMA_ISR_TCIF7 EQU 0x02000000 ; Channel 7 Transfer Complete flag
DMA_ISR_HTIF7 EQU 0x04000000 ; Channel 7 Half Transfer flag
DMA_ISR_TEIF7 EQU 0x08000000 ; Channel 7 Transfer Error flag
;****************** Bit definition for DMA_IFCR register ******************
DMA_IFCR_CGIF1 EQU 0x00000001 ; Channel 1 Global interrupt clearr
DMA_IFCR_CTCIF1 EQU 0x00000002 ; Channel 1 Transfer Complete clear
DMA_IFCR_CHTIF1 EQU 0x00000004 ; Channel 1 Half Transfer clear
DMA_IFCR_CTEIF1 EQU 0x00000008 ; Channel 1 Transfer Error clear
DMA_IFCR_CGIF2 EQU 0x00000010 ; Channel 2 Global interrupt clear
DMA_IFCR_CTCIF2 EQU 0x00000020 ; Channel 2 Transfer Complete clear
DMA_IFCR_CHTIF2 EQU 0x00000040 ; Channel 2 Half Transfer clear
DMA_IFCR_CTEIF2 EQU 0x00000080 ; Channel 2 Transfer Error clear
DMA_IFCR_CGIF3 EQU 0x00000100 ; Channel 3 Global interrupt clear
DMA_IFCR_CTCIF3 EQU 0x00000200 ; Channel 3 Transfer Complete clear
DMA_IFCR_CHTIF3 EQU 0x00000400 ; Channel 3 Half Transfer clear
DMA_IFCR_CTEIF3 EQU 0x00000800 ; Channel 3 Transfer Error clear
DMA_IFCR_CGIF4 EQU 0x00001000 ; Channel 4 Global interrupt clear
DMA_IFCR_CTCIF4 EQU 0x00002000 ; Channel 4 Transfer Complete clear
DMA_IFCR_CHTIF4 EQU 0x00004000 ; Channel 4 Half Transfer clear
DMA_IFCR_CTEIF4 EQU 0x00008000 ; Channel 4 Transfer Error clear
DMA_IFCR_CGIF5 EQU 0x00010000 ; Channel 5 Global interrupt clear
DMA_IFCR_CTCIF5 EQU 0x00020000 ; Channel 5 Transfer Complete clear
DMA_IFCR_CHTIF5 EQU 0x00040000 ; Channel 5 Half Transfer clear
DMA_IFCR_CTEIF5 EQU 0x00080000 ; Channel 5 Transfer Error clear
DMA_IFCR_CGIF6 EQU 0x00100000 ; Channel 6 Global interrupt clear
DMA_IFCR_CTCIF6 EQU 0x00200000 ; Channel 6 Transfer Complete clear
DMA_IFCR_CHTIF6 EQU 0x00400000 ; Channel 6 Half Transfer clear
DMA_IFCR_CTEIF6 EQU 0x00800000 ; Channel 6 Transfer Error clear
DMA_IFCR_CGIF7 EQU 0x01000000 ; Channel 7 Global interrupt clear
DMA_IFCR_CTCIF7 EQU 0x02000000 ; Channel 7 Transfer Complete clear
DMA_IFCR_CHTIF7 EQU 0x04000000 ; Channel 7 Half Transfer clear
DMA_IFCR_CTEIF7 EQU 0x08000000 ; Channel 7 Transfer Error clear
;****************** Bit definition for DMA_CCR1 register ******************
DMA_CCR1_EN EQU 0x0001 ; Channel enable
DMA_CCR1_TCIE EQU 0x0002 ; Transfer complete interrupt enable
DMA_CCR1_HTIE EQU 0x0004 ; Half Transfer interrupt enable
DMA_CCR1_TEIE EQU 0x0008 ; Transfer error interrupt enable
DMA_CCR1_DIR EQU 0x0010 ; Data transfer direction
DMA_CCR1_CIRC EQU 0x0020 ; Circular mode
DMA_CCR1_PINC EQU 0x0040 ; Peripheral increment mode
DMA_CCR1_MINC EQU 0x0080 ; Memory increment mode
DMA_CCR1_PSIZE EQU 0x0300 ; PSIZE[1:0] bits (Peripheral size)
DMA_CCR1_PSIZE_0 EQU 0x0100 ; Bit 0
DMA_CCR1_PSIZE_1 EQU 0x0200 ; Bit 1
DMA_CCR1_MSIZE EQU 0x0C00 ; MSIZE[1:0] bits (Memory size)
DMA_CCR1_MSIZE_0 EQU 0x0400 ; Bit 0
DMA_CCR1_MSIZE_1 EQU 0x0800 ; Bit 1
DMA_CCR1_PL EQU 0x3000 ; PL[1:0] bits(Channel Priority level)
DMA_CCR1_PL_0 EQU 0x1000 ; Bit 0
DMA_CCR1_PL_1 EQU 0x2000 ; Bit 1
DMA_CCR1_MEM2MEM EQU 0x4000 ; Memory to memory mode
;****************** Bit definition for DMA_CCR2 register ******************
DMA_CCR2_EN EQU 0x0001 ; Channel enable
DMA_CCR2_TCIE EQU 0x0002 ; ransfer complete interrupt enable
DMA_CCR2_HTIE EQU 0x0004 ; Half Transfer interrupt enable
DMA_CCR2_TEIE EQU 0x0008 ; Transfer error interrupt enable
DMA_CCR2_DIR EQU 0x0010 ; Data transfer direction
DMA_CCR2_CIRC EQU 0x0020 ; Circular mode
DMA_CCR2_PINC EQU 0x0040 ; Peripheral increment mode
DMA_CCR2_MINC EQU 0x0080 ; Memory increment mode
DMA_CCR2_PSIZE EQU 0x0300 ; PSIZE[1:0] bits (Peripheral size)
DMA_CCR2_PSIZE_0 EQU 0x0100 ; Bit 0
DMA_CCR2_PSIZE_1 EQU 0x0200 ; Bit 1
DMA_CCR2_MSIZE EQU 0x0C00 ; MSIZE[1:0] bits (Memory size)
DMA_CCR2_MSIZE_0 EQU 0x0400 ; Bit 0
DMA_CCR2_MSIZE_1 EQU 0x0800 ; Bit 1
DMA_CCR2_PL EQU 0x3000 ; PL[1:0] bits (Channel Priority level)
DMA_CCR2_PL_0 EQU 0x1000 ; Bit 0
DMA_CCR2_PL_1 EQU 0x2000 ; Bit 1
DMA_CCR2_MEM2MEM EQU 0x4000 ; Memory to memory mode
;****************** Bit definition for DMA_CCR3 register ******************
DMA_CCR3_EN EQU 0x0001 ; Channel enable
DMA_CCR3_TCIE EQU 0x0002 ; Transfer complete interrupt enable
DMA_CCR3_HTIE EQU 0x0004 ; Half Transfer interrupt enable
DMA_CCR3_TEIE EQU 0x0008 ; Transfer error interrupt enable
DMA_CCR3_DIR EQU 0x0010 ; Data transfer direction
DMA_CCR3_CIRC EQU 0x0020 ; Circular mode
DMA_CCR3_PINC EQU 0x0040 ; Peripheral increment mode
DMA_CCR3_MINC EQU 0x0080 ; Memory increment mode
DMA_CCR3_PSIZE EQU 0x0300 ; PSIZE[1:0] bits (Peripheral size)
DMA_CCR3_PSIZE_0 EQU 0x0100 ; Bit 0
DMA_CCR3_PSIZE_1 EQU 0x0200 ; Bit 1
DMA_CCR3_MSIZE EQU 0x0C00 ; MSIZE[1:0] bits (Memory size)
DMA_CCR3_MSIZE_0 EQU 0x0400 ; Bit 0
DMA_CCR3_MSIZE_1 EQU 0x0800 ; Bit 1
DMA_CCR3_PL EQU 0x3000 ; PL[1:0] bits (Channel Priority level)
DMA_CCR3_PL_0 EQU 0x1000 ; Bit 0
DMA_CCR3_PL_1 EQU 0x2000 ; Bit 1
DMA_CCR3_MEM2MEM EQU 0x4000 ; Memory to memory mode
; ****************** Bit definition for DMA_CCR4 register ******************
DMA_CCR4_EN EQU 0x0001 ; Channel enable
DMA_CCR4_TCIE EQU 0x0002 ; Transfer complete interrupt enable
DMA_CCR4_HTIE EQU 0x0004 ; Half Transfer interrupt enable
DMA_CCR4_TEIE EQU 0x0008 ; Transfer error interrupt enable
DMA_CCR4_DIR EQU 0x0010 ; Data transfer direction
DMA_CCR4_CIRC EQU 0x0020 ; Circular mode
DMA_CCR4_PINC EQU 0x0040 ; Peripheral increment mode
DMA_CCR4_MINC EQU 0x0080 ; Memory increment mode
DMA_CCR4_PSIZE EQU 0x0300 ; PSIZE[1:0] bits (Peripheral size)
DMA_CCR4_PSIZE_0 EQU 0x0100 ; Bit 0
DMA_CCR4_PSIZE_1 EQU 0x0200 ; Bit 1
DMA_CCR4_MSIZE EQU 0x0C00 ; MSIZE[1:0] bits (Memory size)
DMA_CCR4_MSIZE_0 EQU 0x0400 ; Bit 0
DMA_CCR4_MSIZE_1 EQU 0x0800 ; Bit 1
DMA_CCR4_PL EQU 0x3000 ; PL[1:0] bits (Channel Priority level)
DMA_CCR4_PL_0 EQU 0x1000 ; Bit 0
DMA_CCR4_PL_1 EQU 0x2000 ; Bit 1
DMA_CCR4_MEM2MEM EQU 0x4000 ; Memory to memory mode
;***************** Bit definition for DMA_CCR5 register ******************
DMA_CCR5_EN EQU 0x0001 ; Channel enable
DMA_CCR5_TCIE EQU 0x0002 ; Transfer complete interrupt enable
DMA_CCR5_HTIE EQU 0x0004 ; Half Transfer interrupt enable
DMA_CCR5_TEIE EQU 0x0008 ; Transfer error interrupt enable
DMA_CCR5_DIR EQU 0x0010 ; Data transfer direction
DMA_CCR5_CIRC EQU 0x0020 ; Circular mode
DMA_CCR5_PINC EQU 0x0040 ; Peripheral increment mode
DMA_CCR5_MINC EQU 0x0080 ; Memory increment mode
DMA_CCR5_PSIZE EQU 0x0300 ; PSIZE[1:0] bits (Peripheral size)
DMA_CCR5_PSIZE_0 EQU 0x0100 ; Bit 0
DMA_CCR5_PSIZE_1 EQU 0x0200 ; Bit 1
DMA_CCR5_MSIZE EQU 0x0C00 ; MSIZE[1:0] bits (Memory size)
DMA_CCR5_MSIZE_0 EQU 0x0400 ; Bit 0
DMA_CCR5_MSIZE_1 EQU 0x0800 ; Bit 1
DMA_CCR5_PL EQU 0x3000 ; PL[1:0] bits (Channel Priority level)
DMA_CCR5_PL_0 EQU 0x1000 ; Bit 0
DMA_CCR5_PL_1 EQU 0x2000 ; Bit 1
DMA_CCR5_MEM2MEM EQU 0x4000 ; Memory to memory mode enable
;****************** Bit definition for DMA_CCR6 register ******************
DMA_CCR6_EN EQU 0x0001 ; Channel enable
DMA_CCR6_TCIE EQU 0x0002 ; Transfer complete interrupt enable
DMA_CCR6_HTIE EQU 0x0004 ; Half Transfer interrupt enable
DMA_CCR6_TEIE EQU 0x0008 ; Transfer error interrupt enable
DMA_CCR6_DIR EQU 0x0010 ; Data transfer direction
DMA_CCR6_CIRC EQU 0x0020 ; Circular mode
DMA_CCR6_PINC EQU 0x0040 ; Peripheral increment mode
DMA_CCR6_MINC EQU 0x0080 ; Memory increment mode
DMA_CCR6_PSIZE EQU 0x0300 ; PSIZE[1:0] bits (Peripheral size)
DMA_CCR6_PSIZE_0 EQU 0x0100 ; Bit 0
DMA_CCR6_PSIZE_1 EQU 0x0200 ; Bit 1
DMA_CCR6_MSIZE EQU 0x0C00 ; MSIZE[1:0] bits (Memory size)
DMA_CCR6_MSIZE_0 EQU 0x0400 ; Bit 0
DMA_CCR6_MSIZE_1 EQU 0x0800 ; Bit 1
DMA_CCR6_PL EQU 0x3000 ; PL[1:0] bits (Channel Priority level)
DMA_CCR6_PL_0 EQU 0x1000 ; Bit 0
DMA_CCR6_PL_1 EQU 0x2000 ; Bit 1
DMA_CCR6_MEM2MEM EQU 0x4000 ; Memory to memory mode
;****************** Bit definition for DMA_CCR7 register ******************
DMA_CCR7_EN EQU 0x0001 ; Channel enable
DMA_CCR7_TCIE EQU 0x0002 ; Transfer complete interrupt enable
DMA_CCR7_HTIE EQU 0x0004 ; Half Transfer interrupt enable
DMA_CCR7_TEIE EQU 0x0008 ; Transfer error interrupt enable
DMA_CCR7_DIR EQU 0x0010 ; Data transfer direction
DMA_CCR7_CIRC EQU 0x0020 ; Circular mode
DMA_CCR7_PINC EQU 0x0040 ; Peripheral increment mode
DMA_CCR7_MINC EQU 0x0080 ; Memory increment mode
DMA_CCR7_PSIZE EQU 0x0300 ; PSIZE[1:0] bits (Peripheral size)
DMA_CCR7_PSIZE_0 EQU 0x0100 ; Bit 0
DMA_CCR7_PSIZE_1 EQU 0x0200 ; Bit 1
DMA_CCR7_MSIZE EQU 0x0C00 ; MSIZE[1:0] bits (Memory size)
DMA_CCR7_MSIZE_0 EQU 0x0400 ; Bit 0
DMA_CCR7_MSIZE_1 EQU 0x0800 ; Bit 1
DMA_CCR7_PL EQU 0x3000 ; PL[1:0] bits (Channel Priority level)
DMA_CCR7_PL_0 EQU 0x1000 ; Bit 0
DMA_CCR7_PL_1 EQU 0x2000 ; Bit 1
DMA_CCR7_MEM2MEM EQU 0x4000 ; Memory to memory mode enable
;***************** Bit definition for DMA_CNDTR1 register *****************
DMA_CNDTR1_NDT EQU 0xFFFF ; Number of data to Transfer
;***************** Bit definition for DMA_CNDTR2 register *****************
DMA_CNDTR2_NDT EQU 0xFFFF ; Number of data to Transfer
;***************** Bit definition for DMA_CNDTR3 register *****************
DMA_CNDTR3_NDT EQU 0xFFFF ; Number of data to Transfer
;***************** Bit definition for DMA_CNDTR4 register *****************
DMA_CNDTR4_NDT EQU 0xFFFF ; Number of data to Transfer
;***************** Bit definition for DMA_CNDTR5 register *****************
DMA_CNDTR5_NDT EQU 0xFFFF ; Number of data to Transfer
;***************** Bit definition for DMA_CNDTR6 register *****************
DMA_CNDTR6_NDT EQU 0xFFFF ; Number of data to Transfer
;***************** Bit definition for DMA_CNDTR7 register *****************
DMA_CNDTR7_NDT EQU 0xFFFF ; Number of data to Transfer
;***************** Bit definition for DMA_CPAR1 register ******************
DMA_CPAR1_PA EQU 0xFFFFFFFF ; Peripheral Address
;***************** Bit definition for DMA_CPAR2 register ******************
DMA_CPAR2_PA EQU 0xFFFFFFFF ; Peripheral Address
;***************** Bit definition for DMA_CPAR3 register ******************
DMA_CPAR3_PA EQU 0xFFFFFFFF ; Peripheral Address
;***************** Bit definition for DMA_CPAR4 register ******************
DMA_CPAR4_PA EQU 0xFFFFFFFF ; Peripheral Address
;***************** Bit definition for DMA_CPAR5 register ******************
DMA_CPAR5_PA EQU 0xFFFFFFFF ; Peripheral Address
;***************** Bit definition for DMA_CPAR6 register ******************
DMA_CPAR6_PA EQU 0xFFFFFFFF ; Peripheral Address
;***************** Bit definition for DMA_CPAR7 register ******************
DMA_CPAR7_PA EQU 0xFFFFFFFF ; Peripheral Address
;***************** Bit definition for DMA_CMAR1 register ******************
DMA_CMAR1_MA EQU 0xFFFFFFFF ; Memory Address
;***************** Bit definition for DMA_CMAR2 register ******************
DMA_CMAR2_MA EQU 0xFFFFFFFF ; Memory Address
;***************** Bit definition for DMA_CMAR3 register ******************
DMA_CMAR3_MA EQU 0xFFFFFFFF ; Memory Address
;***************** Bit definition for DMA_CMAR4 register ******************
DMA_CMAR4_MA EQU 0xFFFFFFFF ; Memory Address
;***************** Bit definition for DMA_CMAR5 register ******************
DMA_CMAR5_MA EQU 0xFFFFFFFF ; Memory Address
;***************** Bit definition for DMA_CMAR6 register ******************
DMA_CMAR6_MA EQU 0xFFFFFFFF ; Memory Address
;***************** Bit definition for DMA_CMAR7 register ******************
DMA_CMAR7_MA EQU 0xFFFFFFFF ; Memory Address
END

@ -0,0 +1,173 @@
;********************************************************************************
; SOUBOR : INI_BITS_EXTI.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro EXTI (ext. interrupt)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; External Interrupt/Event Controller (EXTI)
;
;****************************************************************************
;****************** Bit definition for EXTI_IMR register ******************
EXTI_IMR_MR0 EQU 0x00000001 ; Interrupt Mask on line 0
EXTI_IMR_MR1 EQU 0x00000002 ; Interrupt Mask on line 1
EXTI_IMR_MR2 EQU 0x00000004 ; Interrupt Mask on line 2
EXTI_IMR_MR3 EQU 0x00000008 ; Interrupt Mask on line 3
EXTI_IMR_MR4 EQU 0x00000010 ; Interrupt Mask on line 4
EXTI_IMR_MR5 EQU 0x00000020 ; Interrupt Mask on line 5
EXTI_IMR_MR6 EQU 0x00000040 ; Interrupt Mask on line 6
EXTI_IMR_MR7 EQU 0x00000080 ; Interrupt Mask on line 7
EXTI_IMR_MR8 EQU 0x00000100 ; Interrupt Mask on line 8
EXTI_IMR_MR9 EQU 0x00000200 ; Interrupt Mask on line 9
EXTI_IMR_MR10 EQU 0x00000400 ; Interrupt Mask on line 10
EXTI_IMR_MR11 EQU 0x00000800 ; Interrupt Mask on line 11
EXTI_IMR_MR12 EQU 0x00001000 ; Interrupt Mask on line 12
EXTI_IMR_MR13 EQU 0x00002000 ; Interrupt Mask on line 13
EXTI_IMR_MR14 EQU 0x00004000 ; Interrupt Mask on line 14
EXTI_IMR_MR15 EQU 0x00008000 ; Interrupt Mask on line 15
EXTI_IMR_MR16 EQU 0x00010000 ; Interrupt Mask on line 16
EXTI_IMR_MR17 EQU 0x00020000 ; Interrupt Mask on line 17
EXTI_IMR_MR18 EQU 0x00040000 ; Interrupt Mask on line 18
EXTI_IMR_MR19 EQU 0x00080000 ; Interrupt Mask on line 19
EXTI_IMR_MR20 EQU 0x00100000 ; Interrupt Mask on line 20
EXTI_IMR_MR21 EQU 0x00200000 ; Interrupt Mask on line 21
EXTI_IMR_MR22 EQU 0x00400000 ; Interrupt Mask on line 22
EXTI_IMR_MR23 EQU 0x00800000 ; Interrupt Mask on line 23
;****************** Bit definition for EXTI_EMR register ******************
EXTI_EMR_MR0 EQU 0x00000001 ; Event Mask on line 0
EXTI_EMR_MR1 EQU 0x00000002 ; Event Mask on line 1
EXTI_EMR_MR2 EQU 0x00000004 ; Event Mask on line 2
EXTI_EMR_MR3 EQU 0x00000008 ; Event Mask on line 3
EXTI_EMR_MR4 EQU 0x00000010 ; Event Mask on line 4
EXTI_EMR_MR5 EQU 0x00000020 ; Event Mask on line 5
EXTI_EMR_MR6 EQU 0x00000040 ; Event Mask on line 6
EXTI_EMR_MR7 EQU 0x00000080 ; Event Mask on line 7
EXTI_EMR_MR8 EQU 0x00000100 ; Event Mask on line 8
EXTI_EMR_MR9 EQU 0x00000200 ; Event Mask on line 9
EXTI_EMR_MR10 EQU 0x00000400 ; Event Mask on line 10
EXTI_EMR_MR11 EQU 0x00000800 ; Event Mask on line 11
EXTI_EMR_MR12 EQU 0x00001000 ; Event Mask on line 12
EXTI_EMR_MR13 EQU 0x00002000 ; Event Mask on line 13
EXTI_EMR_MR14 EQU 0x00004000 ; Event Mask on line 14
EXTI_EMR_MR15 EQU 0x00008000 ; Event Mask on line 15
EXTI_EMR_MR16 EQU 0x00010000 ; Event Mask on line 16
EXTI_EMR_MR17 EQU 0x00020000 ; Event Mask on line 17
EXTI_EMR_MR18 EQU 0x00040000 ; Event Mask on line 18
EXTI_EMR_MR19 EQU 0x00080000 ; Event Mask on line 19
EXTI_EMR_MR20 EQU 0x00100000 ; Event Mask on line 20
EXTI_EMR_MR21 EQU 0x00200000 ; Event Mask on line 21
EXTI_EMR_MR22 EQU 0x00400000 ; Event Mask on line 22
EXTI_EMR_MR23 EQU 0x00800000 ; Event Mask on line 23
;***************** Bit definition for EXTI_RTSR register ******************
EXTI_RTSR_TR0 EQU 0x00000001 ; Rising trigger event configuration bit of line 0
EXTI_RTSR_TR1 EQU 0x00000002 ; Rising trigger event configuration bit of line 1
EXTI_RTSR_TR2 EQU 0x00000004 ; Rising trigger event configuration bit of line 2
EXTI_RTSR_TR3 EQU 0x00000008 ; Rising trigger event configuration bit of line 3
EXTI_RTSR_TR4 EQU 0x00000010 ; Rising trigger event configuration bit of line 4
EXTI_RTSR_TR5 EQU 0x00000020 ; Rising trigger event configuration bit of line 5
EXTI_RTSR_TR6 EQU 0x00000040 ; Rising trigger event configuration bit of line 6
EXTI_RTSR_TR7 EQU 0x00000080 ; Rising trigger event configuration bit of line 7
EXTI_RTSR_TR8 EQU 0x00000100 ; Rising trigger event configuration bit of line 8
EXTI_RTSR_TR9 EQU 0x00000200 ; Rising trigger event configuration bit of line 9
EXTI_RTSR_TR10 EQU 0x00000400 ; Rising trigger event configuration bit of line 10
EXTI_RTSR_TR11 EQU 0x00000800 ; Rising trigger event configuration bit of line 11
EXTI_RTSR_TR12 EQU 0x00001000 ; Rising trigger event configuration bit of line 12
EXTI_RTSR_TR13 EQU 0x00002000 ; Rising trigger event configuration bit of line 13
EXTI_RTSR_TR14 EQU 0x00004000 ; Rising trigger event configuration bit of line 14
EXTI_RTSR_TR15 EQU 0x00008000 ; Rising trigger event configuration bit of line 15
EXTI_RTSR_TR16 EQU 0x00010000 ; Rising trigger event configuration bit of line 16
EXTI_RTSR_TR17 EQU 0x00020000 ; Rising trigger event configuration bit of line 17
EXTI_RTSR_TR18 EQU 0x00040000 ; Rising trigger event configuration bit of line 18
EXTI_RTSR_TR19 EQU 0x00080000 ; Rising trigger event configuration bit of line 19
EXTI_RTSR_TR20 EQU 0x00100000 ; Rising trigger event configuration bit of line 20
EXTI_RTSR_TR21 EQU 0x00200000 ; Rising trigger event configuration bit of line 21
EXTI_RTSR_TR22 EQU 0x00400000 ; Rising trigger event configuration bit of line 22
EXTI_RTSR_TR23 EQU 0x00800000 ; Rising trigger event configuration bit of line 23
;***************** Bit definition for EXTI_FTSR register ******************
EXTI_FTSR_TR0 EQU 0x00000001 ; Falling trigger event configuration bit of line 0
EXTI_FTSR_TR1 EQU 0x00000002 ; Falling trigger event configuration bit of line 1
EXTI_FTSR_TR2 EQU 0x00000004 ; Falling trigger event configuration bit of line 2
EXTI_FTSR_TR3 EQU 0x00000008 ; Falling trigger event configuration bit of line 3
EXTI_FTSR_TR4 EQU 0x00000010 ; Falling trigger event configuration bit of line 4
EXTI_FTSR_TR5 EQU 0x00000020 ; Falling trigger event configuration bit of line 5
EXTI_FTSR_TR6 EQU 0x00000040 ; Falling trigger event configuration bit of line 6
EXTI_FTSR_TR7 EQU 0x00000080 ; Falling trigger event configuration bit of line 7
EXTI_FTSR_TR8 EQU 0x00000100 ; Falling trigger event configuration bit of line 8
EXTI_FTSR_TR9 EQU 0x00000200 ; Falling trigger event configuration bit of line 9
EXTI_FTSR_TR10 EQU 0x00000400 ; Falling trigger event configuration bit of line 10
EXTI_FTSR_TR11 EQU 0x00000800 ; Falling trigger event configuration bit of line 11
EXTI_FTSR_TR12 EQU 0x00001000 ; Falling trigger event configuration bit of line 12
EXTI_FTSR_TR13 EQU 0x00002000 ; Falling trigger event configuration bit of line 13
EXTI_FTSR_TR14 EQU 0x00004000 ; Falling trigger event configuration bit of line 14
EXTI_FTSR_TR15 EQU 0x00008000 ; Falling trigger event configuration bit of line 15
EXTI_FTSR_TR16 EQU 0x00010000 ; Falling trigger event configuration bit of line 16
EXTI_FTSR_TR17 EQU 0x00020000 ; Falling trigger event configuration bit of line 17
EXTI_FTSR_TR18 EQU 0x00040000 ; Falling trigger event configuration bit of line 18
EXTI_FTSR_TR19 EQU 0x00080000 ; Falling trigger event configuration bit of line 19
EXTI_FTSR_TR20 EQU 0x00100000 ; Falling trigger event configuration bit of line 20
EXTI_FTSR_TR21 EQU 0x00200000 ; Falling trigger event configuration bit of line 21
EXTI_FTSR_TR22 EQU 0x00400000 ; Falling trigger event configuration bit of line 22
EXTI_FTSR_TR23 EQU 0x00800000 ; Falling trigger event configuration bit of line 23
;***************** Bit definition for EXTI_SWIER register *****************
EXTI_SWIER_SWIER0 EQU 0x00000001 ; Software Interrupt on line 0
EXTI_SWIER_SWIER1 EQU 0x00000002 ; Software Interrupt on line 1
EXTI_SWIER_SWIER2 EQU 0x00000004 ; Software Interrupt on line 2
EXTI_SWIER_SWIER3 EQU 0x00000008 ; Software Interrupt on line 3
EXTI_SWIER_SWIER4 EQU 0x00000010 ; Software Interrupt on line 4
EXTI_SWIER_SWIER5 EQU 0x00000020 ; Software Interrupt on line 5
EXTI_SWIER_SWIER6 EQU 0x00000040 ; Software Interrupt on line 6
EXTI_SWIER_SWIER7 EQU 0x00000080 ; Software Interrupt on line 7
EXTI_SWIER_SWIER8 EQU 0x00000100 ; Software Interrupt on line 8
EXTI_SWIER_SWIER9 EQU 0x00000200 ; Software Interrupt on line 9
EXTI_SWIER_SWIER10 EQU 0x00000400 ; Software Interrupt on line 10
EXTI_SWIER_SWIER11 EQU 0x00000800 ; Software Interrupt on line 11
EXTI_SWIER_SWIER12 EQU 0x00001000 ; Software Interrupt on line 12
EXTI_SWIER_SWIER13 EQU 0x00002000 ; Software Interrupt on line 13
EXTI_SWIER_SWIER14 EQU 0x00004000 ; Software Interrupt on line 14
EXTI_SWIER_SWIER15 EQU 0x00008000 ; Software Interrupt on line 15
EXTI_SWIER_SWIER16 EQU 0x00010000 ; Software Interrupt on line 16
EXTI_SWIER_SWIER17 EQU 0x00020000 ; Software Interrupt on line 17
EXTI_SWIER_SWIER18 EQU 0x00040000 ; Software Interrupt on line 18
EXTI_SWIER_SWIER19 EQU 0x00080000 ; Software Interrupt on line 19
EXTI_SWIER_SWIER20 EQU 0x00100000 ; Software Interrupt on line 20
EXTI_SWIER_SWIER21 EQU 0x00200000 ; Software Interrupt on line 21
EXTI_SWIER_SWIER22 EQU 0x00400000 ; Software Interrupt on line 22
EXTI_SWIER_SWIER23 EQU 0x00800000 ; Software Interrupt on line 23
;****************** Bit definition for EXTI_PR register *******************
EXTI_PR_PR0 EQU 0x00000001 ; Pending bit 0
EXTI_PR_PR1 EQU 0x00000002 ; Pending bit 1
EXTI_PR_PR2 EQU 0x00000004 ; Pending bit 2
EXTI_PR_PR3 EQU 0x00000008 ; Pending bit 3
EXTI_PR_PR4 EQU 0x00000010 ; Pending bit 4
EXTI_PR_PR5 EQU 0x00000020 ; Pending bit 5
EXTI_PR_PR6 EQU 0x00000040 ; Pending bit 6
EXTI_PR_PR7 EQU 0x00000080 ; Pending bit 7
EXTI_PR_PR8 EQU 0x00000100 ; Pending bit 8
EXTI_PR_PR9 EQU 0x00000200 ; Pending bit 9
EXTI_PR_PR10 EQU 0x00000400 ; Pending bit 10
EXTI_PR_PR11 EQU 0x00000800 ; Pending bit 11
EXTI_PR_PR12 EQU 0x00001000 ; Pending bit 12
EXTI_PR_PR13 EQU 0x00002000 ; Pending bit 13
EXTI_PR_PR14 EQU 0x00004000 ; Pending bit 14
EXTI_PR_PR15 EQU 0x00008000 ; Pending bit 15
EXTI_PR_PR16 EQU 0x00010000 ; Pending bit 16
EXTI_PR_PR17 EQU 0x00020000 ; Pending bit 17
EXTI_PR_PR18 EQU 0x00040000 ; Pending bit 18
EXTI_PR_PR19 EQU 0x00080000 ; Pending bit 19
EXTI_PR_PR20 EQU 0x00100000 ; Pending bit 20
EXTI_PR_PR21 EQU 0x00200000 ; Pending bit 21
EXTI_PR_PR22 EQU 0x00400000 ; Pending bit 22
EXTI_PR_PR23 EQU 0x00800000 ; Pending bit 23
END

@ -0,0 +1,82 @@
;********************************************************************************
; SOUBOR : INI_BITS_FLASH.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro FLASH
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; FLASH, DATA EEPROM and Option Bytes Registers
; EQU (FLASH, DATA_EEPROM, OB)
;
;****************************************************************************
;****************** Bit definition for FLASH_ACR register *****************
FLASH_ACR_LATENCY EQU 0x00000001 ; Latency
FLASH_ACR_PRFTEN EQU 0x00000002 ; Prefetch Buffer Enable
FLASH_ACR_ACC64 EQU 0x00000004 ; Access 64 bits
FLASH_ACR_SLEEP_PD EQU 0x00000008 ; Flash mode during sleep mode
FLASH_ACR_RUN_PD EQU 0x00000010 ; Flash mode during RUN mode
;****************** Bit definition for FLASH_PECR register *****************
FLASH_PECR_PELOCK EQU 0x00000001 ; FLASH_PECR and Flash data Lock
FLASH_PECR_PRGLOCK EQU 0x00000002 ; Program matrix Lock
FLASH_PECR_OPTLOCK EQU 0x00000004 ; Option byte matrix Lock
FLASH_PECR_PROG EQU 0x00000008 ; Program matrix selection
FLASH_PECR_DATA EQU 0x00000010 ; Data matrix selection
FLASH_PECR_FTDW EQU 0x00000100 ; Fixed Time Data write for Word/Half Word/Byte programming
FLASH_PECR_ERASE EQU 0x00000200 ; Page erasing mode
FLASH_PECR_FPRG EQU 0x00000400 ; Fast Page/Half Page programming mode
FLASH_PECR_PARALLBANK EQU 0x00008000 ; Parallel Bank mode
FLASH_PECR_EOPIE EQU 0x00010000 ; End of programming interrupt
FLASH_PECR_ERRIE EQU 0x00020000 ; Error interrupt
FLASH_PECR_OBL_LAUNCH EQU 0x00040000 ; Launch the option byte loading
;***************** Bit definition for FLASH_PDKEYR register *****************
FLASH_PDKEYR_PDKEYR EQU 0xFFFFFFFF ; FLASH_PEC and data matrix Key
;***************** Bit definition for FLASH_PEKEYR register *****************
FLASH_PEKEYR_PEKEYR EQU 0xFFFFFFFF ; FLASH_PEC and data matrix Key
;***************** Bit definition for FLASH_PRGKEYR register *****************
FLASH_PRGKEYR_PRGKEYR EQU 0xFFFFFFFF ; Program matrix Key
;***************** Bit definition for FLASH_OPTKEYR register *****************
FLASH_OPTKEYR_OPTKEYR EQU 0xFFFFFFFF ; Option bytes matrix Key
;***************** Bit definition for FLASH_SR register ******************
FLASH_SR_BSY EQU 0x00000001 ; Busy
FLASH_SR_EOP EQU 0x00000002 ; End Of Programming
FLASH_SR_ENHV EQU 0x00000004 ; End of high voltage
FLASH_SR_READY EQU 0x00000008 ; Flash ready after low power mode
FLASH_SR_WRPERR EQU 0x00000100 ; Write protected error
FLASH_SR_PGAERR EQU 0x00000200 ; Programming Alignment Error
FLASH_SR_SIZERR EQU 0x00000400 ; Size error
FLASH_SR_OPTVERR EQU 0x00000800 ; Option validity error
FLASH_SR_OPTVERRUSR EQU 0x00001000 ; Option User validity error
FLASH_SR_RDERR EQU 0x00002000 ; Read protected error
;***************** Bit definition for FLASH_OBR register ******************
FLASH_OBR_RDPRT EQU 0x000000AA ; Read Protection
FLASH_OBR_SPRMOD EQU 0x00000100 ; Selection of protection mode of WPRi bits (available only in STM32L1xx Medium-density Plus devices)
FLASH_OBR_BOR_LEV EQU 0x000F0000 ; BOR_LEV[3:0] Brown Out Reset Threshold Level
FLASH_OBR_IWDG_SW EQU 0x00100000 ; IWDG_SW
FLASH_OBR_nRST_STOP EQU 0x00200000 ; nRST_STOP
FLASH_OBR_nRST_STDBY EQU 0x00400000 ; nRST_STDBY
FLASH_OBR_BFB2 EQU 0x00800000 ; BFB2(available only in STM32L1xx High-density devices)
;***************** Bit definition for FLASH_WRPR register *****************
FLASH_WRPR_WRP EQU 0xFFFFFFFF ; Write Protection bits
;***************** Bit definition for FLASH_WRPR1 register ****************
FLASH_WRPR1_WRP EQU 0xFFFFFFFF ; Write Protection bits (available only in STM32L1xx Medium-density Plus and High-density devices)
;***************** Bit definition for FLASH_WRPR2 register ****************
FLASH_WRPR2_WRP EQU 0xFFFFFFFF ; Write Protection bits (available only in STM32L1xx High-density devices)
END

@ -0,0 +1,413 @@
;********************************************************************************
; SOUBOR : INI_BITS_FSMC.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro FSMC (ext. memory communication)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Flexible Static Memory Controller
;
;****************************************************************************
;***************** Bit definition for FSMC_BCR1 register ******************
FSMC_BCR1_MBKEN EQU 0x00000001 ; Memory bank enable bit
FSMC_BCR1_MUXEN EQU 0x00000002 ; Address/data multiplexing enable bit
FSMC_BCR1_MTYP EQU 0x0000000C ; MTYP[1:0] bits (Memory type)
FSMC_BCR1_MTYP_0 EQU 0x00000004 ; Bit 0
FSMC_BCR1_MTYP_1 EQU 0x00000008 ; Bit 1
FSMC_BCR1_MWID EQU 0x00000030 ; MWID[1:0] bits (Memory data bus width)
FSMC_BCR1_MWID_0 EQU 0x00000010 ; Bit 0
FSMC_BCR1_MWID_1 EQU 0x00000020 ; Bit 1
FSMC_BCR1_FACCEN EQU 0x00000040 ; Flash access enable
FSMC_BCR1_BURSTEN EQU 0x00000100 ; Burst enable bit
FSMC_BCR1_WAITPOL EQU 0x00000200 ; Wait signal polarity bit
FSMC_BCR1_WRAPMOD EQU 0x00000400 ; Wrapped burst mode support
FSMC_BCR1_WAITCFG EQU 0x00000800 ; Wait timing configuration
FSMC_BCR1_WREN EQU 0x00001000 ; Write enable bit
FSMC_BCR1_WAITEN EQU 0x00002000 ; Wait enable bit
FSMC_BCR1_EXTMOD EQU 0x00004000 ; Extended mode enable
FSMC_BCR1_ASYNCWAIT EQU 0x00008000 ; Asynchronous wait
FSMC_BCR1_CBURSTRW EQU 0x00080000 ; Write burst enable
;***************** Bit definition for FSMC_BCR2 register ******************
FSMC_BCR2_MBKEN EQU 0x00000001 ; Memory bank enable bit
FSMC_BCR2_MUXEN EQU 0x00000002 ; Address/data multiplexing enable bit
FSMC_BCR2_MTYP EQU 0x0000000C ; MTYP[1:0] bits (Memory type)
FSMC_BCR2_MTYP_0 EQU 0x00000004 ; Bit 0
FSMC_BCR2_MTYP_1 EQU 0x00000008 ; Bit 1
FSMC_BCR2_MWID EQU 0x00000030 ; MWID[1:0] bits (Memory data bus width)
FSMC_BCR2_MWID_0 EQU 0x00000010 ; Bit 0
FSMC_BCR2_MWID_1 EQU 0x00000020 ; Bit 1
FSMC_BCR2_FACCEN EQU 0x00000040 ; Flash access enable
FSMC_BCR2_BURSTEN EQU 0x00000100 ; Burst enable bit
FSMC_BCR2_WAITPOL EQU 0x00000200 ; Wait signal polarity bit
FSMC_BCR2_WRAPMOD EQU 0x00000400 ; Wrapped burst mode support
FSMC_BCR2_WAITCFG EQU 0x00000800 ; Wait timing configuration
FSMC_BCR2_WREN EQU 0x00001000 ; Write enable bit
FSMC_BCR2_WAITEN EQU 0x00002000 ; Wait enable bit
FSMC_BCR2_EXTMOD EQU 0x00004000 ; Extended mode enable
FSMC_BCR2_ASYNCWAIT EQU 0x00008000 ; Asynchronous wait
FSMC_BCR2_CBURSTRW EQU 0x00080000 ; Write burst enable
;***************** Bit definition for FSMC_BCR3 register ******************
FSMC_BCR3_MBKEN EQU 0x00000001 ; Memory bank enable bit
FSMC_BCR3_MUXEN EQU 0x00000002 ; Address/data multiplexing enable bit
FSMC_BCR3_MTYP EQU 0x0000000C ; MTYP[1:0] bits (Memory type)
FSMC_BCR3_MTYP_0 EQU 0x00000004 ; Bit 0
FSMC_BCR3_MTYP_1 EQU 0x00000008 ; Bit 1
FSMC_BCR3_MWID EQU 0x00000030 ; MWID[1:0] bits (Memory data bus width)
FSMC_BCR3_MWID_0 EQU 0x00000010 ; Bit 0
FSMC_BCR3_MWID_1 EQU 0x00000020 ; Bit 1
FSMC_BCR3_FACCEN EQU 0x00000040 ; Flash access enable
FSMC_BCR3_BURSTEN EQU 0x00000100 ; Burst enable bit
FSMC_BCR3_WAITPOL EQU 0x00000200 ; Wait signal polarity bit.
FSMC_BCR3_WRAPMOD EQU 0x00000400 ; Wrapped burst mode support
FSMC_BCR3_WAITCFG EQU 0x00000800 ; Wait timing configuration
FSMC_BCR3_WREN EQU 0x00001000 ; Write enable bit
FSMC_BCR3_WAITEN EQU 0x00002000 ; Wait enable bit
FSMC_BCR3_EXTMOD EQU 0x00004000 ; Extended mode enable
FSMC_BCR3_ASYNCWAIT EQU 0x00008000 ; Asynchronous wait
FSMC_BCR3_CBURSTRW EQU 0x00080000 ; Write burst enable
;***************** Bit definition for FSMC_BCR4 register ******************
FSMC_BCR4_MBKEN EQU 0x00000001 ; Memory bank enable bit
FSMC_BCR4_MUXEN EQU 0x00000002 ; Address/data multiplexing enable bit
FSMC_BCR4_MTYP EQU 0x0000000C ; MTYP[1:0] bits (Memory type)
FSMC_BCR4_MTYP_0 EQU 0x00000004 ; Bit 0
FSMC_BCR4_MTYP_1 EQU 0x00000008 ; Bit 1
FSMC_BCR4_MWID EQU 0x00000030 ; MWID[1:0] bits (Memory data bus width)
FSMC_BCR4_MWID_0 EQU 0x00000010 ; Bit 0
FSMC_BCR4_MWID_1 EQU 0x00000020 ; Bit 1
FSMC_BCR4_FACCEN EQU 0x00000040 ; Flash access enable
FSMC_BCR4_BURSTEN EQU 0x00000100 ; Burst enable bit
FSMC_BCR4_WAITPOL EQU 0x00000200 ; Wait signal polarity bit
FSMC_BCR4_WRAPMOD EQU 0x00000400 ; Wrapped burst mode support
FSMC_BCR4_WAITCFG EQU 0x00000800 ; Wait timing configuration
FSMC_BCR4_WREN EQU 0x00001000 ; Write enable bit
FSMC_BCR4_WAITEN EQU 0x00002000 ; Wait enable bit
FSMC_BCR4_EXTMOD EQU 0x00004000 ; Extended mode enable
FSMC_BCR4_ASYNCWAIT EQU 0x00008000 ; Asynchronous wait
FSMC_BCR4_CBURSTRW EQU 0x00080000 ; Write burst enable
;***************** Bit definition for FSMC_BTR1 register *****************
FSMC_BTR1_ADDSET EQU 0x0000000F ; ADDSET[3:0] bits (Address setup phase duration)
FSMC_BTR1_ADDSET_0 EQU 0x00000001 ; Bit 0
FSMC_BTR1_ADDSET_1 EQU 0x00000002 ; Bit 1
FSMC_BTR1_ADDSET_2 EQU 0x00000004 ; Bit 2
FSMC_BTR1_ADDSET_3 EQU 0x00000008 ; Bit 3
FSMC_BTR1_ADDHLD EQU 0x000000F0 ; ADDHLD[3:0] bits (Address-hold phase duration)
FSMC_BTR1_ADDHLD_0 EQU 0x00000010 ; Bit 0
FSMC_BTR1_ADDHLD_1 EQU 0x00000020 ; Bit 1
FSMC_BTR1_ADDHLD_2 EQU 0x00000040 ; Bit 2
FSMC_BTR1_ADDHLD_3 EQU 0x00000080 ; Bit 3
FSMC_BTR1_DATAST EQU 0x0000FF00 ; DATAST [3:0] bits (Data-phase duration)
FSMC_BTR1_DATAST_0 EQU 0x00000100 ; Bit 0
FSMC_BTR1_DATAST_1 EQU 0x00000200 ; Bit 1
FSMC_BTR1_DATAST_2 EQU 0x00000400 ; Bit 2
FSMC_BTR1_DATAST_3 EQU 0x00000800 ; Bit 3
FSMC_BTR1_BUSTURN EQU 0x000F0000 ; BUSTURN[3:0] bits (Bus turnaround phase duration)
FSMC_BTR1_BUSTURN_0 EQU 0x00010000 ; Bit 0
FSMC_BTR1_BUSTURN_1 EQU 0x00020000 ; Bit 1
FSMC_BTR1_BUSTURN_2 EQU 0x00040000 ; Bit 2
FSMC_BTR1_BUSTURN_3 EQU 0x00080000 ; Bit 3
FSMC_BTR1_CLKDIV EQU 0x00F00000 ; CLKDIV[3:0] bits (Clock divide ratio)
FSMC_BTR1_CLKDIV_0 EQU 0x00100000 ; Bit 0
FSMC_BTR1_CLKDIV_1 EQU 0x00200000 ; Bit 1
FSMC_BTR1_CLKDIV_2 EQU 0x00400000 ; Bit 2
FSMC_BTR1_CLKDIV_3 EQU 0x00800000 ; Bit 3
FSMC_BTR1_DATLAT EQU 0x0F000000 ; DATLA[3:0] bits (Data latency)
FSMC_BTR1_DATLAT_0 EQU 0x01000000 ; Bit 0
FSMC_BTR1_DATLAT_1 EQU 0x02000000 ; Bit 1
FSMC_BTR1_DATLAT_2 EQU 0x04000000 ; Bit 2
FSMC_BTR1_DATLAT_3 EQU 0x08000000 ; Bit 3
FSMC_BTR1_ACCMOD EQU 0x30000000 ; ACCMOD[1:0] bits (Access mode)
FSMC_BTR1_ACCMOD_0 EQU 0x10000000 ; Bit 0
FSMC_BTR1_ACCMOD_1 EQU 0x20000000 ; Bit 1
;***************** Bit definition for FSMC_BTR2 register ******************
FSMC_BTR2_ADDSET EQU 0x0000000F ; ADDSET[3:0] bits (Address setup phase duration)
FSMC_BTR2_ADDSET_0 EQU 0x00000001 ; Bit 0
FSMC_BTR2_ADDSET_1 EQU 0x00000002 ; Bit 1
FSMC_BTR2_ADDSET_2 EQU 0x00000004 ; Bit 2
FSMC_BTR2_ADDSET_3 EQU 0x00000008 ; Bit 3
FSMC_BTR2_ADDHLD EQU 0x000000F0 ; ADDHLD[3:0] bits (Address-hold phase duration)
FSMC_BTR2_ADDHLD_0 EQU 0x00000010 ; Bit 0
FSMC_BTR2_ADDHLD_1 EQU 0x00000020 ; Bit 1
FSMC_BTR2_ADDHLD_2 EQU 0x00000040 ; Bit 2
FSMC_BTR2_ADDHLD_3 EQU 0x00000080 ; Bit 3
FSMC_BTR2_DATAST EQU 0x0000FF00 ; DATAST [3:0] bits (Data-phase duration)
FSMC_BTR2_DATAST_0 EQU 0x00000100 ; Bit 0
FSMC_BTR2_DATAST_1 EQU 0x00000200 ; Bit 1
FSMC_BTR2_DATAST_2 EQU 0x00000400 ; Bit 2
FSMC_BTR2_DATAST_3 EQU 0x00000800 ; Bit 3
FSMC_BTR2_BUSTURN EQU 0x000F0000 ; BUSTURN[3:0] bits (Bus turnaround phase duration)
FSMC_BTR2_BUSTURN_0 EQU 0x00010000 ; Bit 0
FSMC_BTR2_BUSTURN_1 EQU 0x00020000 ; Bit 1
FSMC_BTR2_BUSTURN_2 EQU 0x00040000 ; Bit 2
FSMC_BTR2_BUSTURN_3 EQU 0x00080000 ; Bit 3
FSMC_BTR2_CLKDIV EQU 0x00F00000 ; CLKDIV[3:0] bits (Clock divide ratio)
FSMC_BTR2_CLKDIV_0 EQU 0x00100000 ; Bit 0
FSMC_BTR2_CLKDIV_1 EQU 0x00200000 ; Bit 1
FSMC_BTR2_CLKDIV_2 EQU 0x00400000 ; Bit 2
FSMC_BTR2_CLKDIV_3 EQU 0x00800000 ; Bit 3
FSMC_BTR2_DATLAT EQU 0x0F000000 ; DATLA[3:0] bits (Data latency)
FSMC_BTR2_DATLAT_0 EQU 0x01000000 ; Bit 0
FSMC_BTR2_DATLAT_1 EQU 0x02000000 ; Bit 1
FSMC_BTR2_DATLAT_2 EQU 0x04000000 ; Bit 2
FSMC_BTR2_DATLAT_3 EQU 0x08000000 ; Bit 3
FSMC_BTR2_ACCMOD EQU 0x30000000 ; ACCMOD[1:0] bits (Access mode)
FSMC_BTR2_ACCMOD_0 EQU 0x10000000 ; Bit 0
FSMC_BTR2_ACCMOD_1 EQU 0x20000000 ; Bit 1
;****************** Bit definition for FSMC_BTR3 register ******************
FSMC_BTR3_ADDSET EQU 0x0000000F ; ADDSET[3:0] bits (Address setup phase duration)
FSMC_BTR3_ADDSET_0 EQU 0x00000001 ; Bit 0
FSMC_BTR3_ADDSET_1 EQU 0x00000002 ; Bit 1
FSMC_BTR3_ADDSET_2 EQU 0x00000004 ; Bit 2
FSMC_BTR3_ADDSET_3 EQU 0x00000008 ; Bit 3
FSMC_BTR3_ADDHLD EQU 0x000000F0 ; ADDHLD[3:0] bits (Address-hold phase duration)
FSMC_BTR3_ADDHLD_0 EQU 0x00000010 ; Bit 0
FSMC_BTR3_ADDHLD_1 EQU 0x00000020 ; Bit 1
FSMC_BTR3_ADDHLD_2 EQU 0x00000040 ; Bit 2
FSMC_BTR3_ADDHLD_3 EQU 0x00000080 ; Bit 3
FSMC_BTR3_DATAST EQU 0x0000FF00 ; DATAST [3:0] bits (Data-phase duration)
FSMC_BTR3_DATAST_0 EQU 0x00000100 ; Bit 0
FSMC_BTR3_DATAST_1 EQU 0x00000200 ; Bit 1
FSMC_BTR3_DATAST_2 EQU 0x00000400 ; Bit 2
FSMC_BTR3_DATAST_3 EQU 0x00000800 ; Bit 3
FSMC_BTR3_BUSTURN EQU 0x000F0000 ; BUSTURN[3:0] bits (Bus turnaround phase duration)
FSMC_BTR3_BUSTURN_0 EQU 0x00010000 ; Bit 0
FSMC_BTR3_BUSTURN_1 EQU 0x00020000 ; Bit 1
FSMC_BTR3_BUSTURN_2 EQU 0x00040000 ; Bit 2
FSMC_BTR3_BUSTURN_3 EQU 0x00080000 ; Bit 3
FSMC_BTR3_CLKDIV EQU 0x00F00000 ; CLKDIV[3:0] bits (Clock divide ratio)
FSMC_BTR3_CLKDIV_0 EQU 0x00100000 ; Bit 0
FSMC_BTR3_CLKDIV_1 EQU 0x00200000 ; Bit 1
FSMC_BTR3_CLKDIV_2 EQU 0x00400000 ; Bit 2
FSMC_BTR3_CLKDIV_3 EQU 0x00800000 ; Bit 3
FSMC_BTR3_DATLAT EQU 0x0F000000 ; DATLA[3:0] bits (Data latency)
FSMC_BTR3_DATLAT_0 EQU 0x01000000 ; Bit 0
FSMC_BTR3_DATLAT_1 EQU 0x02000000 ; Bit 1
FSMC_BTR3_DATLAT_2 EQU 0x04000000 ; Bit 2
FSMC_BTR3_DATLAT_3 EQU 0x08000000 ; Bit 3
FSMC_BTR3_ACCMOD EQU 0x30000000 ; ACCMOD[1:0] bits (Access mode)
FSMC_BTR3_ACCMOD_0 EQU 0x10000000 ; Bit 0
FSMC_BTR3_ACCMOD_1 EQU 0x20000000 ; Bit 1
;***************** Bit definition for FSMC_BTR4 register ******************
FSMC_BTR4_ADDSET EQU 0x0000000F ; ADDSET[3:0] bits (Address setup phase duration)
FSMC_BTR4_ADDSET_0 EQU 0x00000001 ; Bit 0
FSMC_BTR4_ADDSET_1 EQU 0x00000002 ; Bit 1
FSMC_BTR4_ADDSET_2 EQU 0x00000004 ; Bit 2
FSMC_BTR4_ADDSET_3 EQU 0x00000008 ; Bit 3
FSMC_BTR4_ADDHLD EQU 0x000000F0 ; ADDHLD[3:0] bits (Address-hold phase duration)
FSMC_BTR4_ADDHLD_0 EQU 0x00000010 ; Bit 0
FSMC_BTR4_ADDHLD_1 EQU 0x00000020 ; Bit 1
FSMC_BTR4_ADDHLD_2 EQU 0x00000040 ; Bit 2
FSMC_BTR4_ADDHLD_3 EQU 0x00000080 ; Bit 3
FSMC_BTR4_DATAST EQU 0x0000FF00 ; DATAST [3:0] bits (Data-phase duration)
FSMC_BTR4_DATAST_0 EQU 0x00000100 ; Bit 0
FSMC_BTR4_DATAST_1 EQU 0x00000200 ; Bit 1
FSMC_BTR4_DATAST_2 EQU 0x00000400 ; Bit 2
FSMC_BTR4_DATAST_3 EQU 0x00000800 ; Bit 3
FSMC_BTR4_BUSTURN EQU 0x000F0000 ; BUSTURN[3:0] bits (Bus turnaround phase duration)
FSMC_BTR4_BUSTURN_0 EQU 0x00010000 ; Bit 0
FSMC_BTR4_BUSTURN_1 EQU 0x00020000 ; Bit 1
FSMC_BTR4_BUSTURN_2 EQU 0x00040000 ; Bit 2
FSMC_BTR4_BUSTURN_3 EQU 0x00080000 ; Bit 3
FSMC_BTR4_CLKDIV EQU 0x00F00000 ; CLKDIV[3:0] bits (Clock divide ratio)
FSMC_BTR4_CLKDIV_0 EQU 0x00100000 ; Bit 0
FSMC_BTR4_CLKDIV_1 EQU 0x00200000 ; Bit 1
FSMC_BTR4_CLKDIV_2 EQU 0x00400000 ; Bit 2
FSMC_BTR4_CLKDIV_3 EQU 0x00800000 ; Bit 3
FSMC_BTR4_DATLAT EQU 0x0F000000 ; DATLA[3:0] bits (Data latency)
FSMC_BTR4_DATLAT_0 EQU 0x01000000 ; Bit 0
FSMC_BTR4_DATLAT_1 EQU 0x02000000 ; Bit 1
FSMC_BTR4_DATLAT_2 EQU 0x04000000 ; Bit 2
FSMC_BTR4_DATLAT_3 EQU 0x08000000 ; Bit 3
FSMC_BTR4_ACCMOD EQU 0x30000000 ; ACCMOD[1:0] bits (Access mode)
FSMC_BTR4_ACCMOD_0 EQU 0x10000000 ; Bit 0
FSMC_BTR4_ACCMOD_1 EQU 0x20000000 ; Bit 1
;***************** Bit definition for FSMC_BWTR1 register *****************
FSMC_BWTR1_ADDSET EQU 0x0000000F ; ADDSET[3:0] bits (Address setup phase duration)
FSMC_BWTR1_ADDSET_0 EQU 0x00000001 ; Bit 0
FSMC_BWTR1_ADDSET_1 EQU 0x00000002 ; Bit 1
FSMC_BWTR1_ADDSET_2 EQU 0x00000004 ; Bit 2
FSMC_BWTR1_ADDSET_3 EQU 0x00000008 ; Bit 3
FSMC_BWTR1_ADDHLD EQU 0x000000F0 ; ADDHLD[3:0] bits (Address-hold phase duration)
FSMC_BWTR1_ADDHLD_0 EQU 0x00000010 ; Bit 0
FSMC_BWTR1_ADDHLD_1 EQU 0x00000020 ; Bit 1
FSMC_BWTR1_ADDHLD_2 EQU 0x00000040 ; Bit 2
FSMC_BWTR1_ADDHLD_3 EQU 0x00000080 ; Bit 3
FSMC_BWTR1_DATAST EQU 0x0000FF00 ; DATAST [3:0] bits (Data-phase duration)
FSMC_BWTR1_DATAST_0 EQU 0x00000100 ; Bit 0
FSMC_BWTR1_DATAST_1 EQU 0x00000200 ; Bit 1
FSMC_BWTR1_DATAST_2 EQU 0x00000400 ; Bit 2
FSMC_BWTR1_DATAST_3 EQU 0x00000800 ; Bit 3
FSMC_BWTR1_CLKDIV EQU 0x00F00000 ; CLKDIV[3:0] bits (Clock divide ratio)
FSMC_BWTR1_CLKDIV_0 EQU 0x00100000 ; Bit 0
FSMC_BWTR1_CLKDIV_1 EQU 0x00200000 ; Bit 1
FSMC_BWTR1_CLKDIV_2 EQU 0x00400000 ; Bit 2
FSMC_BWTR1_CLKDIV_3 EQU 0x00800000 ; Bit 3
FSMC_BWTR1_DATLAT EQU 0x0F000000 ; DATLA[3:0] bits (Data latency)
FSMC_BWTR1_DATLAT_0 EQU 0x01000000 ; Bit 0
FSMC_BWTR1_DATLAT_1 EQU 0x02000000 ; Bit 1
FSMC_BWTR1_DATLAT_2 EQU 0x04000000 ; Bit 2
FSMC_BWTR1_DATLAT_3 EQU 0x08000000 ; Bit 3
FSMC_BWTR1_ACCMOD EQU 0x30000000 ; ACCMOD[1:0] bits (Access mode)
FSMC_BWTR1_ACCMOD_0 EQU 0x10000000 ; Bit 0
FSMC_BWTR1_ACCMOD_1 EQU 0x20000000 ; Bit 1
;***************** Bit definition for FSMC_BWTR2 register *****************
FSMC_BWTR2_ADDSET EQU 0x0000000F ; ADDSET[3:0] bits (Address setup phase duration)
FSMC_BWTR2_ADDSET_0 EQU 0x00000001 ; Bit 0
FSMC_BWTR2_ADDSET_1 EQU 0x00000002 ; Bit 1
FSMC_BWTR2_ADDSET_2 EQU 0x00000004 ; Bit 2
FSMC_BWTR2_ADDSET_3 EQU 0x00000008 ; Bit 3
FSMC_BWTR2_ADDHLD EQU 0x000000F0 ; ADDHLD[3:0] bits (Address-hold phase duration)
FSMC_BWTR2_ADDHLD_0 EQU 0x00000010 ; Bit 0
FSMC_BWTR2_ADDHLD_1 EQU 0x00000020 ; Bit 1
FSMC_BWTR2_ADDHLD_2 EQU 0x00000040 ; Bit 2
FSMC_BWTR2_ADDHLD_3 EQU 0x00000080 ; Bit 3
FSMC_BWTR2_DATAST EQU 0x0000FF00 ; DATAST [3:0] bits (Data-phase duration)
FSMC_BWTR2_DATAST_0 EQU 0x00000100 ; Bit 0
FSMC_BWTR2_DATAST_1 EQU 0x00000200 ; Bit 1
FSMC_BWTR2_DATAST_2 EQU 0x00000400 ; Bit 2
FSMC_BWTR2_DATAST_3 EQU 0x00000800 ; Bit 3
FSMC_BWTR2_CLKDIV EQU 0x00F00000 ; CLKDIV[3:0] bits (Clock divide ratio)
FSMC_BWTR2_CLKDIV_0 EQU 0x00100000 ; Bit 0
FSMC_BWTR2_CLKDIV_1 EQU 0x00200000 ; Bit 1
FSMC_BWTR2_CLKDIV_2 EQU 0x00400000 ; Bit 2
FSMC_BWTR2_CLKDIV_3 EQU 0x00800000 ; Bit 3
FSMC_BWTR2_DATLAT EQU 0x0F000000 ; DATLA[3:0] bits (Data latency)
FSMC_BWTR2_DATLAT_0 EQU 0x01000000 ; Bit 0
FSMC_BWTR2_DATLAT_1 EQU 0x02000000 ; Bit 1
FSMC_BWTR2_DATLAT_2 EQU 0x04000000 ; Bit 2
FSMC_BWTR2_DATLAT_3 EQU 0x08000000 ; Bit 3
FSMC_BWTR2_ACCMOD EQU 0x30000000 ; ACCMOD[1:0] bits (Access mode)
FSMC_BWTR2_ACCMOD_0 EQU 0x10000000 ; Bit 0
FSMC_BWTR2_ACCMOD_1 EQU 0x20000000 ; Bit 1
;***************** Bit definition for FSMC_BWTR3 register *****************
FSMC_BWTR3_ADDSET EQU 0x0000000F ; ADDSET[3:0] bits (Address setup phase duration)
FSMC_BWTR3_ADDSET_0 EQU 0x00000001 ; Bit 0
FSMC_BWTR3_ADDSET_1 EQU 0x00000002 ; Bit 1
FSMC_BWTR3_ADDSET_2 EQU 0x00000004 ; Bit 2
FSMC_BWTR3_ADDSET_3 EQU 0x00000008 ; Bit 3
FSMC_BWTR3_ADDHLD EQU 0x000000F0 ; ADDHLD[3:0] bits (Address-hold phase duration)
FSMC_BWTR3_ADDHLD_0 EQU 0x00000010 ; Bit 0
FSMC_BWTR3_ADDHLD_1 EQU 0x00000020 ; Bit 1
FSMC_BWTR3_ADDHLD_2 EQU 0x00000040 ; Bit 2
FSMC_BWTR3_ADDHLD_3 EQU 0x00000080 ; Bit 3
FSMC_BWTR3_DATAST EQU 0x0000FF00 ; DATAST [3:0] bits (Data-phase duration)
FSMC_BWTR3_DATAST_0 EQU 0x00000100 ; Bit 0
FSMC_BWTR3_DATAST_1 EQU 0x00000200 ; Bit 1
FSMC_BWTR3_DATAST_2 EQU 0x00000400 ; Bit 2
FSMC_BWTR3_DATAST_3 EQU 0x00000800 ; Bit 3
FSMC_BWTR3_CLKDIV EQU 0x00F00000 ; CLKDIV[3:0] bits (Clock divide ratio)
FSMC_BWTR3_CLKDIV_0 EQU 0x00100000 ; Bit 0
FSMC_BWTR3_CLKDIV_1 EQU 0x00200000 ; Bit 1
FSMC_BWTR3_CLKDIV_2 EQU 0x00400000 ; Bit 2
FSMC_BWTR3_CLKDIV_3 EQU 0x00800000 ; Bit 3
FSMC_BWTR3_DATLAT EQU 0x0F000000 ; DATLA[3:0] bits (Data latency)
FSMC_BWTR3_DATLAT_0 EQU 0x01000000 ; Bit 0
FSMC_BWTR3_DATLAT_1 EQU 0x02000000 ; Bit 1
FSMC_BWTR3_DATLAT_2 EQU 0x04000000 ; Bit 2
FSMC_BWTR3_DATLAT_3 EQU 0x08000000 ; Bit 3
FSMC_BWTR3_ACCMOD EQU 0x30000000 ; ACCMOD[1:0] bits (Access mode)
FSMC_BWTR3_ACCMOD_0 EQU 0x10000000 ; Bit 0
FSMC_BWTR3_ACCMOD_1 EQU 0x20000000 ; Bit 1
;***************** Bit definition for FSMC_BWTR4 register *****************
FSMC_BWTR4_ADDSET EQU 0x0000000F ; ADDSET[3:0] bits (Address setup phase duration)
FSMC_BWTR4_ADDSET_0 EQU 0x00000001 ; Bit 0
FSMC_BWTR4_ADDSET_1 EQU 0x00000002 ; Bit 1
FSMC_BWTR4_ADDSET_2 EQU 0x00000004 ; Bit 2
FSMC_BWTR4_ADDSET_3 EQU 0x00000008 ; Bit 3
FSMC_BWTR4_ADDHLD EQU 0x000000F0 ; ADDHLD[3:0] bits (Address-hold phase duration)
FSMC_BWTR4_ADDHLD_0 EQU 0x00000010 ; Bit 0
FSMC_BWTR4_ADDHLD_1 EQU 0x00000020 ; Bit 1
FSMC_BWTR4_ADDHLD_2 EQU 0x00000040 ; Bit 2
FSMC_BWTR4_ADDHLD_3 EQU 0x00000080 ; Bit 3
FSMC_BWTR4_DATAST EQU 0x0000FF00 ; DATAST [3:0] bits (Data-phase duration)
FSMC_BWTR4_DATAST_0 EQU 0x00000100 ; Bit 0
FSMC_BWTR4_DATAST_1 EQU 0x00000200 ; Bit 1
FSMC_BWTR4_DATAST_2 EQU 0x00000400 ; Bit 2
FSMC_BWTR4_DATAST_3 EQU 0x00000800 ; Bit 3
FSMC_BWTR4_CLKDIV EQU 0x00F00000 ; CLKDIV[3:0] bits (Clock divide ratio)
FSMC_BWTR4_CLKDIV_0 EQU 0x00100000 ; Bit 0
FSMC_BWTR4_CLKDIV_1 EQU 0x00200000 ; Bit 1
FSMC_BWTR4_CLKDIV_2 EQU 0x00400000 ; Bit 2
FSMC_BWTR4_CLKDIV_3 EQU 0x00800000 ; Bit 3
FSMC_BWTR4_DATLAT EQU 0x0F000000 ; DATLA[3:0] bits (Data latency)
FSMC_BWTR4_DATLAT_0 EQU 0x01000000 ; Bit 0
FSMC_BWTR4_DATLAT_1 EQU 0x02000000 ; Bit 1
FSMC_BWTR4_DATLAT_2 EQU 0x04000000 ; Bit 2
FSMC_BWTR4_DATLAT_3 EQU 0x08000000 ; Bit 3
FSMC_BWTR4_ACCMOD EQU 0x30000000 ; ACCMOD[1:0] bits (Access mode)
FSMC_BWTR4_ACCMOD_0 EQU 0x10000000 ; Bit 0
FSMC_BWTR4_ACCMOD_1 EQU 0x20000000 ; Bit 1
END

@ -0,0 +1,240 @@
;********************************************************************************
; SOUBOR : INI_BITS_GPIO.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro GPIO (I/O brany)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; General Purpose IOs (GPIO)
;
;****************************************************************************
; Short pin masks. Valid for OTYPER, IDR and ODR.
GPIO0 EQU 0x00000001
GPIO1 EQU 0x00000002
GPIO2 EQU 0x00000004
GPIO3 EQU 0x00000008
GPIO4 EQU 0x00000010
GPIO5 EQU 0x00000020
GPIO6 EQU 0x00000040
GPIO7 EQU 0x00000080
GPIO8 EQU 0x00000100
GPIO9 EQU 0x00000200
GPIO10 EQU 0x00000400
GPIO11 EQU 0x00000800
GPIO12 EQU 0x00001000
GPIO13 EQU 0x00002000
GPIO14 EQU 0x00004000
GPIO15 EQU 0x00008000
; OTYPER pattern masks - use as (GPIO_OTYPER_6 & GPIO_OTYPER_OD)
GPIO_OTYPER_PP EQU 0x00000000
GPIO_OTYPER_OD EQU 0xFFFFFFFF
; For completenes, aliases also for OTYPER, ODR and IDR
GPIO_OTYPER_0 EQU 0x00000001
GPIO_OTYPER_1 EQU 0x00000002
GPIO_OTYPER_2 EQU 0x00000004
GPIO_OTYPER_3 EQU 0x00000008
GPIO_OTYPER_4 EQU 0x00000010
GPIO_OTYPER_5 EQU 0x00000020
GPIO_OTYPER_6 EQU 0x00000040
GPIO_OTYPER_7 EQU 0x00000080
GPIO_OTYPER_8 EQU 0x00000100
GPIO_OTYPER_9 EQU 0x00000200
GPIO_OTYPER_10 EQU 0x00000400
GPIO_OTYPER_11 EQU 0x00000800
GPIO_OTYPER_12 EQU 0x00001000
GPIO_OTYPER_13 EQU 0x00002000
GPIO_OTYPER_14 EQU 0x00004000
GPIO_OTYPER_15 EQU 0x00008000
GPIO_ODR_0 EQU 0x00000001
GPIO_ODR_1 EQU 0x00000002
GPIO_ODR_2 EQU 0x00000004
GPIO_ODR_3 EQU 0x00000008
GPIO_ODR_4 EQU 0x00000010
GPIO_ODR_5 EQU 0x00000020
GPIO_ODR_6 EQU 0x00000040
GPIO_ODR_7 EQU 0x00000080
GPIO_ODR_8 EQU 0x00000100
GPIO_ODR_9 EQU 0x00000200
GPIO_ODR_10 EQU 0x00000400
GPIO_ODR_11 EQU 0x00000800
GPIO_ODR_12 EQU 0x00001000
GPIO_ODR_13 EQU 0x00002000
GPIO_ODR_14 EQU 0x00004000
GPIO_ODR_15 EQU 0x00008000
GPIO_IDR_0 EQU 0x00000001
GPIO_IDR_1 EQU 0x00000002
GPIO_IDR_2 EQU 0x00000004
GPIO_IDR_3 EQU 0x00000008
GPIO_IDR_4 EQU 0x00000010
GPIO_IDR_5 EQU 0x00000020
GPIO_IDR_6 EQU 0x00000040
GPIO_IDR_7 EQU 0x00000080
GPIO_IDR_8 EQU 0x00000100
GPIO_IDR_9 EQU 0x00000200
GPIO_IDR_10 EQU 0x00000400
GPIO_IDR_11 EQU 0x00000800
GPIO_IDR_12 EQU 0x00001000
GPIO_IDR_13 EQU 0x00002000
GPIO_IDR_14 EQU 0x00004000
GPIO_IDR_15 EQU 0x00008000
;****************** Bit definition for GPIO_MODER register ****************
; pattern masks. Use as: (GPIO_MODER_0 & GPIO_MODER_OUTPUT)
GPIO_MODER_INPUT EQU 0x00000000
GPIO_MODER_OUTPUT EQU 0x55555555
GPIO_MODER_AF EQU 0xAAAAAAAA
GPIO_MODER_ANALOG EQU 0xFFFFFFFF
GPIO_MODER_0 EQU 0x00000003
GPIO_MODER_1 EQU 0x0000000C
GPIO_MODER_2 EQU 0x00000030
GPIO_MODER_3 EQU 0x000000C0
GPIO_MODER_4 EQU 0x00000300
GPIO_MODER_5 EQU 0x00000C00
GPIO_MODER_6 EQU 0x00003000
GPIO_MODER_7 EQU 0x0000C000
GPIO_MODER_8 EQU 0x00030000
GPIO_MODER_9 EQU 0x000C0000
GPIO_MODER_10 EQU 0x00300000
GPIO_MODER_11 EQU 0x00C00000
GPIO_MODER_12 EQU 0x03000000
GPIO_MODER_13 EQU 0x0C000000
GPIO_MODER_14 EQU 0x30000000
GPIO_MODER_15 EQU 0xC0000000
;****************** Bit definition for GPIO_OSPEEDR register **************
; pattern masks. Use as: (GPIO_OSPEEDR_2 & GPIO_OSPEEDR_LOW)
GPIO_OSPEEDR_LOW EQU 0x00000000
GPIO_OSPEEDR_MEDIUM EQU 0x55555555
GPIO_OSPEEDR_HIGH EQU 0xFFFFFFFF
GPIO_OSPEEDR_0 EQU (0x00000003)
GPIO_OSPEEDR_1 EQU (0x0000000C)
GPIO_OSPEEDR_2 EQU (0x00000030)
GPIO_OSPEEDR_3 EQU (0x000000C0)
GPIO_OSPEEDR_4 EQU (0x00000300)
GPIO_OSPEEDR_5 EQU (0x00000C00)
GPIO_OSPEEDR_6 EQU (0x00003000)
GPIO_OSPEEDR_7 EQU (0x0000C000)
GPIO_OSPEEDR_8 EQU (0x00030000)
GPIO_OSPEEDR_9 EQU (0x000C0000)
GPIO_OSPEEDR_10 EQU (0x00300000)
GPIO_OSPEEDR_11 EQU (0x00C00000)
GPIO_OSPEEDR_12 EQU (0x03000000)
GPIO_OSPEEDR_13 EQU (0x0C000000)
GPIO_OSPEEDR_14 EQU (0x30000000)
GPIO_OSPEEDR_15 EQU (0xC0000000)
;****************** Bit definition for GPIO_PUPDR register ****************
; pattern masks. Use as: (GPIO_PUPDR_6 & GPIO_PUPDR_UP)
GPIO_PUPDR_NONE EQU 0x00000000
GPIO_PUPDR_UP EQU 0x55555555
GPIO_PUPDR_DOWN EQU 0xAAAAAAAA
GPIO_PUPDR_0 EQU (0x00000003)
GPIO_PUPDR_1 EQU (0x0000000C)
GPIO_PUPDR_2 EQU (0x00000030)
GPIO_PUPDR_3 EQU (0x000000C0)
GPIO_PUPDR_4 EQU (0x00000300)
GPIO_PUPDR_5 EQU (0x00000C00)
GPIO_PUPDR_6 EQU (0x00003000)
GPIO_PUPDR_7 EQU (0x0000C000)
GPIO_PUPDR_8 EQU (0x00030000)
GPIO_PUPDR_9 EQU (0x000C0000)
GPIO_PUPDR_10 EQU (0x00300000)
GPIO_PUPDR_11 EQU (0x00C00000)
GPIO_PUPDR_12 EQU (0x03000000)
GPIO_PUPDR_13 EQU (0x0C000000)
GPIO_PUPDR_14 EQU (0x30000000)
GPIO_PUPDR_15 EQU (0xC0000000)
;****************** Bit definition for GPIO_BSRR register *****************
GPIO_BSRR_BS_0 EQU (0x00000001)
GPIO_BSRR_BS_1 EQU (0x00000002)
GPIO_BSRR_BS_2 EQU (0x00000004)
GPIO_BSRR_BS_3 EQU (0x00000008)
GPIO_BSRR_BS_4 EQU (0x00000010)
GPIO_BSRR_BS_5 EQU (0x00000020)
GPIO_BSRR_BS_6 EQU (0x00000040)
GPIO_BSRR_BS_7 EQU (0x00000080)
GPIO_BSRR_BS_8 EQU (0x00000100)
GPIO_BSRR_BS_9 EQU (0x00000200)
GPIO_BSRR_BS_10 EQU (0x00000400)
GPIO_BSRR_BS_11 EQU (0x00000800)
GPIO_BSRR_BS_12 EQU (0x00001000)
GPIO_BSRR_BS_13 EQU (0x00002000)
GPIO_BSRR_BS_14 EQU (0x00004000)
GPIO_BSRR_BS_15 EQU (0x00008000)
GPIO_BSRR_BR_0 EQU (0x00010000)
GPIO_BSRR_BR_1 EQU (0x00020000)
GPIO_BSRR_BR_2 EQU (0x00040000)
GPIO_BSRR_BR_3 EQU (0x00080000)
GPIO_BSRR_BR_4 EQU (0x00100000)
GPIO_BSRR_BR_5 EQU (0x00200000)
GPIO_BSRR_BR_6 EQU (0x00400000)
GPIO_BSRR_BR_7 EQU (0x00800000)
GPIO_BSRR_BR_8 EQU (0x01000000)
GPIO_BSRR_BR_9 EQU (0x02000000)
GPIO_BSRR_BR_10 EQU (0x04000000)
GPIO_BSRR_BR_11 EQU (0x08000000)
GPIO_BSRR_BR_12 EQU (0x10000000)
GPIO_BSRR_BR_13 EQU (0x20000000)
GPIO_BSRR_BR_14 EQU (0x40000000)
GPIO_BSRR_BR_15 EQU (0x80000000)
;****************** Bit definition for GPIO_LCKR register *****************
GPIO_LCKR_0 EQU (0x00000001)
GPIO_LCKR_1 EQU (0x00000002)
GPIO_LCKR_2 EQU (0x00000004)
GPIO_LCKR_3 EQU (0x00000008)
GPIO_LCKR_4 EQU (0x00000010)
GPIO_LCKR_5 EQU (0x00000020)
GPIO_LCKR_6 EQU (0x00000040)
GPIO_LCKR_7 EQU (0x00000080)
GPIO_LCKR_8 EQU (0x00000100)
GPIO_LCKR_9 EQU (0x00000200)
GPIO_LCKR_10 EQU (0x00000400)
GPIO_LCKR_11 EQU (0x00000800)
GPIO_LCKR_12 EQU (0x00001000)
GPIO_LCKR_13 EQU (0x00002000)
GPIO_LCKR_14 EQU (0x00004000)
GPIO_LCKR_15 EQU (0x00008000)
GPIO_LCKR_K EQU (0x00010000)
;****************** Bit definition for GPIO_AFRL register *****************
GPIO_AFRL_0 EQU (0x0000000F)
GPIO_AFRL_1 EQU (0x000000F0)
GPIO_AFRL_2 EQU (0x00000F00)
GPIO_AFRL_3 EQU (0x0000F000)
GPIO_AFRL_4 EQU (0x000F0000)
GPIO_AFRL_5 EQU (0x00F00000)
GPIO_AFRL_6 EQU (0x0F000000)
GPIO_AFRL_7 EQU (0xF0000000)
;****************** Bit definition for GPIO_AFRH register *****************
GPIO_AFRH_8 EQU (0x0000000F)
GPIO_AFRH_9 EQU (0x000000F0)
GPIO_AFRH_10 EQU (0x00000F00)
GPIO_AFRH_11 EQU (0x0000F000)
GPIO_AFRH_12 EQU (0x000F0000)
GPIO_AFRH_13 EQU (0x00F00000)
GPIO_AFRH_14 EQU (0x0F000000)
GPIO_AFRH_15 EQU (0xF0000000)
END

@ -0,0 +1,106 @@
;********************************************************************************
; SOUBOR : INI_BITS_I2C.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro I2C
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Inter-integrated Circuit Interface (I2C)
;
;****************************************************************************
;****************** Bit definition for I2C_CR1 register *******************
I2C_CR1_PE EQU 0x0001 ; Peripheral Enable
I2C_CR1_SMBUS EQU 0x0002 ; SMBus Mode
I2C_CR1_SMBTYPE EQU 0x0008 ; SMBus Type
I2C_CR1_ENARP EQU 0x0010 ; ARP Enable
I2C_CR1_ENPEC EQU 0x0020 ; PEC Enable
I2C_CR1_ENGC EQU 0x0040 ; General Call Enable
I2C_CR1_NOSTRETCH EQU 0x0080 ; Clock Stretching Disable (Slave mode)
I2C_CR1_START EQU 0x0100 ; Start Generation
I2C_CR1_STOP EQU 0x0200 ; Stop Generation
I2C_CR1_ACK EQU 0x0400 ; Acknowledge Enable
I2C_CR1_POS EQU 0x0800 ; Acknowledge/PEC Position (for data reception)
I2C_CR1_PEC EQU 0x1000 ; Packet Error Checking
I2C_CR1_ALERT EQU 0x2000 ; SMBus Alert
I2C_CR1_SWRST EQU 0x8000 ; Software Reset
;****************** Bit definition for I2C_CR2 register *******************
I2C_CR2_FREQ EQU 0x003F ; FREQ[5:0] bits (Peripheral Clock Frequency)
I2C_CR2_FREQ_0 EQU 0x0001 ; Bit 0
I2C_CR2_FREQ_1 EQU 0x0002 ; Bit 1
I2C_CR2_FREQ_2 EQU 0x0004 ; Bit 2
I2C_CR2_FREQ_3 EQU 0x0008 ; Bit 3
I2C_CR2_FREQ_4 EQU 0x0010 ; Bit 4
I2C_CR2_FREQ_5 EQU 0x0020 ; Bit 5
I2C_CR2_ITERREN EQU 0x0100 ; Error Interrupt Enable
I2C_CR2_ITEVTEN EQU 0x0200 ; Event Interrupt Enable
I2C_CR2_ITBUFEN EQU 0x0400 ; Buffer Interrupt Enable
I2C_CR2_DMAEN EQU 0x0800 ; DMA Requests Enable
I2C_CR2_LAST EQU 0x1000 ; DMA Last Transfer
;****************** Bit definition for I2C_OAR1 register ******************
I2C_OAR1_ADD1_7 EQU 0x00FE ; Interface Address
I2C_OAR1_ADD8_9 EQU 0x0300 ; Interface Address
I2C_OAR1_ADD0 EQU 0x0001 ; Bit 0
I2C_OAR1_ADD1 EQU 0x0002 ; Bit 1
I2C_OAR1_ADD2 EQU 0x0004 ; Bit 2
I2C_OAR1_ADD3 EQU 0x0008 ; Bit 3
I2C_OAR1_ADD4 EQU 0x0010 ; Bit 4
I2C_OAR1_ADD5 EQU 0x0020 ; Bit 5
I2C_OAR1_ADD6 EQU 0x0040 ; Bit 6
I2C_OAR1_ADD7 EQU 0x0080 ; Bit 7
I2C_OAR1_ADD8 EQU 0x0100 ; Bit 8
I2C_OAR1_ADD9 EQU 0x0200 ; Bit 9
I2C_OAR1_ADDMODE EQU 0x8000 ; Addressing Mode (Slave mode)
;****************** Bit definition for I2C_OAR2 register ******************
I2C_OAR2_ENDUAL EQU 0x01 ; Dual addressing mode enable
I2C_OAR2_ADD2 EQU 0xFE ; Interface address
;******************* Bit definition for I2C_DR register *******************
I2C_DR_DR EQU 0xFF ; 8-bit Data Register
;****************** Bit definition for I2C_SR1 register *******************
I2C_SR1_SB EQU 0x0001 ; Start Bit (Master mode)
I2C_SR1_ADDR EQU 0x0002 ; Address sent (master mode)/matched (slave mode)
I2C_SR1_BTF EQU 0x0004 ; Byte Transfer Finished
I2C_SR1_ADD10 EQU 0x0008 ; 10-bit header sent (Master mode)
I2C_SR1_STOPF EQU 0x0010 ; Stop detection (Slave mode)
I2C_SR1_RXNE EQU 0x0040 ; Data Register not Empty (receivers)
I2C_SR1_TXE EQU 0x0080 ; Data Register Empty (transmitters)
I2C_SR1_BERR EQU 0x0100 ; Bus Error
I2C_SR1_ARLO EQU 0x0200 ; Arbitration Lost (master mode)
I2C_SR1_AF EQU 0x0400 ; Acknowledge Failure
I2C_SR1_OVR EQU 0x0800 ; Overrun/Underrun
I2C_SR1_PECERR EQU 0x1000 ; PEC Error in reception
I2C_SR1_TIMEOUT EQU 0x4000 ; Timeout or Tlow Error
I2C_SR1_SMBALERT EQU 0x8000 ; SMBus Alert
;****************** Bit definition for I2C_SR2 register *******************
I2C_SR2_MSL EQU 0x0001 ; Master/Slave
I2C_SR2_BUSY EQU 0x0002 ; Bus Busy
I2C_SR2_TRA EQU 0x0004 ; Transmitter/Receiver
I2C_SR2_GENCALL EQU 0x0010 ; General Call Address (Slave mode)
I2C_SR2_SMBDEFAULT EQU 0x0020 ; SMBus Device Default Address (Slave mode)
I2C_SR2_SMBHOST EQU 0x0040 ; SMBus Host Header (Slave mode)
I2C_SR2_DUALF EQU 0x0080 ; Dual Flag (Slave mode)
I2C_SR2_PEC EQU 0xFF00 ; Packet Error Checking Register
;****************** Bit definition for I2C_CCR register *******************
I2C_CCR_CCR EQU 0x0FFF ; Clock Control Register in Fast/Standard mode (Master mode)
I2C_CCR_DUTY EQU 0x4000 ; Fast Mode Duty Cycle
I2C_CCR_FS EQU 0x8000 ; I2C Master Mode Selection
;***************** Bit definition for I2C_TRISE register ******************
I2C_TRISE_TRISE EQU 0x3F ; Maximum Rise Time in Fast/Standard mode (Master mode)
END

@ -0,0 +1,33 @@
;********************************************************************************
; SOUBOR : INI_BITS_IWDG.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro IWDG
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Independent WATCHDOG (IWDG)
;
;****************************************************************************
;****************** Bit definition for IWDG_KR register *******************
IWDG_KR_KEY EQU 0xFFFF ; Key value (write only, read 0000h)
;****************** Bit definition for IWDG_PR register *******************
IWDG_PR_PR EQU 0x07 ; PR[2:0] (Prescaler divider)
IWDG_PR_PR_0 EQU 0x01 ; Bit 0
IWDG_PR_PR_1 EQU 0x02 ; Bit 1
IWDG_PR_PR_2 EQU 0x04 ; Bit 2
;****************** Bit definition for IWDG_RLR register ******************
IWDG_RLR_RL EQU 0x0FFF ; Watchdog counter reload value
;****************** Bit definition for IWDG_SR register *******************
IWDG_SR_PVU EQU 0x01 ; Watchdog prescaler value update
IWDG_SR_RVU EQU 0x02 ; Watchdog counter reload value update
END

@ -0,0 +1,79 @@
;********************************************************************************
; SOUBOR : INI_BITS_LCD.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro LCD
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; LCD Controller (LCD)
;
;****************************************************************************
;****************** Bit definition for LCD_CR register ********************
LCD_CR_LCDEN EQU 0x00000001 ; LCD Enable Bit
LCD_CR_VSEL EQU 0x00000002 ; Voltage source selector Bit
LCD_CR_DUTY EQU 0x0000001C ; DUTY[2:0] bits (Duty selector)
LCD_CR_DUTY_0 EQU 0x00000004 ; Duty selector Bit 0
LCD_CR_DUTY_1 EQU 0x00000008 ; Duty selector Bit 1
LCD_CR_DUTY_2 EQU 0x00000010 ; Duty selector Bit 2
LCD_CR_BIAS EQU 0x00000060 ; BIAS[1:0] bits (Bias selector)
LCD_CR_BIAS_0 EQU 0x00000020 ; Bias selector Bit 0
LCD_CR_BIAS_1 EQU 0x00000040 ; Bias selector Bit 1
LCD_CR_MUX_SEG EQU 0x00000080 ; Mux Segment Enable Bit
;****************** Bit definition for LCD_FCR register *******************
LCD_FCR_HD EQU 0x00000001 ; High Drive Enable Bit
LCD_FCR_SOFIE EQU 0x00000002 ; Start of Frame Interrupt Enable Bit
LCD_FCR_UDDIE EQU 0x00000008 ; Update Display Done Interrupt Enable Bit
LCD_FCR_PON EQU 0x00000070 ; PON[2:0] bits (Puls ON Duration)
LCD_FCR_PON_0 EQU 0x00000010 ; Bit 0
LCD_FCR_PON_1 EQU 0x00000020 ; Bit 1
LCD_FCR_PON_2 EQU 0x00000040 ; Bit 2
LCD_FCR_DEAD EQU 0x00000380 ; DEAD[2:0] bits (DEAD Time)
LCD_FCR_DEAD_0 EQU 0x00000080 ; Bit 0
LCD_FCR_DEAD_1 EQU 0x00000100 ; Bit 1
LCD_FCR_DEAD_2 EQU 0x00000200 ; Bit 2
LCD_FCR_CC EQU 0x00001C00 ; CC[2:0] bits (Contrast Control)
LCD_FCR_CC_0 EQU 0x00000400 ; Bit 0
LCD_FCR_CC_1 EQU 0x00000800 ; Bit 1
LCD_FCR_CC_2 EQU 0x00001000 ; Bit 2
LCD_FCR_BLINKF EQU 0x0000E000 ; BLINKF[2:0] bits (Blink Frequency)
LCD_FCR_BLINKF_0 EQU 0x00002000 ; Bit 0
LCD_FCR_BLINKF_1 EQU 0x00004000 ; Bit 1
LCD_FCR_BLINKF_2 EQU 0x00008000 ; Bit 2
LCD_FCR_BLINK EQU 0x00030000 ; BLINK[1:0] bits (Blink Enable)
LCD_FCR_BLINK_0 EQU 0x00010000 ; Bit 0
LCD_FCR_BLINK_1 EQU 0x00020000 ; Bit 1
LCD_FCR_DIV EQU 0x003C0000 ; DIV[3:0] bits (Divider)
LCD_FCR_PS EQU 0x03C00000 ; PS[3:0] bits (Prescaler)
;****************** Bit definition for LCD_SR register ********************
LCD_SR_ENS EQU 0x00000001 ; LCD Enabled Bit
LCD_SR_SOF EQU 0x00000002 ; Start Of Frame Flag Bit
LCD_SR_UDR EQU 0x00000004 ; Update Display Request Bit
LCD_SR_UDD EQU 0x00000008 ; Update Display Done Flag Bit
LCD_SR_RDY EQU 0x00000010 ; Ready Flag Bit
LCD_SR_FCRSR EQU 0x00000020 ; LCD FCR Register Synchronization Flag Bit
;****************** Bit definition for LCD_CLR register *******************
LCD_CLR_SOFC EQU 0x00000002 ; Start Of Frame Flag Clear Bit
LCD_CLR_UDDC EQU 0x00000008 ; Update Display Done Flag Clear Bit
;****************** Bit definition for LCD_RAM register *******************
LCD_RAM_SEGMENT_DATA EQU 0xFFFFFFFF ; Segment Data Bits
END

@ -0,0 +1,240 @@
;********************************************************************************
; SOUBOR : INI_BITS_NVIC.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro NVIC (system preruseni)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Nested Vectored Interrupt Controller (NVIC)
;
;****************************************************************************
;***************** Bit definition for NVIC_ISER register ******************
NVIC_ISER_SETENA EQU 0xFFFFFFFF ; Interrupt set enable bits
NVIC_ISER_SETENA_0 EQU 0x00000001 ; bit 0
NVIC_ISER_SETENA_1 EQU 0x00000002 ; bit 1
NVIC_ISER_SETENA_2 EQU 0x00000004 ; bit 2
NVIC_ISER_SETENA_3 EQU 0x00000008 ; bit 3
NVIC_ISER_SETENA_4 EQU 0x00000010 ; bit 4
NVIC_ISER_SETENA_5 EQU 0x00000020 ; bit 5
NVIC_ISER_SETENA_6 EQU 0x00000040 ; bit 6
NVIC_ISER_SETENA_7 EQU 0x00000080 ; bit 7
NVIC_ISER_SETENA_8 EQU 0x00000100 ; bit 8
NVIC_ISER_SETENA_9 EQU 0x00000200 ; bit 9
NVIC_ISER_SETENA_10 EQU 0x00000400 ; bit 10
NVIC_ISER_SETENA_11 EQU 0x00000800 ; bit 11
NVIC_ISER_SETENA_12 EQU 0x00001000 ; bit 12
NVIC_ISER_SETENA_13 EQU 0x00002000 ; bit 13
NVIC_ISER_SETENA_14 EQU 0x00004000 ; bit 14
NVIC_ISER_SETENA_15 EQU 0x00008000 ; bit 15
NVIC_ISER_SETENA_16 EQU 0x00010000 ; bit 16
NVIC_ISER_SETENA_17 EQU 0x00020000 ; bit 17
NVIC_ISER_SETENA_18 EQU 0x00040000 ; bit 18
NVIC_ISER_SETENA_19 EQU 0x00080000 ; bit 19
NVIC_ISER_SETENA_20 EQU 0x00100000 ; bit 20
NVIC_ISER_SETENA_21 EQU 0x00200000 ; bit 21
NVIC_ISER_SETENA_22 EQU 0x00400000 ; bit 22
NVIC_ISER_SETENA_23 EQU 0x00800000 ; bit 23
NVIC_ISER_SETENA_24 EQU 0x01000000 ; bit 24
NVIC_ISER_SETENA_25 EQU 0x02000000 ; bit 25
NVIC_ISER_SETENA_26 EQU 0x04000000 ; bit 26
NVIC_ISER_SETENA_27 EQU 0x08000000 ; bit 27
NVIC_ISER_SETENA_28 EQU 0x10000000 ; bit 28
NVIC_ISER_SETENA_29 EQU 0x20000000 ; bit 29
NVIC_ISER_SETENA_30 EQU 0x40000000 ; bit 30
NVIC_ISER_SETENA_31 EQU 0x80000000 ; bit 31
;***************** Bit definition for NVIC_ICER register ******************
NVIC_ICER_CLRENA EQU 0xFFFFFFFF ; Interrupt clear-enable bits
NVIC_ICER_CLRENA_0 EQU 0x00000001 ; bit 0
NVIC_ICER_CLRENA_1 EQU 0x00000002 ; bit 1
NVIC_ICER_CLRENA_2 EQU 0x00000004 ; bit 2
NVIC_ICER_CLRENA_3 EQU 0x00000008 ; bit 3
NVIC_ICER_CLRENA_4 EQU 0x00000010 ; bit 4
NVIC_ICER_CLRENA_5 EQU 0x00000020 ; bit 5
NVIC_ICER_CLRENA_6 EQU 0x00000040 ; bit 6
NVIC_ICER_CLRENA_7 EQU 0x00000080 ; bit 7
NVIC_ICER_CLRENA_8 EQU 0x00000100 ; bit 8
NVIC_ICER_CLRENA_9 EQU 0x00000200 ; bit 9
NVIC_ICER_CLRENA_10 EQU 0x00000400 ; bit 10
NVIC_ICER_CLRENA_11 EQU 0x00000800 ; bit 11
NVIC_ICER_CLRENA_12 EQU 0x00001000 ; bit 12
NVIC_ICER_CLRENA_13 EQU 0x00002000 ; bit 13
NVIC_ICER_CLRENA_14 EQU 0x00004000 ; bit 14
NVIC_ICER_CLRENA_15 EQU 0x00008000 ; bit 15
NVIC_ICER_CLRENA_16 EQU 0x00010000 ; bit 16
NVIC_ICER_CLRENA_17 EQU 0x00020000 ; bit 17
NVIC_ICER_CLRENA_18 EQU 0x00040000 ; bit 18
NVIC_ICER_CLRENA_19 EQU 0x00080000 ; bit 19
NVIC_ICER_CLRENA_20 EQU 0x00100000 ; bit 20
NVIC_ICER_CLRENA_21 EQU 0x00200000 ; bit 21
NVIC_ICER_CLRENA_22 EQU 0x00400000 ; bit 22
NVIC_ICER_CLRENA_23 EQU 0x00800000 ; bit 23
NVIC_ICER_CLRENA_24 EQU 0x01000000 ; bit 24
NVIC_ICER_CLRENA_25 EQU 0x02000000 ; bit 25
NVIC_ICER_CLRENA_26 EQU 0x04000000 ; bit 26
NVIC_ICER_CLRENA_27 EQU 0x08000000 ; bit 27
NVIC_ICER_CLRENA_28 EQU 0x10000000 ; bit 28
NVIC_ICER_CLRENA_29 EQU 0x20000000 ; bit 29
NVIC_ICER_CLRENA_30 EQU 0x40000000 ; bit 30
NVIC_ICER_CLRENA_31 EQU 0x80000000 ; bit 31
;***************** Bit definition for NVIC_ISPR register ******************
NVIC_ISPR_SETPEND EQU 0xFFFFFFFF ; Interrupt set-pending bits
NVIC_ISPR_SETPEND_0 EQU 0x00000001 ; bit 0
NVIC_ISPR_SETPEND_1 EQU 0x00000002 ; bit 1
NVIC_ISPR_SETPEND_2 EQU 0x00000004 ; bit 2
NVIC_ISPR_SETPEND_3 EQU 0x00000008 ; bit 3
NVIC_ISPR_SETPEND_4 EQU 0x00000010 ; bit 4
NVIC_ISPR_SETPEND_5 EQU 0x00000020 ; bit 5
NVIC_ISPR_SETPEND_6 EQU 0x00000040 ; bit 6
NVIC_ISPR_SETPEND_7 EQU 0x00000080 ; bit 7
NVIC_ISPR_SETPEND_8 EQU 0x00000100 ; bit 8
NVIC_ISPR_SETPEND_9 EQU 0x00000200 ; bit 9
NVIC_ISPR_SETPEND_10 EQU 0x00000400 ; bit 10
NVIC_ISPR_SETPEND_11 EQU 0x00000800 ; bit 11
NVIC_ISPR_SETPEND_12 EQU 0x00001000 ; bit 12
NVIC_ISPR_SETPEND_13 EQU 0x00002000 ; bit 13
NVIC_ISPR_SETPEND_14 EQU 0x00004000 ; bit 14
NVIC_ISPR_SETPEND_15 EQU 0x00008000 ; bit 15
NVIC_ISPR_SETPEND_16 EQU 0x00010000 ; bit 16
NVIC_ISPR_SETPEND_17 EQU 0x00020000 ; bit 17
NVIC_ISPR_SETPEND_18 EQU 0x00040000 ; bit 18
NVIC_ISPR_SETPEND_19 EQU 0x00080000 ; bit 19
NVIC_ISPR_SETPEND_20 EQU 0x00100000 ; bit 20
NVIC_ISPR_SETPEND_21 EQU 0x00200000 ; bit 21
NVIC_ISPR_SETPEND_22 EQU 0x00400000 ; bit 22
NVIC_ISPR_SETPEND_23 EQU 0x00800000 ; bit 23
NVIC_ISPR_SETPEND_24 EQU 0x01000000 ; bit 24
NVIC_ISPR_SETPEND_25 EQU 0x02000000 ; bit 25
NVIC_ISPR_SETPEND_26 EQU 0x04000000 ; bit 26
NVIC_ISPR_SETPEND_27 EQU 0x08000000 ; bit 27
NVIC_ISPR_SETPEND_28 EQU 0x10000000 ; bit 28
NVIC_ISPR_SETPEND_29 EQU 0x20000000 ; bit 29
NVIC_ISPR_SETPEND_30 EQU 0x40000000 ; bit 30
NVIC_ISPR_SETPEND_31 EQU 0x80000000 ; bit 31
;***************** Bit definition for NVIC_ICPR register ******************
NVIC_ICPR_CLRPEND EQU 0xFFFFFFFF ; Interrupt clear-pending bits
NVIC_ICPR_CLRPEND_0 EQU 0x00000001 ; bit 0
NVIC_ICPR_CLRPEND_1 EQU 0x00000002 ; bit 1
NVIC_ICPR_CLRPEND_2 EQU 0x00000004 ; bit 2
NVIC_ICPR_CLRPEND_3 EQU 0x00000008 ; bit 3
NVIC_ICPR_CLRPEND_4 EQU 0x00000010 ; bit 4
NVIC_ICPR_CLRPEND_5 EQU 0x00000020 ; bit 5
NVIC_ICPR_CLRPEND_6 EQU 0x00000040 ; bit 6
NVIC_ICPR_CLRPEND_7 EQU 0x00000080 ; bit 7
NVIC_ICPR_CLRPEND_8 EQU 0x00000100 ; bit 8
NVIC_ICPR_CLRPEND_9 EQU 0x00000200 ; bit 9
NVIC_ICPR_CLRPEND_10 EQU 0x00000400 ; bit 10
NVIC_ICPR_CLRPEND_11 EQU 0x00000800 ; bit 11
NVIC_ICPR_CLRPEND_12 EQU 0x00001000 ; bit 12
NVIC_ICPR_CLRPEND_13 EQU 0x00002000 ; bit 13
NVIC_ICPR_CLRPEND_14 EQU 0x00004000 ; bit 14
NVIC_ICPR_CLRPEND_15 EQU 0x00008000 ; bit 15
NVIC_ICPR_CLRPEND_16 EQU 0x00010000 ; bit 16
NVIC_ICPR_CLRPEND_17 EQU 0x00020000 ; bit 17
NVIC_ICPR_CLRPEND_18 EQU 0x00040000 ; bit 18
NVIC_ICPR_CLRPEND_19 EQU 0x00080000 ; bit 19
NVIC_ICPR_CLRPEND_20 EQU 0x00100000 ; bit 20
NVIC_ICPR_CLRPEND_21 EQU 0x00200000 ; bit 21
NVIC_ICPR_CLRPEND_22 EQU 0x00400000 ; bit 22
NVIC_ICPR_CLRPEND_23 EQU 0x00800000 ; bit 23
NVIC_ICPR_CLRPEND_24 EQU 0x01000000 ; bit 24
NVIC_ICPR_CLRPEND_25 EQU 0x02000000 ; bit 25
NVIC_ICPR_CLRPEND_26 EQU 0x04000000 ; bit 26
NVIC_ICPR_CLRPEND_27 EQU 0x08000000 ; bit 27
NVIC_ICPR_CLRPEND_28 EQU 0x10000000 ; bit 28
NVIC_ICPR_CLRPEND_29 EQU 0x20000000 ; bit 29
NVIC_ICPR_CLRPEND_30 EQU 0x40000000 ; bit 30
NVIC_ICPR_CLRPEND_31 EQU 0x80000000 ; bit 31
;***************** Bit definition for NVIC_IABR register ******************
NVIC_IABR_ACTIVE EQU 0xFFFFFFFF ; Interrupt active flags
NVIC_IABR_ACTIVE_0 EQU 0x00000001 ; bit 0
NVIC_IABR_ACTIVE_1 EQU 0x00000002 ; bit 1
NVIC_IABR_ACTIVE_2 EQU 0x00000004 ; bit 2
NVIC_IABR_ACTIVE_3 EQU 0x00000008 ; bit 3
NVIC_IABR_ACTIVE_4 EQU 0x00000010 ; bit 4
NVIC_IABR_ACTIVE_5 EQU 0x00000020 ; bit 5
NVIC_IABR_ACTIVE_6 EQU 0x00000040 ; bit 6
NVIC_IABR_ACTIVE_7 EQU 0x00000080 ; bit 7
NVIC_IABR_ACTIVE_8 EQU 0x00000100 ; bit 8
NVIC_IABR_ACTIVE_9 EQU 0x00000200 ; bit 9
NVIC_IABR_ACTIVE_10 EQU 0x00000400 ; bit 10
NVIC_IABR_ACTIVE_11 EQU 0x00000800 ; bit 11
NVIC_IABR_ACTIVE_12 EQU 0x00001000 ; bit 12
NVIC_IABR_ACTIVE_13 EQU 0x00002000 ; bit 13
NVIC_IABR_ACTIVE_14 EQU 0x00004000 ; bit 14
NVIC_IABR_ACTIVE_15 EQU 0x00008000 ; bit 15
NVIC_IABR_ACTIVE_16 EQU 0x00010000 ; bit 16
NVIC_IABR_ACTIVE_17 EQU 0x00020000 ; bit 17
NVIC_IABR_ACTIVE_18 EQU 0x00040000 ; bit 18
NVIC_IABR_ACTIVE_19 EQU 0x00080000 ; bit 19
NVIC_IABR_ACTIVE_20 EQU 0x00100000 ; bit 20
NVIC_IABR_ACTIVE_21 EQU 0x00200000 ; bit 21
NVIC_IABR_ACTIVE_22 EQU 0x00400000 ; bit 22
NVIC_IABR_ACTIVE_23 EQU 0x00800000 ; bit 23
NVIC_IABR_ACTIVE_24 EQU 0x01000000 ; bit 24
NVIC_IABR_ACTIVE_25 EQU 0x02000000 ; bit 25
NVIC_IABR_ACTIVE_26 EQU 0x04000000 ; bit 26
NVIC_IABR_ACTIVE_27 EQU 0x08000000 ; bit 27
NVIC_IABR_ACTIVE_28 EQU 0x10000000 ; bit 28
NVIC_IABR_ACTIVE_29 EQU 0x20000000 ; bit 29
NVIC_IABR_ACTIVE_30 EQU 0x40000000 ; bit 30
NVIC_IABR_ACTIVE_31 EQU 0x80000000 ; bit 31
;***************** Bit definition for NVIC_PRI0 register ******************
NVIC_IPR0_PRI_0 EQU 0x000000FF ; Priority of interrupt 0
NVIC_IPR0_PRI_1 EQU 0x0000FF00 ; Priority of interrupt 1
NVIC_IPR0_PRI_2 EQU 0x00FF0000 ; Priority of interrupt 2
NVIC_IPR0_PRI_3 EQU 0xFF000000 ; Priority of interrupt 3
;***************** Bit definition for NVIC_PRI1 register ******************
NVIC_IPR1_PRI_4 EQU 0x000000FF ; Priority of interrupt 4
NVIC_IPR1_PRI_5 EQU 0x0000FF00 ; Priority of interrupt 5
NVIC_IPR1_PRI_6 EQU 0x00FF0000 ; Priority of interrupt 6
NVIC_IPR1_PRI_7 EQU 0xFF000000 ; Priority of interrupt 7
;***************** Bit definition for NVIC_PRI2 register ******************
NVIC_IPR2_PRI_8 EQU 0x000000FF ; Priority of interrupt 8
NVIC_IPR2_PRI_9 EQU 0x0000FF00 ; Priority of interrupt 9
NVIC_IPR2_PRI_10 EQU 0x00FF0000 ; Priority of interrupt 10
NVIC_IPR2_PRI_11 EQU 0xFF000000 ; Priority of interrupt 11
;***************** Bit definition for NVIC_PRI3 register ******************
NVIC_IPR3_PRI_12 EQU 0x000000FF ; Priority of interrupt 12
NVIC_IPR3_PRI_13 EQU 0x0000FF00 ; Priority of interrupt 13
NVIC_IPR3_PRI_14 EQU 0x00FF0000 ; Priority of interrupt 14
NVIC_IPR3_PRI_15 EQU 0xFF000000 ; Priority of interrupt 15
;***************** Bit definition for NVIC_PRI4 register ******************
NVIC_IPR4_PRI_16 EQU 0x000000FF ; Priority of interrupt 16
NVIC_IPR4_PRI_17 EQU 0x0000FF00 ; Priority of interrupt 17
NVIC_IPR4_PRI_18 EQU 0x00FF0000 ; Priority of interrupt 18
NVIC_IPR4_PRI_19 EQU 0xFF000000 ; Priority of interrupt 19
;***************** Bit definition for NVIC_PRI5 register ******************
NVIC_IPR5_PRI_20 EQU 0x000000FF ; Priority of interrupt 20
NVIC_IPR5_PRI_21 EQU 0x0000FF00 ; Priority of interrupt 21
NVIC_IPR5_PRI_22 EQU 0x00FF0000 ; Priority of interrupt 22
NVIC_IPR5_PRI_23 EQU 0xFF000000 ; Priority of interrupt 23
;***************** Bit definition for NVIC_PRI6 register ******************
NVIC_IPR6_PRI_24 EQU 0x000000FF ; Priority of interrupt 24
NVIC_IPR6_PRI_25 EQU 0x0000FF00 ; Priority of interrupt 25
NVIC_IPR6_PRI_26 EQU 0x00FF0000 ; Priority of interrupt 26
NVIC_IPR6_PRI_27 EQU 0xFF000000 ; Priority of interrupt 27
;***************** Bit definition for NVIC_PRI7 register ******************
NVIC_IPR7_PRI_28 EQU 0x000000FF ; Priority of interrupt 28
NVIC_IPR7_PRI_29 EQU 0x0000FF00 ; Priority of interrupt 29
NVIC_IPR7_PRI_30 EQU 0x00FF0000 ; Priority of interrupt 30
NVIC_IPR7_PRI_31 EQU 0xFF000000 ; Priority of interrupt 31
END

@ -0,0 +1,62 @@
;********************************************************************************
; SOUBOR : INI_BITS_OPAMP.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro OPAMP
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Operational Amplifier (OPAMP)
;
;****************************************************************************
;****************** Bit definition for OPAMP_CSR register *****************
OPAMP_CSR_OPA1PD EQU 0x00000001 ; OPAMP1 disable
OPAMP_CSR_S3SEL1 EQU 0x00000002 ; Switch 3 for OPAMP1 Enable
OPAMP_CSR_S4SEL1 EQU 0x00000004 ; Switch 4 for OPAMP1 Enable
OPAMP_CSR_S5SEL1 EQU 0x00000008 ; Switch 5 for OPAMP1 Enable
OPAMP_CSR_S6SEL1 EQU 0x00000010 ; Switch 6 for OPAMP1 Enable
OPAMP_CSR_OPA1CAL_L EQU 0x00000020 ; OPAMP1 Offset calibration for P differential pair
OPAMP_CSR_OPA1CAL_H EQU 0x00000040 ; OPAMP1 Offset calibration for N differential pair
OPAMP_CSR_OPA1LPM EQU 0x00000080 ; OPAMP1 Low power enable
OPAMP_CSR_OPA2PD EQU 0x00000100 ; OPAMP2 disable
OPAMP_CSR_S3SEL2 EQU 0x00000200 ; Switch 3 for OPAMP2 Enable
OPAMP_CSR_S4SEL2 EQU 0x00000400 ; Switch 4 for OPAMP2 Enable
OPAMP_CSR_S5SEL2 EQU 0x00000800 ; Switch 5 for OPAMP2 Enable
OPAMP_CSR_S6SEL2 EQU 0x00001000 ; Switch 6 for OPAMP2 Enable
OPAMP_CSR_OPA2CAL_L EQU 0x00002000 ; OPAMP2 Offset calibration for P differential pair
OPAMP_CSR_OPA2CAL_H EQU 0x00004000 ; OPAMP2 Offset calibration for N differential pair
OPAMP_CSR_OPA2LPM EQU 0x00008000 ; OPAMP2 Low power enable
OPAMP_CSR_OPA3PD EQU 0x00010000 ; OPAMP3 disable
OPAMP_CSR_S3SEL3 EQU 0x00020000 ; Switch 3 for OPAMP3 Enable
OPAMP_CSR_S4SEL3 EQU 0x00040000 ; Switch 4 for OPAMP3 Enable
OPAMP_CSR_S5SEL3 EQU 0x00080000 ; Switch 5 for OPAMP3 Enable
OPAMP_CSR_S6SEL3 EQU 0x00100000 ; Switch 6 for OPAMP3 Enable
OPAMP_CSR_OPA3CAL_L EQU 0x00200000 ; OPAMP3 Offset calibration for P differential pair
OPAMP_CSR_OPA3CAL_H EQU 0x00400000 ; OPAMP3 Offset calibration for N differential pair
OPAMP_CSR_OPA3LPM EQU 0x00800000 ; OPAMP3 Low power enable
OPAMP_CSR_ANAWSEL1 EQU 0x01000000 ; Switch ANA Enable for OPAMP1
OPAMP_CSR_ANAWSEL2 EQU 0x02000000 ; Switch ANA Enable for OPAMP2
OPAMP_CSR_ANAWSEL3 EQU 0x04000000 ; Switch ANA Enable for OPAMP3
OPAMP_CSR_S7SEL2 EQU 0x08000000 ; Switch 7 for OPAMP2 Enable
OPAMP_CSR_AOP_RANGE EQU 0x10000000 ; Power range selection
OPAMP_CSR_OPA1CALOUT EQU 0x20000000 ; OPAMP1 calibration output
OPAMP_CSR_OPA2CALOUT EQU 0x40000000 ; OPAMP2 calibration output
OPAMP_CSR_OPA3CALOUT EQU 0x80000000 ; OPAMP3 calibration output
;****************** Bit definition for OPAMP_OTR register *****************
OPAMP_OTR_AO1_OPT_OFFSET_TRIM EQU 0x000003FF ; Offset trim for OPAMP1
OPAMP_OTR_AO2_OPT_OFFSET_TRIM EQU 0x000FFC00 ; Offset trim for OPAMP2
OPAMP_OTR_AO3_OPT_OFFSET_TRIM EQU 0x3FF00000 ; Offset trim for OPAMP2
OPAMP_OTR_OT_USER EQU 0x80000000 ; Switch to OPAMP offset user trimmed values
;****************** Bit definition for OPAMP_LPOTR register ***************
OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP EQU 0x000003FF ; Offset trim in low power for OPAMP1
OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP EQU 0x000FFC00 ; Offset trim in low power for OPAMP2
OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP EQU 0x3FF00000 ; Offset trim in low power for OPAMP3
END

@ -0,0 +1,60 @@
;********************************************************************************
; SOUBOR : INI_BITS_PWR.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro PWR (napajeni, sleep...)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Power Control (PWR)
;
;****************************************************************************
;******************* Bit definition for PWR_CR register *******************
PWR_CR_LPSDSR EQU 0x0001 ; Low-power deepsleep/sleep/low power run
PWR_CR_PDDS EQU 0x0002 ; Power Down Deepsleep
PWR_CR_CWUF EQU 0x0004 ; Clear Wakeup Flag
PWR_CR_CSBF EQU 0x0008 ; Clear Standby Flag
PWR_CR_PVDE EQU 0x0010 ; Power Voltage Detector Enable
PWR_CR_PLS EQU 0x00E0 ; PLS[2:0] bits (PVD Level Selection)
PWR_CR_PLS_0 EQU 0x0020 ; Bit 0
PWR_CR_PLS_1 EQU 0x0040 ; Bit 1
PWR_CR_PLS_2 EQU 0x0080 ; Bit 2
; PVD level configuration
PWR_CR_PLS_LEV0 EQU 0x0000 ; PVD level 0
PWR_CR_PLS_LEV1 EQU 0x0020 ; PVD level 1
PWR_CR_PLS_LEV2 EQU 0x0040 ; PVD level 2
PWR_CR_PLS_LEV3 EQU 0x0060 ; PVD level 3
PWR_CR_PLS_LEV4 EQU 0x0080 ; PVD level 4
PWR_CR_PLS_LEV5 EQU 0x00A0 ; PVD level 5
PWR_CR_PLS_LEV6 EQU 0x00C0 ; PVD level 6
PWR_CR_PLS_LEV7 EQU 0x00E0 ; PVD level 7
PWR_CR_DBP EQU 0x0100 ; Disable Backup Domain write protection
PWR_CR_ULP EQU 0x0200 ; Ultra Low Power mode
PWR_CR_FWU EQU 0x0400 ; Fast wakeup
PWR_CR_VOS EQU 0x1800 ; VOS[1:0] bits (Voltage scaling range selection)
PWR_CR_VOS_0 EQU 0x0800 ; Bit 0
PWR_CR_VOS_1 EQU 0x1000 ; Bit 1
PWR_CR_LPRUN EQU 0x4000 ; Low power run mode
;****************** Bit definition for PWR_CSR register *******************
PWR_CSR_WUF EQU 0x0001 ; Wakeup Flag
PWR_CSR_SBF EQU 0x0002 ; Standby Flag
PWR_CSR_PVDO EQU 0x0004 ; PVD Output
PWR_CSR_VREFINTRDYF EQU 0x0008 ; Internal voltage reference (VREFINT) ready flag
PWR_CSR_VOSF EQU 0x0010 ; Voltage Scaling select flag
PWR_CSR_REGLPF EQU 0x0020 ; Regulator LP flag
PWR_CSR_EWUP1 EQU 0x0100 ; Enable WKUP pin 1
PWR_CSR_EWUP2 EQU 0x0200 ; Enable WKUP pin 2
PWR_CSR_EWUP3 EQU 0x0400 ; Enable WKUP pin 3
END

@ -0,0 +1,361 @@
;********************************************************************************
; SOUBOR : INI_BITS_RCC.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro RCC (nastaveni hodin)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Reset and Clock Control (RCC)
;
;****************************************************************************
;******************* Bit definition for RCC_CR register *******************
RCC_CR_HSION EQU 0x00000001 ; Internal High Speed clock enable
RCC_CR_HSIRDY EQU 0x00000002 ; Internal High Speed clock ready flag
RCC_CR_MSION EQU 0x00000100 ; Internal Multi Speed clock enable
RCC_CR_MSIRDY EQU 0x00000200 ; Internal Multi Speed clock ready flag
RCC_CR_HSEON EQU 0x00010000 ; External High Speed clock enable
RCC_CR_HSERDY EQU 0x00020000 ; External High Speed clock ready flag
RCC_CR_HSEBYP EQU 0x00040000 ; External High Speed clock Bypass
RCC_CR_PLLON EQU 0x01000000 ; PLL enable
RCC_CR_PLLRDY EQU 0x02000000 ; PLL clock ready flag
RCC_CR_CSSON EQU 0x10000000 ; Clock Security System enable
RCC_CR_RTCPRE EQU 0x60000000 ; RTC/LCD Prescaler
; prescaler levels
RCC_CR_RTCPRE_DIV2 EQU 0x00000000
RCC_CR_RTCPRE_DIV4 EQU 0x20000000
RCC_CR_RTCPRE_DIV8 EQU 0x40000000
RCC_CR_RTCPRE_DIV16 EQU 0x60000000
;******************* Bit definition for RCC_ICSCR register ****************
RCC_ICSCR_HSICAL EQU 0x000000FF ; Internal High Speed clock Calibration
RCC_ICSCR_HSITRIM EQU 0x00001F00 ; Internal High Speed clock trimming
RCC_ICSCR_MSIRANGE EQU 0x0000E000 ; Internal Multi Speed clock Range
RCC_ICSCR_MSIRANGE_0 EQU 0x00000000 ; Internal Multi Speed clock Range 65.536 KHz
RCC_ICSCR_MSIRANGE_1 EQU 0x00002000 ; Internal Multi Speed clock Range 131.072 KHz
RCC_ICSCR_MSIRANGE_2 EQU 0x00004000 ; Internal Multi Speed clock Range 262.144 KHz
RCC_ICSCR_MSIRANGE_3 EQU 0x00006000 ; Internal Multi Speed clock Range 524.288 KHz
RCC_ICSCR_MSIRANGE_4 EQU 0x00008000 ; Internal Multi Speed clock Range 1.048 MHz
RCC_ICSCR_MSIRANGE_5 EQU 0x0000A000 ; Internal Multi Speed clock Range 2.097 MHz
RCC_ICSCR_MSIRANGE_6 EQU 0x0000C000 ; Internal Multi Speed clock Range 4.194 MHz
RCC_ICSCR_MSICAL EQU 0x00FF0000 ; Internal Multi Speed clock Calibration
RCC_ICSCR_MSITRIM EQU 0xFF000000 ; Internal Multi Speed clock trimming
;******************* Bit definition for RCC_CFGR register *****************
RCC_CFGR_SW EQU 0x00000003 ; SW[1:0] bits (System clock Switch)
; SW configuration
RCC_CFGR_SW_MSI EQU 0x00000000 ; MSI selected as system clock
RCC_CFGR_SW_HSI EQU 0x00000001 ; HSI selected as system clock
RCC_CFGR_SW_HSE EQU 0x00000002 ; HSE selected as system clock
RCC_CFGR_SW_PLL EQU 0x00000003 ; PLL selected as system clock
RCC_CFGR_SWS EQU 0x0000000C ; SWS[1:0] bits (System Clock Switch Status)
; SWS configuration
RCC_CFGR_SWS_MSI EQU 0x00000000 ; MSI oscillator used as system clock
RCC_CFGR_SWS_HSI EQU 0x00000004 ; HSI oscillator used as system clock
RCC_CFGR_SWS_HSE EQU 0x00000008 ; HSE oscillator used as system clock
RCC_CFGR_SWS_PLL EQU 0x0000000C ; PLL used as system clock
RCC_CFGR_HPRE EQU 0x000000F0 ; HPRE[3:0] bits (AHB prescaler)
; HPRE configuration
RCC_CFGR_HPRE_DIV1 EQU 0x00000000 ; SYSCLK not divided
RCC_CFGR_HPRE_DIV2 EQU 0x00000080 ; SYSCLK divided by 2
RCC_CFGR_HPRE_DIV4 EQU 0x00000090 ; SYSCLK divided by 4
RCC_CFGR_HPRE_DIV8 EQU 0x000000A0 ; SYSCLK divided by 8
RCC_CFGR_HPRE_DIV16 EQU 0x000000B0 ; SYSCLK divided by 16
RCC_CFGR_HPRE_DIV64 EQU 0x000000C0 ; SYSCLK divided by 64
RCC_CFGR_HPRE_DIV128 EQU 0x000000D0 ; SYSCLK divided by 128
RCC_CFGR_HPRE_DIV256 EQU 0x000000E0 ; SYSCLK divided by 256
RCC_CFGR_HPRE_DIV512 EQU 0x000000F0 ; SYSCLK divided by 512
RCC_CFGR_PPRE1 EQU 0x00000700 ; PRE1[2:0] bits (APB1 prescaler)
; PPRE1 configuration
RCC_CFGR_PPRE1_DIV1 EQU 0x00000000 ; HCLK not divided
RCC_CFGR_PPRE1_DIV2 EQU 0x00000400 ; HCLK divided by 2
RCC_CFGR_PPRE1_DIV4 EQU 0x00000500 ; HCLK divided by 4
RCC_CFGR_PPRE1_DIV8 EQU 0x00000600 ; HCLK divided by 8
RCC_CFGR_PPRE1_DIV16 EQU 0x00000700 ; HCLK divided by 16
RCC_CFGR_PPRE2 EQU 0x00003800 ; PRE2[2:0] bits (APB2 prescaler)
; PPRE2 configuration
RCC_CFGR_PPRE2_DIV1 EQU 0x00000000 ; HCLK not divided
RCC_CFGR_PPRE2_DIV2 EQU 0x00002000 ; HCLK divided by 2
RCC_CFGR_PPRE2_DIV4 EQU 0x00002800 ; HCLK divided by 4
RCC_CFGR_PPRE2_DIV8 EQU 0x00003000 ; HCLK divided by 8
RCC_CFGR_PPRE2_DIV16 EQU 0x00003800 ; HCLK divided by 16
; PLL entry clock source
RCC_CFGR_PLLSRC EQU 0x00010000 ; PLL entry clock source
RCC_CFGR_PLLSRC_HSI EQU 0x00000000 ; HSI as PLL entry clock source
RCC_CFGR_PLLSRC_HSE EQU 0x00010000 ; HSE as PLL entry clock source
RCC_CFGR_PLLMUL EQU 0x003C0000 ; PLLMUL[3:0] bits (PLL multiplication factor)
; PLLMUL configuration
RCC_CFGR_PLLMUL3 EQU 0x00000000 ; PLL input clock * 3
RCC_CFGR_PLLMUL4 EQU 0x00040000 ; PLL input clock * 4
RCC_CFGR_PLLMUL6 EQU 0x00080000 ; PLL input clock * 6
RCC_CFGR_PLLMUL8 EQU 0x000C0000 ; PLL input clock * 8
RCC_CFGR_PLLMUL12 EQU 0x00100000 ; PLL input clock * 12
RCC_CFGR_PLLMUL16 EQU 0x00140000 ; PLL input clock * 16
RCC_CFGR_PLLMUL24 EQU 0x00180000 ; PLL input clock * 24
RCC_CFGR_PLLMUL32 EQU 0x001C0000 ; PLL input clock * 32
RCC_CFGR_PLLMUL48 EQU 0x00200000 ; PLL input clock * 48
; PLLDIV configuration
RCC_CFGR_PLLDIV EQU 0x00C00000 ; PLLDIV[1:0] bits (PLL Output Division)
; PLLDIV configuration
RCC_CFGR_PLLDIV1 EQU 0x00000000 ; PLL clock output = CKVCO / 1
RCC_CFGR_PLLDIV2 EQU 0x00400000 ; PLL clock output = CKVCO / 2
RCC_CFGR_PLLDIV3 EQU 0x00800000 ; PLL clock output = CKVCO / 3
RCC_CFGR_PLLDIV4 EQU 0x00C00000 ; PLL clock output = CKVCO / 4
RCC_CFGR_MCOSEL EQU 0x07000000 ; MCO[2:0] bits (Microcontroller Clock Output)
; MCO configuration
RCC_CFGR_MCO_NOCLOCK EQU 0x00000000 ; No clock
RCC_CFGR_MCO_SYSCLK EQU 0x01000000 ; System clock selected
RCC_CFGR_MCO_HSI EQU 0x02000000 ; Internal 16 MHz RC oscillator clock selected
RCC_CFGR_MCO_MSI EQU 0x03000000 ; Internal Medium Speed RC oscillator clock selected
RCC_CFGR_MCO_HSE EQU 0x04000000 ; External 1-25 MHz oscillator clock selected
RCC_CFGR_MCO_PLL EQU 0x05000000 ; PLL clock divided
RCC_CFGR_MCO_LSI EQU 0x06000000 ; LSI selected
RCC_CFGR_MCO_LSE EQU 0x07000000 ; LSE selected
RCC_CFGR_MCOPRE EQU 0x70000000 ; MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler)
; MCO Prescaler configuration
RCC_CFGR_MCO_DIV1 EQU 0x00000000 ; MCO Clock divided by 1
RCC_CFGR_MCO_DIV2 EQU 0x10000000 ; MCO Clock divided by 2
RCC_CFGR_MCO_DIV4 EQU 0x20000000 ; MCO Clock divided by 4
RCC_CFGR_MCO_DIV8 EQU 0x30000000 ; MCO Clock divided by 8
RCC_CFGR_MCO_DIV16 EQU 0x40000000 ; MCO Clock divided by 16
; ****************** Bit definition for RCC_CIR register *******************
RCC_CIR_LSIRDYF EQU 0x00000001 ; LSI Ready Interrupt flag
RCC_CIR_LSERDYF EQU 0x00000002 ; LSE Ready Interrupt flag
RCC_CIR_HSIRDYF EQU 0x00000004 ; HSI Ready Interrupt flag
RCC_CIR_HSERDYF EQU 0x00000008 ; HSE Ready Interrupt flag
RCC_CIR_PLLRDYF EQU 0x00000010 ; PLL Ready Interrupt flag
RCC_CIR_MSIRDYF EQU 0x00000020 ; MSI Ready Interrupt flag
RCC_CIR_LSECSS EQU 0x00000040 ; LSE CSS Interrupt flag
RCC_CIR_CSSF EQU 0x00000080 ; Clock Security System Interrupt flag
RCC_CIR_LSIRDYIE EQU 0x00000100 ; LSI Ready Interrupt Enable
RCC_CIR_LSERDYIE EQU 0x00000200 ; LSE Ready Interrupt Enable
RCC_CIR_HSIRDYIE EQU 0x00000400 ; HSI Ready Interrupt Enable
RCC_CIR_HSERDYIE EQU 0x00000800 ; HSE Ready Interrupt Enable
RCC_CIR_PLLRDYIE EQU 0x00001000 ; PLL Ready Interrupt Enable
RCC_CIR_MSIRDYIE EQU 0x00002000 ; MSI Ready Interrupt Enable
RCC_CIR_LSECSSIE EQU 0x00004000 ; LSE CSS Interrupt Enable
RCC_CIR_LSIRDYC EQU 0x00010000 ; LSI Ready Interrupt Clear
RCC_CIR_LSERDYC EQU 0x00020000 ; LSE Ready Interrupt Clear
RCC_CIR_HSIRDYC EQU 0x00040000 ; HSI Ready Interrupt Clear
RCC_CIR_HSERDYC EQU 0x00080000 ; HSE Ready Interrupt Clear
RCC_CIR_PLLRDYC EQU 0x00100000 ; PLL Ready Interrupt Clear
RCC_CIR_MSIRDYC EQU 0x00200000 ; MSI Ready Interrupt Clear
RCC_CIR_LSECSSC EQU 0x00400000 ; LSE CSS Interrupt Clear
RCC_CIR_CSSC EQU 0x00800000 ; Clock Security System Interrupt Clear
;**************** Bit definition for RCC_AHBRSTR register *****************
RCC_AHBRSTR_GPIOARST EQU 0x00000001 ; GPIO port A reset
RCC_AHBRSTR_GPIOBRST EQU 0x00000002 ; GPIO port B reset
RCC_AHBRSTR_GPIOCRST EQU 0x00000004 ; GPIO port C reset
RCC_AHBRSTR_GPIODRST EQU 0x00000008 ; GPIO port D reset
RCC_AHBRSTR_GPIOERST EQU 0x00000010 ; GPIO port E reset
RCC_AHBRSTR_GPIOHRST EQU 0x00000020 ; GPIO port H reset
RCC_AHBRSTR_GPIOFRST EQU 0x00000040 ; GPIO port F reset
RCC_AHBRSTR_GPIOGRST EQU 0x00000080 ; GPIO port G reset
RCC_AHBRSTR_CRCRST EQU 0x00001000 ; CRC reset
RCC_AHBRSTR_FLITFRST EQU 0x00008000 ; FLITF reset
RCC_AHBRSTR_DMA1RST EQU 0x01000000 ; DMA1 reset
RCC_AHBRSTR_DMA2RST EQU 0x02000000 ; DMA2 reset
RCC_AHBRSTR_AESRST EQU 0x08000000 ; AES reset
RCC_AHBRSTR_FSMCRST EQU 0x40000000 ; FSMC reset
;**************** Bit definition for RCC_APB2RSTR register ****************
RCC_APB2RSTR_SYSCFGRST EQU 0x00000001 ; System Configuration SYSCFG reset
RCC_APB2RSTR_TIM9RST EQU 0x00000004 ; TIM9 reset
RCC_APB2RSTR_TIM10RST EQU 0x00000008 ; TIM10 reset
RCC_APB2RSTR_TIM11RST EQU 0x00000010 ; TIM11 reset
RCC_APB2RSTR_ADC1RST EQU 0x00000200 ; ADC1 reset
RCC_APB2RSTR_SDIORST EQU 0x00000800 ; SDIO reset
RCC_APB2RSTR_SPI1RST EQU 0x00001000 ; SPI1 reset
RCC_APB2RSTR_USART1RST EQU 0x00004000 ; USART1 reset
;**************** Bit definition for RCC_APB1RSTR register ****************
RCC_APB1RSTR_TIM2RST EQU 0x00000001 ; Timer 2 reset
RCC_APB1RSTR_TIM3RST EQU 0x00000002 ; Timer 3 reset
RCC_APB1RSTR_TIM4RST EQU 0x00000004 ; Timer 4 reset
RCC_APB1RSTR_TIM5RST EQU 0x00000008 ; Timer 5 reset
RCC_APB1RSTR_TIM6RST EQU 0x00000010 ; Timer 6 reset
RCC_APB1RSTR_TIM7RST EQU 0x00000020 ; Timer 7 reset
RCC_APB1RSTR_LCDRST EQU 0x00000200 ; LCD reset
RCC_APB1RSTR_WWDGRST EQU 0x00000800 ; Window Watchdog reset
RCC_APB1RSTR_SPI2RST EQU 0x00004000 ; SPI 2 reset
RCC_APB1RSTR_SPI3RST EQU 0x00008000 ; SPI 3 reset
RCC_APB1RSTR_USART2RST EQU 0x00020000 ; USART 2 reset
RCC_APB1RSTR_USART3RST EQU 0x00040000 ; USART 3 reset
RCC_APB1RSTR_UART4RST EQU 0x00080000 ; UART 4 reset
RCC_APB1RSTR_UART5RST EQU 0x00100000 ; UART 5 reset
RCC_APB1RSTR_I2C1RST EQU 0x00200000 ; I2C 1 reset
RCC_APB1RSTR_I2C2RST EQU 0x00400000 ; I2C 2 reset
RCC_APB1RSTR_USBRST EQU 0x00800000 ; USB reset
RCC_APB1RSTR_PWRRST EQU 0x10000000 ; Power interface reset
RCC_APB1RSTR_DACRST EQU 0x20000000 ; DAC interface reset
RCC_APB1RSTR_COMPRST EQU 0x80000000 ; Comparator interface reset
;***************** Bit definition for RCC_AHBENR register *****************
RCC_AHBENR_GPIOAEN EQU 0x00000001 ; GPIO port A clock enable
RCC_AHBENR_GPIOBEN EQU 0x00000002 ; GPIO port B clock enable
RCC_AHBENR_GPIOCEN EQU 0x00000004 ; GPIO port C clock enable
RCC_AHBENR_GPIODEN EQU 0x00000008 ; GPIO port D clock enable
RCC_AHBENR_GPIOEEN EQU 0x00000010 ; GPIO port E clock enable
RCC_AHBENR_GPIOHEN EQU 0x00000020 ; GPIO port H clock enable
RCC_AHBENR_GPIOFEN EQU 0x00000040 ; GPIO port F clock enable
RCC_AHBENR_GPIOGEN EQU 0x00000080 ; GPIO port G clock enable
RCC_AHBENR_CRCEN EQU 0x00001000 ; CRC clock enable
RCC_AHBENR_FLITFEN EQU 0x00008000 ; FLITF clock enable (has effect only when the Flash memory is in power down mode)
RCC_AHBENR_DMA1EN EQU 0x01000000 ; DMA1 clock enable
RCC_AHBENR_DMA2EN EQU 0x02000000 ; DMA2 clock enable
RCC_AHBENR_AESEN EQU 0x08000000 ; AES clock enable
RCC_AHBENR_FSMCEN EQU 0x40000000 ; FSMC clock enable
;***************** Bit definition for RCC_APB2ENR register ****************
RCC_APB2ENR_SYSCFGEN EQU 0x00000001 ; System Configuration SYSCFG clock enable
RCC_APB2ENR_TIM9EN EQU 0x00000004 ; TIM9 interface clock enable
RCC_APB2ENR_TIM10EN EQU 0x00000008 ; TIM10 interface clock enable
RCC_APB2ENR_TIM11EN EQU 0x00000010 ; TIM11 Timer clock enable
RCC_APB2ENR_ADC1EN EQU 0x00000200 ; ADC1 clock enable
RCC_APB2ENR_SDIOEN EQU 0x00000800 ; SDIO clock enable
RCC_APB2ENR_SPI1EN EQU 0x00001000 ; SPI1 clock enable
RCC_APB2ENR_USART1EN EQU 0x00004000 ; USART1 clock enable
;**************** Bit definition for RCC_APB1ENR register *****************
RCC_APB1ENR_TIM2EN EQU 0x00000001 ; Timer 2 clock enabled
RCC_APB1ENR_TIM3EN EQU 0x00000002 ; Timer 3 clock enable
RCC_APB1ENR_TIM4EN EQU 0x00000004 ; Timer 4 clock enable
RCC_APB1ENR_TIM5EN EQU 0x00000008 ; Timer 5 clock enable
RCC_APB1ENR_TIM6EN EQU 0x00000010 ; Timer 6 clock enable
RCC_APB1ENR_TIM7EN EQU 0x00000020 ; Timer 7 clock enable
RCC_APB1ENR_LCDEN EQU 0x00000200 ; LCD clock enable
RCC_APB1ENR_WWDGEN EQU 0x00000800 ; Window Watchdog clock enable
RCC_APB1ENR_SPI2EN EQU 0x00004000 ; SPI 2 clock enable
RCC_APB1ENR_SPI3EN EQU 0x00008000 ; SPI 3 clock enable
RCC_APB1ENR_USART2EN EQU 0x00020000 ; USART 2 clock enable
RCC_APB1ENR_USART3EN EQU 0x00040000 ; USART 3 clock enable
RCC_APB1ENR_UART4EN EQU 0x00080000 ; UART 4 clock enable
RCC_APB1ENR_UART5EN EQU 0x00100000 ; UART 5 clock enable
RCC_APB1ENR_I2C1EN EQU 0x00200000 ; I2C 1 clock enable
RCC_APB1ENR_I2C2EN EQU 0x00400000 ; I2C 2 clock enable
RCC_APB1ENR_USBEN EQU 0x00800000 ; USB clock enable
RCC_APB1ENR_PWREN EQU 0x10000000 ; Power interface clock enable
RCC_APB1ENR_DACEN EQU 0x20000000 ; DAC interface clock enable
RCC_APB1ENR_COMPEN EQU 0x80000000 ; Comparator interface clock enable
;***************** Bit definition for RCC_AHBLPENR register ***************
RCC_AHBLPENR_GPIOALPEN EQU 0x00000001 ; GPIO port A clock enabled in sleep mode
RCC_AHBLPENR_GPIOBLPEN EQU 0x00000002 ; GPIO port B clock enabled in sleep mode
RCC_AHBLPENR_GPIOCLPEN EQU 0x00000004 ; GPIO port C clock enabled in sleep mode
RCC_AHBLPENR_GPIODLPEN EQU 0x00000008 ; GPIO port D clock enabled in sleep mode
RCC_AHBLPENR_GPIOELPEN EQU 0x00000010 ; GPIO port E clock enabled in sleep mode
RCC_AHBLPENR_GPIOHLPEN EQU 0x00000020 ; GPIO port H clock enabled in sleep mode
RCC_AHBLPENR_GPIOFLPEN EQU 0x00000040 ; GPIO port F clock enabled in sleep mode
RCC_AHBLPENR_GPIOGLPEN EQU 0x00000080 ; GPIO port G clock enabled in sleep mode
RCC_AHBLPENR_CRCLPEN EQU 0x00001000 ; CRC clock enabled in sleep mode
RCC_AHBLPENR_FLITFLPEN EQU 0x00008000 ; Flash Interface clock enabled in sleep mode (has effect only when the Flash memory is in power down mode)
RCC_AHBLPENR_SRAMLPEN EQU 0x00010000 ; SRAM clock enabled in sleep mode
RCC_AHBLPENR_DMA1LPEN EQU 0x01000000 ; DMA1 clock enabled in sleep mode
RCC_AHBLPENR_DMA2LPEN EQU 0x02000000 ; DMA2 clock enabled in sleep mode
RCC_AHBLPENR_AESLPEN EQU 0x08000000 ; AES clock enabled in sleep mode
RCC_AHBLPENR_FSMCLPEN EQU 0x40000000 ; FSMC clock enabled in sleep mode
;***************** Bit definition for RCC_APB2LPENR register **************
RCC_APB2LPENR_SYSCFGLPEN EQU 0x00000001 ; System Configuration SYSCFG clock enabled in sleep mode
RCC_APB2LPENR_TIM9LPEN EQU 0x00000004 ; TIM9 interface clock enabled in sleep mode
RCC_APB2LPENR_TIM10LPEN EQU 0x00000008 ; TIM10 interface clock enabled in sleep mode
RCC_APB2LPENR_TIM11LPEN EQU 0x00000010 ; TIM11 Timer clock enabled in sleep mode
RCC_APB2LPENR_ADC1LPEN EQU 0x00000200 ; ADC1 clock enabled in sleep mode
RCC_APB2LPENR_SDIOLPEN EQU 0x00000800 ; SDIO clock enabled in sleep mode
RCC_APB2LPENR_SPI1LPEN EQU 0x00001000 ; SPI1 clock enabled in sleep mode
RCC_APB2LPENR_USART1LPEN EQU 0x00004000 ; USART1 clock enabled in sleep mode
;**************** Bit definition for RCC_APB1LPENR register ***************
RCC_APB1LPENR_TIM2LPEN EQU 0x00000001 ; Timer 2 clock enabled in sleep mode
RCC_APB1LPENR_TIM3LPEN EQU 0x00000002 ; Timer 3 clock enabled in sleep mode
RCC_APB1LPENR_TIM4LPEN EQU 0x00000004 ; Timer 4 clock enabled in sleep mode
RCC_APB1LPENR_TIM5LPEN EQU 0x00000008 ; Timer 5 clock enabled in sleep mode
RCC_APB1LPENR_TIM6LPEN EQU 0x00000010 ; Timer 6 clock enabled in sleep mode
RCC_APB1LPENR_TIM7LPEN EQU 0x00000020 ; Timer 7 clock enabled in sleep mode
RCC_APB1LPENR_LCDLPEN EQU 0x00000200 ; LCD clock enabled in sleep mode
RCC_APB1LPENR_WWDGLPEN EQU 0x00000800 ; Window Watchdog clock enabled in sleep mode
RCC_APB1LPENR_SPI2LPEN EQU 0x00004000 ; SPI 2 clock enabled in sleep mode
RCC_APB1LPENR_SPI3LPEN EQU 0x00008000 ; SPI 3 clock enabled in sleep mode
RCC_APB1LPENR_USART2LPEN EQU 0x00020000 ; USART 2 clock enabled in sleep mode
RCC_APB1LPENR_USART3LPEN EQU 0x00040000 ; USART 3 clock enabled in sleep mode
RCC_APB1LPENR_UART4LPEN EQU 0x00080000 ; UART 4 clock enabled in sleep mode
RCC_APB1LPENR_UART5LPEN EQU 0x00100000 ; UART 5 clock enabled in sleep mode
RCC_APB1LPENR_I2C1LPEN EQU 0x00200000 ; I2C 1 clock enabled in sleep mode
RCC_APB1LPENR_I2C2LPEN EQU 0x00400000 ; I2C 2 clock enabled in sleep mode
RCC_APB1LPENR_USBLPEN EQU 0x00800000 ; USB clock enabled in sleep mode
RCC_APB1LPENR_PWRLPEN EQU 0x10000000 ; Power interface clock enabled in sleep mode
RCC_APB1LPENR_DACLPEN EQU 0x20000000 ; DAC interface clock enabled in sleep mode
RCC_APB1LPENR_COMPLPEN EQU 0x80000000 ; Comparator interface clock enabled in sleep mode
;****************** Bit definition for RCC_CSR register *******************
RCC_CSR_LSION EQU 0x00000001 ; Internal Low Speed oscillator enable
RCC_CSR_LSIRDY EQU 0x00000002 ; Internal Low Speed oscillator Ready
RCC_CSR_LSEON EQU 0x00000100 ; External Low Speed oscillator enable
RCC_CSR_LSERDY EQU 0x00000200 ; External Low Speed oscillator Ready
RCC_CSR_LSEBYP EQU 0x00000400 ; External Low Speed oscillator Bypass
RCC_CSR_LSECSSON EQU 0x00000800 ; External Low Speed oscillator CSS Enable
RCC_CSR_LSECSSD EQU 0x00001000 ; External Low Speed oscillator CSS Detected
RCC_CSR_RTCSEL EQU 0x00030000 ; RTCSEL[1:0] bits (RTC clock source selection)
RCC_CSR_RTCSEL_0 EQU 0x00010000 ; Bit 0
RCC_CSR_RTCSEL_1 EQU 0x00020000 ; Bit 1
; RTC congiguration
RCC_CSR_RTCSEL_NOCLOCK EQU 0x00000000 ; No clock
RCC_CSR_RTCSEL_LSE EQU 0x00010000 ; LSE oscillator clock used as RTC clock
RCC_CSR_RTCSEL_LSI EQU 0x00020000 ; LSI oscillator clock used as RTC clock
RCC_CSR_RTCSEL_HSE EQU 0x00030000 ; HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock
RCC_CSR_RTCEN EQU 0x00400000 ; RTC clock enable
RCC_CSR_RTCRST EQU 0x00800000 ; RTC reset
RCC_CSR_RMVF EQU 0x01000000 ; Remove reset flag
RCC_CSR_OBLRSTF EQU 0x02000000 ; Option Bytes Loader reset flag
RCC_CSR_PINRSTF EQU 0x04000000 ; PIN reset flag
RCC_CSR_PORRSTF EQU 0x08000000 ; POR/PDR reset flag
RCC_CSR_SFTRSTF EQU 0x10000000 ; Software Reset flag
RCC_CSR_IWDGRSTF EQU 0x20000000 ; Independent Watchdog reset flag
RCC_CSR_WWDGRSTF EQU 0x40000000 ; Window watchdog reset flag
RCC_CSR_LPWRRSTF EQU 0x80000000 ; Low-Power reset flag
END

@ -0,0 +1,529 @@
;********************************************************************************
; SOUBOR : INI_BITS_RI.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro RI (analogove propojky)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Routing Interface (RI)
;
;****************************************************************************
;******************* Bit definition for RI_ICR register *******************
RI_ICR_IC1Z EQU 0x0000000F ; IC1Z[3:0] bits (Input Capture 1 select bits)
RI_ICR_IC1Z_0 EQU 0x00000001 ; Bit 0
RI_ICR_IC1Z_1 EQU 0x00000002 ; Bit 1
RI_ICR_IC1Z_2 EQU 0x00000004 ; Bit 2
RI_ICR_IC1Z_3 EQU 0x00000008 ; Bit 3
RI_ICR_IC2Z EQU 0x000000F0 ; IC2Z[3:0] bits (Input Capture 2 select bits)
RI_ICR_IC2Z_0 EQU 0x00000010 ; Bit 0
RI_ICR_IC2Z_1 EQU 0x00000020 ; Bit 1
RI_ICR_IC2Z_2 EQU 0x00000040 ; Bit 2
RI_ICR_IC2Z_3 EQU 0x00000080 ; Bit 3
RI_ICR_IC3Z EQU 0x00000F00 ; IC3Z[3:0] bits (Input Capture 3 select bits)
RI_ICR_IC3Z_0 EQU 0x00000100 ; Bit 0
RI_ICR_IC3Z_1 EQU 0x00000200 ; Bit 1
RI_ICR_IC3Z_2 EQU 0x00000400 ; Bit 2
RI_ICR_IC3Z_3 EQU 0x00000800 ; Bit 3
RI_ICR_IC4Z EQU 0x0000F000 ; IC4Z[3:0] bits (Input Capture 4 select bits)
RI_ICR_IC4Z_0 EQU 0x00001000 ; Bit 0
RI_ICR_IC4Z_1 EQU 0x00002000 ; Bit 1
RI_ICR_IC4Z_2 EQU 0x00004000 ; Bit 2
RI_ICR_IC4Z_3 EQU 0x00008000 ; Bit 3
RI_ICR_TIM EQU 0x00030000 ; TIM[3:0] bits (Timers select bits)
RI_ICR_TIM_0 EQU 0x00010000 ; Bit 0
RI_ICR_TIM_1 EQU 0x00020000 ; Bit 1
RI_ICR_IC1 EQU 0x00040000 ; Input capture 1
RI_ICR_IC2 EQU 0x00080000 ; Input capture 2
RI_ICR_IC3 EQU 0x00100000 ; Input capture 3
RI_ICR_IC4 EQU 0x00200000 ; Input capture 4
;******************* Bit definition for RI_ASCR1 register *******************
RI_ASCR1_CH EQU 0x03FCFFFF ; AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits)
RI_ASCR1_CH_0 EQU 0x00000001 ; Bit 0
RI_ASCR1_CH_1 EQU 0x00000002 ; Bit 1
RI_ASCR1_CH_2 EQU 0x00000004 ; Bit 2
RI_ASCR1_CH_3 EQU 0x00000008 ; Bit 3
RI_ASCR1_CH_4 EQU 0x00000010 ; Bit 4
RI_ASCR1_CH_5 EQU 0x00000020 ; Bit 5
RI_ASCR1_CH_6 EQU 0x00000040 ; Bit 6
RI_ASCR1_CH_7 EQU 0x00000080 ; Bit 7
RI_ASCR1_CH_8 EQU 0x00000100 ; Bit 8
RI_ASCR1_CH_9 EQU 0x00000200 ; Bit 9
RI_ASCR1_CH_10 EQU 0x00000400 ; Bit 10
RI_ASCR1_CH_11 EQU 0x00000800 ; Bit 11
RI_ASCR1_CH_12 EQU 0x00001000 ; Bit 12
RI_ASCR1_CH_13 EQU 0x00002000 ; Bit 13
RI_ASCR1_CH_14 EQU 0x00004000 ; Bit 14
RI_ASCR1_CH_15 EQU 0x00008000 ; Bit 15
RI_ASCR1_CH_31 EQU 0x00010000 ; Bit 16
RI_ASCR1_CH_18 EQU 0x00040000 ; Bit 18
RI_ASCR1_CH_19 EQU 0x00080000 ; Bit 19
RI_ASCR1_CH_20 EQU 0x00100000 ; Bit 20
RI_ASCR1_CH_21 EQU 0x00200000 ; Bit 21
RI_ASCR1_CH_22 EQU 0x00400000 ; Bit 22
RI_ASCR1_CH_23 EQU 0x00800000 ; Bit 23
RI_ASCR1_CH_24 EQU 0x01000000 ; Bit 24
RI_ASCR1_CH_25 EQU 0x02000000 ; Bit 25
RI_ASCR1_VCOMP EQU 0x04000000 ; ADC analog switch selection for internal node to COMP1
RI_ASCR1_CH_27 EQU 0x00400000 ; Bit 27
RI_ASCR1_CH_28 EQU 0x00800000 ; Bit 28
RI_ASCR1_CH_29 EQU 0x01000000 ; Bit 29
RI_ASCR1_CH_30 EQU 0x02000000 ; Bit 30
RI_ASCR1_SCM EQU 0x80000000 ; I/O Switch control mode
;******************* Bit definition for RI_ASCR2 register *******************
RI_ASCR2_GR10_1 EQU 0x00000001 ; GR10-1 selection bit
RI_ASCR2_GR10_2 EQU 0x00000002 ; GR10-2 selection bit
RI_ASCR2_GR10_3 EQU 0x00000004 ; GR10-3 selection bit
RI_ASCR2_GR10_4 EQU 0x00000008 ; GR10-4 selection bit
RI_ASCR2_GR6_1 EQU 0x00000010 ; GR6-1 selection bit
RI_ASCR2_GR6_2 EQU 0x00000020 ; GR6-2 selection bit
RI_ASCR2_GR5_1 EQU 0x00000040 ; GR5-1 selection bit
RI_ASCR2_GR5_2 EQU 0x00000080 ; GR5-2 selection bit
RI_ASCR2_GR5_3 EQU 0x00000100 ; GR5-3 selection bit
RI_ASCR2_GR4_1 EQU 0x00000200 ; GR4-1 selection bit
RI_ASCR2_GR4_2 EQU 0x00000400 ; GR4-2 selection bit
RI_ASCR2_GR4_3 EQU 0x00000800 ; GR4-3 selection bit
RI_ASCR2_GR4_4 EQU 0x00008000 ; GR4-4 selection bit
RI_ASCR2_CH0b EQU 0x00010000 ; CH0b selection bit
RI_ASCR2_CH1b EQU 0x00020000 ; CH1b selection bit
RI_ASCR2_CH2b EQU 0x00040000 ; CH2b selection bit
RI_ASCR2_CH3b EQU 0x00080000 ; CH3b selection bit
RI_ASCR2_CH6b EQU 0x00100000 ; CH6b selection bit
RI_ASCR2_CH7b EQU 0x00200000 ; CH7b selection bit
RI_ASCR2_CH8b EQU 0x00400000 ; CH8b selection bit
RI_ASCR2_CH9b EQU 0x00800000 ; CH9b selection bit
RI_ASCR2_CH10b EQU 0x01000000 ; CH10b selection bit
RI_ASCR2_CH11b EQU 0x02000000 ; CH11b selection bit
RI_ASCR2_CH12b EQU 0x04000000 ; CH12b selection bit
RI_ASCR2_GR6_3 EQU 0x08000000 ; GR6-3 selection bit
RI_ASCR2_GR6_4 EQU 0x10000000 ; GR6-4 selection bit
RI_ASCR2_GR5_4 EQU 0x20000000 ; GR5-4 selection bit
;******************* Bit definition for RI_HYSCR1 register *******************
RI_HYSCR1_PA EQU 0x0000FFFF ; PA[15:0] Port A Hysteresis selection
RI_HYSCR1_PA_0 EQU 0x00000001 ; Bit 0
RI_HYSCR1_PA_1 EQU 0x00000002 ; Bit 1
RI_HYSCR1_PA_2 EQU 0x00000004 ; Bit 2
RI_HYSCR1_PA_3 EQU 0x00000008 ; Bit 3
RI_HYSCR1_PA_4 EQU 0x00000010 ; Bit 4
RI_HYSCR1_PA_5 EQU 0x00000020 ; Bit 5
RI_HYSCR1_PA_6 EQU 0x00000040 ; Bit 6
RI_HYSCR1_PA_7 EQU 0x00000080 ; Bit 7
RI_HYSCR1_PA_8 EQU 0x00000100 ; Bit 8
RI_HYSCR1_PA_9 EQU 0x00000200 ; Bit 9
RI_HYSCR1_PA_10 EQU 0x00000400 ; Bit 10
RI_HYSCR1_PA_11 EQU 0x00000800 ; Bit 11
RI_HYSCR1_PA_12 EQU 0x00001000 ; Bit 12
RI_HYSCR1_PA_13 EQU 0x00002000 ; Bit 13
RI_HYSCR1_PA_14 EQU 0x00004000 ; Bit 14
RI_HYSCR1_PA_15 EQU 0x00008000 ; Bit 15
RI_HYSCR1_PB EQU 0xFFFF0000 ; PB[15:0] Port B Hysteresis selection
RI_HYSCR1_PB_0 EQU 0x00010000 ; Bit 0
RI_HYSCR1_PB_1 EQU 0x00020000 ; Bit 1
RI_HYSCR1_PB_2 EQU 0x00040000 ; Bit 2
RI_HYSCR1_PB_3 EQU 0x00080000 ; Bit 3
RI_HYSCR1_PB_4 EQU 0x00100000 ; Bit 4
RI_HYSCR1_PB_5 EQU 0x00200000 ; Bit 5
RI_HYSCR1_PB_6 EQU 0x00400000 ; Bit 6
RI_HYSCR1_PB_7 EQU 0x00800000 ; Bit 7
RI_HYSCR1_PB_8 EQU 0x01000000 ; Bit 8
RI_HYSCR1_PB_9 EQU 0x02000000 ; Bit 9
RI_HYSCR1_PB_10 EQU 0x04000000 ; Bit 10
RI_HYSCR1_PB_11 EQU 0x08000000 ; Bit 11
RI_HYSCR1_PB_12 EQU 0x10000000 ; Bit 12
RI_HYSCR1_PB_13 EQU 0x20000000 ; Bit 13
RI_HYSCR1_PB_14 EQU 0x40000000 ; Bit 14
RI_HYSCR1_PB_15 EQU 0x80000000 ; Bit 15
;******************* Bit definition for RI_HYSCR2 register *******************
RI_HYSCR2_PC EQU 0x0000FFFF ; PC[15:0] Port C Hysteresis selection
RI_HYSCR2_PC_0 EQU 0x00000001 ; Bit 0
RI_HYSCR2_PC_1 EQU 0x00000002 ; Bit 1
RI_HYSCR2_PC_2 EQU 0x00000004 ; Bit 2
RI_HYSCR2_PC_3 EQU 0x00000008 ; Bit 3
RI_HYSCR2_PC_4 EQU 0x00000010 ; Bit 4
RI_HYSCR2_PC_5 EQU 0x00000020 ; Bit 5
RI_HYSCR2_PC_6 EQU 0x00000040 ; Bit 6
RI_HYSCR2_PC_7 EQU 0x00000080 ; Bit 7
RI_HYSCR2_PC_8 EQU 0x00000100 ; Bit 8
RI_HYSCR2_PC_9 EQU 0x00000200 ; Bit 9
RI_HYSCR2_PC_10 EQU 0x00000400 ; Bit 10
RI_HYSCR2_PC_11 EQU 0x00000800 ; Bit 11
RI_HYSCR2_PC_12 EQU 0x00001000 ; Bit 12
RI_HYSCR2_PC_13 EQU 0x00002000 ; Bit 13
RI_HYSCR2_PC_14 EQU 0x00004000 ; Bit 14
RI_HYSCR2_PC_15 EQU 0x00008000 ; Bit 15
RI_HYSCR2_PD EQU 0xFFFF0000 ; PD[15:0] Port D Hysteresis selection
RI_HYSCR2_PD_0 EQU 0x00010000 ; Bit 0
RI_HYSCR2_PD_1 EQU 0x00020000 ; Bit 1
RI_HYSCR2_PD_2 EQU 0x00040000 ; Bit 2
RI_HYSCR2_PD_3 EQU 0x00080000 ; Bit 3
RI_HYSCR2_PD_4 EQU 0x00100000 ; Bit 4
RI_HYSCR2_PD_5 EQU 0x00200000 ; Bit 5
RI_HYSCR2_PD_6 EQU 0x00400000 ; Bit 6
RI_HYSCR2_PD_7 EQU 0x00800000 ; Bit 7
RI_HYSCR2_PD_8 EQU 0x01000000 ; Bit 8
RI_HYSCR2_PD_9 EQU 0x02000000 ; Bit 9
RI_HYSCR2_PD_10 EQU 0x04000000 ; Bit 10
RI_HYSCR2_PD_11 EQU 0x08000000 ; Bit 11
RI_HYSCR2_PD_12 EQU 0x10000000 ; Bit 12
RI_HYSCR2_PD_13 EQU 0x20000000 ; Bit 13
RI_HYSCR2_PD_14 EQU 0x40000000 ; Bit 14
RI_HYSCR2_PD_15 EQU 0x80000000 ; Bit 15
;******************* Bit definition for RI_HYSCR3 register *******************
RI_HYSCR2_PE EQU 0x0000FFFF ; PE[15:0] Port E Hysteresis selection
RI_HYSCR2_PE_0 EQU 0x00000001 ; Bit 0
RI_HYSCR2_PE_1 EQU 0x00000002 ; Bit 1
RI_HYSCR2_PE_2 EQU 0x00000004 ; Bit 2
RI_HYSCR2_PE_3 EQU 0x00000008 ; Bit 3
RI_HYSCR2_PE_4 EQU 0x00000010 ; Bit 4
RI_HYSCR2_PE_5 EQU 0x00000020 ; Bit 5
RI_HYSCR2_PE_6 EQU 0x00000040 ; Bit 6
RI_HYSCR2_PE_7 EQU 0x00000080 ; Bit 7
RI_HYSCR2_PE_8 EQU 0x00000100 ; Bit 8
RI_HYSCR2_PE_9 EQU 0x00000200 ; Bit 9
RI_HYSCR2_PE_10 EQU 0x00000400 ; Bit 10
RI_HYSCR2_PE_11 EQU 0x00000800 ; Bit 11
RI_HYSCR2_PE_12 EQU 0x00001000 ; Bit 12
RI_HYSCR2_PE_13 EQU 0x00002000 ; Bit 13
RI_HYSCR2_PE_14 EQU 0x00004000 ; Bit 14
RI_HYSCR2_PE_15 EQU 0x00008000 ; Bit 15
RI_HYSCR3_PF EQU 0xFFFF0000 ; PF[15:0] Port F Hysteresis selection
RI_HYSCR3_PF_0 EQU 0x00010000 ; Bit 0
RI_HYSCR3_PF_1 EQU 0x00020000 ; Bit 1
RI_HYSCR3_PF_2 EQU 0x00040000 ; Bit 2
RI_HYSCR3_PF_3 EQU 0x00080000 ; Bit 3
RI_HYSCR3_PF_4 EQU 0x00100000 ; Bit 4
RI_HYSCR3_PF_5 EQU 0x00200000 ; Bit 5
RI_HYSCR3_PF_6 EQU 0x00400000 ; Bit 6
RI_HYSCR3_PF_7 EQU 0x00800000 ; Bit 7
RI_HYSCR3_PF_8 EQU 0x01000000 ; Bit 8
RI_HYSCR3_PF_9 EQU 0x02000000 ; Bit 9
RI_HYSCR3_PF_10 EQU 0x04000000 ; Bit 10
RI_HYSCR3_PF_11 EQU 0x08000000 ; Bit 11
RI_HYSCR3_PF_12 EQU 0x10000000 ; Bit 12
RI_HYSCR3_PF_13 EQU 0x20000000 ; Bit 13
RI_HYSCR3_PF_14 EQU 0x40000000 ; Bit 14
RI_HYSCR3_PF_15 EQU 0x80000000 ; Bit 15
;******************* Bit definition for RI_HYSCR4 register *******************
RI_HYSCR4_PG EQU 0x0000FFFF ; PG[15:0] Port G Hysteresis selection
RI_HYSCR4_PG_0 EQU 0x00000001 ; Bit 0
RI_HYSCR4_PG_1 EQU 0x00000002 ; Bit 1
RI_HYSCR4_PG_2 EQU 0x00000004 ; Bit 2
RI_HYSCR4_PG_3 EQU 0x00000008 ; Bit 3
RI_HYSCR4_PG_4 EQU 0x00000010 ; Bit 4
RI_HYSCR4_PG_5 EQU 0x00000020 ; Bit 5
RI_HYSCR4_PG_6 EQU 0x00000040 ; Bit 6
RI_HYSCR4_PG_7 EQU 0x00000080 ; Bit 7
RI_HYSCR4_PG_8 EQU 0x00000100 ; Bit 8
RI_HYSCR4_PG_9 EQU 0x00000200 ; Bit 9
RI_HYSCR4_PG_10 EQU 0x00000400 ; Bit 10
RI_HYSCR4_PG_11 EQU 0x00000800 ; Bit 11
RI_HYSCR4_PG_12 EQU 0x00001000 ; Bit 12
RI_HYSCR4_PG_13 EQU 0x00002000 ; Bit 13
RI_HYSCR4_PG_14 EQU 0x00004000 ; Bit 14
RI_HYSCR4_PG_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_ASMR1 register *******************
RI_ASMR1_PA EQU 0x0000FFFF ; PA[15:0] Port A analog switch mode selection
RI_ASMR1_PA_0 EQU 0x00000001 ; Bit 0
RI_ASMR1_PA_1 EQU 0x00000002 ; Bit 1
RI_ASMR1_PA_2 EQU 0x00000004 ; Bit 2
RI_ASMR1_PA_3 EQU 0x00000008 ; Bit 3
RI_ASMR1_PA_4 EQU 0x00000010 ; Bit 4
RI_ASMR1_PA_5 EQU 0x00000020 ; Bit 5
RI_ASMR1_PA_6 EQU 0x00000040 ; Bit 6
RI_ASMR1_PA_7 EQU 0x00000080 ; Bit 7
RI_ASMR1_PA_8 EQU 0x00000100 ; Bit 8
RI_ASMR1_PA_9 EQU 0x00000200 ; Bit 9
RI_ASMR1_PA_10 EQU 0x00000400 ; Bit 10
RI_ASMR1_PA_11 EQU 0x00000800 ; Bit 11
RI_ASMR1_PA_12 EQU 0x00001000 ; Bit 12
RI_ASMR1_PA_13 EQU 0x00002000 ; Bit 13
RI_ASMR1_PA_14 EQU 0x00004000 ; Bit 14
RI_ASMR1_PA_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_CMR1 register *******************
RI_CMR1_PA EQU 0x0000FFFF ; PA[15:0] Port A channel masking
RI_CMR1_PA_0 EQU 0x00000001 ; Bit 0
RI_CMR1_PA_1 EQU 0x00000002 ; Bit 1
RI_CMR1_PA_2 EQU 0x00000004 ; Bit 2
RI_CMR1_PA_3 EQU 0x00000008 ; Bit 3
RI_CMR1_PA_4 EQU 0x00000010 ; Bit 4
RI_CMR1_PA_5 EQU 0x00000020 ; Bit 5
RI_CMR1_PA_6 EQU 0x00000040 ; Bit 6
RI_CMR1_PA_7 EQU 0x00000080 ; Bit 7
RI_CMR1_PA_8 EQU 0x00000100 ; Bit 8
RI_CMR1_PA_9 EQU 0x00000200 ; Bit 9
RI_CMR1_PA_10 EQU 0x00000400 ; Bit 10
RI_CMR1_PA_11 EQU 0x00000800 ; Bit 11
RI_CMR1_PA_12 EQU 0x00001000 ; Bit 12
RI_CMR1_PA_13 EQU 0x00002000 ; Bit 13
RI_CMR1_PA_14 EQU 0x00004000 ; Bit 14
RI_CMR1_PA_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_CICR1 register *******************
RI_CICR1_PA EQU 0x0000FFFF ; PA[15:0] Port A channel identification for capture
RI_CICR1_PA_0 EQU 0x00000001 ; Bit 0
RI_CICR1_PA_1 EQU 0x00000002 ; Bit 1
RI_CICR1_PA_2 EQU 0x00000004 ; Bit 2
RI_CICR1_PA_3 EQU 0x00000008 ; Bit 3
RI_CICR1_PA_4 EQU 0x00000010 ; Bit 4
RI_CICR1_PA_5 EQU 0x00000020 ; Bit 5
RI_CICR1_PA_6 EQU 0x00000040 ; Bit 6
RI_CICR1_PA_7 EQU 0x00000080 ; Bit 7
RI_CICR1_PA_8 EQU 0x00000100 ; Bit 8
RI_CICR1_PA_9 EQU 0x00000200 ; Bit 9
RI_CICR1_PA_10 EQU 0x00000400 ; Bit 10
RI_CICR1_PA_11 EQU 0x00000800 ; Bit 11
RI_CICR1_PA_12 EQU 0x00001000 ; Bit 12
RI_CICR1_PA_13 EQU 0x00002000 ; Bit 13
RI_CICR1_PA_14 EQU 0x00004000 ; Bit 14
RI_CICR1_PA_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_ASMR2 register *******************
RI_ASMR2_PB EQU 0x0000FFFF ; PB[15:0] Port B analog switch mode selection
RI_ASMR2_PB_0 EQU 0x00000001 ; Bit 0
RI_ASMR2_PB_1 EQU 0x00000002 ; Bit 1
RI_ASMR2_PB_2 EQU 0x00000004 ; Bit 2
RI_ASMR2_PB_3 EQU 0x00000008 ; Bit 3
RI_ASMR2_PB_4 EQU 0x00000010 ; Bit 4
RI_ASMR2_PB_5 EQU 0x00000020 ; Bit 5
RI_ASMR2_PB_6 EQU 0x00000040 ; Bit 6
RI_ASMR2_PB_7 EQU 0x00000080 ; Bit 7
RI_ASMR2_PB_8 EQU 0x00000100 ; Bit 8
RI_ASMR2_PB_9 EQU 0x00000200 ; Bit 9
RI_ASMR2_PB_10 EQU 0x00000400 ; Bit 10
RI_ASMR2_PB_11 EQU 0x00000800 ; Bit 11
RI_ASMR2_PB_12 EQU 0x00001000 ; Bit 12
RI_ASMR2_PB_13 EQU 0x00002000 ; Bit 13
RI_ASMR2_PB_14 EQU 0x00004000 ; Bit 14
RI_ASMR2_PB_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_CMR2 register *******************
RI_CMR2_PB EQU 0x0000FFFF ; PB[15:0] Port B channel masking
RI_CMR2_PB_0 EQU 0x00000001 ; Bit 0
RI_CMR2_PB_1 EQU 0x00000002 ; Bit 1
RI_CMR2_PB_2 EQU 0x00000004 ; Bit 2
RI_CMR2_PB_3 EQU 0x00000008 ; Bit 3
RI_CMR2_PB_4 EQU 0x00000010 ; Bit 4
RI_CMR2_PB_5 EQU 0x00000020 ; Bit 5
RI_CMR2_PB_6 EQU 0x00000040 ; Bit 6
RI_CMR2_PB_7 EQU 0x00000080 ; Bit 7
RI_CMR2_PB_8 EQU 0x00000100 ; Bit 8
RI_CMR2_PB_9 EQU 0x00000200 ; Bit 9
RI_CMR2_PB_10 EQU 0x00000400 ; Bit 10
RI_CMR2_PB_11 EQU 0x00000800 ; Bit 11
RI_CMR2_PB_12 EQU 0x00001000 ; Bit 12
RI_CMR2_PB_13 EQU 0x00002000 ; Bit 13
RI_CMR2_PB_14 EQU 0x00004000 ; Bit 14
RI_CMR2_PB_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_CICR2 register *******************
RI_CICR2_PB EQU 0x0000FFFF ; PB[15:0] Port B channel identification for capture
RI_CICR2_PB_0 EQU 0x00000001 ; Bit 0
RI_CICR2_PB_1 EQU 0x00000002 ; Bit 1
RI_CICR2_PB_2 EQU 0x00000004 ; Bit 2
RI_CICR2_PB_3 EQU 0x00000008 ; Bit 3
RI_CICR2_PB_4 EQU 0x00000010 ; Bit 4
RI_CICR2_PB_5 EQU 0x00000020 ; Bit 5
RI_CICR2_PB_6 EQU 0x00000040 ; Bit 6
RI_CICR2_PB_7 EQU 0x00000080 ; Bit 7
RI_CICR2_PB_8 EQU 0x00000100 ; Bit 8
RI_CICR2_PB_9 EQU 0x00000200 ; Bit 9
RI_CICR2_PB_10 EQU 0x00000400 ; Bit 10
RI_CICR2_PB_11 EQU 0x00000800 ; Bit 11
RI_CICR2_PB_12 EQU 0x00001000 ; Bit 12
RI_CICR2_PB_13 EQU 0x00002000 ; Bit 13
RI_CICR2_PB_14 EQU 0x00004000 ; Bit 14
RI_CICR2_PB_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_ASMR3 register *******************
RI_ASMR3_PC EQU 0x0000FFFF ; PC[15:0] Port C analog switch mode selection
RI_ASMR3_PC_0 EQU 0x00000001 ; Bit 0
RI_ASMR3_PC_1 EQU 0x00000002 ; Bit 1
RI_ASMR3_PC_2 EQU 0x00000004 ; Bit 2
RI_ASMR3_PC_3 EQU 0x00000008 ; Bit 3
RI_ASMR3_PC_4 EQU 0x00000010 ; Bit 4
RI_ASMR3_PC_5 EQU 0x00000020 ; Bit 5
RI_ASMR3_PC_6 EQU 0x00000040 ; Bit 6
RI_ASMR3_PC_7 EQU 0x00000080 ; Bit 7
RI_ASMR3_PC_8 EQU 0x00000100 ; Bit 8
RI_ASMR3_PC_9 EQU 0x00000200 ; Bit 9
RI_ASMR3_PC_10 EQU 0x00000400 ; Bit 10
RI_ASMR3_PC_11 EQU 0x00000800 ; Bit 11
RI_ASMR3_PC_12 EQU 0x00001000 ; Bit 12
RI_ASMR3_PC_13 EQU 0x00002000 ; Bit 13
RI_ASMR3_PC_14 EQU 0x00004000 ; Bit 14
RI_ASMR3_PC_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_CMR3 register *******************
RI_CMR3_PC EQU 0x0000FFFF ; PC[15:0] Port C channel masking
RI_CMR3_PC_0 EQU 0x00000001 ; Bit 0
RI_CMR3_PC_1 EQU 0x00000002 ; Bit 1
RI_CMR3_PC_2 EQU 0x00000004 ; Bit 2
RI_CMR3_PC_3 EQU 0x00000008 ; Bit 3
RI_CMR3_PC_4 EQU 0x00000010 ; Bit 4
RI_CMR3_PC_5 EQU 0x00000020 ; Bit 5
RI_CMR3_PC_6 EQU 0x00000040 ; Bit 6
RI_CMR3_PC_7 EQU 0x00000080 ; Bit 7
RI_CMR3_PC_8 EQU 0x00000100 ; Bit 8
RI_CMR3_PC_9 EQU 0x00000200 ; Bit 9
RI_CMR3_PC_10 EQU 0x00000400 ; Bit 10
RI_CMR3_PC_11 EQU 0x00000800 ; Bit 11
RI_CMR3_PC_12 EQU 0x00001000 ; Bit 12
RI_CMR3_PC_13 EQU 0x00002000 ; Bit 13
RI_CMR3_PC_14 EQU 0x00004000 ; Bit 14
RI_CMR3_PC_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_CICR3 register *******************
RI_CICR3_PC EQU 0x0000FFFF ; PC[15:0] Port C channel identification for capture
RI_CICR3_PC_0 EQU 0x00000001 ; Bit 0
RI_CICR3_PC_1 EQU 0x00000002 ; Bit 1
RI_CICR3_PC_2 EQU 0x00000004 ; Bit 2
RI_CICR3_PC_3 EQU 0x00000008 ; Bit 3
RI_CICR3_PC_4 EQU 0x00000010 ; Bit 4
RI_CICR3_PC_5 EQU 0x00000020 ; Bit 5
RI_CICR3_PC_6 EQU 0x00000040 ; Bit 6
RI_CICR3_PC_7 EQU 0x00000080 ; Bit 7
RI_CICR3_PC_8 EQU 0x00000100 ; Bit 8
RI_CICR3_PC_9 EQU 0x00000200 ; Bit 9
RI_CICR3_PC_10 EQU 0x00000400 ; Bit 10
RI_CICR3_PC_11 EQU 0x00000800 ; Bit 11
RI_CICR3_PC_12 EQU 0x00001000 ; Bit 12
RI_CICR3_PC_13 EQU 0x00002000 ; Bit 13
RI_CICR3_PC_14 EQU 0x00004000 ; Bit 14
RI_CICR3_PC_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_ASMR4 register *******************
RI_ASMR4_PF EQU 0x0000FFFF ; PF[15:0] Port F analog switch mode selection
RI_ASMR4_PF_0 EQU 0x00000001 ; Bit 0
RI_ASMR4_PF_1 EQU 0x00000002 ; Bit 1
RI_ASMR4_PF_2 EQU 0x00000004 ; Bit 2
RI_ASMR4_PF_3 EQU 0x00000008 ; Bit 3
RI_ASMR4_PF_4 EQU 0x00000010 ; Bit 4
RI_ASMR4_PF_5 EQU 0x00000020 ; Bit 5
RI_ASMR4_PF_6 EQU 0x00000040 ; Bit 6
RI_ASMR4_PF_7 EQU 0x00000080 ; Bit 7
RI_ASMR4_PF_8 EQU 0x00000100 ; Bit 8
RI_ASMR4_PF_9 EQU 0x00000200 ; Bit 9
RI_ASMR4_PF_10 EQU 0x00000400 ; Bit 10
RI_ASMR4_PF_11 EQU 0x00000800 ; Bit 11
RI_ASMR4_PF_12 EQU 0x00001000 ; Bit 12
RI_ASMR4_PF_13 EQU 0x00002000 ; Bit 13
RI_ASMR4_PF_14 EQU 0x00004000 ; Bit 14
RI_ASMR4_PF_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_CMR4 register *******************
RI_CMR4_PF EQU 0x0000FFFF ; PF[15:0] Port F channel masking
RI_CMR4_PF_0 EQU 0x00000001 ; Bit 0
RI_CMR4_PF_1 EQU 0x00000002 ; Bit 1
RI_CMR4_PF_2 EQU 0x00000004 ; Bit 2
RI_CMR4_PF_3 EQU 0x00000008 ; Bit 3
RI_CMR4_PF_4 EQU 0x00000010 ; Bit 4
RI_CMR4_PF_5 EQU 0x00000020 ; Bit 5
RI_CMR4_PF_6 EQU 0x00000040 ; Bit 6
RI_CMR4_PF_7 EQU 0x00000080 ; Bit 7
RI_CMR4_PF_8 EQU 0x00000100 ; Bit 8
RI_CMR4_PF_9 EQU 0x00000200 ; Bit 9
RI_CMR4_PF_10 EQU 0x00000400 ; Bit 10
RI_CMR4_PF_11 EQU 0x00000800 ; Bit 11
RI_CMR4_PF_12 EQU 0x00001000 ; Bit 12
RI_CMR4_PF_13 EQU 0x00002000 ; Bit 13
RI_CMR4_PF_14 EQU 0x00004000 ; Bit 14
RI_CMR4_PF_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_CICR4 register *******************
RI_CICR4_PF EQU 0x0000FFFF ; PF[15:0] Port F channel identification for capture
RI_CICR4_PF_0 EQU 0x00000001 ; Bit 0
RI_CICR4_PF_1 EQU 0x00000002 ; Bit 1
RI_CICR4_PF_2 EQU 0x00000004 ; Bit 2
RI_CICR4_PF_3 EQU 0x00000008 ; Bit 3
RI_CICR4_PF_4 EQU 0x00000010 ; Bit 4
RI_CICR4_PF_5 EQU 0x00000020 ; Bit 5
RI_CICR4_PF_6 EQU 0x00000040 ; Bit 6
RI_CICR4_PF_7 EQU 0x00000080 ; Bit 7
RI_CICR4_PF_8 EQU 0x00000100 ; Bit 8
RI_CICR4_PF_9 EQU 0x00000200 ; Bit 9
RI_CICR4_PF_10 EQU 0x00000400 ; Bit 10
RI_CICR4_PF_11 EQU 0x00000800 ; Bit 11
RI_CICR4_PF_12 EQU 0x00001000 ; Bit 12
RI_CICR4_PF_13 EQU 0x00002000 ; Bit 13
RI_CICR4_PF_14 EQU 0x00004000 ; Bit 14
RI_CICR4_PF_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_ASMR5 register *******************
RI_ASMR5_PG EQU 0x0000FFFF ; PG[15:0] Port G analog switch mode selection
RI_ASMR5_PG_0 EQU 0x00000001 ; Bit 0
RI_ASMR5_PG_1 EQU 0x00000002 ; Bit 1
RI_ASMR5_PG_2 EQU 0x00000004 ; Bit 2
RI_ASMR5_PG_3 EQU 0x00000008 ; Bit 3
RI_ASMR5_PG_4 EQU 0x00000010 ; Bit 4
RI_ASMR5_PG_5 EQU 0x00000020 ; Bit 5
RI_ASMR5_PG_6 EQU 0x00000040 ; Bit 6
RI_ASMR5_PG_7 EQU 0x00000080 ; Bit 7
RI_ASMR5_PG_8 EQU 0x00000100 ; Bit 8
RI_ASMR5_PG_9 EQU 0x00000200 ; Bit 9
RI_ASMR5_PG_10 EQU 0x00000400 ; Bit 10
RI_ASMR5_PG_11 EQU 0x00000800 ; Bit 11
RI_ASMR5_PG_12 EQU 0x00001000 ; Bit 12
RI_ASMR5_PG_13 EQU 0x00002000 ; Bit 13
RI_ASMR5_PG_14 EQU 0x00004000 ; Bit 14
RI_ASMR5_PG_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_CMR5 register *******************
RI_CMR5_PG EQU 0x0000FFFF ; PG[15:0] Port G channel masking
RI_CMR5_PG_0 EQU 0x00000001 ; Bit 0
RI_CMR5_PG_1 EQU 0x00000002 ; Bit 1
RI_CMR5_PG_2 EQU 0x00000004 ; Bit 2
RI_CMR5_PG_3 EQU 0x00000008 ; Bit 3
RI_CMR5_PG_4 EQU 0x00000010 ; Bit 4
RI_CMR5_PG_5 EQU 0x00000020 ; Bit 5
RI_CMR5_PG_6 EQU 0x00000040 ; Bit 6
RI_CMR5_PG_7 EQU 0x00000080 ; Bit 7
RI_CMR5_PG_8 EQU 0x00000100 ; Bit 8
RI_CMR5_PG_9 EQU 0x00000200 ; Bit 9
RI_CMR5_PG_10 EQU 0x00000400 ; Bit 10
RI_CMR5_PG_11 EQU 0x00000800 ; Bit 11
RI_CMR5_PG_12 EQU 0x00001000 ; Bit 12
RI_CMR5_PG_13 EQU 0x00002000 ; Bit 13
RI_CMR5_PG_14 EQU 0x00004000 ; Bit 14
RI_CMR5_PG_15 EQU 0x00008000 ; Bit 15
;******************* Bit definition for RI_CICR5 register *******************
RI_CICR5_PG EQU 0x0000FFFF ; PG[15:0] Port G channel identification for capture
RI_CICR5_PG_0 EQU 0x00000001 ; Bit 0
RI_CICR5_PG_1 EQU 0x00000002 ; Bit 1
RI_CICR5_PG_2 EQU 0x00000004 ; Bit 2
RI_CICR5_PG_3 EQU 0x00000008 ; Bit 3
RI_CICR5_PG_4 EQU 0x00000010 ; Bit 4
RI_CICR5_PG_5 EQU 0x00000020 ; Bit 5
RI_CICR5_PG_6 EQU 0x00000040 ; Bit 6
RI_CICR5_PG_7 EQU 0x00000080 ; Bit 7
RI_CICR5_PG_8 EQU 0x00000100 ; Bit 8
RI_CICR5_PG_9 EQU 0x00000200 ; Bit 9
RI_CICR5_PG_10 EQU 0x00000400 ; Bit 10
RI_CICR5_PG_11 EQU 0x00000800 ; Bit 11
RI_CICR5_PG_12 EQU 0x00001000 ; Bit 12
RI_CICR5_PG_13 EQU 0x00002000 ; Bit 13
RI_CICR5_PG_14 EQU 0x00004000 ; Bit 14
RI_CICR5_PG_15 EQU 0x00008000 ; Bit 15
END

@ -0,0 +1,429 @@
;********************************************************************************
; SOUBOR : INI_BITS_RTC.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro RTC (obvod realneho casu)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Real-Time Clock (RTC)
;
;****************************************************************************
;******************* Bits definition for RTC_TR register ******************
RTC_TR_PM EQU 0x00400000
RTC_TR_HT EQU 0x00300000
RTC_TR_HT_0 EQU 0x00100000
RTC_TR_HT_1 EQU 0x00200000
RTC_TR_HU EQU 0x000F0000
RTC_TR_HU_0 EQU 0x00010000
RTC_TR_HU_1 EQU 0x00020000
RTC_TR_HU_2 EQU 0x00040000
RTC_TR_HU_3 EQU 0x00080000
RTC_TR_MNT EQU 0x00007000
RTC_TR_MNT_0 EQU 0x00001000
RTC_TR_MNT_1 EQU 0x00002000
RTC_TR_MNT_2 EQU 0x00004000
RTC_TR_MNU EQU 0x00000F00
RTC_TR_MNU_0 EQU 0x00000100
RTC_TR_MNU_1 EQU 0x00000200
RTC_TR_MNU_2 EQU 0x00000400
RTC_TR_MNU_3 EQU 0x00000800
RTC_TR_ST EQU 0x00000070
RTC_TR_ST_0 EQU 0x00000010
RTC_TR_ST_1 EQU 0x00000020
RTC_TR_ST_2 EQU 0x00000040
RTC_TR_SU EQU 0x0000000F
RTC_TR_SU_0 EQU 0x00000001
RTC_TR_SU_1 EQU 0x00000002
RTC_TR_SU_2 EQU 0x00000004
RTC_TR_SU_3 EQU 0x00000008
;******************* Bits definition for RTC_DR register ******************
RTC_DR_YT EQU 0x00F00000
RTC_DR_YT_0 EQU 0x00100000
RTC_DR_YT_1 EQU 0x00200000
RTC_DR_YT_2 EQU 0x00400000
RTC_DR_YT_3 EQU 0x00800000
RTC_DR_YU EQU 0x000F0000
RTC_DR_YU_0 EQU 0x00010000
RTC_DR_YU_1 EQU 0x00020000
RTC_DR_YU_2 EQU 0x00040000
RTC_DR_YU_3 EQU 0x00080000
RTC_DR_WDU EQU 0x0000E000
RTC_DR_WDU_0 EQU 0x00002000
RTC_DR_WDU_1 EQU 0x00004000
RTC_DR_WDU_2 EQU 0x00008000
RTC_DR_MT EQU 0x00001000
RTC_DR_MU EQU 0x00000F00
RTC_DR_MU_0 EQU 0x00000100
RTC_DR_MU_1 EQU 0x00000200
RTC_DR_MU_2 EQU 0x00000400
RTC_DR_MU_3 EQU 0x00000800
RTC_DR_DT EQU 0x00000030
RTC_DR_DT_0 EQU 0x00000010
RTC_DR_DT_1 EQU 0x00000020
RTC_DR_DU EQU 0x0000000F
RTC_DR_DU_0 EQU 0x00000001
RTC_DR_DU_1 EQU 0x00000002
RTC_DR_DU_2 EQU 0x00000004
RTC_DR_DU_3 EQU 0x00000008
;******************* Bits definition for RTC_CR register ******************
RTC_CR_COE EQU 0x00800000
RTC_CR_OSEL EQU 0x00600000
RTC_CR_OSEL_0 EQU 0x00200000
RTC_CR_OSEL_1 EQU 0x00400000
RTC_CR_POL EQU 0x00100000
RTC_CR_COSEL EQU 0x00080000
RTC_CR_BCK EQU 0x00040000
RTC_CR_SUB1H EQU 0x00020000
RTC_CR_ADD1H EQU 0x00010000
RTC_CR_TSIE EQU 0x00008000
RTC_CR_WUTIE EQU 0x00004000
RTC_CR_ALRBIE EQU 0x00002000
RTC_CR_ALRAIE EQU 0x00001000
RTC_CR_TSE EQU 0x00000800
RTC_CR_WUTE EQU 0x00000400
RTC_CR_ALRBE EQU 0x00000200
RTC_CR_ALRAE EQU 0x00000100
RTC_CR_DCE EQU 0x00000080
RTC_CR_FMT EQU 0x00000040
RTC_CR_BYPSHAD EQU 0x00000020
RTC_CR_REFCKON EQU 0x00000010
RTC_CR_TSEDGE EQU 0x00000008
RTC_CR_WUCKSEL EQU 0x00000007
RTC_CR_WUCKSEL_0 EQU 0x00000001
RTC_CR_WUCKSEL_1 EQU 0x00000002
RTC_CR_WUCKSEL_2 EQU 0x00000004
;******************* Bits definition for RTC_ISR register *****************
RTC_ISR_RECALPF EQU 0x00010000
RTC_ISR_TAMP3F EQU 0x00008000
RTC_ISR_TAMP2F EQU 0x00004000
RTC_ISR_TAMP1F EQU 0x00002000
RTC_ISR_TSOVF EQU 0x00001000
RTC_ISR_TSF EQU 0x00000800
RTC_ISR_WUTF EQU 0x00000400
RTC_ISR_ALRBF EQU 0x00000200
RTC_ISR_ALRAF EQU 0x00000100
RTC_ISR_INIT EQU 0x00000080
RTC_ISR_INITF EQU 0x00000040
RTC_ISR_RSF EQU 0x00000020
RTC_ISR_INITS EQU 0x00000010
RTC_ISR_SHPF EQU 0x00000008
RTC_ISR_WUTWF EQU 0x00000004
RTC_ISR_ALRBWF EQU 0x00000002
RTC_ISR_ALRAWF EQU 0x00000001
;******************* Bits definition for RTC_PRER register ****************
RTC_PRER_PREDIV_A EQU 0x007F0000
RTC_PRER_PREDIV_S EQU 0x00007FFF
;******************* Bits definition for RTC_WUTR register ****************
RTC_WUTR_WUT EQU 0x0000FFFF
;******************* Bits definition for RTC_CALIBR register **************
RTC_CALIBR_DCS EQU 0x00000080
RTC_CALIBR_DC EQU 0x0000001F
;******************* Bits definition for RTC_ALRMAR register **************
RTC_ALRMAR_MSK4 EQU 0x80000000
RTC_ALRMAR_WDSEL EQU 0x40000000
RTC_ALRMAR_DT EQU 0x30000000
RTC_ALRMAR_DT_0 EQU 0x10000000
RTC_ALRMAR_DT_1 EQU 0x20000000
RTC_ALRMAR_DU EQU 0x0F000000
RTC_ALRMAR_DU_0 EQU 0x01000000
RTC_ALRMAR_DU_1 EQU 0x02000000
RTC_ALRMAR_DU_2 EQU 0x04000000
RTC_ALRMAR_DU_3 EQU 0x08000000
RTC_ALRMAR_MSK3 EQU 0x00800000
RTC_ALRMAR_PM EQU 0x00400000
RTC_ALRMAR_HT EQU 0x00300000
RTC_ALRMAR_HT_0 EQU 0x00100000
RTC_ALRMAR_HT_1 EQU 0x00200000
RTC_ALRMAR_HU EQU 0x000F0000
RTC_ALRMAR_HU_0 EQU 0x00010000
RTC_ALRMAR_HU_1 EQU 0x00020000
RTC_ALRMAR_HU_2 EQU 0x00040000
RTC_ALRMAR_HU_3 EQU 0x00080000
RTC_ALRMAR_MSK2 EQU 0x00008000
RTC_ALRMAR_MNT EQU 0x00007000
RTC_ALRMAR_MNT_0 EQU 0x00001000
RTC_ALRMAR_MNT_1 EQU 0x00002000
RTC_ALRMAR_MNT_2 EQU 0x00004000
RTC_ALRMAR_MNU EQU 0x00000F00
RTC_ALRMAR_MNU_0 EQU 0x00000100
RTC_ALRMAR_MNU_1 EQU 0x00000200
RTC_ALRMAR_MNU_2 EQU 0x00000400
RTC_ALRMAR_MNU_3 EQU 0x00000800
RTC_ALRMAR_MSK1 EQU 0x00000080
RTC_ALRMAR_ST EQU 0x00000070
RTC_ALRMAR_ST_0 EQU 0x00000010
RTC_ALRMAR_ST_1 EQU 0x00000020
RTC_ALRMAR_ST_2 EQU 0x00000040
RTC_ALRMAR_SU EQU 0x0000000F
RTC_ALRMAR_SU_0 EQU 0x00000001
RTC_ALRMAR_SU_1 EQU 0x00000002
RTC_ALRMAR_SU_2 EQU 0x00000004
RTC_ALRMAR_SU_3 EQU 0x00000008
;******************* Bits definition for RTC_ALRMBR register **************
RTC_ALRMBR_MSK4 EQU 0x80000000
RTC_ALRMBR_WDSEL EQU 0x40000000
RTC_ALRMBR_DT EQU 0x30000000
RTC_ALRMBR_DT_0 EQU 0x10000000
RTC_ALRMBR_DT_1 EQU 0x20000000
RTC_ALRMBR_DU EQU 0x0F000000
RTC_ALRMBR_DU_0 EQU 0x01000000
RTC_ALRMBR_DU_1 EQU 0x02000000
RTC_ALRMBR_DU_2 EQU 0x04000000
RTC_ALRMBR_DU_3 EQU 0x08000000
RTC_ALRMBR_MSK3 EQU 0x00800000
RTC_ALRMBR_PM EQU 0x00400000
RTC_ALRMBR_HT EQU 0x00300000
RTC_ALRMBR_HT_0 EQU 0x00100000
RTC_ALRMBR_HT_1 EQU 0x00200000
RTC_ALRMBR_HU EQU 0x000F0000
RTC_ALRMBR_HU_0 EQU 0x00010000
RTC_ALRMBR_HU_1 EQU 0x00020000
RTC_ALRMBR_HU_2 EQU 0x00040000
RTC_ALRMBR_HU_3 EQU 0x00080000
RTC_ALRMBR_MSK2 EQU 0x00008000
RTC_ALRMBR_MNT EQU 0x00007000
RTC_ALRMBR_MNT_0 EQU 0x00001000
RTC_ALRMBR_MNT_1 EQU 0x00002000
RTC_ALRMBR_MNT_2 EQU 0x00004000
RTC_ALRMBR_MNU EQU 0x00000F00
RTC_ALRMBR_MNU_0 EQU 0x00000100
RTC_ALRMBR_MNU_1 EQU 0x00000200
RTC_ALRMBR_MNU_2 EQU 0x00000400
RTC_ALRMBR_MNU_3 EQU 0x00000800
RTC_ALRMBR_MSK1 EQU 0x00000080
RTC_ALRMBR_ST EQU 0x00000070
RTC_ALRMBR_ST_0 EQU 0x00000010
RTC_ALRMBR_ST_1 EQU 0x00000020
RTC_ALRMBR_ST_2 EQU 0x00000040
RTC_ALRMBR_SU EQU 0x0000000F
RTC_ALRMBR_SU_0 EQU 0x00000001
RTC_ALRMBR_SU_1 EQU 0x00000002
RTC_ALRMBR_SU_2 EQU 0x00000004
RTC_ALRMBR_SU_3 EQU 0x00000008
;******************* Bits definition for RTC_WPR register *****************
RTC_WPR_KEY EQU 0x000000FF
;******************* Bits definition for RTC_SSR register *****************
RTC_SSR_SS EQU 0x0000FFFF
;******************* Bits definition for RTC_SHIFTR register **************
RTC_SHIFTR_SUBFS EQU 0x00007FFF
RTC_SHIFTR_ADD1S EQU 0x80000000
;******************* Bits definition for RTC_TSTR register ****************
RTC_TSTR_PM EQU 0x00400000
RTC_TSTR_HT EQU 0x00300000
RTC_TSTR_HT_0 EQU 0x00100000
RTC_TSTR_HT_1 EQU 0x00200000
RTC_TSTR_HU EQU 0x000F0000
RTC_TSTR_HU_0 EQU 0x00010000
RTC_TSTR_HU_1 EQU 0x00020000
RTC_TSTR_HU_2 EQU 0x00040000
RTC_TSTR_HU_3 EQU 0x00080000
RTC_TSTR_MNT EQU 0x00007000
RTC_TSTR_MNT_0 EQU 0x00001000
RTC_TSTR_MNT_1 EQU 0x00002000
RTC_TSTR_MNT_2 EQU 0x00004000
RTC_TSTR_MNU EQU 0x00000F00
RTC_TSTR_MNU_0 EQU 0x00000100
RTC_TSTR_MNU_1 EQU 0x00000200
RTC_TSTR_MNU_2 EQU 0x00000400
RTC_TSTR_MNU_3 EQU 0x00000800
RTC_TSTR_ST EQU 0x00000070
RTC_TSTR_ST_0 EQU 0x00000010
RTC_TSTR_ST_1 EQU 0x00000020
RTC_TSTR_ST_2 EQU 0x00000040
RTC_TSTR_SU EQU 0x0000000F
RTC_TSTR_SU_0 EQU 0x00000001
RTC_TSTR_SU_1 EQU 0x00000002
RTC_TSTR_SU_2 EQU 0x00000004
RTC_TSTR_SU_3 EQU 0x00000008
;******************* Bits definition for RTC_TSDR register ****************
RTC_TSDR_WDU EQU 0x0000E000
RTC_TSDR_WDU_0 EQU 0x00002000
RTC_TSDR_WDU_1 EQU 0x00004000
RTC_TSDR_WDU_2 EQU 0x00008000
RTC_TSDR_MT EQU 0x00001000
RTC_TSDR_MU EQU 0x00000F00
RTC_TSDR_MU_0 EQU 0x00000100
RTC_TSDR_MU_1 EQU 0x00000200
RTC_TSDR_MU_2 EQU 0x00000400
RTC_TSDR_MU_3 EQU 0x00000800
RTC_TSDR_DT EQU 0x00000030
RTC_TSDR_DT_0 EQU 0x00000010
RTC_TSDR_DT_1 EQU 0x00000020
RTC_TSDR_DU EQU 0x0000000F
RTC_TSDR_DU_0 EQU 0x00000001
RTC_TSDR_DU_1 EQU 0x00000002
RTC_TSDR_DU_2 EQU 0x00000004
RTC_TSDR_DU_3 EQU 0x00000008
;******************* Bits definition for RTC_TSSSR register ***************
RTC_TSSSR_SS EQU 0x0000FFFF
;******************* Bits definition for RTC_CAL register ****************
RTC_CALR_CALP EQU 0x00008000
RTC_CALR_CALW8 EQU 0x00004000
RTC_CALR_CALW16 EQU 0x00002000
RTC_CALR_CALM EQU 0x000001FF
RTC_CALR_CALM_0 EQU 0x00000001
RTC_CALR_CALM_1 EQU 0x00000002
RTC_CALR_CALM_2 EQU 0x00000004
RTC_CALR_CALM_3 EQU 0x00000008
RTC_CALR_CALM_4 EQU 0x00000010
RTC_CALR_CALM_5 EQU 0x00000020
RTC_CALR_CALM_6 EQU 0x00000040
RTC_CALR_CALM_7 EQU 0x00000080
RTC_CALR_CALM_8 EQU 0x00000100
;******************* Bits definition for RTC_TAFCR register ***************
RTC_TAFCR_ALARMOUTTYPE EQU 0x00040000
RTC_TAFCR_TAMPPUDIS EQU 0x00008000
RTC_TAFCR_TAMPPRCH EQU 0x00006000
RTC_TAFCR_TAMPPRCH_0 EQU 0x00002000
RTC_TAFCR_TAMPPRCH_1 EQU 0x00004000
RTC_TAFCR_TAMPFLT EQU 0x00001800
RTC_TAFCR_TAMPFLT_0 EQU 0x00000800
RTC_TAFCR_TAMPFLT_1 EQU 0x00001000
RTC_TAFCR_TAMPFREQ EQU 0x00000700
RTC_TAFCR_TAMPFREQ_0 EQU 0x00000100
RTC_TAFCR_TAMPFREQ_1 EQU 0x00000200
RTC_TAFCR_TAMPFREQ_2 EQU 0x00000400
RTC_TAFCR_TAMPTS EQU 0x00000080
RTC_TAFCR_TAMP3TRG EQU 0x00000040
RTC_TAFCR_TAMP3E EQU 0x00000020
RTC_TAFCR_TAMP2TRG EQU 0x00000010
RTC_TAFCR_TAMP2E EQU 0x00000008
RTC_TAFCR_TAMPIE EQU 0x00000004
RTC_TAFCR_TAMP1TRG EQU 0x00000002
RTC_TAFCR_TAMP1E EQU 0x00000001
;******************* Bits definition for RTC_ALRMASSR register ************
RTC_ALRMASSR_MASKSS EQU 0x0F000000
RTC_ALRMASSR_MASKSS_0 EQU 0x01000000
RTC_ALRMASSR_MASKSS_1 EQU 0x02000000
RTC_ALRMASSR_MASKSS_2 EQU 0x04000000
RTC_ALRMASSR_MASKSS_3 EQU 0x08000000
RTC_ALRMASSR_SS EQU 0x00007FFF
;******************* Bits definition for RTC_ALRMBSSR register ************
RTC_ALRMBSSR_MASKSS EQU 0x0F000000
RTC_ALRMBSSR_MASKSS_0 EQU 0x01000000
RTC_ALRMBSSR_MASKSS_1 EQU 0x02000000
RTC_ALRMBSSR_MASKSS_2 EQU 0x04000000
RTC_ALRMBSSR_MASKSS_3 EQU 0x08000000
RTC_ALRMBSSR_SS EQU 0x00007FFF
;******************* Bits definition for RTC_BKP0R register ***************
RTC_BKP0R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP1R register ***************
RTC_BKP1R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP2R register ***************
RTC_BKP2R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP3R register ***************
RTC_BKP3R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP4R register ***************
RTC_BKP4R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP5R register ***************
RTC_BKP5R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP6R register ***************
RTC_BKP6R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP7R register ***************
RTC_BKP7R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP8R register ***************
RTC_BKP8R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP9R register ***************
RTC_BKP9R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP10R register **************
RTC_BKP10R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP11R register **************
RTC_BKP11R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP12R register **************
RTC_BKP12R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP13R register **************
RTC_BKP13R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP14R register **************
RTC_BKP14R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP15R register **************
RTC_BKP15R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP16R register **************
RTC_BKP16R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP17R register **************
RTC_BKP17R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP18R register **************
RTC_BKP18R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP19R register **************
RTC_BKP19R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP20R register **************
RTC_BKP20R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP21R register **************
RTC_BKP21R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP22R register **************
RTC_BKP22R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP23R register **************
RTC_BKP23R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP24R register **************
RTC_BKP24R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP25R register **************
RTC_BKP25R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP26R register **************
RTC_BKP26R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP27R register **************
RTC_BKP27R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP28R register **************
RTC_BKP28R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP29R register **************
RTC_BKP29R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP30R register **************
RTC_BKP30R EQU 0xFFFFFFFF
;******************* Bits definition for RTC_BKP31R register **************
RTC_BKP31R EQU 0xFFFFFFFF
END

@ -0,0 +1,142 @@
;********************************************************************************
; SOUBOR : INI_BITS_SCB.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro SCB (ovladani systemu + hw info)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; System Control Block (SCB)
;
;****************************************************************************
;***************** Bit definition for SCB_CPUID register ******************
SCB_CPUID_REVISION EQU 0x0000000F ; Implementation defined revision number
SCB_CPUID_PARTNO EQU 0x0000FFF0 ; Number of processor within family
SCB_CPUID_Constant EQU 0x000F0000 ; Reads as 0x0F
SCB_CPUID_VARIANT EQU 0x00F00000 ; Implementation defined variant number
SCB_CPUID_IMPLEMENTER EQU 0xFF000000 ; Implementer code. ARM is 0x41
;****************** Bit definition for SCB_ICSR register ******************
SCB_ICSR_VECTACTIVE EQU 0x000001FF ; Active ISR number field
SCB_ICSR_RETTOBASE EQU 0x00000800 ; All active exceptions minus the IPSR_current_exception yields the empty set
SCB_ICSR_VECTPENDING EQU 0x003FF000 ; Pending ISR number field
SCB_ICSR_ISRPENDING EQU 0x00400000 ; Interrupt pending flag
SCB_ICSR_ISRPREEMPT EQU 0x00800000 ; It indicates that a pending interrupt becomes active in the next running cycle
SCB_ICSR_PENDSTCLR EQU 0x02000000 ; Clear pending SysTick bit
SCB_ICSR_PENDSTSET EQU 0x04000000 ; Set pending SysTick bit
SCB_ICSR_PENDSVCLR EQU 0x08000000 ; Clear pending pendSV bit
SCB_ICSR_PENDSVSET EQU 0x10000000 ; Set pending pendSV bit
SCB_ICSR_NMIPENDSET EQU 0x80000000 ; Set pending NMI bit
;****************** Bit definition for SCB_VTOR register ******************
SCB_VTOR_TBLOFF EQU 0x1FFFFF80 ; Vector table base offset field
SCB_VTOR_TBLBASE EQU 0x20000000 ; Table base in code(0) or RAM(1)
; ***************** Bit definition for SCB_AIRCR register ******************
SCB_AIRCR_VECTKEY EQU 0x05FA0000 ; Value required to enable write to this register
SCB_AIRCR_VECTRESET EQU 0x00000001 ; System Reset bit
SCB_AIRCR_VECTCLRACTIVE EQU 0x00000002 ; Clear active vector bit
SCB_AIRCR_SYSRESETREQ EQU 0x00000004 ; Requests chip control logic to generate a reset
SCB_AIRCR_PRIGROUP EQU 0x00000700 ; PRIGROUP[2:0] bits (Priority group)
SCB_AIRCR_PRIGROUP_0 EQU 0x00000100 ; Bit 0
SCB_AIRCR_PRIGROUP_1 EQU 0x00000200 ; Bit 1
SCB_AIRCR_PRIGROUP_2 EQU 0x00000400 ; Bit 2
; prority group configuration
SCB_AIRCR_PRIGROUP0 EQU 0x00000000 ; Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)
SCB_AIRCR_PRIGROUP1 EQU 0x00000100 ; Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)
SCB_AIRCR_PRIGROUP2 EQU 0x00000200 ; Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)
SCB_AIRCR_PRIGROUP3 EQU 0x00000300 ; Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)
SCB_AIRCR_PRIGROUP4 EQU 0x00000400 ; Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)
SCB_AIRCR_PRIGROUP5 EQU 0x00000500 ; Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)
SCB_AIRCR_PRIGROUP6 EQU 0x00000600 ; Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)
SCB_AIRCR_PRIGROUP7 EQU 0x00000700 ; Priority group=7 (no pre-emption priority, 8 bits of subpriority)
SCB_AIRCR_ENDIANESS EQU 0x00008000 ; Data endianness bit
SCB_AIRCR_VECTKEY EQU 0xFFFF0000 ; Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)
;****************** Bit definition for SCB_SCR register *******************
SCB_SCR_SLEEPONEXIT EQU 0x02 ; Sleep on exit bit
SCB_SCR_SLEEPDEEP EQU 0x04 ; Sleep deep bit
SCB_SCR_SEVONPEND EQU 0x10 ; Wake up from WFE
;******************* Bit definition for SCB_CCR register ******************
SCB_CCR_NONBASETHRDENA EQU 0x0001 ; Thread mode can be entered from any level in Handler mode by controlled return value
SCB_CCR_USERSETMPEND EQU 0x0002 ; Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception
SCB_CCR_UNALIGN_TRP EQU 0x0008 ; Trap for unaligned access
SCB_CCR_DIV_0_TRP EQU 0x0010 ; Trap on Divide by 0
SCB_CCR_BFHFNMIGN EQU 0x0100 ; Handlers running at priority -1 and -2
SCB_CCR_STKALIGN EQU 0x0200 ; On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned
;****************** Bit definition for SCB_SHPR register *******************
SCB_SHPR_PRI_N EQU 0x000000FF ; Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor
SCB_SHPR_PRI_N1 EQU 0x0000FF00 ; Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved
SCB_SHPR_PRI_N2 EQU 0x00FF0000 ; Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV
SCB_SHPR_PRI_N3 EQU 0xFF000000 ; Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick
;***************** Bit definition for SCB_SHCSR register ******************
SCB_SHCSR_MEMFAULTACT EQU 0x00000001 ; MemManage is active
SCB_SHCSR_BUSFAULTACT EQU 0x00000002 ; BusFault is active
SCB_SHCSR_USGFAULTACT EQU 0x00000008 ; UsageFault is active
SCB_SHCSR_SVCALLACT EQU 0x00000080 ; SVCall is active
SCB_SHCSR_MONITORACT EQU 0x00000100 ; Monitor is active
SCB_SHCSR_PENDSVACT EQU 0x00000400 ; PendSV is active
SCB_SHCSR_SYSTICKACT EQU 0x00000800 ; SysTick is active
SCB_SHCSR_USGFAULTPENDED EQU 0x00001000 ; Usage Fault is pended
SCB_SHCSR_MEMFAULTPENDED EQU 0x00002000 ; MemManage is pended
SCB_SHCSR_BUSFAULTPENDED EQU 0x00004000 ; Bus Fault is pended
SCB_SHCSR_SVCALLPENDED EQU 0x00008000 ; SVCall is pended
SCB_SHCSR_MEMFAULTENA EQU 0x00010000 ; MemManage enable
SCB_SHCSR_BUSFAULTENA EQU 0x00020000 ; Bus Fault enable
SCB_SHCSR_USGFAULTENA EQU 0x00040000 ; UsageFault enable
;****************** Bit definition for SCB_CFSR register ******************
; MFSR
SCB_CFSR_IACCVIOL EQU 0x00000001 ; Instruction access violation
SCB_CFSR_DACCVIOL EQU 0x00000002 ; Data access violation
SCB_CFSR_MUNSTKERR EQU 0x00000008 ; Unstacking error
SCB_CFSR_MSTKERR EQU 0x00000010 ; Stacking error
SCB_CFSR_MMARVALID EQU 0x00000080 ; Memory Manage Address Register address valid flag
; BFSR
SCB_CFSR_IBUSERR EQU 0x00000100 ; Instruction bus error flag
SCB_CFSR_PRECISERR EQU 0x00000200 ; Precise data bus error
SCB_CFSR_IMPRECISERR EQU 0x00000400 ; Imprecise data bus error
SCB_CFSR_UNSTKERR EQU 0x00000800 ; Unstacking error
SCB_CFSR_STKERR EQU 0x00001000 ; Stacking error
SCB_CFSR_BFARVALID EQU 0x00008000 ; Bus Fault Address Register address valid flag
; UFSR
SCB_CFSR_UNDEFINSTR EQU 0x00010000 ; The processor attempt to excecute an undefined instruction
SCB_CFSR_INVSTATE EQU 0x00020000 ; Invalid combination of EPSR and instruction
SCB_CFSR_INVPC EQU 0x00040000 ; Attempt to load EXC_RETURN into pc illegally
SCB_CFSR_NOCP EQU 0x00080000 ; Attempt to use a coprocessor instruction
SCB_CFSR_UNALIGNED EQU 0x01000000 ; Fault occurs when there is an attempt to make an unaligned memory access
SCB_CFSR_DIVBYZERO EQU 0x02000000 ; Fault occurs when SDIV or DIV instruction is used with a divisor of 0
;****************** Bit definition for SCB_HFSR register ******************
SCB_HFSR_VECTTBL EQU 0x00000002 ; Fault occures because of vector table read on exception processing
SCB_HFSR_FORCED EQU 0x40000000 ; Hard Fault activated when a configurable Fault was received and cannot activate
SCB_HFSR_DEBUGEVT EQU 0x80000000 ; Fault related to debug
;****************** Bit definition for SCB_DFSR register ******************
SCB_DFSR_HALTED EQU 0x01 ; Halt request flag
SCB_DFSR_BKPT EQU 0x02 ; BKPT flag
SCB_DFSR_DWTTRAP EQU 0x04 ; Data Watchpoint and Trace (DWT) flag
SCB_DFSR_VCATCH EQU 0x08 ; Vector catch flag
SCB_DFSR_EXTERNAL EQU 0x10 ; External debug request flag
;****************** Bit definition for SCB_MMFAR register *****************
SCB_MMFAR_ADDRESS EQU 0xFFFFFFFF ; Mem Manage fault address field
;****************** Bit definition for SCB_BFAR register ******************
SCB_BFAR_ADDRESS EQU 0xFFFFFFFF ; Bus fault address field
;****************** Bit definition for SCB_afsr register ******************
SCB_AFSR_IMPDEF EQU 0xFFFFFFFF ; Implementation defined
END

@ -0,0 +1,170 @@
;********************************************************************************
; SOUBOR : INI_BITS_SDIO.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro SDIO
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; SD host Interface
;
;****************************************************************************
;***************** Bit definition for SDIO_POWER register *****************
SDIO_POWER_PWRCTRL EQU 0x03 ; PWRCTRL[1:0] bits (Power supply control bits)
SDIO_POWER_PWRCTRL_0 EQU 0x01 ; Bit 0
SDIO_POWER_PWRCTRL_1 EQU 0x02 ; Bit 1
;***************** Bit definition for SDIO_CLKCR register *****************
SDIO_CLKCR_CLKDIV EQU 0x00FF ; Clock divide factor
SDIO_CLKCR_CLKEN EQU 0x0100 ; Clock enable bit
SDIO_CLKCR_PWRSAV EQU 0x0200 ; Power saving configuration bit
SDIO_CLKCR_BYPASS EQU 0x0400 ; Clock divider bypass enable bit
SDIO_CLKCR_WIDBUS EQU 0x1800 ; WIDBUS[1:0] bits (Wide bus mode enable bit)
SDIO_CLKCR_WIDBUS_0 EQU 0x0800 ; Bit 0
SDIO_CLKCR_WIDBUS_1 EQU 0x1000 ; Bit 1
SDIO_CLKCR_NEGEDGE EQU 0x2000 ; SDIO_CK dephasing selection bit
SDIO_CLKCR_HWFC_EN EQU 0x4000 ; HW Flow Control enable
;****************** Bit definition for SDIO_ARG register ******************
SDIO_ARG_CMDARG EQU 0xFFFFFFFF ; Command argument
;****************** Bit definition for SDIO_CMD register ******************
SDIO_CMD_CMDINDEX EQU 0x003F ; Command Index
SDIO_CMD_WAITRESP EQU 0x00C0 ; WAITRESP[1:0] bits (Wait for response bits)
SDIO_CMD_WAITRESP_0 EQU 0x0040 ; Bit 0
SDIO_CMD_WAITRESP_1 EQU 0x0080 ; Bit 1
SDIO_CMD_WAITINT EQU 0x0100 ; CPSM Waits for Interrupt Request
SDIO_CMD_WAITPEND EQU 0x0200 ; CPSM Waits for ends of data transfer (CmdPend internal signal)
SDIO_CMD_CPSMEN EQU 0x0400 ; Command path state machine (CPSM) Enable bit
SDIO_CMD_SDIOSUSPEND EQU 0x0800 ; SD I/O suspend command
SDIO_CMD_ENCMDCOMPL EQU 0x1000 ; Enable CMD completion
SDIO_CMD_NIEN EQU 0x2000 ; Not Interrupt Enable
SDIO_CMD_CEATACMD EQU 0x4000 ; CE-ATA command
;**************** Bit definition for SDIO_RESPCMD register ****************
SDIO_RESPCMD_RESPCMD EQU 0x3F ; Response command index
;***************** Bit definition for SDIO_RESP0 register *****************
SDIO_RESP0_CARDSTATUS0 EQU 0xFFFFFFFF ; Card Status
;***************** Bit definition for SDIO_RESP1 register *****************
SDIO_RESP1_CARDSTATUS1 EQU 0xFFFFFFFF ; Card Status
;***************** Bit definition for SDIO_RESP2 register *****************
SDIO_RESP2_CARDSTATUS2 EQU 0xFFFFFFFF ; Card Status
;***************** Bit definition for SDIO_RESP3 register *****************
SDIO_RESP3_CARDSTATUS3 EQU 0xFFFFFFFF ; Card Status
;***************** Bit definition for SDIO_RESP4 register *****************
SDIO_RESP4_CARDSTATUS4 EQU 0xFFFFFFFF ; Card Status
;***************** Bit definition for SDIO_DTIMER register ****************
SDIO_DTIMER_DATATIME EQU 0xFFFFFFFF ; Data timeout period.
;***************** Bit definition for SDIO_DLEN register ******************
SDIO_DLEN_DATALENGTH EQU 0x01FFFFFF ; Data length value
;***************** Bit definition for SDIO_DCTRL register *****************
SDIO_DCTRL_DTEN EQU 0x0001 ; Data transfer enabled bit
SDIO_DCTRL_DTDIR EQU 0x0002 ; Data transfer direction selection
SDIO_DCTRL_DTMODE EQU 0x0004 ; Data transfer mode selection
SDIO_DCTRL_DMAEN EQU 0x0008 ; DMA enabled bit
SDIO_DCTRL_DBLOCKSIZE EQU 0x00F0 ; DBLOCKSIZE[3:0] bits (Data block size)
SDIO_DCTRL_DBLOCKSIZE_0 EQU 0x0010 ; Bit 0
SDIO_DCTRL_DBLOCKSIZE_1 EQU 0x0020 ; Bit 1
SDIO_DCTRL_DBLOCKSIZE_2 EQU 0x0040 ; Bit 2
SDIO_DCTRL_DBLOCKSIZE_3 EQU 0x0080 ; Bit 3
SDIO_DCTRL_RWSTART EQU 0x0100 ; Read wait start
SDIO_DCTRL_RWSTOP EQU 0x0200 ; Read wait stop
SDIO_DCTRL_RWMOD EQU 0x0400 ; Read wait mode
SDIO_DCTRL_SDIOEN EQU 0x0800 ; SD I/O enable functions
;***************** Bit definition for SDIO_DCOUNT register ****************
SDIO_DCOUNT_DATACOUNT EQU 0x01FFFFFF ; Data count value
;***************** Bit definition for SDIO_STA register *******************
SDIO_STA_CCRCFAIL EQU 0x00000001 ; Command response received (CRC check failed)
SDIO_STA_DCRCFAIL EQU 0x00000002 ; Data block sent/received (CRC check failed)
SDIO_STA_CTIMEOUT EQU 0x00000004 ; Command response timeout
SDIO_STA_DTIMEOUT EQU 0x00000008 ; Data timeout
SDIO_STA_TXUNDERR EQU 0x00000010 ; Transmit FIFO underrun error
SDIO_STA_RXOVERR EQU 0x00000020 ; Received FIFO overrun error
SDIO_STA_CMDREND EQU 0x00000040 ; Command response received (CRC check passed)
SDIO_STA_CMDSENT EQU 0x00000080 ; Command sent (no response required)
SDIO_STA_DATAEND EQU 0x00000100 ; Data end (data counter, SDIDCOUNT, is zero)
SDIO_STA_STBITERR EQU 0x00000200 ; Start bit not detected on all data signals in wide bus mode
SDIO_STA_DBCKEND EQU 0x00000400 ; Data block sent/received (CRC check passed)
SDIO_STA_CMDACT EQU 0x00000800 ; Command transfer in progress
SDIO_STA_TXACT EQU 0x00001000 ; Data transmit in progress
SDIO_STA_RXACT EQU 0x00002000 ; Data receive in progress
SDIO_STA_TXFIFOHE EQU 0x00004000 ; Transmit FIFO Half Empty: at least 8 words can be written into the FIFO
SDIO_STA_RXFIFOHF EQU 0x00008000 ; Receive FIFO Half Full: there are at least 8 words in the FIFO
SDIO_STA_TXFIFOF EQU 0x00010000 ; Transmit FIFO full
SDIO_STA_RXFIFOF EQU 0x00020000 ; Receive FIFO full
SDIO_STA_TXFIFOE EQU 0x00040000 ; Transmit FIFO empty
SDIO_STA_RXFIFOE EQU 0x00080000 ; Receive FIFO empty
SDIO_STA_TXDAVL EQU 0x00100000 ; Data available in transmit FIFO
SDIO_STA_RXDAVL EQU 0x00200000 ; Data available in receive FIFO
SDIO_STA_SDIOIT EQU 0x00400000 ; SDIO interrupt received
SDIO_STA_CEATAEND EQU 0x00800000 ; CE-ATA command completion signal received for CMD61
;****************** Bit definition for SDIO_ICR register ******************
SDIO_ICR_CCRCFAILC EQU 0x00000001 ; CCRCFAIL flag clear bit
SDIO_ICR_DCRCFAILC EQU 0x00000002 ; DCRCFAIL flag clear bit
SDIO_ICR_CTIMEOUTC EQU 0x00000004 ; CTIMEOUT flag clear bit
SDIO_ICR_DTIMEOUTC EQU 0x00000008 ; DTIMEOUT flag clear bit
SDIO_ICR_TXUNDERRC EQU 0x00000010 ; TXUNDERR flag clear bit
SDIO_ICR_RXOVERRC EQU 0x00000020 ; RXOVERR flag clear bit
SDIO_ICR_CMDRENDC EQU 0x00000040 ; CMDREND flag clear bit
SDIO_ICR_CMDSENTC EQU 0x00000080 ; CMDSENT flag clear bit
SDIO_ICR_DATAENDC EQU 0x00000100 ; DATAEND flag clear bit
SDIO_ICR_STBITERRC EQU 0x00000200 ; STBITERR flag clear bit
SDIO_ICR_DBCKENDC EQU 0x00000400 ; DBCKEND flag clear bit
SDIO_ICR_SDIOITC EQU 0x00400000 ; SDIOIT flag clear bit
SDIO_ICR_CEATAENDC EQU 0x00800000 ; CEATAEND flag clear bit
;***************** Bit definition for SDIO_MASK register ******************
SDIO_MASK_CCRCFAILIE EQU 0x00000001 ; Command CRC Fail Interrupt Enable
SDIO_MASK_DCRCFAILIE EQU 0x00000002 ; Data CRC Fail Interrupt Enable
SDIO_MASK_CTIMEOUTIE EQU 0x00000004 ; Command TimeOut Interrupt Enable
SDIO_MASK_DTIMEOUTIE EQU 0x00000008 ; Data TimeOut Interrupt Enable
SDIO_MASK_TXUNDERRIE EQU 0x00000010 ; Tx FIFO UnderRun Error Interrupt Enable
SDIO_MASK_RXOVERRIE EQU 0x00000020 ; Rx FIFO OverRun Error Interrupt Enable
SDIO_MASK_CMDRENDIE EQU 0x00000040 ; Command Response Received Interrupt Enable
SDIO_MASK_CMDSENTIE EQU 0x00000080 ; Command Sent Interrupt Enable
SDIO_MASK_DATAENDIE EQU 0x00000100 ; Data End Interrupt Enable
SDIO_MASK_STBITERRIE EQU 0x00000200 ; Start Bit Error Interrupt Enable
SDIO_MASK_DBCKENDIE EQU 0x00000400 ; Data Block End Interrupt Enable
SDIO_MASK_CMDACTIE EQU 0x00000800 ; Command Acting Interrupt Enable
SDIO_MASK_TXACTIE EQU 0x00001000 ; Data Transmit Acting Interrupt Enable
SDIO_MASK_RXACTIE EQU 0x00002000 ; Data receive acting interrupt enabled
SDIO_MASK_TXFIFOHEIE EQU 0x00004000 ; Tx FIFO Half Empty interrupt Enable
SDIO_MASK_RXFIFOHFIE EQU 0x00008000 ; Rx FIFO Half Full interrupt Enable
SDIO_MASK_TXFIFOFIE EQU 0x00010000 ; Tx FIFO Full interrupt Enable
SDIO_MASK_RXFIFOFIE EQU 0x00020000 ; Rx FIFO Full interrupt Enable
SDIO_MASK_TXFIFOEIE EQU 0x00040000 ; Tx FIFO Empty interrupt Enable
SDIO_MASK_RXFIFOEIE EQU 0x00080000 ; Rx FIFO Empty interrupt Enable
SDIO_MASK_TXDAVLIE EQU 0x00100000 ; Data available in Tx FIFO interrupt Enable
SDIO_MASK_RXDAVLIE EQU 0x00200000 ; Data available in Rx FIFO interrupt Enable
SDIO_MASK_SDIOITIE EQU 0x00400000 ; SDIO Mode Interrupt Received interrupt Enable
SDIO_MASK_CEATAENDIE EQU 0x00800000 ; CE-ATA command completion signal received Interrupt Enable
;**************** Bit definition for SDIO_FIFOCNT register ****************
SDIO_FIFOCNT_FIFOCOUNT EQU 0x00FFFFFF ; Remaining number of words to be written to or read from the FIFO
;***************** Bit definition for SDIO_FIFO register ******************
SDIO_FIFO_FIFODATA EQU 0xFFFFFFFF ; Receive and transmit FIFO data
END

@ -0,0 +1,96 @@
;********************************************************************************
; SOUBOR : INI_BITS_SPI.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro SPI
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Serial Peripheral Interface (SPI)
;
;****************************************************************************
;****************** Bit definition for SPI_CR1 register *******************
SPI_CR1_CPHA EQU 0x0001 ; Clock Phase
SPI_CR1_CPOL EQU 0x0002 ; Clock Polarity
SPI_CR1_MSTR EQU 0x0004 ; Master Selection
SPI_CR1_BR EQU 0x0038 ; BR[2:0] bits (Baud Rate Control)
SPI_CR1_BR_0 EQU 0x0008 ; Bit 0
SPI_CR1_BR_1 EQU 0x0010 ; Bit 1
SPI_CR1_BR_2 EQU 0x0020 ; Bit 2
SPI_CR1_SPE EQU 0x0040 ; SPI Enable
SPI_CR1_LSBFIRST EQU 0x0080 ; Frame Format
SPI_CR1_SSI EQU 0x0100 ; Internal slave select
SPI_CR1_SSM EQU 0x0200 ; Software slave management
SPI_CR1_RXONLY EQU 0x0400 ; Receive only
SPI_CR1_DFF EQU 0x0800 ; Data Frame Format
SPI_CR1_CRCNEXT EQU 0x1000 ; Transmit CRC next
SPI_CR1_CRCEN EQU 0x2000 ; Hardware CRC calculation enable
SPI_CR1_BIDIOE EQU 0x4000 ; Output enable in bidirectional mode
SPI_CR1_BIDIMODE EQU 0x8000 ; Bidirectional data mode enable
;****************** Bit definition for SPI_CR2 register *******************
SPI_CR2_RXDMAEN EQU 0x01 ; Rx Buffer DMA Enable
SPI_CR2_TXDMAEN EQU 0x02 ; Tx Buffer DMA Enable
SPI_CR2_SSOE EQU 0x04 ; SS Output Enable
SPI_CR2_FRF EQU 0x08 ; Frame format
SPI_CR2_ERRIE EQU 0x20 ; Error Interrupt Enable
SPI_CR2_RXNEIE EQU 0x40 ; RX buffer Not Empty Interrupt Enable
SPI_CR2_TXEIE EQU 0x80 ; Tx buffer Empty Interrupt Enable
;******************* Bit definition for SPI_SR register *******************
SPI_SR_RXNE EQU 0x01 ; Receive buffer Not Empty
SPI_SR_TXE EQU 0x02 ; Transmit buffer Empty
SPI_SR_CHSIDE EQU 0x04 ; Channel side
SPI_SR_UDR EQU 0x08 ; Underrun flag
SPI_SR_CRCERR EQU 0x10 ; CRC Error flag
SPI_SR_MODF EQU 0x20 ; Mode fault
SPI_SR_OVR EQU 0x40 ; Overrun flag
SPI_SR_BSY EQU 0x80 ; Busy flag
;******************* Bit definition for SPI_DR register *******************
SPI_DR_DR EQU 0xFFFF ; Data Register
;****************** Bit definition for SPI_CRCPR register *****************
SPI_CRCPR_CRCPOLY EQU 0xFFFF ; CRC polynomial register
;***************** Bit definition for SPI_RXCRCR register *****************
SPI_RXCRCR_RXCRC EQU 0xFFFF ; Rx CRC Register
;***************** Bit definition for SPI_TXCRCR register *****************
SPI_TXCRCR_TXCRC EQU 0xFFFF ; Tx CRC Register
;***************** Bit definition for SPI_I2SCFGR register ****************
SPI_I2SCFGR_CHLEN EQU 0x0001 ; Channel length (number of bits per audio channel)
SPI_I2SCFGR_DATLEN EQU 0x0006 ; DATLEN[1:0] bits (Data length to be transferred)
SPI_I2SCFGR_DATLEN_0 EQU 0x0002 ; Bit 0
SPI_I2SCFGR_DATLEN_1 EQU 0x0004 ; Bit 1
SPI_I2SCFGR_CKPOL EQU 0x0008 ; steady state clock polarity
SPI_I2SCFGR_I2SSTD EQU 0x0030 ; I2SSTD[1:0] bits (I2S standard selection)
SPI_I2SCFGR_I2SSTD_0 EQU 0x0010 ; Bit 0
SPI_I2SCFGR_I2SSTD_1 EQU 0x0020 ; Bit 1
SPI_I2SCFGR_PCMSYNC EQU 0x0080 ; PCM frame synchronization
SPI_I2SCFGR_I2SCFG EQU 0x0300 ; I2SCFG[1:0] bits (I2S configuration mode)
SPI_I2SCFGR_I2SCFG_0 EQU 0x0100 ; Bit 0
SPI_I2SCFGR_I2SCFG_1 EQU 0x0200 ; Bit 1
SPI_I2SCFGR_I2SE EQU 0x0400 ; I2S Enable
SPI_I2SCFGR_I2SMOD EQU 0x0800 ; I2S mode selection
;***************** Bit definition for SPI_I2SPR register ******************
SPI_I2SPR_I2SDIV EQU 0x00FF ; I2S Linear prescaler
SPI_I2SPR_ODD EQU 0x0100 ; Odd factor for the prescaler
SPI_I2SPR_MCKOE EQU 0x0200 ; Master Clock Output Enable
END

@ -0,0 +1,231 @@
;********************************************************************************
; SOUBOR : INI_BITS_SYSCFG.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro SYSCFG (EXTI routing atd.)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; System Configuration (SYSCFG)
;
;****************************************************************************
;**************** Bit definition for SYSCFG_MEMRMP register ***************
SYSCFG_MEMRMP_MEM_MODE EQU 0x00000003 ; SYSCFG_Memory Remap Config
SYSCFG_MEMRMP_MEM_MODE_0 EQU 0x00000001 ; Bit 0
SYSCFG_MEMRMP_MEM_MODE_1 EQU 0x00000002 ; Bit 1
SYSCFG_MEMRMP_BOOT_MODE EQU 0x00000300 ; Boot mode Config
SYSCFG_MEMRMP_BOOT_MODE_0 EQU 0x00000100 ; Bit 0
SYSCFG_MEMRMP_BOOT_MODE_1 EQU 0x00000200 ; Bit 1
;**************** Bit definition for SYSCFG_PMC register ******************
SYSCFG_PMC_USB_PU EQU 0x00000001 ; SYSCFG PMC
;**************** Bit definition for SYSCFG_EXTICR1 register **************
SYSCFG_EXTICR1_EXTI0 EQU 0x000F ; EXTI 0 configuration
SYSCFG_EXTICR1_EXTI1 EQU 0x00F0 ; EXTI 1 configuration
SYSCFG_EXTICR1_EXTI2 EQU 0x0F00 ; EXTI 2 configuration
SYSCFG_EXTICR1_EXTI3 EQU 0xF000 ; EXTI 3 configuration
; EXTI0 configuration
SYSCFG_EXTICR1_EXTI0_PA EQU 0x0000 ; PA[0] pin
SYSCFG_EXTICR1_EXTI0_PB EQU 0x0001 ; PB[0] pin
SYSCFG_EXTICR1_EXTI0_PC EQU 0x0002 ; PC[0] pin
SYSCFG_EXTICR1_EXTI0_PD EQU 0x0003 ; PD[0] pin
SYSCFG_EXTICR1_EXTI0_PE EQU 0x0004 ; PE[0] pin
SYSCFG_EXTICR1_EXTI0_PH EQU 0x0005 ; PH[0] pin
SYSCFG_EXTICR1_EXTI0_PF EQU 0x0006 ; PF[0] pin
SYSCFG_EXTICR1_EXTI0_PG EQU 0x0007 ; PG[0] pin
; EXTI1 configuration
SYSCFG_EXTICR1_EXTI1_PA EQU 0x0000 ; PA[1] pin
SYSCFG_EXTICR1_EXTI1_PB EQU 0x0010 ; PB[1] pin
SYSCFG_EXTICR1_EXTI1_PC EQU 0x0020 ; PC[1] pin
SYSCFG_EXTICR1_EXTI1_PD EQU 0x0030 ; PD[1] pin
SYSCFG_EXTICR1_EXTI1_PE EQU 0x0040 ; PE[1] pin
SYSCFG_EXTICR1_EXTI1_PH EQU 0x0050 ; PH[1] pin
SYSCFG_EXTICR1_EXTI1_PF EQU 0x0060 ; PF[1] pin
SYSCFG_EXTICR1_EXTI1_PG EQU 0x0070 ; PG[1] pin
; EXTI2 configuration
SYSCFG_EXTICR1_EXTI2_PA EQU 0x0000 ; PA[2] pin
SYSCFG_EXTICR1_EXTI2_PB EQU 0x0100 ; PB[2] pin
SYSCFG_EXTICR1_EXTI2_PC EQU 0x0200 ; PC[2] pin
SYSCFG_EXTICR1_EXTI2_PD EQU 0x0300 ; PD[2] pin
SYSCFG_EXTICR1_EXTI2_PE EQU 0x0400 ; PE[2] pin
SYSCFG_EXTICR1_EXTI2_PH EQU 0x0500 ; PH[2] pin
SYSCFG_EXTICR1_EXTI2_PF EQU 0x0600 ; PF[2] pin
SYSCFG_EXTICR1_EXTI2_PG EQU 0x0700 ; PG[2] pin
; EXTI3 configuration
SYSCFG_EXTICR1_EXTI3_PA EQU 0x0000 ; PA[3] pin
SYSCFG_EXTICR1_EXTI3_PB EQU 0x1000 ; PB[3] pin
SYSCFG_EXTICR1_EXTI3_PC EQU 0x2000 ; PC[3] pin
SYSCFG_EXTICR1_EXTI3_PD EQU 0x3000 ; PD[3] pin
SYSCFG_EXTICR1_EXTI3_PE EQU 0x4000 ; PE[3] pin
SYSCFG_EXTICR1_EXTI3_PF EQU 0x3000 ; PF[3] pin
SYSCFG_EXTICR1_EXTI3_PG EQU 0x4000 ; PG[3] pin
;**************** Bit definition for SYSCFG_EXTICR2 register ****************
SYSCFG_EXTICR2_EXTI4 EQU 0x000F ; EXTI 4 configuration
SYSCFG_EXTICR2_EXTI5 EQU 0x00F0 ; EXTI 5 configuration
SYSCFG_EXTICR2_EXTI6 EQU 0x0F00 ; EXTI 6 configuration
SYSCFG_EXTICR2_EXTI7 EQU 0xF000 ; EXTI 7 configuration
; EXTI4 configuration
SYSCFG_EXTICR2_EXTI4_PA EQU 0x0000 ; PA[4] pin
SYSCFG_EXTICR2_EXTI4_PB EQU 0x0001 ; PB[4] pin
SYSCFG_EXTICR2_EXTI4_PC EQU 0x0002 ; PC[4] pin
SYSCFG_EXTICR2_EXTI4_PD EQU 0x0003 ; PD[4] pin
SYSCFG_EXTICR2_EXTI4_PE EQU 0x0004 ; PE[4] pin
SYSCFG_EXTICR2_EXTI4_PF EQU 0x0006 ; PF[4] pin
SYSCFG_EXTICR2_EXTI4_PG EQU 0x0007 ; PG[4] pin
; EXTI5 configuration
SYSCFG_EXTICR2_EXTI5_PA EQU 0x0000 ; PA[5] pin
SYSCFG_EXTICR2_EXTI5_PB EQU 0x0010 ; PB[5] pin
SYSCFG_EXTICR2_EXTI5_PC EQU 0x0020 ; PC[5] pin
SYSCFG_EXTICR2_EXTI5_PD EQU 0x0030 ; PD[5] pin
SYSCFG_EXTICR2_EXTI5_PE EQU 0x0040 ; PE[5] pin
SYSCFG_EXTICR2_EXTI5_PF EQU 0x0060 ; PF[5] pin
SYSCFG_EXTICR2_EXTI5_PG EQU 0x0070 ; PG[5] pin
; EXTI6 configuration
SYSCFG_EXTICR2_EXTI6_PA EQU 0x0000 ; PA[6] pin
SYSCFG_EXTICR2_EXTI6_PB EQU 0x0100 ; PB[6] pin
SYSCFG_EXTICR2_EXTI6_PC EQU 0x0200 ; PC[6] pin
SYSCFG_EXTICR2_EXTI6_PD EQU 0x0300 ; PD[6] pin
SYSCFG_EXTICR2_EXTI6_PE EQU 0x0400 ; PE[6] pin
SYSCFG_EXTICR2_EXTI6_PF EQU 0x0600 ; PF[6] pin
SYSCFG_EXTICR2_EXTI6_PG EQU 0x0700 ; PG[6] pin
; EXTI7 configuration
SYSCFG_EXTICR2_EXTI7_PA EQU 0x0000 ; PA[7] pin
SYSCFG_EXTICR2_EXTI7_PB EQU 0x1000 ; PB[7] pin
SYSCFG_EXTICR2_EXTI7_PC EQU 0x2000 ; PC[7] pin
SYSCFG_EXTICR2_EXTI7_PD EQU 0x3000 ; PD[7] pin
SYSCFG_EXTICR2_EXTI7_PE EQU 0x4000 ; PE[7] pin
SYSCFG_EXTICR2_EXTI7_PF EQU 0x6000 ; PF[7] pin
SYSCFG_EXTICR2_EXTI7_PG EQU 0x7000 ; PG[7] pin
;**************** Bit definition for SYSCFG_EXTICR3 register ****************
SYSCFG_EXTICR3_EXTI8 EQU 0x000F ; EXTI 8 configuration
SYSCFG_EXTICR3_EXTI9 EQU 0x00F0 ; EXTI 9 configuration
SYSCFG_EXTICR3_EXTI10 EQU 0x0F00 ; EXTI 10 configuration
SYSCFG_EXTICR3_EXTI11 EQU 0xF000 ; EXTI 11 configuration
; EXTI8 configuration
SYSCFG_EXTICR3_EXTI8_PA EQU 0x0000 ; PA[8] pin
SYSCFG_EXTICR3_EXTI8_PB EQU 0x0001 ; PB[8] pin
SYSCFG_EXTICR3_EXTI8_PC EQU 0x0002 ; PC[8] pin
SYSCFG_EXTICR3_EXTI8_PD EQU 0x0003 ; PD[8] pin
SYSCFG_EXTICR3_EXTI8_PE EQU 0x0004 ; PE[8] pin
SYSCFG_EXTICR3_EXTI8_PF EQU 0x0006 ; PF[8] pin
SYSCFG_EXTICR3_EXTI8_PG EQU 0x0007 ; PG[8] pin
; EXTI9 configuration
SYSCFG_EXTICR3_EXTI9_PA EQU 0x0000 ; PA[9] pin
SYSCFG_EXTICR3_EXTI9_PB EQU 0x0010 ; PB[9] pin
SYSCFG_EXTICR3_EXTI9_PC EQU 0x0020 ; PC[9] pin
SYSCFG_EXTICR3_EXTI9_PD EQU 0x0030 ; PD[9] pin
SYSCFG_EXTICR3_EXTI9_PE EQU 0x0040 ; PE[9] pin
SYSCFG_EXTICR3_EXTI9_PF EQU 0x0060 ; PF[9] pin
SYSCFG_EXTICR3_EXTI9_PG EQU 0x0070 ; PG[9] pin
; EXTI10 configuration
SYSCFG_EXTICR3_EXTI10_PA EQU 0x0000 ; PA[10] pin
SYSCFG_EXTICR3_EXTI10_PB EQU 0x0100 ; PB[10] pin
SYSCFG_EXTICR3_EXTI10_PC EQU 0x0200 ; PC[10] pin
SYSCFG_EXTICR3_EXTI10_PD EQU 0x0300 ; PD[10] pin
SYSCFG_EXTICR3_EXTI10_PE EQU 0x0400 ; PE[10] pin
SYSCFG_EXTICR3_EXTI10_PF EQU 0x0600 ; PF[10] pin
SYSCFG_EXTICR3_EXTI10_PG EQU 0x0700 ; PG[10] pin
; EXTI11 configuration
SYSCFG_EXTICR3_EXTI11_PA EQU 0x0000 ; PA[11] pin
SYSCFG_EXTICR3_EXTI11_PB EQU 0x1000 ; PB[11] pin
SYSCFG_EXTICR3_EXTI11_PC EQU 0x2000 ; PC[11] pin
SYSCFG_EXTICR3_EXTI11_PD EQU 0x3000 ; PD[11] pin
SYSCFG_EXTICR3_EXTI11_PE EQU 0x4000 ; PE[11] pin
SYSCFG_EXTICR3_EXTI11_PF EQU 0x6000 ; PF[11] pin
SYSCFG_EXTICR3_EXTI11_PG EQU 0x7000 ; PG[11] pin
;**************** Bit definition for SYSCFG_EXTICR4 register ****************
SYSCFG_EXTICR4_EXTI12 EQU 0x000F ; EXTI 12 configuration
SYSCFG_EXTICR4_EXTI13 EQU 0x00F0 ; EXTI 13 configuration
SYSCFG_EXTICR4_EXTI14 EQU 0x0F00 ; EXTI 14 configuration
SYSCFG_EXTICR4_EXTI15 EQU 0xF000 ; EXTI 15 configuration
; EXTI12 configuration
SYSCFG_EXTICR4_EXTI12_PA EQU 0x0000 ; PA[12] pin
SYSCFG_EXTICR4_EXTI12_PB EQU 0x0001 ; PB[12] pin
SYSCFG_EXTICR4_EXTI12_PC EQU 0x0002 ; PC[12] pin
SYSCFG_EXTICR4_EXTI12_PD EQU 0x0003 ; PD[12] pin
SYSCFG_EXTICR4_EXTI12_PE EQU 0x0004 ; PE[12] pin
SYSCFG_EXTICR4_EXTI12_PF EQU 0x0006 ; PF[12] pin
SYSCFG_EXTICR4_EXTI12_PG EQU 0x0007 ; PG[12] pin
; EXTI13 configuration
SYSCFG_EXTICR4_EXTI13_PA EQU 0x0000 ; PA[13] pin
SYSCFG_EXTICR4_EXTI13_PB EQU 0x0010 ; PB[13] pin
SYSCFG_EXTICR4_EXTI13_PC EQU 0x0020 ; PC[13] pin
SYSCFG_EXTICR4_EXTI13_PD EQU 0x0030 ; PD[13] pin
SYSCFG_EXTICR4_EXTI13_PE EQU 0x0040 ; PE[13] pin
SYSCFG_EXTICR4_EXTI13_PF EQU 0x0060 ; PF[13] pin
SYSCFG_EXTICR4_EXTI13_PG EQU 0x0070 ; PG[13] pin
; EXTI14 configuration
SYSCFG_EXTICR4_EXTI14_PA EQU 0x0000 ; PA[14] pin
SYSCFG_EXTICR4_EXTI14_PB EQU 0x0100 ; PB[14] pin
SYSCFG_EXTICR4_EXTI14_PC EQU 0x0200 ; PC[14] pin
SYSCFG_EXTICR4_EXTI14_PD EQU 0x0300 ; PD[14] pin
SYSCFG_EXTICR4_EXTI14_PE EQU 0x0400 ; PE[14] pin
SYSCFG_EXTICR4_EXTI14_PF EQU 0x0600 ; PF[14] pin
SYSCFG_EXTICR4_EXTI14_PG EQU 0x0700 ; PG[14] pin
; EXTI15 configuration
SYSCFG_EXTICR4_EXTI15_PA EQU 0x0000 ; PA[15] pin
SYSCFG_EXTICR4_EXTI15_PB EQU 0x1000 ; PB[15] pin
SYSCFG_EXTICR4_EXTI15_PC EQU 0x2000 ; PC[15] pin
SYSCFG_EXTICR4_EXTI15_PD EQU 0x3000 ; PD[15] pin
SYSCFG_EXTICR4_EXTI15_PE EQU 0x4000 ; PE[15] pin
SYSCFG_EXTICR4_EXTI15_PF EQU 0x6000 ; PF[15] pin
SYSCFG_EXTICR4_EXTI15_PG EQU 0x7000 ; PG[15] pin
END

@ -0,0 +1,38 @@
;********************************************************************************
; SOUBOR : INI_BITS_SYSTICK.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro SYSTICK (casovac pro RTOS)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; SystemTick (SysTick)
;
;****************************************************************************
;**************** Bit definition for SysTick_CSR register ****************
SysTick_CSR_ENABLE EQU 0x00000001 ; Counter enable
SysTick_CSR_TICKINT EQU 0x00000002 ; Enable interrupt when counter reaches zero
SysTick_CSR_CLKSOURCE EQU 0x00000004 ; Clock source (0 - external, 1 - core clock)
SysTick_CSR_CLKSOURCE_CORE EQU 0x00000004 ; Clock source - core clock
SysTick_CSR_CLKSOURCE_DIV8 EQU 0x00000000 ; Clock source - core clock / 8
SysTick_CSR_COUNTFLAG EQU 0x00010000 ; Count Flag (only if interrupt is disabled)
;**************** Bit definition for SysTick_LOAD register ****************
SysTick_RELOAD_MASK EQU 0x00FFFFFF ; Value to load into the SysTick Current Value Register when the counter reaches 0
;**************** Bit definition for SysTick_VAL register *****************
SysTick_VAL_MASK EQU 0x00FFFFFF ; Current value at the time the register is accessed
;**************** Bit definition for SysTick_CALIB register ***************
SysTick_CALIB_TENMS EQU 0x00FFFFFF ; Reload value to use for 10ms timing
SysTick_CALIB_SKEW EQU 0x40000000 ; Calibration value is not exactly 10 ms
SysTick_CALIB_NOREF EQU 0x80000000 ; The reference clock is not provided
END

@ -0,0 +1,266 @@
;********************************************************************************
; SOUBOR : INI_BITS_TIM.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro TIM (casovace)
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Timers (TIM)
;
;****************************************************************************
;****************** Bit definition for TIM_CR1 register *******************
TIM_CR1_CEN EQU 0x0001 ; Counter enable
TIM_CR1_UDIS EQU 0x0002 ; Update disable
TIM_CR1_URS EQU 0x0004 ; Update request source
TIM_CR1_OPM EQU 0x0008 ; One pulse mode
TIM_CR1_DIR EQU 0x0010 ; Direction
TIM_CR1_CMS EQU 0x0060 ; CMS[1:0] bits (Center-aligned mode selection)
TIM_CR1_CMS_0 EQU 0x0020 ; Bit 0
TIM_CR1_CMS_1 EQU 0x0040 ; Bit 1
TIM_CR1_ARPE EQU 0x0080 ; Auto-reload preload enable
TIM_CR1_CKD EQU 0x0300 ; CKD[1:0] bits (clock division)
TIM_CR1_CKD_0 EQU 0x0100 ; Bit 0
TIM_CR1_CKD_1 EQU 0x0200 ; Bit 1
;****************** Bit definition for TIM_CR2 register *******************
TIM_CR2_CCDS EQU 0x0008 ; Capture/Compare DMA Selection
TIM_CR2_MMS EQU 0x0070 ; MMS[2:0] bits (Master Mode Selection)
TIM_CR2_MMS_0 EQU 0x0010 ; Bit 0
TIM_CR2_MMS_1 EQU 0x0020 ; Bit 1
TIM_CR2_MMS_2 EQU 0x0040 ; Bit 2
TIM_CR2_TI1S EQU 0x0080 ; TI1 Selection
;****************** Bit definition for TIM_SMCR register ******************
TIM_SMCR_SMS EQU 0x0007 ; SMS[2:0] bits (Slave mode selection)
TIM_SMCR_SMS_0 EQU 0x0001 ; Bit 0
TIM_SMCR_SMS_1 EQU 0x0002 ; Bit 1
TIM_SMCR_SMS_2 EQU 0x0004 ; Bit 2
TIM_SMCR_OCCS EQU 0x0008 ; OCCS bits (OCref Clear Selection)
TIM_SMCR_TS EQU 0x0070 ; TS[2:0] bits (Trigger selection)
TIM_SMCR_TS_0 EQU 0x0010 ; Bit 0
TIM_SMCR_TS_1 EQU 0x0020 ; Bit 1
TIM_SMCR_TS_2 EQU 0x0040 ; Bit 2
TIM_SMCR_MSM EQU 0x0080 ; Master/slave mode
TIM_SMCR_ETF EQU 0x0F00 ; ETF[3:0] bits (External trigger filter)
TIM_SMCR_ETF_0 EQU 0x0100 ; Bit 0
TIM_SMCR_ETF_1 EQU 0x0200 ; Bit 1
TIM_SMCR_ETF_2 EQU 0x0400 ; Bit 2
TIM_SMCR_ETF_3 EQU 0x0800 ; Bit 3
TIM_SMCR_ETPS EQU 0x3000 ; ETPS[1:0] bits (External trigger prescaler)
TIM_SMCR_ETPS_0 EQU 0x1000 ; Bit 0
TIM_SMCR_ETPS_1 EQU 0x2000 ; Bit 1
TIM_SMCR_ECE EQU 0x4000 ; External clock enable
TIM_SMCR_ETP EQU 0x8000 ; External trigger polarity
;****************** Bit definition for TIM_DIER register ******************
TIM_DIER_UIE EQU 0x0001 ; Update interrupt enable
TIM_DIER_CC1IE EQU 0x0002 ; Capture/Compare 1 interrupt enable
TIM_DIER_CC2IE EQU 0x0004 ; Capture/Compare 2 interrupt enable
TIM_DIER_CC3IE EQU 0x0008 ; Capture/Compare 3 interrupt enable
TIM_DIER_CC4IE EQU 0x0010 ; Capture/Compare 4 interrupt enable
TIM_DIER_TIE EQU 0x0040 ; Trigger interrupt enable
TIM_DIER_UDE EQU 0x0100 ; Update DMA request enable
TIM_DIER_CC1DE EQU 0x0200 ; Capture/Compare 1 DMA request enable
TIM_DIER_CC2DE EQU 0x0400 ; Capture/Compare 2 DMA request enable
TIM_DIER_CC3DE EQU 0x0800 ; Capture/Compare 3 DMA request enable
TIM_DIER_CC4DE EQU 0x1000 ; Capture/Compare 4 DMA request enable
TIM_DIER_TDE EQU 0x4000 ; Trigger DMA request enable
;******************* Bit definition for TIM_SR register *******************
TIM_SR_UIF EQU 0x0001 ; Update interrupt Flag
TIM_SR_CC1IF EQU 0x0002 ; Capture/Compare 1 interrupt Flag
TIM_SR_CC2IF EQU 0x0004 ; Capture/Compare 2 interrupt Flag
TIM_SR_CC3IF EQU 0x0008 ; Capture/Compare 3 interrupt Flag
TIM_SR_CC4IF EQU 0x0010 ; Capture/Compare 4 interrupt Flag
TIM_SR_TIF EQU 0x0040 ; Trigger interrupt Flag
TIM_SR_CC1OF EQU 0x0200 ; Capture/Compare 1 Overcapture Flag
TIM_SR_CC2OF EQU 0x0400 ; Capture/Compare 2 Overcapture Flag
TIM_SR_CC3OF EQU 0x0800 ; Capture/Compare 3 Overcapture Flag
TIM_SR_CC4OF EQU 0x1000 ; Capture/Compare 4 Overcapture Flag
;****************** Bit definition for TIM_EGR register *******************
TIM_EGR_UG EQU 0x01 ; Update Generation
TIM_EGR_CC1G EQU 0x02 ; Capture/Compare 1 Generation
TIM_EGR_CC2G EQU 0x04 ; Capture/Compare 2 Generation
TIM_EGR_CC3G EQU 0x08 ; Capture/Compare 3 Generation
TIM_EGR_CC4G EQU 0x10 ; Capture/Compare 4 Generation
TIM_EGR_TG EQU 0x40 ; Trigger Generation
;***************** Bit definition for TIM_CCMR1 register ******************
TIM_CCMR1_CC1S EQU 0x0003 ; CC1S[1:0] bits (Capture/Compare 1 Selection)
TIM_CCMR1_CC1S_0 EQU 0x0001 ; Bit 0
TIM_CCMR1_CC1S_1 EQU 0x0002 ; Bit 1
TIM_CCMR1_OC1FE EQU 0x0004 ; Output Compare 1 Fast enable
TIM_CCMR1_OC1PE EQU 0x0008 ; Output Compare 1 Preload enable
TIM_CCMR1_OC1M EQU 0x0070 ; OC1M[2:0] bits (Output Compare 1 Mode)
TIM_CCMR1_OC1M_0 EQU 0x0010 ; Bit 0
TIM_CCMR1_OC1M_1 EQU 0x0020 ; Bit 1
TIM_CCMR1_OC1M_2 EQU 0x0040 ; Bit 2
TIM_CCMR1_OC1CE EQU 0x0080 ; Output Compare 1Clear Enable
TIM_CCMR1_CC2S EQU 0x0300 ; CC2S[1:0] bits (Capture/Compare 2 Selection)
TIM_CCMR1_CC2S_0 EQU 0x0100 ; Bit 0
TIM_CCMR1_CC2S_1 EQU 0x0200 ; Bit 1
TIM_CCMR1_OC2FE EQU 0x0400 ; Output Compare 2 Fast enable
TIM_CCMR1_OC2PE EQU 0x0800 ; Output Compare 2 Preload enable
TIM_CCMR1_OC2M EQU 0x7000 ; OC2M[2:0] bits (Output Compare 2 Mode)
TIM_CCMR1_OC2M_0 EQU 0x1000 ; Bit 0
TIM_CCMR1_OC2M_1 EQU 0x2000 ; Bit 1
TIM_CCMR1_OC2M_2 EQU 0x4000 ; Bit 2
TIM_CCMR1_OC2CE EQU 0x8000 ; Output Compare 2 Clear Enable
;----------------------------------------------------------------------------
TIM_CCMR1_IC1PSC EQU 0x000C ; IC1PSC[1:0] bits (Input Capture 1 Prescaler)
TIM_CCMR1_IC1PSC_0 EQU 0x0004 ; Bit 0
TIM_CCMR1_IC1PSC_1 EQU 0x0008 ; Bit 1
TIM_CCMR1_IC1F EQU 0x00F0 ; IC1F[3:0] bits (Input Capture 1 Filter)
TIM_CCMR1_IC1F_0 EQU 0x0010 ; Bit 0
TIM_CCMR1_IC1F_1 EQU 0x0020 ; Bit 1
TIM_CCMR1_IC1F_2 EQU 0x0040 ; Bit 2
TIM_CCMR1_IC1F_3 EQU 0x0080 ; Bit 3
TIM_CCMR1_IC2PSC EQU 0x0C00 ; IC2PSC[1:0] bits (Input Capture 2 Prescaler)
TIM_CCMR1_IC2PSC_0 EQU 0x0400 ; Bit 0
TIM_CCMR1_IC2PSC_1 EQU 0x0800 ; Bit 1
TIM_CCMR1_IC2F EQU 0xF000 ; IC2F[3:0] bits (Input Capture 2 Filter)
TIM_CCMR1_IC2F_0 EQU 0x1000 ; Bit 0
TIM_CCMR1_IC2F_1 EQU 0x2000 ; Bit 1
TIM_CCMR1_IC2F_2 EQU 0x4000 ; Bit 2
TIM_CCMR1_IC2F_3 EQU 0x8000 ; Bit 3
;***************** Bit definition for TIM_CCMR2 register ******************
TIM_CCMR2_CC3S EQU 0x0003 ; CC3S[1:0] bits (Capture/Compare 3 Selection)
TIM_CCMR2_CC3S_0 EQU 0x0001 ; Bit 0
TIM_CCMR2_CC3S_1 EQU 0x0002 ; Bit 1
TIM_CCMR2_OC3FE EQU 0x0004 ; Output Compare 3 Fast enable
TIM_CCMR2_OC3PE EQU 0x0008 ; Output Compare 3 Preload enable
TIM_CCMR2_OC3M EQU 0x0070 ; OC3M[2:0] bits (Output Compare 3 Mode)
TIM_CCMR2_OC3M_0 EQU 0x0010 ; Bit 0
TIM_CCMR2_OC3M_1 EQU 0x0020 ; Bit 1
TIM_CCMR2_OC3M_2 EQU 0x0040 ; Bit 2
TIM_CCMR2_OC3CE EQU 0x0080 ; Output Compare 3 Clear Enable
TIM_CCMR2_CC4S EQU 0x0300 ; CC4S[1:0] bits (Capture/Compare 4 Selection)
TIM_CCMR2_CC4S_0 EQU 0x0100 ; Bit 0
TIM_CCMR2_CC4S_1 EQU 0x0200 ; Bit 1
TIM_CCMR2_OC4FE EQU 0x0400 ; Output Compare 4 Fast enable
TIM_CCMR2_OC4PE EQU 0x0800 ; Output Compare 4 Preload enable
TIM_CCMR2_OC4M EQU 0x7000 ; OC4M[2:0] bits (Output Compare 4 Mode)
TIM_CCMR2_OC4M_0 EQU 0x1000 ; Bit 0
TIM_CCMR2_OC4M_1 EQU 0x2000 ; Bit 1
TIM_CCMR2_OC4M_2 EQU 0x4000 ; Bit 2
TIM_CCMR2_OC4CE EQU 0x8000 ; Output Compare 4 Clear Enable
;----------------------------------------------------------------------------
TIM_CCMR2_IC3PSC EQU 0x000C ; IC3PSC[1:0] bits (Input Capture 3 Prescaler)
TIM_CCMR2_IC3PSC_0 EQU 0x0004 ; Bit 0
TIM_CCMR2_IC3PSC_1 EQU 0x0008 ; Bit 1
TIM_CCMR2_IC3F EQU 0x00F0 ; IC3F[3:0] bits (Input Capture 3 Filter)
TIM_CCMR2_IC3F_0 EQU 0x0010 ; Bit 0
TIM_CCMR2_IC3F_1 EQU 0x0020 ; Bit 1
TIM_CCMR2_IC3F_2 EQU 0x0040 ; Bit 2
TIM_CCMR2_IC3F_3 EQU 0x0080 ; Bit 3
TIM_CCMR2_IC4PSC EQU 0x0C00 ; IC4PSC[1:0] bits (Input Capture 4 Prescaler)
TIM_CCMR2_IC4PSC_0 EQU 0x0400 ; Bit 0
TIM_CCMR2_IC4PSC_1 EQU 0x0800 ; Bit 1
TIM_CCMR2_IC4F EQU 0xF000 ; IC4F[3:0] bits (Input Capture 4 Filter)
TIM_CCMR2_IC4F_0 EQU 0x1000 ; Bit 0
TIM_CCMR2_IC4F_1 EQU 0x2000 ; Bit 1
TIM_CCMR2_IC4F_2 EQU 0x4000 ; Bit 2
TIM_CCMR2_IC4F_3 EQU 0x8000 ; Bit 3
;****************** Bit definition for TIM_CCER register ******************
TIM_CCER_CC1E EQU 0x0001 ; Capture/Compare 1 output enable
TIM_CCER_CC1P EQU 0x0002 ; Capture/Compare 1 output Polarity
TIM_CCER_CC1NP EQU 0x0008 ; Capture/Compare 1 Complementary output Polarity
TIM_CCER_CC2E EQU 0x0010 ; Capture/Compare 2 output enable
TIM_CCER_CC2P EQU 0x0020 ; Capture/Compare 2 output Polarity
TIM_CCER_CC2NP EQU 0x0080 ; Capture/Compare 2 Complementary output Polarity
TIM_CCER_CC3E EQU 0x0100 ; Capture/Compare 3 output enable
TIM_CCER_CC3P EQU 0x0200 ; Capture/Compare 3 output Polarity
TIM_CCER_CC3NP EQU 0x0800 ; Capture/Compare 3 Complementary output Polarity
TIM_CCER_CC4E EQU 0x1000 ; Capture/Compare 4 output enable
TIM_CCER_CC4P EQU 0x2000 ; Capture/Compare 4 output Polarity
TIM_CCER_CC4NP EQU 0x8000 ; Capture/Compare 4 Complementary output Polarity
;****************** Bit definition for TIM_CNT register *******************
TIM_CNT_CNT EQU 0xFFFF ; Counter Value
;****************** Bit definition for TIM_PSC register *******************
TIM_PSC_PSC EQU 0xFFFF ; Prescaler Value
;****************** Bit definition for TIM_ARR register *******************
TIM_ARR_ARR EQU 0xFFFF ; actual auto-reload Value
;****************** Bit definition for TIM_CCR1 register ******************
TIM_CCR1_CCR1 EQU 0xFFFF ; Capture/Compare 1 Value
;****************** Bit definition for TIM_CCR2 register ******************
TIM_CCR2_CCR2 EQU 0xFFFF ; Capture/Compare 2 Value
;****************** Bit definition for TIM_CCR3 register ******************
TIM_CCR3_CCR3 EQU 0xFFFF ; Capture/Compare 3 Value
;****************** Bit definition for TIM_CCR4 register ******************
TIM_CCR4_CCR4 EQU 0xFFFF ; Capture/Compare 4 Value
;****************** Bit definition for TIM_DCR register *******************
TIM_DCR_DBA EQU 0x001F ; DBA[4:0] bits (DMA Base Address)
TIM_DCR_DBA_0 EQU 0x0001 ; Bit 0
TIM_DCR_DBA_1 EQU 0x0002 ; Bit 1
TIM_DCR_DBA_2 EQU 0x0004 ; Bit 2
TIM_DCR_DBA_3 EQU 0x0008 ; Bit 3
TIM_DCR_DBA_4 EQU 0x0010 ; Bit 4
TIM_DCR_DBL EQU 0x1F00 ; DBL[4:0] bits (DMA Burst Length)
TIM_DCR_DBL_0 EQU 0x0100 ; Bit 0
TIM_DCR_DBL_1 EQU 0x0200 ; Bit 1
TIM_DCR_DBL_2 EQU 0x0400 ; Bit 2
TIM_DCR_DBL_3 EQU 0x0800 ; Bit 3
TIM_DCR_DBL_4 EQU 0x1000 ; Bit 4
;****************** Bit definition for TIM_DMAR register ******************
TIM_DMAR_DMAB EQU 0xFFFF ; DMA register for burst accesses
;****************** Bit definition for TIM_OR register ********************
TIM_OR_TI1RMP EQU 0x0003 ; Option register for TI1 Remapping
TIM_OR_TI1RMP_0 EQU 0x0001 ; Bit 0
TIM_OR_TI1RMP_1 EQU 0x0002 ; Bit 1
END

@ -0,0 +1,95 @@
;********************************************************************************
; SOUBOR : INI_BITS_USART.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro USART
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Universal Synchronous Asynchronous Receiver Transmitter (USART)
;
;****************************************************************************
;****************** Bit definition for USART_SR register ******************
USART_SR_PE EQU 0x0001 ; Parity Error
USART_SR_FE EQU 0x0002 ; Framing Error
USART_SR_NE EQU 0x0004 ; Noise Error Flag
USART_SR_ORE EQU 0x0008 ; OverRun Error
USART_SR_IDLE EQU 0x0010 ; IDLE line detected
USART_SR_RXNE EQU 0x0020 ; Read Data Register Not Empty
USART_SR_TC EQU 0x0040 ; Transmission Complete
USART_SR_TXE EQU 0x0080 ; Transmit Data Register Empty
USART_SR_LBD EQU 0x0100 ; LIN Break Detection Flag
USART_SR_CTS EQU 0x0200 ; CTS Flag
;****************** Bit definition for USART_DR register ******************
USART_DR_DR EQU 0x01FF ; Data value
;***************** Bit definition for USART_BRR register ******************
USART_BRR_DIV_FRACTION EQU 0x000F ; Fraction of USARTDIV
USART_BRR_DIV_MANTISSA EQU 0xFFF0 ; Mantissa of USARTDIV
;***************** Bit definition for USART_CR1 register ******************
USART_CR1_SBK EQU 0x0001 ; Send Break
USART_CR1_RWU EQU 0x0002 ; Receiver wakeup
USART_CR1_RE EQU 0x0004 ; Receiver Enable
USART_CR1_TE EQU 0x0008 ; Transmitter Enable
USART_CR1_IDLEIE EQU 0x0010 ; IDLE Interrupt Enable
USART_CR1_RXNEIE EQU 0x0020 ; RXNE Interrupt Enable
USART_CR1_TCIE EQU 0x0040 ; Transmission Complete Interrupt Enable
USART_CR1_TXEIE EQU 0x0080 ; PE Interrupt Enable
USART_CR1_PEIE EQU 0x0100 ; PE Interrupt Enable
USART_CR1_PS EQU 0x0200 ; Parity Selection
USART_CR1_PCE EQU 0x0400 ; Parity Control Enable
USART_CR1_WAKE EQU 0x0800 ; Wakeup method
USART_CR1_M EQU 0x1000 ; Word length
USART_CR1_UE EQU 0x2000 ; USART Enable
USART_CR1_OVER8 EQU 0x8000 ; Oversampling by 8-bit mode
;***************** Bit definition for USART_CR2 register ******************
USART_CR2_ADD EQU 0x000F ; Address of the USART node
USART_CR2_LBDL EQU 0x0020 ; LIN Break Detection Length
USART_CR2_LBDIE EQU 0x0040 ; LIN Break Detection Interrupt Enable
USART_CR2_LBCL EQU 0x0100 ; Last Bit Clock pulse
USART_CR2_CPHA EQU 0x0200 ; Clock Phase
USART_CR2_CPOL EQU 0x0400 ; Clock Polarity
USART_CR2_CLKEN EQU 0x0800 ; Clock Enable
USART_CR2_STOP EQU 0x3000 ; STOP[1:0] bits (STOP bits)
USART_CR2_STOP_0 EQU 0x1000 ; Bit 0
USART_CR2_STOP_1 EQU 0x2000 ; Bit 1
USART_CR2_LINEN EQU 0x4000 ; LIN mode enable
;***************** Bit definition for USART_CR3 register ******************
USART_CR3_EIE EQU 0x0001 ; Error Interrupt Enable
USART_CR3_IREN EQU 0x0002 ; IrDA mode Enable
USART_CR3_IRLP EQU 0x0004 ; IrDA Low-Power
USART_CR3_HDSEL EQU 0x0008 ; Half-Duplex Selection
USART_CR3_NACK EQU 0x0010 ; Smartcard NACK enable
USART_CR3_SCEN EQU 0x0020 ; Smartcard mode enable
USART_CR3_DMAR EQU 0x0040 ; DMA Enable Receiver
USART_CR3_DMAT EQU 0x0080 ; DMA Enable Transmitter
USART_CR3_RTSE EQU 0x0100 ; RTS Enable
USART_CR3_CTSE EQU 0x0200 ; CTS Enable
USART_CR3_CTSIE EQU 0x0400 ; CTS Interrupt Enable
USART_CR3_ONEBIT EQU 0x0800 ; One sample bit method enable
;***************** Bit definition for USART_GTPR register *****************
USART_GTPR_PSC EQU 0x00FF ; PSC[7:0] bits (Prescaler value)
USART_GTPR_PSC_0 EQU 0x0001 ; Bit 0
USART_GTPR_PSC_1 EQU 0x0002 ; Bit 1
USART_GTPR_PSC_2 EQU 0x0004 ; Bit 2
USART_GTPR_PSC_3 EQU 0x0008 ; Bit 3
USART_GTPR_PSC_4 EQU 0x0010 ; Bit 4
USART_GTPR_PSC_5 EQU 0x0020 ; Bit 5
USART_GTPR_PSC_6 EQU 0x0040 ; Bit 6
USART_GTPR_PSC_7 EQU 0x0080 ; Bit 7
USART_GTPR_GT EQU 0xFF00 ; Guard time value
END

@ -0,0 +1,679 @@
;********************************************************************************
; SOUBOR : INI_BITS_USB.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro USB
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Universal Serial Bus (USB)
;
;****************************************************************************
; Endpoint-specific registers
;****************** Bit definition for USB_EP0R register ******************
USB_EP0R_EA EQU 0x000F ; Endpoint Address
USB_EP0R_STAT_TX EQU 0x0030 ; STAT_TX[1:0] bits (Status bits, for transmission transfers)
USB_EP0R_STAT_TX_0 EQU 0x0010 ; Bit 0
USB_EP0R_STAT_TX_1 EQU 0x0020 ; Bit 1
USB_EP0R_DTOG_TX EQU 0x0040 ; Data Toggle, for transmission transfers
USB_EP0R_CTR_TX EQU 0x0080 ; Correct Transfer for transmission
USB_EP0R_EP_KIND EQU 0x0100 ; Endpoint Kind
USB_EP0R_EP_TYPE EQU 0x0600 ; EP_TYPE[1:0] bits (Endpoint type)
USB_EP0R_EP_TYPE_0 EQU 0x0200 ; Bit 0
USB_EP0R_EP_TYPE_1 EQU 0x0400 ; Bit 1
USB_EP0R_SETUP EQU 0x0800 ; Setup transaction completed
USB_EP0R_STAT_RX EQU 0x3000 ; STAT_RX[1:0] bits (Status bits, for reception transfers)
USB_EP0R_STAT_RX_0 EQU 0x1000 ; Bit 0
USB_EP0R_STAT_RX_1 EQU 0x2000 ; Bit 1
USB_EP0R_DTOG_RX EQU 0x4000 ; Data Toggle, for reception transfers
USB_EP0R_CTR_RX EQU 0x8000 ; Correct Transfer for reception
;****************** Bit definition for USB_EP1R register ******************
USB_EP1R_EA EQU 0x000F ; Endpoint Address
USB_EP1R_STAT_TX EQU 0x0030 ; STAT_TX[1:0] bits (Status bits, for transmission transfers)
USB_EP1R_STAT_TX_0 EQU 0x0010 ; Bit 0
USB_EP1R_STAT_TX_1 EQU 0x0020 ; Bit 1
USB_EP1R_DTOG_TX EQU 0x0040 ; Data Toggle, for transmission transfers
USB_EP1R_CTR_TX EQU 0x0080 ; Correct Transfer for transmission
USB_EP1R_EP_KIND EQU 0x0100 ; Endpoint Kind
USB_EP1R_EP_TYPE EQU 0x0600 ; EP_TYPE[1:0] bits (Endpoint type)
USB_EP1R_EP_TYPE_0 EQU 0x0200 ; Bit 0
USB_EP1R_EP_TYPE_1 EQU 0x0400 ; Bit 1
USB_EP1R_SETUP EQU 0x0800 ; Setup transaction completed
USB_EP1R_STAT_RX EQU 0x3000 ; STAT_RX[1:0] bits (Status bits, for reception transfers)
USB_EP1R_STAT_RX_0 EQU 0x1000 ; Bit 0
USB_EP1R_STAT_RX_1 EQU 0x2000 ; Bit 1
USB_EP1R_DTOG_RX EQU 0x4000 ; Data Toggle, for reception transfers
USB_EP1R_CTR_RX EQU 0x8000 ; Correct Transfer for reception
;****************** Bit definition for USB_EP2R register ******************
USB_EP2R_EA EQU 0x000F ; Endpoint Address
USB_EP2R_STAT_TX EQU 0x0030 ; STAT_TX[1:0] bits (Status bits, for transmission transfers)
USB_EP2R_STAT_TX_0 EQU 0x0010 ; Bit 0
USB_EP2R_STAT_TX_1 EQU 0x0020 ; Bit 1
USB_EP2R_DTOG_TX EQU 0x0040 ; Data Toggle, for transmission transfers
USB_EP2R_CTR_TX EQU 0x0080 ; Correct Transfer for transmission
USB_EP2R_EP_KIND EQU 0x0100 ; Endpoint Kind
USB_EP2R_EP_TYPE EQU 0x0600 ; EP_TYPE[1:0] bits (Endpoint type)
USB_EP2R_EP_TYPE_0 EQU 0x0200 ; Bit 0
USB_EP2R_EP_TYPE_1 EQU 0x0400 ; Bit 1
USB_EP2R_SETUP EQU 0x0800 ; Setup transaction completed
USB_EP2R_STAT_RX EQU 0x3000 ; STAT_RX[1:0] bits (Status bits, for reception transfers)
USB_EP2R_STAT_RX_0 EQU 0x1000 ; Bit 0
USB_EP2R_STAT_RX_1 EQU 0x2000 ; Bit 1
USB_EP2R_DTOG_RX EQU 0x4000 ; Data Toggle, for reception transfers
USB_EP2R_CTR_RX EQU 0x8000 ; Correct Transfer for reception
;****************** Bit definition for USB_EP3R register ******************
USB_EP3R_EA EQU 0x000F ; Endpoint Address
USB_EP3R_STAT_TX EQU 0x0030 ; STAT_TX[1:0] bits (Status bits, for transmission transfers)
USB_EP3R_STAT_TX_0 EQU 0x0010 ; Bit 0
USB_EP3R_STAT_TX_1 EQU 0x0020 ; Bit 1
USB_EP3R_DTOG_TX EQU 0x0040 ; Data Toggle, for transmission transfers
USB_EP3R_CTR_TX EQU 0x0080 ; Correct Transfer for transmission
USB_EP3R_EP_KIND EQU 0x0100 ; Endpoint Kind
USB_EP3R_EP_TYPE EQU 0x0600 ; EP_TYPE[1:0] bits (Endpoint type)
USB_EP3R_EP_TYPE_0 EQU 0x0200 ; Bit 0
USB_EP3R_EP_TYPE_1 EQU 0x0400 ; Bit 1
USB_EP3R_SETUP EQU 0x0800 ; Setup transaction completed
USB_EP3R_STAT_RX EQU 0x3000 ; STAT_RX[1:0] bits (Status bits, for reception transfers)
USB_EP3R_STAT_RX_0 EQU 0x1000 ; Bit 0
USB_EP3R_STAT_RX_1 EQU 0x2000 ; Bit 1
USB_EP3R_DTOG_RX EQU 0x4000 ; Data Toggle, for reception transfers
USB_EP3R_CTR_RX EQU 0x8000 ; Correct Transfer for reception
;****************** Bit definition for USB_EP4R register ******************
USB_EP4R_EA EQU 0x000F ; Endpoint Address
USB_EP4R_STAT_TX EQU 0x0030 ; STAT_TX[1:0] bits (Status bits, for transmission transfers)
USB_EP4R_STAT_TX_0 EQU 0x0010 ; Bit 0
USB_EP4R_STAT_TX_1 EQU 0x0020 ; Bit 1
USB_EP4R_DTOG_TX EQU 0x0040 ; Data Toggle, for transmission transfers
USB_EP4R_CTR_TX EQU 0x0080 ; Correct Transfer for transmission
USB_EP4R_EP_KIND EQU 0x0100 ; Endpoint Kind
USB_EP4R_EP_TYPE EQU 0x0600 ; EP_TYPE[1:0] bits (Endpoint type)
USB_EP4R_EP_TYPE_0 EQU 0x0200 ; Bit 0
USB_EP4R_EP_TYPE_1 EQU 0x0400 ; Bit 1
USB_EP4R_SETUP EQU 0x0800 ; Setup transaction completed
USB_EP4R_STAT_RX EQU 0x3000 ; STAT_RX[1:0] bits (Status bits, for reception transfers)
USB_EP4R_STAT_RX_0 EQU 0x1000 ; Bit 0
USB_EP4R_STAT_RX_1 EQU 0x2000 ; Bit 1
USB_EP4R_DTOG_RX EQU 0x4000 ; Data Toggle, for reception transfers
USB_EP4R_CTR_RX EQU 0x8000 ; Correct Transfer for reception
;****************** Bit definition for USB_EP5R register ******************
USB_EP5R_EA EQU 0x000F ; Endpoint Address
USB_EP5R_STAT_TX EQU 0x0030 ; STAT_TX[1:0] bits (Status bits, for transmission transfers)
USB_EP5R_STAT_TX_0 EQU 0x0010 ; Bit 0
USB_EP5R_STAT_TX_1 EQU 0x0020 ; Bit 1
USB_EP5R_DTOG_TX EQU 0x0040 ; Data Toggle, for transmission transfers
USB_EP5R_CTR_TX EQU 0x0080 ; Correct Transfer for transmission
USB_EP5R_EP_KIND EQU 0x0100 ; Endpoint Kind
USB_EP5R_EP_TYPE EQU 0x0600 ; EP_TYPE[1:0] bits (Endpoint type)
USB_EP5R_EP_TYPE_0 EQU 0x0200 ; Bit 0
USB_EP5R_EP_TYPE_1 EQU 0x0400 ; Bit 1
USB_EP5R_SETUP EQU 0x0800 ; Setup transaction completed
USB_EP5R_STAT_RX EQU 0x3000 ; STAT_RX[1:0] bits (Status bits, for reception transfers)
USB_EP5R_STAT_RX_0 EQU 0x1000 ; Bit 0
USB_EP5R_STAT_RX_1 EQU 0x2000 ; Bit 1
USB_EP5R_DTOG_RX EQU 0x4000 ; Data Toggle, for reception transfers
USB_EP5R_CTR_RX EQU 0x8000 ; Correct Transfer for reception
;****************** Bit definition for USB_EP6R register ******************
USB_EP6R_EA EQU 0x000F ; Endpoint Address
USB_EP6R_STAT_TX EQU 0x0030 ; STAT_TX[1:0] bits (Status bits, for transmission transfers)
USB_EP6R_STAT_TX_0 EQU 0x0010 ; Bit 0
USB_EP6R_STAT_TX_1 EQU 0x0020 ; Bit 1
USB_EP6R_DTOG_TX EQU 0x0040 ; Data Toggle, for transmission transfers
USB_EP6R_CTR_TX EQU 0x0080 ; Correct Transfer for transmission
USB_EP6R_EP_KIND EQU 0x0100 ; Endpoint Kind
USB_EP6R_EP_TYPE EQU 0x0600 ; EP_TYPE[1:0] bits (Endpoint type)
USB_EP6R_EP_TYPE_0 EQU 0x0200 ; Bit 0
USB_EP6R_EP_TYPE_1 EQU 0x0400 ; Bit 1
USB_EP6R_SETUP EQU 0x0800 ; Setup transaction completed
USB_EP6R_STAT_RX EQU 0x3000 ; STAT_RX[1:0] bits (Status bits, for reception transfers)
USB_EP6R_STAT_RX_0 EQU 0x1000 ; Bit 0
USB_EP6R_STAT_RX_1 EQU 0x2000 ; Bit 1
USB_EP6R_DTOG_RX EQU 0x4000 ; Data Toggle, for reception transfers
USB_EP6R_CTR_RX EQU 0x8000 ; Correct Transfer for reception
;****************** Bit definition for USB_EP7R register ******************
USB_EP7R_EA EQU 0x000F ; Endpoint Address
USB_EP7R_STAT_TX EQU 0x0030 ; STAT_TX[1:0] bits (Status bits, for transmission transfers)
USB_EP7R_STAT_TX_0 EQU 0x0010 ; Bit 0
USB_EP7R_STAT_TX_1 EQU 0x0020 ; Bit 1
USB_EP7R_DTOG_TX EQU 0x0040 ; Data Toggle, for transmission transfers
USB_EP7R_CTR_TX EQU 0x0080 ; Correct Transfer for transmission
USB_EP7R_EP_KIND EQU 0x0100 ; Endpoint Kind
USB_EP7R_EP_TYPE EQU 0x0600 ; EP_TYPE[1:0] bits (Endpoint type)
USB_EP7R_EP_TYPE_0 EQU 0x0200 ; Bit 0
USB_EP7R_EP_TYPE_1 EQU 0x0400 ; Bit 1
USB_EP7R_SETUP EQU 0x0800 ; Setup transaction completed
USB_EP7R_STAT_RX EQU 0x3000 ; STAT_RX[1:0] bits (Status bits, for reception transfers)
USB_EP7R_STAT_RX_0 EQU 0x1000 ; Bit 0
USB_EP7R_STAT_RX_1 EQU 0x2000 ; Bit 1
USB_EP7R_DTOG_RX EQU 0x4000 ; Data Toggle, for reception transfers
USB_EP7R_CTR_RX EQU 0x8000 ; Correct Transfer for reception
; Common registers
;****************** Bit definition for USB_CNTR register ******************
USB_CNTR_FRES EQU 0x0001 ; Force USB Reset
USB_CNTR_PDWN EQU 0x0002 ; Power down
USB_CNTR_LP_MODE EQU 0x0004 ; Low-power mode
USB_CNTR_FSUSP EQU 0x0008 ; Force suspend
USB_CNTR_RESUME EQU 0x0010 ; Resume request
USB_CNTR_ESOFM EQU 0x0100 ; Expected Start Of Frame Interrupt Mask
USB_CNTR_SOFM EQU 0x0200 ; Start Of Frame Interrupt Mask
USB_CNTR_RESETM EQU 0x0400 ; RESET Interrupt Mask
USB_CNTR_SUSPM EQU 0x0800 ; Suspend mode Interrupt Mask
USB_CNTR_WKUPM EQU 0x1000 ; Wakeup Interrupt Mask
USB_CNTR_ERRM EQU 0x2000 ; Error Interrupt Mask
USB_CNTR_PMAOVRM EQU 0x4000 ; Packet Memory Area Over / Underrun Interrupt Mask
USB_CNTR_CTRM EQU 0x8000 ; Correct Transfer Interrupt Mask
;****************** Bit definition for USB_ISTR register ******************
USB_ISTR_EP_ID EQU 0x000F ; Endpoint Identifier
USB_ISTR_DIR EQU 0x0010 ; Direction of transaction
USB_ISTR_ESOF EQU 0x0100 ; Expected Start Of Frame
USB_ISTR_SOF EQU 0x0200 ; Start Of Frame
USB_ISTR_RESET EQU 0x0400 ; USB RESET request
USB_ISTR_SUSP EQU 0x0800 ; Suspend mode request
USB_ISTR_WKUP EQU 0x1000 ; Wake up
USB_ISTR_ERR EQU 0x2000 ; Error
USB_ISTR_PMAOVR EQU 0x4000 ; Packet Memory Area Over / Underrun
USB_ISTR_CTR EQU 0x8000 ; Correct Transfer
;****************** Bit definition for USB_FNR register *******************
USB_FNR_FN EQU 0x07FF ; Frame Number
USB_FNR_LSOF EQU 0x1800 ; Lost SOF
USB_FNR_LCK EQU 0x2000 ; Locked
USB_FNR_RXDM EQU 0x4000 ; Receive Data - Line Status
USB_FNR_RXDP EQU 0x8000 ; Receive Data + Line Status
;***************** Bit definition for USB_DADDR register ******************
USB_DADDR_ADD EQU 0x7F ; ADD[6:0] bits (Device Address)
USB_DADDR_ADD0 EQU 0x01 ; Bit 0
USB_DADDR_ADD1 EQU 0x02 ; Bit 1
USB_DADDR_ADD2 EQU 0x04 ; Bit 2
USB_DADDR_ADD3 EQU 0x08 ; Bit 3
USB_DADDR_ADD4 EQU 0x10 ; Bit 4
USB_DADDR_ADD5 EQU 0x20 ; Bit 5
USB_DADDR_ADD6 EQU 0x40 ; Bit 6
USB_DADDR_EF EQU 0x80 ; Enable Function
;***************** Bit definition for USB_BTABLE register *****************
USB_BTABLE_BTABLE EQU 0xFFF8 ; Buffer Table
; Buffer descriptor table
;**************** Bit definition for USB_ADDR0_TX register ****************
USB_ADDR0_TX_ADDR0_TX EQU 0xFFFE ; Transmission Buffer Address 0
;**************** Bit definition for USB_ADDR1_TX register ****************
USB_ADDR1_TX_ADDR1_TX EQU 0xFFFE ; Transmission Buffer Address 1
;**************** Bit definition for USB_ADDR2_TX register ****************
USB_ADDR2_TX_ADDR2_TX EQU 0xFFFE ; Transmission Buffer Address 2
;**************** Bit definition for USB_ADDR3_TX register ****************
USB_ADDR3_TX_ADDR3_TX EQU 0xFFFE ; Transmission Buffer Address 3
;**************** Bit definition for USB_ADDR4_TX register ****************
USB_ADDR4_TX_ADDR4_TX EQU 0xFFFE ; Transmission Buffer Address 4
;**************** Bit definition for USB_ADDR5_TX register ****************
USB_ADDR5_TX_ADDR5_TX EQU 0xFFFE ; Transmission Buffer Address 5
;**************** Bit definition for USB_ADDR6_TX register ****************
USB_ADDR6_TX_ADDR6_TX EQU 0xFFFE ; Transmission Buffer Address 6
;**************** Bit definition for USB_ADDR7_TX register ****************
USB_ADDR7_TX_ADDR7_TX EQU 0xFFFE ; Transmission Buffer Address 7
;----------------------------------------------------------------------------
;**************** Bit definition for USB_COUNT0_TX register ***************
USB_COUNT0_TX_COUNT0_TX EQU 0x03FF ; Transmission Byte Count 0
;**************** Bit definition for USB_COUNT1_TX register ***************
USB_COUNT1_TX_COUNT1_TX EQU 0x03FF ; Transmission Byte Count 1
;**************** Bit definition for USB_COUNT2_TX register ***************
USB_COUNT2_TX_COUNT2_TX EQU 0x03FF ; Transmission Byte Count 2
;**************** Bit definition for USB_COUNT3_TX register ***************
USB_COUNT3_TX_COUNT3_TX EQU 0x03FF ; Transmission Byte Count 3
;**************** Bit definition for USB_COUNT4_TX register ***************
USB_COUNT4_TX_COUNT4_TX EQU 0x03FF ; Transmission Byte Count 4
;**************** Bit definition for USB_COUNT5_TX register ***************
USB_COUNT5_TX_COUNT5_TX EQU 0x03FF ; Transmission Byte Count 5
;**************** Bit definition for USB_COUNT6_TX register ***************
USB_COUNT6_TX_COUNT6_TX EQU 0x03FF ; Transmission Byte Count 6
;**************** Bit definition for USB_COUNT7_TX register ***************
USB_COUNT7_TX_COUNT7_TX EQU 0x03FF ; Transmission Byte Count 7
;----------------------------------------------------------------------------
;*************** Bit definition for USB_COUNT0_TX_0 register **************
USB_COUNT0_TX_0_COUNT0_TX_0 EQU 0x000003FF ; Transmission Byte Count 0 (low)
;*************** Bit definition for USB_COUNT0_TX_1 register **************
USB_COUNT0_TX_1_COUNT0_TX_1 EQU 0x03FF0000 ; Transmission Byte Count 0 (high)
;*************** Bit definition for USB_COUNT1_TX_0 register **************
USB_COUNT1_TX_0_COUNT1_TX_0 EQU 0x000003FF ; Transmission Byte Count 1 (low)
;*************** Bit definition for USB_COUNT1_TX_1 register **************
USB_COUNT1_TX_1_COUNT1_TX_1 EQU 0x03FF0000 ; Transmission Byte Count 1 (high)
;*************** Bit definition for USB_COUNT2_TX_0 register **************
USB_COUNT2_TX_0_COUNT2_TX_0 EQU 0x000003FF ; Transmission Byte Count 2 (low)
;*************** Bit definition for USB_COUNT2_TX_1 register **************
USB_COUNT2_TX_1_COUNT2_TX_1 EQU 0x03FF0000 ; Transmission Byte Count 2 (high)
;*************** Bit definition for USB_COUNT3_TX_0 register **************
USB_COUNT3_TX_0_COUNT3_TX_0 EQU 0x000003FF ; Transmission Byte Count 3 (low)
;*************** Bit definition for USB_COUNT3_TX_1 register **************
USB_COUNT3_TX_1_COUNT3_TX_1 EQU 0x03FF0000 ; Transmission Byte Count 3 (high)
;*************** Bit definition for USB_COUNT4_TX_0 register **************
USB_COUNT4_TX_0_COUNT4_TX_0 EQU 0x000003FF ; Transmission Byte Count 4 (low)
;*************** Bit definition for USB_COUNT4_TX_1 register **************
USB_COUNT4_TX_1_COUNT4_TX_1 EQU 0x03FF0000 ; Transmission Byte Count 4 (high)
;*************** Bit definition for USB_COUNT5_TX_0 register **************
USB_COUNT5_TX_0_COUNT5_TX_0 EQU 0x000003FF ; Transmission Byte Count 5 (low)
;*************** Bit definition for USB_COUNT5_TX_1 register **************
USB_COUNT5_TX_1_COUNT5_TX_1 EQU 0x03FF0000 ; Transmission Byte Count 5 (high)
;*************** Bit definition for USB_COUNT6_TX_0 register **************
USB_COUNT6_TX_0_COUNT6_TX_0 EQU 0x000003FF ; Transmission Byte Count 6 (low)
;*************** Bit definition for USB_COUNT6_TX_1 register **************
USB_COUNT6_TX_1_COUNT6_TX_1 EQU 0x03FF0000 ; Transmission Byte Count 6 (high)
;*************** Bit definition for USB_COUNT7_TX_0 register **************
USB_COUNT7_TX_0_COUNT7_TX_0 EQU 0x000003FF ; Transmission Byte Count 7 (low)
;*************** Bit definition for USB_COUNT7_TX_1 register **************
USB_COUNT7_TX_1_COUNT7_TX_1 EQU 0x03FF0000 ; Transmission Byte Count 7 (high)
;----------------------------------------------------------------------------
;**************** Bit definition for USB_ADDR0_RX register ****************
USB_ADDR0_RX_ADDR0_RX EQU 0xFFFE ; Reception Buffer Address 0
;**************** Bit definition for USB_ADDR1_RX register ****************
USB_ADDR1_RX_ADDR1_RX EQU 0xFFFE ; Reception Buffer Address 1
;**************** Bit definition for USB_ADDR2_RX register ****************
USB_ADDR2_RX_ADDR2_RX EQU 0xFFFE ; Reception Buffer Address 2
;**************** Bit definition for USB_ADDR3_RX register ****************
USB_ADDR3_RX_ADDR3_RX EQU 0xFFFE ; Reception Buffer Address 3
;**************** Bit definition for USB_ADDR4_RX register ****************
USB_ADDR4_RX_ADDR4_RX EQU 0xFFFE ; Reception Buffer Address 4
;**************** Bit definition for USB_ADDR5_RX register ****************
USB_ADDR5_RX_ADDR5_RX EQU 0xFFFE ; Reception Buffer Address 5
;**************** Bit definition for USB_ADDR6_RX register ****************
USB_ADDR6_RX_ADDR6_RX EQU 0xFFFE ; Reception Buffer Address 6
;**************** Bit definition for USB_ADDR7_RX register ****************
USB_ADDR7_RX_ADDR7_RX EQU 0xFFFE ; Reception Buffer Address 7
;----------------------------------------------------------------------------
;**************** Bit definition for USB_COUNT0_RX register ***************
USB_COUNT0_RX_COUNT0_RX EQU 0x03FF ; Reception Byte Count
USB_COUNT0_RX_NUM_BLOCK EQU 0x7C00 ; NUM_BLOCK[4:0] bits (Number of blocks)
USB_COUNT0_RX_NUM_BLOCK_0 EQU 0x0400 ; Bit 0
USB_COUNT0_RX_NUM_BLOCK_1 EQU 0x0800 ; Bit 1
USB_COUNT0_RX_NUM_BLOCK_2 EQU 0x1000 ; Bit 2
USB_COUNT0_RX_NUM_BLOCK_3 EQU 0x2000 ; Bit 3
USB_COUNT0_RX_NUM_BLOCK_4 EQU 0x4000 ; Bit 4
USB_COUNT0_RX_BLSIZE EQU 0x8000 ; BLock SIZE
;**************** Bit definition for USB_COUNT1_RX register ***************
USB_COUNT1_RX_COUNT1_RX EQU 0x03FF ; Reception Byte Count
USB_COUNT1_RX_NUM_BLOCK EQU 0x7C00 ; NUM_BLOCK[4:0] bits (Number of blocks)
USB_COUNT1_RX_NUM_BLOCK_0 EQU 0x0400 ; Bit 0
USB_COUNT1_RX_NUM_BLOCK_1 EQU 0x0800 ; Bit 1
USB_COUNT1_RX_NUM_BLOCK_2 EQU 0x1000 ; Bit 2
USB_COUNT1_RX_NUM_BLOCK_3 EQU 0x2000 ; Bit 3
USB_COUNT1_RX_NUM_BLOCK_4 EQU 0x4000 ; Bit 4
USB_COUNT1_RX_BLSIZE EQU 0x8000 ; BLock SIZE
;**************** Bit definition for USB_COUNT2_RX register ***************
USB_COUNT2_RX_COUNT2_RX EQU 0x03FF ; Reception Byte Count
USB_COUNT2_RX_NUM_BLOCK EQU 0x7C00 ; NUM_BLOCK[4:0] bits (Number of blocks)
USB_COUNT2_RX_NUM_BLOCK_0 EQU 0x0400 ; Bit 0
USB_COUNT2_RX_NUM_BLOCK_1 EQU 0x0800 ; Bit 1
USB_COUNT2_RX_NUM_BLOCK_2 EQU 0x1000 ; Bit 2
USB_COUNT2_RX_NUM_BLOCK_3 EQU 0x2000 ; Bit 3
USB_COUNT2_RX_NUM_BLOCK_4 EQU 0x4000 ; Bit 4
USB_COUNT2_RX_BLSIZE EQU 0x8000 ; BLock SIZE
;**************** Bit definition for USB_COUNT3_RX register ***************
USB_COUNT3_RX_COUNT3_RX EQU 0x03FF ; Reception Byte Count
USB_COUNT3_RX_NUM_BLOCK EQU 0x7C00 ; NUM_BLOCK[4:0] bits (Number of blocks)
USB_COUNT3_RX_NUM_BLOCK_0 EQU 0x0400 ; Bit 0
USB_COUNT3_RX_NUM_BLOCK_1 EQU 0x0800 ; Bit 1
USB_COUNT3_RX_NUM_BLOCK_2 EQU 0x1000 ; Bit 2
USB_COUNT3_RX_NUM_BLOCK_3 EQU 0x2000 ; Bit 3
USB_COUNT3_RX_NUM_BLOCK_4 EQU 0x4000 ; Bit 4
USB_COUNT3_RX_BLSIZE EQU 0x8000 ; BLock SIZE
;**************** Bit definition for USB_COUNT4_RX register ***************
USB_COUNT4_RX_COUNT4_RX EQU 0x03FF ; Reception Byte Count
USB_COUNT4_RX_NUM_BLOCK EQU 0x7C00 ; NUM_BLOCK[4:0] bits (Number of blocks)
USB_COUNT4_RX_NUM_BLOCK_0 EQU 0x0400 ; Bit 0
USB_COUNT4_RX_NUM_BLOCK_1 EQU 0x0800 ; Bit 1
USB_COUNT4_RX_NUM_BLOCK_2 EQU 0x1000 ; Bit 2
USB_COUNT4_RX_NUM_BLOCK_3 EQU 0x2000 ; Bit 3
USB_COUNT4_RX_NUM_BLOCK_4 EQU 0x4000 ; Bit 4
USB_COUNT4_RX_BLSIZE EQU 0x8000 ; BLock SIZE
;**************** Bit definition for USB_COUNT5_RX register ***************
USB_COUNT5_RX_COUNT5_RX EQU 0x03FF ; Reception Byte Count
USB_COUNT5_RX_NUM_BLOCK EQU 0x7C00 ; NUM_BLOCK[4:0] bits (Number of blocks)
USB_COUNT5_RX_NUM_BLOCK_0 EQU 0x0400 ; Bit 0
USB_COUNT5_RX_NUM_BLOCK_1 EQU 0x0800 ; Bit 1
USB_COUNT5_RX_NUM_BLOCK_2 EQU 0x1000 ; Bit 2
USB_COUNT5_RX_NUM_BLOCK_3 EQU 0x2000 ; Bit 3
USB_COUNT5_RX_NUM_BLOCK_4 EQU 0x4000 ; Bit 4
USB_COUNT5_RX_BLSIZE EQU 0x8000 ; BLock SIZE
;**************** Bit definition for USB_COUNT6_RX register ***************
USB_COUNT6_RX_COUNT6_RX EQU 0x03FF ; Reception Byte Count
USB_COUNT6_RX_NUM_BLOCK EQU 0x7C00 ; NUM_BLOCK[4:0] bits (Number of blocks)
USB_COUNT6_RX_NUM_BLOCK_0 EQU 0x0400 ; Bit 0
USB_COUNT6_RX_NUM_BLOCK_1 EQU 0x0800 ; Bit 1
USB_COUNT6_RX_NUM_BLOCK_2 EQU 0x1000 ; Bit 2
USB_COUNT6_RX_NUM_BLOCK_3 EQU 0x2000 ; Bit 3
USB_COUNT6_RX_NUM_BLOCK_4 EQU 0x4000 ; Bit 4
USB_COUNT6_RX_BLSIZE EQU 0x8000 ; BLock SIZE
;**************** Bit definition for USB_COUNT7_RX register ***************
USB_COUNT7_RX_COUNT7_RX EQU 0x03FF ; Reception Byte Count
USB_COUNT7_RX_NUM_BLOCK EQU 0x7C00 ; NUM_BLOCK[4:0] bits (Number of blocks)
USB_COUNT7_RX_NUM_BLOCK_0 EQU 0x0400 ; Bit 0
USB_COUNT7_RX_NUM_BLOCK_1 EQU 0x0800 ; Bit 1
USB_COUNT7_RX_NUM_BLOCK_2 EQU 0x1000 ; Bit 2
USB_COUNT7_RX_NUM_BLOCK_3 EQU 0x2000 ; Bit 3
USB_COUNT7_RX_NUM_BLOCK_4 EQU 0x4000 ; Bit 4
USB_COUNT7_RX_BLSIZE EQU 0x8000 ; BLock SIZE
;----------------------------------------------------------------------------
;*************** Bit definition for USB_COUNT0_RX_0 register **************
USB_COUNT0_RX_0_COUNT0_RX_0 EQU 0x000003FF ; Reception Byte Count (low)
USB_COUNT0_RX_0_NUM_BLOCK_0 EQU 0x00007C00 ; NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
USB_COUNT0_RX_0_NUM_BLOCK_0_0 EQU 0x00000400 ; Bit 0
USB_COUNT0_RX_0_NUM_BLOCK_0_1 EQU 0x00000800 ; Bit 1
USB_COUNT0_RX_0_NUM_BLOCK_0_2 EQU 0x00001000 ; Bit 2
USB_COUNT0_RX_0_NUM_BLOCK_0_3 EQU 0x00002000 ; Bit 3
USB_COUNT0_RX_0_NUM_BLOCK_0_4 EQU 0x00004000 ; Bit 4
USB_COUNT0_RX_0_BLSIZE_0 EQU 0x00008000 ; BLock SIZE (low)
;*************** Bit definition for USB_COUNT0_RX_1 register **************
USB_COUNT0_RX_1_COUNT0_RX_1 EQU 0x03FF0000 ; Reception Byte Count (high)
USB_COUNT0_RX_1_NUM_BLOCK_1 EQU 0x7C000000 ; NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
USB_COUNT0_RX_1_NUM_BLOCK_1_0 EQU 0x04000000 ; Bit 1
USB_COUNT0_RX_1_NUM_BLOCK_1_1 EQU 0x08000000 ; Bit 1
USB_COUNT0_RX_1_NUM_BLOCK_1_2 EQU 0x10000000 ; Bit 2
USB_COUNT0_RX_1_NUM_BLOCK_1_3 EQU 0x20000000 ; Bit 3
USB_COUNT0_RX_1_NUM_BLOCK_1_4 EQU 0x40000000 ; Bit 4
USB_COUNT0_RX_1_BLSIZE_1 EQU 0x80000000 ; BLock SIZE (high)
;*************** Bit definition for USB_COUNT1_RX_0 register **************
USB_COUNT1_RX_0_COUNT1_RX_0 EQU 0x000003FF ; Reception Byte Count (low)
USB_COUNT1_RX_0_NUM_BLOCK_0 EQU 0x00007C00 ; NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
USB_COUNT1_RX_0_NUM_BLOCK_0_0 EQU 0x00000400 ; Bit 0
USB_COUNT1_RX_0_NUM_BLOCK_0_1 EQU 0x00000800 ; Bit 1
USB_COUNT1_RX_0_NUM_BLOCK_0_2 EQU 0x00001000 ; Bit 2
USB_COUNT1_RX_0_NUM_BLOCK_0_3 EQU 0x00002000 ; Bit 3
USB_COUNT1_RX_0_NUM_BLOCK_0_4 EQU 0x00004000 ; Bit 4
USB_COUNT1_RX_0_BLSIZE_0 EQU 0x00008000 ; BLock SIZE (low)
;*************** Bit definition for USB_COUNT1_RX_1 register **************
USB_COUNT1_RX_1_COUNT1_RX_1 EQU 0x03FF0000 ; Reception Byte Count (high)
USB_COUNT1_RX_1_NUM_BLOCK_1 EQU 0x7C000000 ; NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
USB_COUNT1_RX_1_NUM_BLOCK_1_0 EQU 0x04000000 ; Bit 0
USB_COUNT1_RX_1_NUM_BLOCK_1_1 EQU 0x08000000 ; Bit 1
USB_COUNT1_RX_1_NUM_BLOCK_1_2 EQU 0x10000000 ; Bit 2
USB_COUNT1_RX_1_NUM_BLOCK_1_3 EQU 0x20000000 ; Bit 3
USB_COUNT1_RX_1_NUM_BLOCK_1_4 EQU 0x40000000 ; Bit 4
USB_COUNT1_RX_1_BLSIZE_1 EQU 0x80000000 ; BLock SIZE (high)
;*************** Bit definition for USB_COUNT2_RX_0 register **************
USB_COUNT2_RX_0_COUNT2_RX_0 EQU 0x000003FF ; Reception Byte Count (low)
USB_COUNT2_RX_0_NUM_BLOCK_0 EQU 0x00007C00 ; NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
USB_COUNT2_RX_0_NUM_BLOCK_0_0 EQU 0x00000400 ; Bit 0
USB_COUNT2_RX_0_NUM_BLOCK_0_1 EQU 0x00000800 ; Bit 1
USB_COUNT2_RX_0_NUM_BLOCK_0_2 EQU 0x00001000 ; Bit 2
USB_COUNT2_RX_0_NUM_BLOCK_0_3 EQU 0x00002000 ; Bit 3
USB_COUNT2_RX_0_NUM_BLOCK_0_4 EQU 0x00004000 ; Bit 4
USB_COUNT2_RX_0_BLSIZE_0 EQU 0x00008000 ; BLock SIZE (low)
;*************** Bit definition for USB_COUNT2_RX_1 register **************
USB_COUNT2_RX_1_COUNT2_RX_1 EQU 0x03FF0000 ; Reception Byte Count (high)
USB_COUNT2_RX_1_NUM_BLOCK_1 EQU 0x7C000000 ; NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
USB_COUNT2_RX_1_NUM_BLOCK_1_0 EQU 0x04000000 ; Bit 0
USB_COUNT2_RX_1_NUM_BLOCK_1_1 EQU 0x08000000 ; Bit 1
USB_COUNT2_RX_1_NUM_BLOCK_1_2 EQU 0x10000000 ; Bit 2
USB_COUNT2_RX_1_NUM_BLOCK_1_3 EQU 0x20000000 ; Bit 3
USB_COUNT2_RX_1_NUM_BLOCK_1_4 EQU 0x40000000 ; Bit 4
USB_COUNT2_RX_1_BLSIZE_1 EQU 0x80000000 ; BLock SIZE (high)
;*************** Bit definition for USB_COUNT3_RX_0 register **************
USB_COUNT3_RX_0_COUNT3_RX_0 EQU 0x000003FF ; Reception Byte Count (low)
USB_COUNT3_RX_0_NUM_BLOCK_0 EQU 0x00007C00 ; NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
USB_COUNT3_RX_0_NUM_BLOCK_0_0 EQU 0x00000400 ; Bit 0
USB_COUNT3_RX_0_NUM_BLOCK_0_1 EQU 0x00000800 ; Bit 1
USB_COUNT3_RX_0_NUM_BLOCK_0_2 EQU 0x00001000 ; Bit 2
USB_COUNT3_RX_0_NUM_BLOCK_0_3 EQU 0x00002000 ; Bit 3
USB_COUNT3_RX_0_NUM_BLOCK_0_4 EQU 0x00004000 ; Bit 4
USB_COUNT3_RX_0_BLSIZE_0 EQU 0x00008000 ; BLock SIZE (low)
;*************** Bit definition for USB_COUNT3_RX_1 register **************
USB_COUNT3_RX_1_COUNT3_RX_1 EQU 0x03FF0000 ; Reception Byte Count (high)
USB_COUNT3_RX_1_NUM_BLOCK_1 EQU 0x7C000000 ; NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
USB_COUNT3_RX_1_NUM_BLOCK_1_0 EQU 0x04000000 ; Bit 0
USB_COUNT3_RX_1_NUM_BLOCK_1_1 EQU 0x08000000 ; Bit 1
USB_COUNT3_RX_1_NUM_BLOCK_1_2 EQU 0x10000000 ; Bit 2
USB_COUNT3_RX_1_NUM_BLOCK_1_3 EQU 0x20000000 ; Bit 3
USB_COUNT3_RX_1_NUM_BLOCK_1_4 EQU 0x40000000 ; Bit 4
USB_COUNT3_RX_1_BLSIZE_1 EQU 0x80000000 ; BLock SIZE (high)
;*************** Bit definition for USB_COUNT4_RX_0 register **************
USB_COUNT4_RX_0_COUNT4_RX_0 EQU 0x000003FF ; Reception Byte Count (low)
USB_COUNT4_RX_0_NUM_BLOCK_0 EQU 0x00007C00 ; NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
USB_COUNT4_RX_0_NUM_BLOCK_0_0 EQU 0x00000400 ; Bit 0
USB_COUNT4_RX_0_NUM_BLOCK_0_1 EQU 0x00000800 ; Bit 1
USB_COUNT4_RX_0_NUM_BLOCK_0_2 EQU 0x00001000 ; Bit 2
USB_COUNT4_RX_0_NUM_BLOCK_0_3 EQU 0x00002000 ; Bit 3
USB_COUNT4_RX_0_NUM_BLOCK_0_4 EQU 0x00004000 ; Bit 4
USB_COUNT4_RX_0_BLSIZE_0 EQU 0x00008000 ; BLock SIZE (low)
;*************** Bit definition for USB_COUNT4_RX_1 register **************
USB_COUNT4_RX_1_COUNT4_RX_1 EQU 0x03FF0000 ; Reception Byte Count (high)
USB_COUNT4_RX_1_NUM_BLOCK_1 EQU 0x7C000000 ; NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
USB_COUNT4_RX_1_NUM_BLOCK_1_0 EQU 0x04000000 ; Bit 0
USB_COUNT4_RX_1_NUM_BLOCK_1_1 EQU 0x08000000 ; Bit 1
USB_COUNT4_RX_1_NUM_BLOCK_1_2 EQU 0x10000000 ; Bit 2
USB_COUNT4_RX_1_NUM_BLOCK_1_3 EQU 0x20000000 ; Bit 3
USB_COUNT4_RX_1_NUM_BLOCK_1_4 EQU 0x40000000 ; Bit 4
USB_COUNT4_RX_1_BLSIZE_1 EQU 0x80000000 ; BLock SIZE (high)
;*************** Bit definition for USB_COUNT5_RX_0 register **************
USB_COUNT5_RX_0_COUNT5_RX_0 EQU 0x000003FF ; Reception Byte Count (low)
USB_COUNT5_RX_0_NUM_BLOCK_0 EQU 0x00007C00 ; NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
USB_COUNT5_RX_0_NUM_BLOCK_0_0 EQU 0x00000400 ; Bit 0
USB_COUNT5_RX_0_NUM_BLOCK_0_1 EQU 0x00000800 ; Bit 1
USB_COUNT5_RX_0_NUM_BLOCK_0_2 EQU 0x00001000 ; Bit 2
USB_COUNT5_RX_0_NUM_BLOCK_0_3 EQU 0x00002000 ; Bit 3
USB_COUNT5_RX_0_NUM_BLOCK_0_4 EQU 0x00004000 ; Bit 4
USB_COUNT5_RX_0_BLSIZE_0 EQU 0x00008000 ; BLock SIZE (low)
;*************** Bit definition for USB_COUNT5_RX_1 register **************
USB_COUNT5_RX_1_COUNT5_RX_1 EQU 0x03FF0000 ; Reception Byte Count (high)
USB_COUNT5_RX_1_NUM_BLOCK_1 EQU 0x7C000000 ; NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
USB_COUNT5_RX_1_NUM_BLOCK_1_0 EQU 0x04000000 ; Bit 0
USB_COUNT5_RX_1_NUM_BLOCK_1_1 EQU 0x08000000 ; Bit 1
USB_COUNT5_RX_1_NUM_BLOCK_1_2 EQU 0x10000000 ; Bit 2
USB_COUNT5_RX_1_NUM_BLOCK_1_3 EQU 0x20000000 ; Bit 3
USB_COUNT5_RX_1_NUM_BLOCK_1_4 EQU 0x40000000 ; Bit 4
USB_COUNT5_RX_1_BLSIZE_1 EQU 0x80000000 ; BLock SIZE (high)
;************** Bit definition for USB_COUNT6_RX_0 register **************
USB_COUNT6_RX_0_COUNT6_RX_0 EQU 0x000003FF ; Reception Byte Count (low)
USB_COUNT6_RX_0_NUM_BLOCK_0 EQU 0x00007C00 ; NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
USB_COUNT6_RX_0_NUM_BLOCK_0_0 EQU 0x00000400 ; Bit 0
USB_COUNT6_RX_0_NUM_BLOCK_0_1 EQU 0x00000800 ; Bit 1
USB_COUNT6_RX_0_NUM_BLOCK_0_2 EQU 0x00001000 ; Bit 2
USB_COUNT6_RX_0_NUM_BLOCK_0_3 EQU 0x00002000 ; Bit 3
USB_COUNT6_RX_0_NUM_BLOCK_0_4 EQU 0x00004000 ; Bit 4
USB_COUNT6_RX_0_BLSIZE_0 EQU 0x00008000 ; BLock SIZE (low)
;*************** Bit definition for USB_COUNT6_RX_1 register **************
USB_COUNT6_RX_1_COUNT6_RX_1 EQU 0x03FF0000 ; Reception Byte Count (high)
USB_COUNT6_RX_1_NUM_BLOCK_1 EQU 0x7C000000 ; NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
USB_COUNT6_RX_1_NUM_BLOCK_1_0 EQU 0x04000000 ; Bit 0
USB_COUNT6_RX_1_NUM_BLOCK_1_1 EQU 0x08000000 ; Bit 1
USB_COUNT6_RX_1_NUM_BLOCK_1_2 EQU 0x10000000 ; Bit 2
USB_COUNT6_RX_1_NUM_BLOCK_1_3 EQU 0x20000000 ; Bit 3
USB_COUNT6_RX_1_NUM_BLOCK_1_4 EQU 0x40000000 ; Bit 4
USB_COUNT6_RX_1_BLSIZE_1 EQU 0x80000000 ; BLock SIZE (high)
;************** Bit definition for USB_COUNT7_RX_0 register ***************
USB_COUNT7_RX_0_COUNT7_RX_0 EQU 0x000003FF ; Reception Byte Count (low)
USB_COUNT7_RX_0_NUM_BLOCK_0 EQU 0x00007C00 ; NUM_BLOCK_0[4:0] bits (Number of blocks) (low)
USB_COUNT7_RX_0_NUM_BLOCK_0_0 EQU 0x00000400 ; Bit 0
USB_COUNT7_RX_0_NUM_BLOCK_0_1 EQU 0x00000800 ; Bit 1
USB_COUNT7_RX_0_NUM_BLOCK_0_2 EQU 0x00001000 ; Bit 2
USB_COUNT7_RX_0_NUM_BLOCK_0_3 EQU 0x00002000 ; Bit 3
USB_COUNT7_RX_0_NUM_BLOCK_0_4 EQU 0x00004000 ; Bit 4
USB_COUNT7_RX_0_BLSIZE_0 EQU 0x00008000 ; BLock SIZE (low)
;************** Bit definition for USB_COUNT7_RX_1 register ***************
USB_COUNT7_RX_1_COUNT7_RX_1 EQU 0x03FF0000 ; Reception Byte Count (high)
USB_COUNT7_RX_1_NUM_BLOCK_1 EQU 0x7C000000 ; NUM_BLOCK_1[4:0] bits (Number of blocks) (high)
USB_COUNT7_RX_1_NUM_BLOCK_1_0 EQU 0x04000000 ; Bit 0
USB_COUNT7_RX_1_NUM_BLOCK_1_1 EQU 0x08000000 ; Bit 1
USB_COUNT7_RX_1_NUM_BLOCK_1_2 EQU 0x10000000 ; Bit 2
USB_COUNT7_RX_1_NUM_BLOCK_1_3 EQU 0x20000000 ; Bit 3
USB_COUNT7_RX_1_NUM_BLOCK_1_4 EQU 0x40000000 ; Bit 4
USB_COUNT7_RX_1_BLSIZE_1 EQU 0x80000000 ; BLock SIZE (high)
END

@ -0,0 +1,48 @@
;********************************************************************************
; SOUBOR : INI_BITS_WWDG.S
; AUTOR : Petr Dousa, Ondrej Hruska
; DATUM : 10/2015
; POPIS : Bitove masky ridicich registru pro WWDG
;
; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
;********************************************************************************
;****************************************************************************
;
; Window WATCHDOG (WWDG)
;
;****************************************************************************
;****************** Bit definition for WWDG_CR register *******************
WWDG_CR_T EQU 0x7F ; T[6:0] bits (7-Bit counter (MSB to LSB))
WWDG_CR_T0 EQU 0x01 ; Bit 0
WWDG_CR_T1 EQU 0x02 ; Bit 1
WWDG_CR_T2 EQU 0x04 ; Bit 2
WWDG_CR_T3 EQU 0x08 ; Bit 3
WWDG_CR_T4 EQU 0x10 ; Bit 4
WWDG_CR_T5 EQU 0x20 ; Bit 5
WWDG_CR_T6 EQU 0x40 ; Bit 6
WWDG_CR_WDGA EQU 0x80 ; Activation bit
;****************** Bit definition for WWDG_CFR register ******************
WWDG_CFR_W EQU 0x007F ; W[6:0] bits (7-bit window value)
WWDG_CFR_W0 EQU 0x0001 ; Bit 0
WWDG_CFR_W1 EQU 0x0002 ; Bit 1
WWDG_CFR_W2 EQU 0x0004 ; Bit 2
WWDG_CFR_W3 EQU 0x0008 ; Bit 3
WWDG_CFR_W4 EQU 0x0010 ; Bit 4
WWDG_CFR_W5 EQU 0x0020 ; Bit 5
WWDG_CFR_W6 EQU 0x0040 ; Bit 6
WWDG_CFR_WDGTB EQU 0x0180 ; WDGTB[1:0] bits (Timer Base)
WWDG_CFR_WDGTB0 EQU 0x0080 ; Bit 0
WWDG_CFR_WDGTB1 EQU 0x0100 ; Bit 1
WWDG_CFR_EWI EQU 0x0200 ; Early Wakeup Interrupt
;****************** Bit definition for WWDG_SR register *******************
WWDG_SR_EWIF EQU 0x01 ; Early Wakeup Interrupt Flag
END

File diff suppressed because it is too large Load Diff

@ -0,0 +1,257 @@
;***************************************************************************************************
;*
;* Misto : CVUT FEL, Katedra Mereni
;* Prednasejici : Doc. Ing. Jan Fischer,CSc.
;* Predmet : A4M38AVS, A4B38NVS
;* Vyvojovy Kit : STM32L100 DISCOVERY (STM32L100RC)
;* Datum : 12/2010, 10/2015
;* Autor : Michal TOMAS (2010), Ondrej Hruska (2015)
;*
;***************************************************************************************************
;***************************************************************************************************
;* Include library files
;***************************************************************************************************
; Register addresses
GET lib/INI_REGS.s
; Bit presets
GET lib/INI_BITS_GPIO.s
GET lib/INI_BITS_RCC.s
GET lib/INI_BITS_FLASH.s
GET lib/INI_BITS_SYSTICK.s
GET lib/INI_BB.s
;***************************************************************************************************
;* Start program AREA and pass compiler flags to the startup script...
;***************************************************************************************************
AREA MAIN, CODE, READONLY
; This is a compiler flag imported by the startup script.
__use_two_region_memory
EXPORT __use_two_region_memory
;***************************************************************************************************
;* System config (clock, ports, timers...)
;*
;* Called by the startup script before calling __main
;***************************************************************************************************
SystemInit
EXPORT SystemInit ; Export the address to startup script
PUSH {LR}
BL RCC_CNF ; Configure clock sources
BL GPIO_CNF ; Configure GPIO power and pin settings
BL SYSTICK_CNF ; Configure SysTick timer
POP {PC}
;***************************************************************************************************
;* Interrupt handlers...
;***************************************************************************************************
SysTick_Handler
EXPORT SysTick_Handler ; Export the address to startup script (replaces a WEAK stub)
PUSH {LR}
; Toggle the PC8 LED (bit-banding access)
LDR R0, =BB_GPIOC_ODR_9
LDR R1, [R0]
EOR R1, R1, #1
STR R1, [R0]
; alternative - writing the register
; LDR R0, =GPIOC_ODR
; LDR R1, [R0]
; EOR R1, R1, #GPIO9
; STR R1, [R0]
POP {PC}
;***************************************************************************************************
;* Main function
;*
;* Called by the startup script after SystemInit.
;* __main is called only once, and does not return!
;***************************************************************************************************
__main
EXPORT __main ; Export the address to startup script
ENTRY ; Marks the program entry point (shouldnt be here)
LOOP
; blink the other led slowly
; (using bit-banding)
LDR R0, =BB_GPIOC_ODR_8
LDR R1, [R0]
EOR R1, R1, #1
STR R1, [R0]
; (writing the entire register) - can cause race condition with SysTick interrupt
; LDR R0, =GPIOC_ODR
; LDR R1, [R0]
; EOR R1, R1, #GPIO8
; STR R1, [R0]
MOV R0, #50
BL DELAY
B LOOP
;**************************************************************************************************
;* GPIO configuration
;*
;* Sets PC08 and PC09 as outputs, PA0 as input.
;**************************************************************************************************
GPIO_CNF
PUSH {R0,R1,LR}
; Enable GPIO peripheral timing
LDR R0, =RCC_AHBENR ; Advanced High-speed Bus ENable Register
LDR R1, [R0]
LDR R2, =(RCC_AHBENR_GPIOAEN :OR: RCC_AHBENR_GPIOCEN)
ORR R1, R1, R2
STR R1, [R0]
; Output pins C8, C9
LDR R0, =GPIOC_MODER
LDR R1, [R0]
BIC R1,R1, #(GPIO_MODER_8 :OR: GPIO_MODER_9)
ORR R1,R1, #(GPIO_MODER_8 :OR: GPIO_MODER_9) & GPIO_MODER_OUTPUT
STR R1, [R0]
; Input pin A0
LDR R0, =GPIOA_MODER
LDR R1, [R0]
BIC R1,R1, #GPIO_MODER_0 ; Clear the bit config area
ORR R1,R1, #(GPIO_MODER_0 & GPIO_MODER_INPUT) ; Write the "input" pattern into the bit config area
STR R1, [R0]
POP {R0,R1,PC}
;**************************************************************************************************
;* SysTick configuration
;*
;* Configures SysTick to fire a SysTick interrupt at 1 Hz
;**************************************************************************************************
SYSTICK_CNF
PUSH {R0, R1, LR}
; Use the core clock (undivided)
LDR R0, =SysTick_CSR
LDR R1, [R0]
ORR R1, R1, #SysTick_CSR_CLKSOURCE_CORE
STR R1, [R0]
; Configure the reload register to 1s
LDR R1, =0xFFFFFF
LDR R0, =SysTick_RELOAD
STR R1, [R0]
; Enable SysTick interrupt & start counting
LDR R0, =SysTick_CSR
LDR R1, [R0]
ORR R1, R1, #(SysTick_CSR_TICKINT :OR: SysTick_CSR_ENABLE)
STR R1, [R0]
POP {R0, R1, PC}
;**************************************************************************************************
;* Delay routine
;*
;* Inputs: R0 = number of loop cycles
;**************************************************************************************************
DELAY
PUSH {R2, LR} ; Push the changed registers & link register
WAIT_OUTER ; Outer loop
LDR R2, =40000 ; Length of inner loop
; Inner loop
WAIT_INNER SUBS R2, R2, #1 ; Decrement INNER loop counter
BNE WAIT_INNER ; Continue the loop if not done
SUBS R0, R0, #1 ; Decrement OUTER loop counter
BNE WAIT_OUTER ; Continue the loop if not done
POP {R2, PC} ; Pop & return
;***************************************************************************************************
;* Konfigurace systemovych hodin a hodin periferii
;*
;* Nastavi hodiny na HSI 16 MHz
;**************************************************************************************************
RCC_CNF
PUSH {R0, R1, LR}
; Flash timing configuration
LDR R0, =FLASH_ACR
LDR R1, [R0]
ORR R1, R1, #FLASH_ACR_ACC64
STR R1, [R0]
LDR R1, [R0]
ORR R1, R1, #(FLASH_ACR_PRFTEN :OR: FLASH_ACR_LATENCY)
STR R1, [R0]
; Nastavit hodinove vstupy
LDR R0, =RCC_CR
; Additional RCC_CR config
; LDR R1, [R0]
; LDR R2, =RCC_CR_RTCPRE ; clear RTC prescaler
; BIC R1, R1, R2
; ; HseByp allows to use external clock source with HSEON
; LDR R2, =(RCC_CR_RTCPRE_DIV2 :OR: RCC_CR_HSEBYP)
; ORR R1, R1, R2
; STR R1, [R0]
; Power on HSI (runs from MSI on start)
LDR R1, [R0]
ORR R1, R1, #RCC_CR_HSION
STR R1, [R0]
; Wait for HSIRDY
ALIGN
NO_HSI_RDY LDR R1, [R0]
TST R1, #RCC_CR_HSIRDY
BEQ NO_HSI_RDY
; Select HSI as the core clock source
LDR R0, =RCC_CFGR
LDR R1, [R0]
BIC R1, R1, #RCC_CFGR_SW
ORR R1, R1, #RCC_CFGR_SW_HSI
STR R1, [R0]
POP {R0, R1, PC}
;**************************************************************************************************
ALIGN ; Adds NOP if needed to complete a 32-bit word
END

@ -0,0 +1,355 @@
;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32l100xc.s
;* Author : MCD Application Team
;* Version : V1.2.0
;* Date : 31-March-2015
;* Description : STM32L100XC Devices vector for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Configure the system clock
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* COPYRIGHT(c) 2015 STMicroelectronics
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400;
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200;
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
DCD RTC_WKUP_IRQHandler ; RTC Wakeup
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_IRQHandler ; USB High Priority
DCD USB_LP_IRQHandler ; USB Low Priority
DCD DAC_IRQHandler ; DAC
DCD COMP_IRQHandler ; COMP through EXTI Line
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD LCD_IRQHandler ; LCD
DCD TIM9_IRQHandler ; TIM9
DCD TIM10_IRQHandler ; TIM10
DCD TIM11_IRQHandler ; TIM11
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT TIM9_IRQHandler [WEAK]
EXPORT TIM10_IRQHandler [WEAK]
EXPORT TIM11_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USB_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT COMP_ACQ_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
DAC_IRQHandler
COMP_IRQHandler
EXTI9_5_IRQHandler
LCD_IRQHandler
TIM9_IRQHandler
TIM10_IRQHandler
TIM11_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USB_FS_WKUP_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
SPI3_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
COMP_ACQ_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
; Re-implement the stackheap init
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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