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146 lines
7.6 KiB
146 lines
7.6 KiB
9 years ago
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;********************************************************************************
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9 years ago
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; FILE : INI_SPI.S
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; AUTHOR : Petr Dousa, Ondrej Hruska
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; DATE : 10/2015
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9 years ago
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; DESCR : Control registers and bit masks for SPI
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9 years ago
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;
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9 years ago
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; Serial Peripheral Interface (SPI)
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;
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; Part of an assembler library for STM32L100, based on the STM32 CMSIS.
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; Developed for educational purposes at the Department of Measure of CTU in Prague.
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; See the LICENSE file for detailed terms of use.
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;********************************************************************************
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;****************************************************************************
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;*
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;* REGISTERS
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;*
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;****************************************************************************
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; SPI 1
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SPI1_CR1 EQU (_SPI1 + 0x00) ; SPI1 control register 1 (not used in I2S mode),
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SPI1_CR2 EQU (_SPI1 + 0x04) ; SPI1 control register 2,
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SPI1_SR EQU (_SPI1 + 0x08) ; SPI1 status register,
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SPI1_DR EQU (_SPI1 + 0x0C) ; SPI1 data register,
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SPI1_CRCPR EQU (_SPI1 + 0x10) ; SPI1 CRC polynomial register (not used in I2S mode),
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SPI1_RXCRCR EQU (_SPI1 + 0x14) ; SPI1 RX CRC register (not used in I2S mode),
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SPI1_TXCRCR EQU (_SPI1 + 0x18) ; SPI1 TX CRC register (not used in I2S mode),
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SPI1_I2SCFGR EQU (_SPI1 + 0x1C) ; SPI1_I2S configuration register,
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SPI1_I2SPR EQU (_SPI1 + 0x20) ; SPI1_I2S prescaler register,
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; SPI 2
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SPI2_CR1 EQU (_SPI2 + 0x00) ; SPI2 control register 1 (not used in I2S mode),
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SPI2_CR2 EQU (_SPI2 + 0x04) ; SPI2 control register 2,
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SPI2_SR EQU (_SPI2 + 0x08) ; SPI2 status register,
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SPI2_DR EQU (_SPI2 + 0x0C) ; SPI2 data register,
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SPI2_CRCPR EQU (_SPI2 + 0x10) ; SPI2 CRC polynomial register (not used in I2S mode),
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SPI2_RXCRCR EQU (_SPI2 + 0x14) ; SPI2 RX CRC register (not used in I2S mode),
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SPI2_TXCRCR EQU (_SPI2 + 0x18) ; SPI2 TX CRC register (not used in I2S mode),
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SPI2_I2SCFGR EQU (_SPI2 + 0x1C) ; SPI2_I2S configuration register,
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SPI2_I2SPR EQU (_SPI2 + 0x20) ; SPI2_I2S prescaler register,
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; SPI 3
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SPI3_CR1 EQU (_SPI3 + 0x00) ; SPI3 control register 1 (not used in I2S mode),
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SPI3_CR2 EQU (_SPI3 + 0x04) ; SPI3 control register 2,
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SPI3_SR EQU (_SPI3 + 0x08) ; SPI3 status register,
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SPI3_DR EQU (_SPI3 + 0x0C) ; SPI3 data register,
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SPI3_CRCPR EQU (_SPI3 + 0x10) ; SPI3 CRC polynomial register (not used in I2S mode),
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SPI3_RXCRCR EQU (_SPI3 + 0x14) ; SPI3 RX CRC register (not used in I2S mode),
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SPI3_TXCRCR EQU (_SPI3 + 0x18) ; SPI3 TX CRC register (not used in I2S mode),
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SPI3_I2SCFGR EQU (_SPI3 + 0x1C) ; SPI3_I2S configuration register,
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SPI3_I2SPR EQU (_SPI3 + 0x20) ; SPI3_I2S prescaler register,
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;****************************************************************************
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;*
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;* BIT MASKS AND DEFINITIONS
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;*
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;****************************************************************************
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;****************** Bit definition for SPI_CR1 register *******************
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SPI_CR1_CPHA EQU 0x0001 ; Clock Phase
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SPI_CR1_CPOL EQU 0x0002 ; Clock Polarity
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SPI_CR1_MSTR EQU 0x0004 ; Master Selection
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SPI_CR1_BR EQU 0x0038 ; BR[2:0] bits (Baud Rate Control)
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SPI_CR1_BR_0 EQU 0x0008 ; Bit 0
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SPI_CR1_BR_1 EQU 0x0010 ; Bit 1
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SPI_CR1_BR_2 EQU 0x0020 ; Bit 2
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SPI_CR1_SPE EQU 0x0040 ; SPI Enable
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SPI_CR1_LSBFIRST EQU 0x0080 ; Frame Format
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SPI_CR1_SSI EQU 0x0100 ; Internal slave select
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SPI_CR1_SSM EQU 0x0200 ; Software slave management
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SPI_CR1_RXONLY EQU 0x0400 ; Receive only
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SPI_CR1_DFF EQU 0x0800 ; Data Frame Format
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SPI_CR1_CRCNEXT EQU 0x1000 ; Transmit CRC next
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SPI_CR1_CRCEN EQU 0x2000 ; Hardware CRC calculation enable
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SPI_CR1_BIDIOE EQU 0x4000 ; Output enable in bidirectional mode
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SPI_CR1_BIDIMODE EQU 0x8000 ; Bidirectional data mode enable
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;****************** Bit definition for SPI_CR2 register *******************
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SPI_CR2_RXDMAEN EQU 0x01 ; Rx Buffer DMA Enable
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SPI_CR2_TXDMAEN EQU 0x02 ; Tx Buffer DMA Enable
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SPI_CR2_SSOE EQU 0x04 ; SS Output Enable
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SPI_CR2_FRF EQU 0x08 ; Frame format
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SPI_CR2_ERRIE EQU 0x20 ; Error Interrupt Enable
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SPI_CR2_RXNEIE EQU 0x40 ; RX buffer Not Empty Interrupt Enable
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SPI_CR2_TXEIE EQU 0x80 ; Tx buffer Empty Interrupt Enable
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;******************* Bit definition for SPI_SR register *******************
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SPI_SR_RXNE EQU 0x01 ; Receive buffer Not Empty
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SPI_SR_TXE EQU 0x02 ; Transmit buffer Empty
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SPI_SR_CHSIDE EQU 0x04 ; Channel side
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SPI_SR_UDR EQU 0x08 ; Underrun flag
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SPI_SR_CRCERR EQU 0x10 ; CRC Error flag
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SPI_SR_MODF EQU 0x20 ; Mode fault
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SPI_SR_OVR EQU 0x40 ; Overrun flag
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SPI_SR_BSY EQU 0x80 ; Busy flag
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;******************* Bit definition for SPI_DR register *******************
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SPI_DR_DR EQU 0xFFFF ; Data Register
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;****************** Bit definition for SPI_CRCPR register *****************
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SPI_CRCPR_CRCPOLY EQU 0xFFFF ; CRC polynomial register
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;***************** Bit definition for SPI_RXCRCR register *****************
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SPI_RXCRCR_RXCRC EQU 0xFFFF ; Rx CRC Register
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;***************** Bit definition for SPI_TXCRCR register *****************
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SPI_TXCRCR_TXCRC EQU 0xFFFF ; Tx CRC Register
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;***************** Bit definition for SPI_I2SCFGR register ****************
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SPI_I2SCFGR_CHLEN EQU 0x0001 ; Channel length (number of bits per audio channel)
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SPI_I2SCFGR_DATLEN EQU 0x0006 ; DATLEN[1:0] bits (Data length to be transferred)
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SPI_I2SCFGR_DATLEN_0 EQU 0x0002 ; Bit 0
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SPI_I2SCFGR_DATLEN_1 EQU 0x0004 ; Bit 1
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SPI_I2SCFGR_CKPOL EQU 0x0008 ; steady state clock polarity
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SPI_I2SCFGR_I2SSTD EQU 0x0030 ; I2SSTD[1:0] bits (I2S standard selection)
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SPI_I2SCFGR_I2SSTD_0 EQU 0x0010 ; Bit 0
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SPI_I2SCFGR_I2SSTD_1 EQU 0x0020 ; Bit 1
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SPI_I2SCFGR_PCMSYNC EQU 0x0080 ; PCM frame synchronization
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SPI_I2SCFGR_I2SCFG EQU 0x0300 ; I2SCFG[1:0] bits (I2S configuration mode)
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SPI_I2SCFGR_I2SCFG_0 EQU 0x0100 ; Bit 0
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SPI_I2SCFGR_I2SCFG_1 EQU 0x0200 ; Bit 1
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SPI_I2SCFGR_I2SE EQU 0x0400 ; I2S Enable
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SPI_I2SCFGR_I2SMOD EQU 0x0800 ; I2S mode selection
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;***************** Bit definition for SPI_I2SPR register ******************
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SPI_I2SPR_I2SDIV EQU 0x00FF ; I2S Linear prescaler
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SPI_I2SPR_ODD EQU 0x0100 ; Odd factor for the prescaler
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SPI_I2SPR_MCKOE EQU 0x0200 ; Master Clock Output Enable
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END
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