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78 lines
3.6 KiB
78 lines
3.6 KiB
9 years ago
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;********************************************************************************
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9 years ago
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; FILE : INI_PWR.S
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; AUTHOR : Petr Dousa, Ondrej Hruska
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; DATE : 10/2015
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9 years ago
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; DESCR : Control registers and bit masks for PWR (power control, sleep)
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9 years ago
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;
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; Power Control (PWR)
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;
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; Part of an assembler library for STM32L100, based on the STM32 CMSIS.
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; Developed for educational purposes at the Department of Measure of CTU in Prague.
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; See the LICENSE file for detailed terms of use.
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;********************************************************************************
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;****************************************************************************
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;*
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;* REGISTERS
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;*
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;****************************************************************************
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; Power control registers
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PWR_CR EQU (_PWR + 0x00) ; PWR power control register,
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PWR_CSR EQU (_PWR + 0x04) ; PWR power control/status register,
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;****************************************************************************
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;*
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;* BIT MASKS AND DEFINITIONS
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;*
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;****************************************************************************
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9 years ago
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;******************* Bit definition for PWR_CR register *******************
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PWR_CR_LPSDSR EQU 0x0001 ; Low-power deepsleep/sleep/low power run
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PWR_CR_PDDS EQU 0x0002 ; Power Down Deepsleep
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PWR_CR_CWUF EQU 0x0004 ; Clear Wakeup Flag
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PWR_CR_CSBF EQU 0x0008 ; Clear Standby Flag
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PWR_CR_PVDE EQU 0x0010 ; Power Voltage Detector Enable
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PWR_CR_PLS EQU 0x00E0 ; PLS[2:0] bits (PVD Level Selection)
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PWR_CR_PLS_0 EQU 0x0020 ; Bit 0
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PWR_CR_PLS_1 EQU 0x0040 ; Bit 1
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PWR_CR_PLS_2 EQU 0x0080 ; Bit 2
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; PVD level configuration
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PWR_CR_PLS_LEV0 EQU 0x0000 ; PVD level 0
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PWR_CR_PLS_LEV1 EQU 0x0020 ; PVD level 1
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PWR_CR_PLS_LEV2 EQU 0x0040 ; PVD level 2
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PWR_CR_PLS_LEV3 EQU 0x0060 ; PVD level 3
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PWR_CR_PLS_LEV4 EQU 0x0080 ; PVD level 4
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PWR_CR_PLS_LEV5 EQU 0x00A0 ; PVD level 5
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PWR_CR_PLS_LEV6 EQU 0x00C0 ; PVD level 6
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PWR_CR_PLS_LEV7 EQU 0x00E0 ; PVD level 7
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PWR_CR_DBP EQU 0x0100 ; Disable Backup Domain write protection
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PWR_CR_ULP EQU 0x0200 ; Ultra Low Power mode
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PWR_CR_FWU EQU 0x0400 ; Fast wakeup
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PWR_CR_VOS EQU 0x1800 ; VOS[1:0] bits (Voltage scaling range selection)
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PWR_CR_VOS_0 EQU 0x0800 ; Bit 0
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PWR_CR_VOS_1 EQU 0x1000 ; Bit 1
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PWR_CR_LPRUN EQU 0x4000 ; Low power run mode
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;****************** Bit definition for PWR_CSR register *******************
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PWR_CSR_WUF EQU 0x0001 ; Wakeup Flag
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PWR_CSR_SBF EQU 0x0002 ; Standby Flag
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PWR_CSR_PVDO EQU 0x0004 ; PVD Output
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PWR_CSR_VREFINTRDYF EQU 0x0008 ; Internal voltage reference (VREFINT) ready flag
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PWR_CSR_VOSF EQU 0x0010 ; Voltage Scaling select flag
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PWR_CSR_REGLPF EQU 0x0020 ; Regulator LP flag
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PWR_CSR_EWUP1 EQU 0x0100 ; Enable WKUP pin 1
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PWR_CSR_EWUP2 EQU 0x0200 ; Enable WKUP pin 2
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PWR_CSR_EWUP3 EQU 0x0400 ; Enable WKUP pin 3
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END
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