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637 lines
22 KiB
637 lines
22 KiB
8 years ago
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/**
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******************************************************************************
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* @file stm32f1xx_hal_pwr.c
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* @author MCD Application Team
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* @version V1.0.4
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* @date 29-April-2016
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* @brief PWR HAL module driver.
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*
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* This file provides firmware functions to manage the following
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* functionalities of the Power Controller (PWR) peripheral:
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* + Initialization/de-initialization functions
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* + Peripheral Control functions
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @defgroup PWR PWR
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* @brief PWR HAL module driver
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* @{
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*/
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#ifdef HAL_PWR_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup PWR_Private_Constants PWR Private Constants
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* @{
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*/
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/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
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* @{
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*/
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#define PVD_MODE_IT ((uint32_t)0x00010000)
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#define PVD_MODE_EVT ((uint32_t)0x00020000)
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#define PVD_RISING_EDGE ((uint32_t)0x00000001)
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#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
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/**
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* @}
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*/
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/** @defgroup PWR_register_alias_address PWR Register alias address
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* @{
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*/
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/* ------------- PWR registers bit address in the alias region ---------------*/
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#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
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#define PWR_CR_OFFSET 0x00
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#define PWR_CSR_OFFSET 0x04
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#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
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#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
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/**
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* @}
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*/
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/** @defgroup PWR_CR_register_alias PWR CR Register alias address
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* @{
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*/
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/* --- CR Register ---*/
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/* Alias word address of LPSDSR bit */
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#define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPDS)
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#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
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/* Alias word address of DBP bit */
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#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
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#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
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/* Alias word address of PVDE bit */
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#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
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#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
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/**
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* @}
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*/
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/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
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* @{
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*/
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/* --- CSR Register ---*/
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/* Alias word address of EWUP1 bit */
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#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup PWR_Private_Functions PWR Private Functions
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* brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
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* @{
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*/
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static void PWR_OverloadWfe(void);
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/* Private functions ---------------------------------------------------------*/
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__NOINLINE
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static void PWR_OverloadWfe(void)
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{
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__asm volatile( "wfe" );
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__asm volatile( "nop" );
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}
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/**
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* @}
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*/
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/** @defgroup PWR_Exported_Functions PWR Exported Functions
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* @{
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*/
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/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and de-initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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After reset, the backup domain (RTC registers, RTC backup data
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registers) is protected against possible unwanted
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write accesses.
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To enable access to the RTC Domain and RTC registers, proceed as follows:
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(+) Enable the Power Controller (PWR) APB1 interface clock using the
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__HAL_RCC_PWR_CLK_ENABLE() macro.
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(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitializes the PWR peripheral registers to their default reset values.
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* @retval None
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*/
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void HAL_PWR_DeInit(void)
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{
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__HAL_RCC_PWR_FORCE_RESET();
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__HAL_RCC_PWR_RELEASE_RESET();
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}
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/**
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* @brief Enables access to the backup domain (RTC registers, RTC
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* backup data registers ).
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* @note If the HSE divided by 128 is used as the RTC clock, the
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* Backup Domain Access should be kept enabled.
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* @retval None
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*/
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void HAL_PWR_EnableBkUpAccess(void)
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{
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/* Enable access to RTC and backup registers */
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*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
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}
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/**
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* @brief Disables access to the backup domain (RTC registers, RTC
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* backup data registers).
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* @note If the HSE divided by 128 is used as the RTC clock, the
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* Backup Domain Access should be kept enabled.
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* @retval None
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*/
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void HAL_PWR_DisableBkUpAccess(void)
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{
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/* Disable access to RTC and backup registers */
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*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
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}
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/**
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* @}
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*/
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/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
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* @brief Low Power modes configuration functions
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*
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@verbatim
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===============================================================================
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##### Peripheral Control functions #####
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===============================================================================
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*** PVD configuration ***
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=========================
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[..]
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(+) The PVD is used to monitor the VDD power supply by comparing it to a
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threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
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(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
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than the PVD threshold. This event is internally connected to the EXTI
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line16 and can generate an interrupt if enabled. This is done through
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__HAL_PVD_EXTI_ENABLE_IT() macro.
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(+) The PVD is stopped in Standby mode.
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*** WakeUp pin configuration ***
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================================
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[..]
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(+) WakeUp pin is used to wake up the system from Standby mode. This pin is
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forced in input pull-down configuration and is active on rising edges.
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(+) There is one WakeUp pin:
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WakeUp Pin 1 on PA.00.
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[..]
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*** Low Power modes configuration ***
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=====================================
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[..]
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The device features 3 low-power modes:
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(+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
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NVIC, SysTick, etc. are kept running
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(+) Stop mode: All clocks are stopped
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(+) Standby mode: 1.8V domain powered off
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*** Sleep mode ***
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==================
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[..]
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(+) Entry:
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The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
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functions with
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(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
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(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
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(+) Exit:
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(++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
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controller (NVIC) can wake up the device from Sleep mode.
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(++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
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(+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
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(+++) Any EXTI Line (Internal or External) configured in Event mode
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*** Stop mode ***
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=================
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[..]
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The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
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clock gating. The voltage regulator can be configured either in normal or low-power mode.
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In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
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oscillators are disabled. SRAM and register contents are preserved.
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In Stop mode, all I/O pins keep the same state as in Run mode.
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(+) Entry:
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The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
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function with:
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(++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
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(++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
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(++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
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(++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
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(+) Exit:
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(++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
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(++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
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*** Standby mode ***
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====================
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[..]
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The Standby mode allows to achieve the lowest power consumption. It is based on the
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Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
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consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
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switched off. SRAM and register contents are lost except for registers in the Backup domain
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and Standby circuitry
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(+) Entry:
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(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
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(+) Exit:
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(++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
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NRSTpin, IWDG Reset
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*** Auto-wakeup (AWU) from low-power mode ***
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=============================================
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[..]
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(+) The MCU can be woken up from low-power mode by an RTC Alarm event,
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without depending on an external interrupt (Auto-wakeup mode).
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(+) RTC auto-wakeup (AWU) from the Stop and Standby modes
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(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
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configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
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*** PWR Workarounds linked to Silicon Limitation ***
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====================================================
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[..]
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Below the list of all silicon limitations known on STM32F1xx prouct.
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(#)Workarounds Implemented inside PWR HAL Driver
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(##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
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@endverbatim
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* @{
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*/
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/**
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* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
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* @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
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* information for the PVD.
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* @note Refer to the electrical characteristics of your device datasheet for
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* more details about the voltage threshold corresponding to each
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* detection level.
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* @retval None
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*/
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void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
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{
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/* Check the parameters */
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assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
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assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
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/* Set PLS[7:5] bits according to PVDLevel value */
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MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
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/* Clear any previous config. Keep it clear if no event or IT mode is selected */
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__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
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__HAL_PWR_PVD_EXTI_DISABLE_IT();
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__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
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__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
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/* Configure interrupt mode */
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if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
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{
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__HAL_PWR_PVD_EXTI_ENABLE_IT();
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}
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/* Configure event mode */
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if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
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{
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__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Configure the edge */
|
||
|
|
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||
|
|
{
|
||
|
|
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||
|
|
}
|
||
|
|
|
||
|
|
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||
|
|
{
|
||
|
|
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enables the Power Voltage Detector(PVD).
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnablePVD(void)
|
||
|
|
{
|
||
|
|
/* Enable the power voltage detector */
|
||
|
|
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disables the Power Voltage Detector(PVD).
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_DisablePVD(void)
|
||
|
|
{
|
||
|
|
/* Disable the power voltage detector */
|
||
|
|
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enables the WakeUp PINx functionality.
|
||
|
|
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg PWR_WAKEUP_PIN1
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||
|
|
{
|
||
|
|
/* Check the parameter */
|
||
|
|
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
|
|
/* Enable the EWUPx pin */
|
||
|
|
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disables the WakeUp PINx functionality.
|
||
|
|
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg PWR_WAKEUP_PIN1
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||
|
|
{
|
||
|
|
/* Check the parameter */
|
||
|
|
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||
|
|
/* Disable the EWUPx pin */
|
||
|
|
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enters Sleep mode.
|
||
|
|
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||
|
|
* @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software
|
||
|
|
* @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||
|
|
* When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||
|
|
* the interrupt wake up source.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||
|
|
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
/* No check on Regulator because parameter not used in SLEEP mode */
|
||
|
|
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||
|
|
|
||
|
|
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
/* Select SLEEP mode entry -------------------------------------------------*/
|
||
|
|
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||
|
|
{
|
||
|
|
/* Request Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Request Wait For Event */
|
||
|
|
__SEV();
|
||
|
|
__WFE();
|
||
|
|
__WFE();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enters Stop mode.
|
||
|
|
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||
|
|
* @note When exiting Stop mode by using an interrupt or a wakeup event,
|
||
|
|
* HSI RC oscillator is selected as system clock.
|
||
|
|
* @note When the voltage regulator operates in low power mode, an additional
|
||
|
|
* startup delay is incurred when waking up from Stop mode.
|
||
|
|
* By keeping the internal regulator ON during Stop mode, the consumption
|
||
|
|
* is higher although the startup time is reduced.
|
||
|
|
* @param Regulator: Specifies the regulator state in Stop mode.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
|
||
|
|
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
|
||
|
|
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
|
||
|
|
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_PWR_REGULATOR(Regulator));
|
||
|
|
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||
|
|
|
||
|
|
/* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
|
||
|
|
CLEAR_BIT(PWR->CR, PWR_CR_PDDS);
|
||
|
|
|
||
|
|
/* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
|
||
|
|
MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
|
||
|
|
|
||
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
/* Select Stop mode entry --------------------------------------------------*/
|
||
|
|
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||
|
|
{
|
||
|
|
/* Request Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Request Wait For Event */
|
||
|
|
__SEV();
|
||
|
|
PWR_OverloadWfe(); /* WFE redefine locally */
|
||
|
|
PWR_OverloadWfe(); /* WFE redefine locally */
|
||
|
|
}
|
||
|
|
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enters Standby mode.
|
||
|
|
* @note In Standby mode, all I/O pins are high impedance except for:
|
||
|
|
* - Reset pad (still available)
|
||
|
|
* - TAMPER pin if configured for tamper or calibration out.
|
||
|
|
* - WKUP pin (PA0) if enabled.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnterSTANDBYMode(void)
|
||
|
|
{
|
||
|
|
/* Select Standby mode */
|
||
|
|
SET_BIT(PWR->CR, PWR_CR_PDDS);
|
||
|
|
|
||
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
/* This option is used to ensure that store operations are completed */
|
||
|
|
#if defined ( __CC_ARM)
|
||
|
|
__force_stores();
|
||
|
|
#endif
|
||
|
|
/* Request Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||
|
|
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
|
|
* re-enters SLEEP mode when an interruption handling is over.
|
||
|
|
* Setting this bit is useful when the processor is expected to run only on
|
||
|
|
* interruptions handling.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnableSleepOnExit(void)
|
||
|
|
{
|
||
|
|
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||
|
|
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||
|
|
* re-enters SLEEP mode when an interruption handling is over.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_DisableSleepOnExit(void)
|
||
|
|
{
|
||
|
|
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enables CORTEX M3 SEVONPEND bit.
|
||
|
|
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
|
|
* WFE to wake up when an interrupt moves from inactive to pended.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnableSEVOnPend(void)
|
||
|
|
{
|
||
|
|
/* Set SEVONPEND bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disables CORTEX M3 SEVONPEND bit.
|
||
|
|
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||
|
|
* WFE to wake up when an interrupt moves from inactive to pended.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_DisableSEVOnPend(void)
|
||
|
|
{
|
||
|
|
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles the PWR PVD interrupt request.
|
||
|
|
* @note This API should be called under the PVD_IRQHandler().
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_PVD_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* Check PWR exti flag */
|
||
|
|
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||
|
|
{
|
||
|
|
/* PWR PVD interrupt user callback */
|
||
|
|
HAL_PWR_PVDCallback();
|
||
|
|
|
||
|
|
/* Clear PWR Exti pending bit */
|
||
|
|
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief PWR PVD interrupt callback
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
__weak void HAL_PWR_PVDCallback(void)
|
||
|
|
{
|
||
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||
|
|
the HAL_PWR_PVDCallback could be implemented in the user file
|
||
|
|
*/
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif /* HAL_PWR_MODULE_ENABLED */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|