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Added ADC, DAC, SPI, I2C, TIM definitions

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master
Ondřej Hruška 9 years ago
parent f18e967dc4
commit 6cc83d875c
17 changed files with 1967 additions and 15 deletions
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  1. 4
      .gitignore
  2. 6
      init.c
  3. 1
      init.h
  4. 6
      lib/common.h
  5. 592
      lib/defs_adc.h
  6. 8
      lib/defs_base.h
  7. 140
      lib/defs_dac.h
  8. 414
      lib/defs_dma.h
  9. 1
      lib/defs_flash.h
  10. 1
      lib/defs_gpio.h
  11. 146
      lib/defs_i2c.h
  12. 1
      lib/defs_rcc.h
  13. 149
      lib/defs_spi.h
  14. 492
      lib/defs_timers.h
  15. 3
      lib/defs_usart.h
  16. 7
      main.c
  17. 11
      proj.pro

4
.gitignore vendored
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@ -36,4 +36,6 @@
/.externalToolBuilders
/trash/
/trash/
*.autosave

6
init.c
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@ -58,3 +58,9 @@ void init_systick(void)
SysTick_RELOAD = 16000; // 1ms interrupt @ 16MHz core clock
SysTick_CSR |= SysTick_CSR_TICKINT | SysTick_CSR_ENABLE;
}
void init_adc(void)
{
// TODO
}

1
init.h
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@ -5,3 +5,4 @@ void init_clock(void);
void init_gpios(void);
void init_usart(void);
void init_systick(void);
void init_adc(void);

6
lib/common.h
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@ -73,3 +73,9 @@ typedef volatile uint64_t* io64_t;
#include "defs_flash.h"
#include "defs_systick.h"
#include "defs_usart.h"
#include "defs_dma.h"
#include "defs_adc.h"
#include "defs_dac.h"
#include "defs_i2c.h"
#include "defs_spi.h"
#include "defs_timers.h"

592
lib/defs_adc.h
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@ -0,0 +1,592 @@
#pragma once
#include "common.h"
// AUTHOR : Ondrej Hruska
// DATE : 12/2015
// DESCR : Control registers and bit masks for ADC
//****************************************************************************
//*
//* REGISTERS
//*
//****************************************************************************
// ADC common config
#define ADC_CSR MMIO32(ADCC_BASE + 0x000) // ADC common status register,
#define ADC_CCR MMIO32(ADCC_BASE + 0x004) // ADC common control register,
// ADC1
#define ADC1_SR MMIO32(ADC1_BASE + 0x00) // ADC status register,
#define ADC1_CR1 MMIO32(ADC1_BASE + 0x04) // ADC control register 1,
#define ADC1_CR2 MMIO32(ADC1_BASE + 0x08) // ADC control register 2,
#define ADC1_SMPR1 MMIO32(ADC1_BASE + 0x0C) // ADC sample time register 1,
#define ADC1_SMPR2 MMIO32(ADC1_BASE + 0x10) // ADC sample time register 2,
#define ADC1_SMPR3 MMIO32(ADC1_BASE + 0x14) // ADC sample time register 3,
#define ADC1_JOFR1 MMIO32(ADC1_BASE + 0x18) // ADC injected channel data offset register 1,
#define ADC1_JOFR2 MMIO32(ADC1_BASE + 0x1C) // ADC injected channel data offset register 2,
#define ADC1_JOFR3 MMIO32(ADC1_BASE + 0x20) // ADC injected channel data offset register 3,
#define ADC1_JOFR4 MMIO32(ADC1_BASE + 0x24) // ADC injected channel data offset register 4,
#define ADC1_HTR MMIO32(ADC1_BASE + 0x28) // ADC watchdog higher threshold register,
#define ADC1_LTR MMIO32(ADC1_BASE + 0x2C) // ADC watchdog lower threshold register,
#define ADC1_SQR1 MMIO32(ADC1_BASE + 0x30) // ADC regular sequence register 1,
#define ADC1_SQR2 MMIO32(ADC1_BASE + 0x34) // ADC regular sequence register 2,
#define ADC1_SQR3 MMIO32(ADC1_BASE + 0x38) // ADC regular sequence register 3,
#define ADC1_SQR4 MMIO32(ADC1_BASE + 0x3C) // ADC regular sequence register 4,
#define ADC1_SQR5 MMIO32(ADC1_BASE + 0x40) // ADC regular sequence register 5,
#define ADC1_JSQR MMIO32(ADC1_BASE + 0x44) // ADC injected sequence register,
#define ADC1_JDR1 MMIO32(ADC1_BASE + 0x48) // ADC injected data register 1,
#define ADC1_JDR2 MMIO32(ADC1_BASE + 0x4C) // ADC injected data register 2,
#define ADC1_JDR3 MMIO32(ADC1_BASE + 0x50) // ADC injected data register 3,
#define ADC1_JDR4 MMIO32(ADC1_BASE + 0x54) // ADC injected data register 4,
#define ADC1_DR MMIO32(ADC1_BASE + 0x58) // ADC regular data register,
#define ADC1_SMPR0 MMIO32(ADC1_BASE + 0x5C) // ADC sample time register 0,
//****************************************************************************
//*
//* BIT MASKS AND DEFINITIONS
//*
//****************************************************************************
//******************* Bit definition for ADC_SR register *******************
#define ADC_SR_AWD 0x00000001 // Analog watchdog flag
#define ADC_SR_EOC 0x00000002 // End of conversion
#define ADC_SR_JEOC 0x00000004 // Injected channel end of conversion
#define ADC_SR_JSTRT 0x00000008 // Injected channel Start flag
#define ADC_SR_STRT 0x00000010 // Regular channel Start flag
#define ADC_SR_OVR 0x00000020 // Overrun flag
#define ADC_SR_ADONS 0x00000040 // ADC ON status
#define ADC_SR_RCNR 0x00000100 // Regular channel not ready flag
#define ADC_SR_JCNR 0x00000200 // Injected channel not ready flag
//****************** Bit definition for ADC_CR1 register *******************
#define ADC_CR1_AWDCH 0x0000001F // AWDCH[4:0] bits (Analog watchdog channel select bits)
#define ADC_CR1_AWDCH_0 0x00000001 // Bit 0
#define ADC_CR1_AWDCH_1 0x00000002 // Bit 1
#define ADC_CR1_AWDCH_2 0x00000004 // Bit 2
#define ADC_CR1_AWDCH_3 0x00000008 // Bit 3
#define ADC_CR1_AWDCH_4 0x00000010 // Bit 4
#define ADC_CR1_EOCIE 0x00000020 // Interrupt enable for EOC
#define ADC_CR1_AWDIE 0x00000040 // Analog Watchdog interrupt enable
#define ADC_CR1_JEOCIE 0x00000080 // Interrupt enable for injected channels
#define ADC_CR1_SCAN 0x00000100 // Scan mode
#define ADC_CR1_AWDSGL 0x00000200 // Enable the watchdog on a single channel in scan mode
#define ADC_CR1_JAUTO 0x00000400 // Automatic injected group conversion
#define ADC_CR1_DISCEN 0x00000800 // Discontinuous mode on regular channels
#define ADC_CR1_JDISCEN 0x00001000 // Discontinuous mode on injected channels
#define ADC_CR1_DISCNUM 0x0000E000 // DISCNUM[2:0] bits (Discontinuous mode channel count)
#define ADC_CR1_DISCNUM_0 0x00002000 // Bit 0
#define ADC_CR1_DISCNUM_1 0x00004000 // Bit 1
#define ADC_CR1_DISCNUM_2 0x00008000 // Bit 2
#define ADC_CR1_PDD 0x00010000 // Power Down during Delay phase
#define ADC_CR1_PDI 0x00020000 // Power Down during Idle phase
#define ADC_CR1_JAWDEN 0x00400000 // Analog watchdog enable on injected channels
#define ADC_CR1_AWDEN 0x00800000 // Analog watchdog enable on regular channels
#define ADC_CR1_RES 0x03000000 // RES[1:0] bits (Resolution)
#define ADC_CR1_RES_0 0x01000000 // Bit 0
#define ADC_CR1_RES_1 0x02000000 // Bit 1
#define ADC_CR1_OVRIE 0x04000000 // Overrun interrupt enable
//****************** Bit definition for ADC_CR2 register *******************
#define ADC_CR2_ADON 0x00000001 // A/D Converter ON / OFF
#define ADC_CR2_CONT 0x00000002 // Continuous Conversion
#define ADC_CR2_CFG 0x00000004 // ADC Configuration
#define ADC_CR2_DELS 0x00000070 // DELS[2:0] bits (Delay selection)
#define ADC_CR2_DELS_0 0x00000010 // Bit 0
#define ADC_CR2_DELS_1 0x00000020 // Bit 1
#define ADC_CR2_DELS_2 0x00000040 // Bit 2
#define ADC_CR2_DMA 0x00000100 // Direct Memory access mode
#define ADC_CR2_DDS 0x00000200 // DMA disable selection (Single ADC)
#define ADC_CR2_EOCS 0x00000400 // End of conversion selection
#define ADC_CR2_ALIGN 0x00000800 // Data Alignment
#define ADC_CR2_JEXTSEL 0x000F0000 // JEXTSEL[3:0] bits (External event select for injected group)
#define ADC_CR2_JEXTSEL_0 0x00010000 // Bit 0
#define ADC_CR2_JEXTSEL_1 0x00020000 // Bit 1
#define ADC_CR2_JEXTSEL_2 0x00040000 // Bit 2
#define ADC_CR2_JEXTSEL_3 0x00080000 // Bit 3
#define ADC_CR2_JEXTEN 0x00300000 // JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels)
#define ADC_CR2_JEXTEN_0 0x00100000 // Bit 0
#define ADC_CR2_JEXTEN_1 0x00200000 // Bit 1
#define ADC_CR2_JSWSTART 0x00400000 // Start Conversion of injected channels
#define ADC_CR2_EXTSEL 0x0F000000 // EXTSEL[3:0] bits (External Event Select for regular group)
#define ADC_CR2_EXTSEL_0 0x01000000 // Bit 0
#define ADC_CR2_EXTSEL_1 0x02000000 // Bit 1
#define ADC_CR2_EXTSEL_2 0x04000000 // Bit 2
#define ADC_CR2_EXTSEL_3 0x08000000 // Bit 3
#define ADC_CR2_EXTEN 0x30000000 // EXTEN[1:0] bits (External Trigger Conversion mode for regular channels)
#define ADC_CR2_EXTEN_0 0x10000000 // Bit 0
#define ADC_CR2_EXTEN_1 0x20000000 // Bit 1
#define ADC_CR2_SWSTART 0x40000000 // Start Conversion of regular channels
//***************** Bit definition for ADC_SMPR1 register ******************
#define ADC_SMPR1_SMP20 0x00000007 // SMP20[2:0] bits (Channel 20 Sample time selection)
#define ADC_SMPR1_SMP20_0 0x00000001 // Bit 0
#define ADC_SMPR1_SMP20_1 0x00000002 // Bit 1
#define ADC_SMPR1_SMP20_2 0x00000004 // Bit 2
#define ADC_SMPR1_SMP21 0x00000038 // SMP21[2:0] bits (Channel 21 Sample time selection)
#define ADC_SMPR1_SMP21_0 0x00000008 // Bit 0
#define ADC_SMPR1_SMP21_1 0x00000010 // Bit 1
#define ADC_SMPR1_SMP21_2 0x00000020 // Bit 2
#define ADC_SMPR1_SMP22 0x000001C0 // SMP22[2:0] bits (Channel 22 Sample time selection)
#define ADC_SMPR1_SMP22_0 0x00000040 // Bit 0
#define ADC_SMPR1_SMP22_1 0x00000080 // Bit 1
#define ADC_SMPR1_SMP22_2 0x00000100 // Bit 2
#define ADC_SMPR1_SMP23 0x00000E00 // SMP23[2:0] bits (Channel 23 Sample time selection)
#define ADC_SMPR1_SMP23_0 0x00000200 // Bit 0
#define ADC_SMPR1_SMP23_1 0x00000400 // Bit 1
#define ADC_SMPR1_SMP23_2 0x00000800 // Bit 2
#define ADC_SMPR1_SMP24 0x00007000 // SMP24[2:0] bits (Channel 24 Sample time selection)
#define ADC_SMPR1_SMP24_0 0x00001000 // Bit 0
#define ADC_SMPR1_SMP24_1 0x00002000 // Bit 1
#define ADC_SMPR1_SMP24_2 0x00004000 // Bit 2
#define ADC_SMPR1_SMP25 0x00038000 // SMP25[2:0] bits (Channel 25 Sample time selection)
#define ADC_SMPR1_SMP25_0 0x00008000 // Bit 0
#define ADC_SMPR1_SMP25_1 0x00010000 // Bit 1
#define ADC_SMPR1_SMP25_2 0x00020000 // Bit 2
#define ADC_SMPR1_SMP26 0x001C0000 // SMP26[2:0] bits (Channel 26 Sample time selection)
#define ADC_SMPR1_SMP26_0 0x00040000 // Bit 0
#define ADC_SMPR1_SMP26_1 0x00080000 // Bit 1
#define ADC_SMPR1_SMP26_2 0x00100000 // Bit 2
#define ADC_SMPR1_SMP27 0x00E00000 // SMP27[2:0] bits (Channel 27 Sample time selection)
#define ADC_SMPR1_SMP27_0 0x00200000 // Bit 0
#define ADC_SMPR1_SMP27_1 0x00400000 // Bit 1
#define ADC_SMPR1_SMP27_2 0x00800000 // Bit 2
#define ADC_SMPR1_SMP28 0x07000000 // SMP28[2:0] bits (Channel 28 Sample time selection)
#define ADC_SMPR1_SMP28_0 0x01000000 // Bit 0
#define ADC_SMPR1_SMP28_1 0x02000000 // Bit 1
#define ADC_SMPR1_SMP28_2 0x04000000 // Bit 2
#define ADC_SMPR1_SMP29 0x38000000 // SMP29[2:0] bits (Channel 29 Sample time selection)
#define ADC_SMPR1_SMP29_0 0x08000000 // Bit 0
#define ADC_SMPR1_SMP29_1 0x10000000 // Bit 1
#define ADC_SMPR1_SMP29_2 0x20000000 // Bit 2
//***************** Bit definition for ADC_SMPR2 register ******************
#define ADC_SMPR2_SMP10 0x00000007 // SMP10[2:0] bits (Channel 10 Sample time selection)
#define ADC_SMPR2_SMP10_0 0x00000001 // Bit 0
#define ADC_SMPR2_SMP10_1 0x00000002 // Bit 1
#define ADC_SMPR2_SMP10_2 0x00000004 // Bit 2
#define ADC_SMPR2_SMP11 0x00000038 // SMP11[2:0] bits (Channel 11 Sample time selection)
#define ADC_SMPR2_SMP11_0 0x00000008 // Bit 0
#define ADC_SMPR2_SMP11_1 0x00000010 // Bit 1
#define ADC_SMPR2_SMP11_2 0x00000020 // Bit 2
#define ADC_SMPR2_SMP12 0x000001C0 // SMP12[2:0] bits (Channel 12 Sample time selection)
#define ADC_SMPR2_SMP12_0 0x00000040 // Bit 0
#define ADC_SMPR2_SMP12_1 0x00000080 // Bit 1
#define ADC_SMPR2_SMP12_2 0x00000100 // Bit 2
#define ADC_SMPR2_SMP13 0x00000E00 // SMP13[2:0] bits (Channel 13 Sample time selection)
#define ADC_SMPR2_SMP13_0 0x00000200 // Bit 0
#define ADC_SMPR2_SMP13_1 0x00000400 // Bit 1
#define ADC_SMPR2_SMP13_2 0x00000800 // Bit 2
#define ADC_SMPR2_SMP14 0x00007000 // SMP14[2:0] bits (Channel 14 Sample time selection)
#define ADC_SMPR2_SMP14_0 0x00001000 // Bit 0
#define ADC_SMPR2_SMP14_1 0x00002000 // Bit 1
#define ADC_SMPR2_SMP14_2 0x00004000 // Bit 2
#define ADC_SMPR2_SMP15 0x00038000 // SMP15[2:0] bits (Channel 5 Sample time selection)
#define ADC_SMPR2_SMP15_0 0x00008000 // Bit 0
#define ADC_SMPR2_SMP15_1 0x00010000 // Bit 1
#define ADC_SMPR2_SMP15_2 0x00020000 // Bit 2
#define ADC_SMPR2_SMP16 0x001C0000 // SMP16[2:0] bits (Channel 16 Sample time selection)
#define ADC_SMPR2_SMP16_0 0x00040000 // Bit 0
#define ADC_SMPR2_SMP16_1 0x00080000 // Bit 1
#define ADC_SMPR2_SMP16_2 0x00100000 // Bit 2
#define ADC_SMPR2_SMP17 0x00E00000 // SMP17[2:0] bits (Channel 17 Sample time selection)
#define ADC_SMPR2_SMP17_0 0x00200000 // Bit 0
#define ADC_SMPR2_SMP17_1 0x00400000 // Bit 1
#define ADC_SMPR2_SMP17_2 0x00800000 // Bit 2
#define ADC_SMPR2_SMP18 0x07000000 // SMP18[2:0] bits (Channel 18 Sample time selection)
#define ADC_SMPR2_SMP18_0 0x01000000 // Bit 0
#define ADC_SMPR2_SMP18_1 0x02000000 // Bit 1
#define ADC_SMPR2_SMP18_2 0x04000000 // Bit 2
#define ADC_SMPR2_SMP19 0x38000000 // SMP19[2:0] bits (Channel 19 Sample time selection)
#define ADC_SMPR2_SMP19_0 0x08000000 // Bit 0
#define ADC_SMPR2_SMP19_1 0x10000000 // Bit 1
#define ADC_SMPR2_SMP19_2 0x20000000 // Bit 2
//***************** Bit definition for ADC_SMPR3 register ******************
#define ADC_SMPR3_SMP0 0x00000007 // SMP0[2:0] bits (Channel 0 Sample time selection)
#define ADC_SMPR3_SMP0_0 0x00000001 // Bit 0
#define ADC_SMPR3_SMP0_1 0x00000002 // Bit 1
#define ADC_SMPR3_SMP0_2 0x00000004 // Bit 2
#define ADC_SMPR3_SMP1 0x00000038 // SMP1[2:0] bits (Channel 1 Sample time selection)
#define ADC_SMPR3_SMP1_0 0x00000008 // Bit 0
#define ADC_SMPR3_SMP1_1 0x00000010 // Bit 1
#define ADC_SMPR3_SMP1_2 0x00000020 // Bit 2
#define ADC_SMPR3_SMP2 0x000001C0 // SMP2[2:0] bits (Channel 2 Sample time selection)
#define ADC_SMPR3_SMP2_0 0x00000040 // Bit 0
#define ADC_SMPR3_SMP2_1 0x00000080 // Bit 1
#define ADC_SMPR3_SMP2_2 0x00000100 // Bit 2
#define ADC_SMPR3_SMP3 0x00000E00 // SMP3[2:0] bits (Channel 3 Sample time selection)
#define ADC_SMPR3_SMP3_0 0x00000200 // Bit 0
#define ADC_SMPR3_SMP3_1 0x00000400 // Bit 1
#define ADC_SMPR3_SMP3_2 0x00000800 // Bit 2
#define ADC_SMPR3_SMP4 0x00007000 // SMP4[2:0] bits (Channel 4 Sample time selection)
#define ADC_SMPR3_SMP4_0 0x00001000 // Bit 0
#define ADC_SMPR3_SMP4_1 0x00002000 // Bit 1
#define ADC_SMPR3_SMP4_2 0x00004000 // Bit 2
#define ADC_SMPR3_SMP5 0x00038000 // SMP5[2:0] bits (Channel 5 Sample time selection)
#define ADC_SMPR3_SMP5_0 0x00008000 // Bit 0
#define ADC_SMPR3_SMP5_1 0x00010000 // Bit 1
#define ADC_SMPR3_SMP5_2 0x00020000 // Bit 2
#define ADC_SMPR3_SMP6 0x001C0000 // SMP6[2:0] bits (Channel 6 Sample time selection)
#define ADC_SMPR3_SMP6_0 0x00040000 // Bit 0
#define ADC_SMPR3_SMP6_1 0x00080000 // Bit 1
#define ADC_SMPR3_SMP6_2 0x00100000 // Bit 2
#define ADC_SMPR3_SMP7 0x00E00000 // SMP7[2:0] bits (Channel 7 Sample time selection)
#define ADC_SMPR3_SMP7_0 0x00200000 // Bit 0
#define ADC_SMPR3_SMP7_1 0x00400000 // Bit 1
#define ADC_SMPR3_SMP7_2 0x00800000 // Bit 2
#define ADC_SMPR3_SMP8 0x07000000 // SMP8[2:0] bits (Channel 8 Sample time selection)
#define ADC_SMPR3_SMP8_0 0x01000000 // Bit 0
#define ADC_SMPR3_SMP8_1 0x02000000 // Bit 1
#define ADC_SMPR3_SMP8_2 0x04000000 // Bit 2
#define ADC_SMPR3_SMP9 0x38000000 // SMP9[2:0] bits (Channel 9 Sample time selection)
#define ADC_SMPR3_SMP9_0 0x08000000 // Bit 0
#define ADC_SMPR3_SMP9_1 0x10000000 // Bit 1
#define ADC_SMPR3_SMP9_2 0x20000000 // Bit 2
//***************** Bit definition for ADC_JOFR1 register ******************
#define ADC_JOFR1_JOFFSET1 0x00000FFF // Data offset for injected channel 1
//***************** Bit definition for ADC_JOFR2 register ******************
#define ADC_JOFR2_JOFFSET2 0x00000FFF // Data offset for injected channel 2
//***************** Bit definition for ADC_JOFR3 register ******************
#define ADC_JOFR3_JOFFSET3 0x00000FFF // Data offset for injected channel 3
//***************** Bit definition for ADC_JOFR4 register ******************
#define ADC_JOFR4_JOFFSET4 0x00000FFF // Data offset for injected channel 4
//****************** Bit definition for ADC_HTR register *******************
#define ADC_HTR_HT 0x00000FFF // Analog watchdog high threshold
//****************** Bit definition for ADC_LTR register *******************
#define ADC_LTR_LT 0x00000FFF // Analog watchdog low threshold
//****************** Bit definition for ADC_SQR1 register ******************
#define ADC_SQR1_L 0x00F00000 // L[3:0] bits (Regular channel sequence length)
#define ADC_SQR1_L_0 0x00100000 // Bit 0
#define ADC_SQR1_L_1 0x00200000 // Bit 1
#define ADC_SQR1_L_2 0x00400000 // Bit 2
#define ADC_SQR1_L_3 0x00800000 // Bit 3
#define ADC_SQR1_SQ28 0x000F8000 // SQ28[4:0] bits (25th conversion in regular sequence)
#define ADC_SQR1_SQ28_0 0x00008000 // Bit 0
#define ADC_SQR1_SQ28_1 0x00010000 // Bit 1
#define ADC_SQR1_SQ28_2 0x00020000 // Bit 2
#define ADC_SQR1_SQ28_3 0x00040000 // Bit 3
#define ADC_SQR1_SQ28_4 0x00080000 // Bit 4
#define ADC_SQR1_SQ27 0x00007C00 // SQ27[4:0] bits (27th conversion in regular sequence)
#define ADC_SQR1_SQ27_0 0x00000400 // Bit 0
#define ADC_SQR1_SQ27_1 0x00000800 // Bit 1
#define ADC_SQR1_SQ27_2 0x00001000 // Bit 2
#define ADC_SQR1_SQ27_3 0x00002000 // Bit 3
#define ADC_SQR1_SQ27_4 0x00004000 // Bit 4
#define ADC_SQR1_SQ26 0x000003E0 // SQ26[4:0] bits (26th conversion in regular sequence)
#define ADC_SQR1_SQ26_0 0x00000020 // Bit 0
#define ADC_SQR1_SQ26_1 0x00000040 // Bit 1
#define ADC_SQR1_SQ26_2 0x00000080 // Bit 2
#define ADC_SQR1_SQ26_3 0x00000100 // Bit 3
#define ADC_SQR1_SQ26_4 0x00000200 // Bit 4
#define ADC_SQR1_SQ25 0x0000001F // SQ25[4:0] bits (25th conversion in regular sequence)
#define ADC_SQR1_SQ25_0 0x00000001 // Bit 0
#define ADC_SQR1_SQ25_1 0x00000002 // Bit 1
#define ADC_SQR1_SQ25_2 0x00000004 // Bit 2
#define ADC_SQR1_SQ25_3 0x00000008 // Bit 3
#define ADC_SQR1_SQ25_4 0x00000010 // Bit 4
//****************** Bit definition for ADC_SQR2 register ******************
#define ADC_SQR2_SQ19 0x0000001F // SQ19[4:0] bits (19th conversion in regular sequence)
#define ADC_SQR2_SQ19_0 0x00000001 // Bit 0
#define ADC_SQR2_SQ19_1 0x00000002 // Bit 1
#define ADC_SQR2_SQ19_2 0x00000004 // Bit 2
#define ADC_SQR2_SQ19_3 0x00000008 // Bit 3
#define ADC_SQR2_SQ19_4 0x00000010 // Bit 4
#define ADC_SQR2_SQ20 0x000003E0 // SQ20[4:0] bits (20th conversion in regular sequence)
#define ADC_SQR2_SQ20_0 0x00000020 // Bit 0
#define ADC_SQR2_SQ20_1 0x00000040 // Bit 1
#define ADC_SQR2_SQ20_2 0x00000080 // Bit 2
#define ADC_SQR2_SQ20_3 0x00000100 // Bit 3
#define ADC_SQR2_SQ20_4 0x00000200 // Bit 4
#define ADC_SQR2_SQ21 0x00007C00 // SQ21[4:0] bits (21th conversion in regular sequence)
#define ADC_SQR2_SQ21_0 0x00000400 // Bit 0
#define ADC_SQR2_SQ21_1 0x00000800 // Bit 1
#define ADC_SQR2_SQ21_2 0x00001000 // Bit 2
#define ADC_SQR2_SQ21_3 0x00002000 // Bit 3
#define ADC_SQR2_SQ21_4 0x00004000 // Bit 4
#define ADC_SQR2_SQ22 0x000F8000 // SQ22[4:0] bits (22th conversion in regular sequence)
#define ADC_SQR2_SQ22_0 0x00008000 // Bit 0
#define ADC_SQR2_SQ22_1 0x00010000 // Bit 1
#define ADC_SQR2_SQ22_2 0x00020000 // Bit 2
#define ADC_SQR2_SQ22_3 0x00040000 // Bit 3
#define ADC_SQR2_SQ22_4 0x00080000 // Bit 4
#define ADC_SQR2_SQ23 0x01F00000 // SQ23[4:0] bits (23th conversion in regular sequence)
#define ADC_SQR2_SQ23_0 0x00100000 // Bit 0
#define ADC_SQR2_SQ23_1 0x00200000 // Bit 1
#define ADC_SQR2_SQ23_2 0x00400000 // Bit 2
#define ADC_SQR2_SQ23_3 0x00800000 // Bit 3
#define ADC_SQR2_SQ23_4 0x01000000 // Bit 4
#define ADC_SQR2_SQ24 0x3E000000 // SQ24[4:0] bits (24th conversion in regular sequence)
#define ADC_SQR2_SQ24_0 0x02000000 // Bit 0
#define ADC_SQR2_SQ24_1 0x04000000 // Bit 1
#define ADC_SQR2_SQ24_2 0x08000000 // Bit 2
#define ADC_SQR2_SQ24_3 0x10000000 // Bit 3
#define ADC_SQR2_SQ24_4 0x20000000 // Bit 4
//****************** Bit definition for ADC_SQR3 register ******************
#define ADC_SQR3_SQ13 0x0000001F // SQ13[4:0] bits (13th conversion in regular sequence)
#define ADC_SQR3_SQ13_0 0x00000001 // Bit 0
#define ADC_SQR3_SQ13_1 0x00000002 // Bit 1
#define ADC_SQR3_SQ13_2 0x00000004 // Bit 2
#define ADC_SQR3_SQ13_3 0x00000008 // Bit 3
#define ADC_SQR3_SQ13_4 0x00000010 // Bit 4
#define ADC_SQR3_SQ14 0x000003E0 // SQ14[4:0] bits (14th conversion in regular sequence)
#define ADC_SQR3_SQ14_0 0x00000020 // Bit 0
#define ADC_SQR3_SQ14_1 0x00000040 // Bit 1
#define ADC_SQR3_SQ14_2 0x00000080 // Bit 2
#define ADC_SQR3_SQ14_3 0x00000100 // Bit 3
#define ADC_SQR3_SQ14_4 0x00000200 // Bit 4
#define ADC_SQR3_SQ15 0x00007C00 // SQ15[4:0] bits (15th conversion in regular sequence)
#define ADC_SQR3_SQ15_0 0x00000400 // Bit 0
#define ADC_SQR3_SQ15_1 0x00000800 // Bit 1
#define ADC_SQR3_SQ15_2 0x00001000 // Bit 2
#define ADC_SQR3_SQ15_3 0x00002000 // Bit 3
#define ADC_SQR3_SQ15_4 0x00004000 // Bit 4
#define ADC_SQR3_SQ16 0x000F8000 // SQ16[4:0] bits (16th conversion in regular sequence)
#define ADC_SQR3_SQ16_0 0x00008000 // Bit 0
#define ADC_SQR3_SQ16_1 0x00010000 // Bit 1
#define ADC_SQR3_SQ16_2 0x00020000 // Bit 2
#define ADC_SQR3_SQ16_3 0x00040000 // Bit 3
#define ADC_SQR3_SQ16_4 0x00080000 // Bit 4
#define ADC_SQR3_SQ17 0x01F00000 // SQ17[4:0] bits (17th conversion in regular sequence)
#define ADC_SQR3_SQ17_0 0x00100000 // Bit 0
#define ADC_SQR3_SQ17_1 0x00200000 // Bit 1
#define ADC_SQR3_SQ17_2 0x00400000 // Bit 2
#define ADC_SQR3_SQ17_3 0x00800000 // Bit 3
#define ADC_SQR3_SQ17_4 0x01000000 // Bit 4
#define ADC_SQR3_SQ18 0x3E000000 // SQ18[4:0] bits (18th conversion in regular sequence)
#define ADC_SQR3_SQ18_0 0x02000000 // Bit 0
#define ADC_SQR3_SQ18_1 0x04000000 // Bit 1
#define ADC_SQR3_SQ18_2 0x08000000 // Bit 2
#define ADC_SQR3_SQ18_3 0x10000000 // Bit 3
#define ADC_SQR3_SQ18_4 0x20000000 // Bit 4
//****************** Bit definition for ADC_SQR4 register ******************
#define ADC_SQR4_SQ7 0x0000001F // SQ7[4:0] bits (7th conversion in regular sequence)
#define ADC_SQR4_SQ7_0 0x00000001 // Bit 0
#define ADC_SQR4_SQ7_1 0x00000002 // Bit 1
#define ADC_SQR4_SQ7_2 0x00000004 // Bit 2
#define ADC_SQR4_SQ7_3 0x00000008 // Bit 3
#define ADC_SQR4_SQ7_4 0x00000010 // Bit 4
#define ADC_SQR4_SQ8 0x000003E0 // SQ8[4:0] bits (8th conversion in regular sequence)
#define ADC_SQR4_SQ8_0 0x00000020 // Bit 0
#define ADC_SQR4_SQ8_1 0x00000040 // Bit 1
#define ADC_SQR4_SQ8_2 0x00000080 // Bit 2
#define ADC_SQR4_SQ8_3 0x00000100 // Bit 3
#define ADC_SQR4_SQ8_4 0x00000200 // Bit 4
#define ADC_SQR4_SQ9 0x00007C00 // SQ9[4:0] bits (9th conversion in regular sequence)
#define ADC_SQR4_SQ9_0 0x00000400 // Bit 0
#define ADC_SQR4_SQ9_1 0x00000800 // Bit 1
#define ADC_SQR4_SQ9_2 0x00001000 // Bit 2
#define ADC_SQR4_SQ9_3 0x00002000 // Bit 3
#define ADC_SQR4_SQ9_4 0x00004000 // Bit 4
#define ADC_SQR4_SQ10 0x000F8000 // SQ10[4:0] bits (10th conversion in regular sequence)
#define ADC_SQR4_SQ10_0 0x00008000 // Bit 0
#define ADC_SQR4_SQ10_1 0x00010000 // Bit 1
#define ADC_SQR4_SQ10_2 0x00020000 // Bit 2
#define ADC_SQR4_SQ10_3 0x00040000 // Bit 3
#define ADC_SQR4_SQ10_4 0x00080000 // Bit 4
#define ADC_SQR4_SQ11 0x01F00000 // SQ11[4:0] bits (11th conversion in regular sequence)
#define ADC_SQR4_SQ11_0 0x00100000 // Bit 0
#define ADC_SQR4_SQ11_1 0x00200000 // Bit 1
#define ADC_SQR4_SQ11_2 0x00400000 // Bit 2
#define ADC_SQR4_SQ11_3 0x00800000 // Bit 3
#define ADC_SQR4_SQ11_4 0x01000000 // Bit 4
#define ADC_SQR4_SQ12 0x3E000000 // SQ12[4:0] bits (12th conversion in regular sequence)
#define ADC_SQR4_SQ12_0 0x02000000 // Bit 0
#define ADC_SQR4_SQ12_1 0x04000000 // Bit 1
#define ADC_SQR4_SQ12_2 0x08000000 // Bit 2
#define ADC_SQR4_SQ12_3 0x10000000 // Bit 3
#define ADC_SQR4_SQ12_4 0x20000000 // Bit 4
//****************** Bit definition for ADC_SQR5 register ******************
#define ADC_SQR5_SQ1 0x0000001F // SQ1[4:0] bits (1st conversion in regular sequence)
#define ADC_SQR5_SQ1_0 0x00000001 // Bit 0
#define ADC_SQR5_SQ1_1 0x00000002 // Bit 1
#define ADC_SQR5_SQ1_2 0x00000004 // Bit 2
#define ADC_SQR5_SQ1_3 0x00000008 // Bit 3
#define ADC_SQR5_SQ1_4 0x00000010 // Bit 4
#define ADC_SQR5_SQ2 0x000003E0 // SQ2[4:0] bits (2nd conversion in regular sequence)
#define ADC_SQR5_SQ2_0 0x00000020 // Bit 0
#define ADC_SQR5_SQ2_1 0x00000040 // Bit 1
#define ADC_SQR5_SQ2_2 0x00000080 // Bit 2
#define ADC_SQR5_SQ2_3 0x00000100 // Bit 3
#define ADC_SQR5_SQ2_4 0x00000200 // Bit 4
#define ADC_SQR5_SQ3 0x00007C00 // SQ3[4:0] bits (3rd conversion in regular sequence)
#define ADC_SQR5_SQ3_0 0x00000400 // Bit 0
#define ADC_SQR5_SQ3_1 0x00000800 // Bit 1
#define ADC_SQR5_SQ3_2 0x00001000 // Bit 2
#define ADC_SQR5_SQ3_3 0x00002000 // Bit 3
#define ADC_SQR5_SQ3_4 0x00004000 // Bit 4
#define ADC_SQR5_SQ4 0x000F8000 // SQ4[4:0] bits (4th conversion in regular sequence)
#define ADC_SQR5_SQ4_0 0x00008000 // Bit 0
#define ADC_SQR5_SQ4_1 0x00010000 // Bit 1
#define ADC_SQR5_SQ4_2 0x00020000 // Bit 2
#define ADC_SQR5_SQ4_3 0x00040000 // Bit 3
#define ADC_SQR5_SQ4_4 0x00080000 // Bit 4
#define ADC_SQR5_SQ5 0x01F00000 // SQ5[4:0] bits (5th conversion in regular sequence)
#define ADC_SQR5_SQ5_0 0x00100000 // Bit 0
#define ADC_SQR5_SQ5_1 0x00200000 // Bit 1
#define ADC_SQR5_SQ5_2 0x00400000 // Bit 2
#define ADC_SQR5_SQ5_3 0x00800000 // Bit 3
#define ADC_SQR5_SQ5_4 0x01000000 // Bit 4
#define ADC_SQR5_SQ6 0x3E000000 // SQ6[4:0] bits (6th conversion in regular sequence)
#define ADC_SQR5_SQ6_0 0x02000000 // Bit 0
#define ADC_SQR5_SQ6_1 0x04000000 // Bit 1
#define ADC_SQR5_SQ6_2 0x08000000 // Bit 2
#define ADC_SQR5_SQ6_3 0x10000000 // Bit 3
#define ADC_SQR5_SQ6_4 0x20000000 // Bit 4
//****************** Bit definition for ADC_JSQR register ******************
#define ADC_JSQR_JSQ1 0x0000001F // JSQ1[4:0] bits (1st conversion in injected sequence)
#define ADC_JSQR_JSQ1_0 0x00000001 // Bit 0
#define ADC_JSQR_JSQ1_1 0x00000002 // Bit 1
#define ADC_JSQR_JSQ1_2 0x00000004 // Bit 2
#define ADC_JSQR_JSQ1_3 0x00000008 // Bit 3
#define ADC_JSQR_JSQ1_4 0x00000010 // Bit 4
#define ADC_JSQR_JSQ2 0x000003E0 // JSQ2[4:0] bits (2nd conversion in injected sequence)
#define ADC_JSQR_JSQ2_0 0x00000020 // Bit 0
#define ADC_JSQR_JSQ2_1 0x00000040 // Bit 1
#define ADC_JSQR_JSQ2_2 0x00000080 // Bit 2
#define ADC_JSQR_JSQ2_3 0x00000100 // Bit 3
#define ADC_JSQR_JSQ2_4 0x00000200 // Bit 4
#define ADC_JSQR_JSQ3 0x00007C00 // JSQ3[4:0] bits (3rd conversion in injected sequence)
#define ADC_JSQR_JSQ3_0 0x00000400 // Bit 0
#define ADC_JSQR_JSQ3_1 0x00000800 // Bit 1
#define ADC_JSQR_JSQ3_2 0x00001000 // Bit 2
#define ADC_JSQR_JSQ3_3 0x00002000 // Bit 3
#define ADC_JSQR_JSQ3_4 0x00004000 // Bit 4
#define ADC_JSQR_JSQ4 0x000F8000 // JSQ4[4:0] bits (4th conversion in injected sequence)
#define ADC_JSQR_JSQ4_0 0x00008000 // Bit 0
#define ADC_JSQR_JSQ4_1 0x00010000 // Bit 1
#define ADC_JSQR_JSQ4_2 0x00020000 // Bit 2
#define ADC_JSQR_JSQ4_3 0x00040000 // Bit 3
#define ADC_JSQR_JSQ4_4 0x00080000 // Bit 4
#define ADC_JSQR_JL 0x00300000 // JL[1:0] bits (Injected Sequence length)
#define ADC_JSQR_JL_0 0x00100000 // Bit 0
#define ADC_JSQR_JL_1 0x00200000 // Bit 1
//****************** Bit definition for ADC_JDR1 register ******************
#define ADC_JDR1_JDATA 0x0000FFFF // Injected data
//****************** Bit definition for ADC_JDR2 register ******************
#define ADC_JDR2_JDATA 0x0000FFFF // Injected data
//****************** Bit definition for ADC_JDR3 register ******************
#define ADC_JDR3_JDATA 0x0000FFFF // Injected data
//****************** Bit definition for ADC_JDR4 register ******************
#define ADC_JDR4_JDATA 0x0000FFFF // Injected data
//******************* Bit definition for ADC_DR register *******************
#define ADC_DR_DATA 0x0000FFFF // Regular data
//***************** Bit definition for ADC_SMPR0 register ******************
#define ADC_SMPR3_SMP30 0x00000007 // SMP30[2:0] bits (Channel 30 Sample time selection)
#define ADC_SMPR3_SMP30_0 0x00000001 // Bit 0
#define ADC_SMPR3_SMP30_1 0x00000002 // Bit 1
#define ADC_SMPR3_SMP30_2 0x00000004 // Bit 2
#define ADC_SMPR3_SMP31 0x00000038 // SMP31[2:0] bits (Channel 31 Sample time selection)
#define ADC_SMPR3_SMP31_0 0x00000008 // Bit 0
#define ADC_SMPR3_SMP31_1 0x00000010 // Bit 1
#define ADC_SMPR3_SMP31_2 0x00000020 // Bit 2
//****************** Bit definition for ADC_CSR register *******************
#define ADC_CSR_AWD1 0x00000001 // ADC1 Analog watchdog flag
#define ADC_CSR_EOC1 0x00000002 // ADC1 End of conversion
#define ADC_CSR_JEOC1 0x00000004 // ADC1 Injected channel end of conversion
#define ADC_CSR_JSTRT1 0x00000008 // ADC1 Injected channel Start flag
#define ADC_CSR_STRT1 0x00000010 // ADC1 Regular channel Start flag
#define ADC_CSR_OVR1 0x00000020 // ADC1 overrun flag
#define ADC_CSR_ADONS1 0x00000040 // ADON status of ADC1
//****************** Bit definition for ADC_CCR register *******************
#define ADC_CCR_ADCPRE 0x00030000 // ADC prescaler
#define ADC_CCR_ADCPRE_0 0x00010000 // Bit 0
#define ADC_CCR_ADCPRE_1 0x00020000 // Bit 1
#define ADC_CCR_TSVREFE 0x00800000 // Temperature Sensor and VREFINT Enable

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lib/defs_base.h
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#define TIM10 (APB2_BASE + 0x0C00)
#define TIM11 (APB2_BASE + 0x1000)
#define SYSCFG_BASE (APB2_BASE + 0x0000) // System config block base
#define EXTI_BASE (APB2_BASE + 0x0400) // External interrupt settings base
#define SYSCFG_BASE (APB2_BASE + 0x0000) // System config block base
#define EXTI_BASE (APB2_BASE + 0x0400) // External interrupt settings base
#define ADC1 (APB2_BASE + 0x2400) // A/D 1
#define ADCC (APB2_BASE + 0x2700) // common A/D registers base
#define ADC1_BASE (APB2_BASE + 0x2400) // A/D 1
#define ADCC_BASE (APB2_BASE + 0x2700) // common A/D registers base
#define SDIO (APB2_BASE + 0x2C00) // SD host
#define SPI1 (APB2_BASE + 0x3000) // SPI

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lib/defs_dac.h
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#pragma once
#include "common.h"
// AUTHOR : Ondrej Hruska
// DATE : 10/2015
// DESCR : Control registers and bit masks for DAC (digital-analog converter)
//****************************************************************************
//*
//* REGISTERS
//*
//****************************************************************************
// D/A converter
#define DAC_CR MMIO32(DAC_BASE + 0x00) // DAC control register,
#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) // DAC software trigger register,
#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) // DAC channel1 12-bit right-aligned data holding register,
#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) // DAC channel1 12-bit left aligned data holding register,
#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) // DAC channel1 8-bit right aligned data holding register,
#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14) // DAC channel2 12-bit right aligned data holding register,
#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18) // DAC channel2 12-bit left aligned data holding register,
#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C) // DAC channel2 8-bit right-aligned data holding register,
#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20) // Dual DAC 12-bit right-aligned data holding register,
#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24) // DUAL DAC 12-bit left aligned data holding register,
#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28) // DUAL DAC 8-bit right aligned data holding register,
#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) // DAC channel1 data output register,
#define DAC_DOR2 MMIO32(DAC_BASE + 0x30) // DAC channel2 data output register,
#define DAC_SR MMIO32(DAC_BASE + 0x34) // DAC status register,
//****************************************************************************
//*
//* BIT MASKS AND DEFINITIONS
//*
//****************************************************************************
//******************* Bit definition for DAC_CR register *******************
#define DAC_CR_EN1 0x00000001 // DAC channel1 enable
#define DAC_CR_BOFF1 0x00000002 // DAC channel1 output buffer disable
#define DAC_CR_TEN1 0x00000004 // DAC channel1 Trigger enable
#define DAC_CR_TSEL1 0x00000038 // TSEL1[2:0] (DAC channel1 Trigger selection)
#define DAC_CR_TSEL1_0 0x00000008 // Bit 0
#define DAC_CR_TSEL1_1 0x00000010 // Bit 1
#define DAC_CR_TSEL1_2 0x00000020 // Bit 2
#define DAC_CR_WAVE1 0x000000C0 // WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
#define DAC_CR_WAVE1_0 0x00000040 // Bit 0
#define DAC_CR_WAVE1_1 0x00000080 // Bit 1
#define DAC_CR_MAMP1 0x00000F00 // MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
#define DAC_CR_MAMP1_0 0x00000100 // Bit 0
#define DAC_CR_MAMP1_1 0x00000200 // Bit 1
#define DAC_CR_MAMP1_2 0x00000400 // Bit 2
#define DAC_CR_MAMP1_3 0x00000800 // Bit 3
#define DAC_CR_DMAEN1 0x00001000 // DAC channel1 DMA enable
#define DAC_CR_DMAUDRIE1 0x00002000 // DAC channel1 DMA underrun interrupt enable
#define DAC_CR_EN2 0x00010000 // DAC channel2 enable
#define DAC_CR_BOFF2 0x00020000 // DAC channel2 output buffer disable
#define DAC_CR_TEN2 0x00040000 // DAC channel2 Trigger enable
#define DAC_CR_TSEL2 0x00380000 // TSEL2[2:0] (DAC channel2 Trigger selection)
#define DAC_CR_TSEL2_0 0x00080000 // Bit 0
#define DAC_CR_TSEL2_1 0x00100000 // Bit 1
#define DAC_CR_TSEL2_2 0x00200000 // Bit 2
#define DAC_CR_WAVE2 0x00C00000 // WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)
#define DAC_CR_WAVE2_0 0x00400000 // Bit 0
#define DAC_CR_WAVE2_1 0x00800000 // Bit 1
#define DAC_CR_MAMP2 0x0F000000 // MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)
#define DAC_CR_MAMP2_0 0x01000000 // Bit 0
#define DAC_CR_MAMP2_1 0x02000000 // Bit 1
#define DAC_CR_MAMP2_2 0x04000000 // Bit 2
#define DAC_CR_MAMP2_3 0x08000000 // Bit 3
#define DAC_CR_DMAEN2 0x10000000 // DAC channel2 DMA enabled
#define DAC_CR_DMAUDRIE2 0x20000000 // DAC channel2 DMA underrun interrupt enable
//**************** Bit definition for DAC_SWTRIGR register *****************
#define DAC_SWTRIGR_SWTRIG1 0x01 // DAC channel1 software trigger
#define DAC_SWTRIGR_SWTRIG2 0x02 // DAC channel2 software trigger
//**************** Bit definition for DAC_DHR12R1 register *****************
#define DAC_DHR12R1_DACC1DHR 0x0FFF // DAC channel1 12-bit Right aligned data
//**************** Bit definition for DAC_DHR12L1 register *****************
#define DAC_DHR12L1_DACC1DHR 0xFFF0 // DAC channel1 12-bit Left aligned data
//***************** Bit definition for DAC_DHR8R1 register *****************
#define DAC_DHR8R1_DACC1DHR 0xFF // DAC channel1 8-bit Right aligned data
//**************** Bit definition for DAC_DHR12R2 register *****************
#define DAC_DHR12R2_DACC2DHR 0x0FFF // DAC channel2 12-bit Right aligned data
//**************** Bit definition for DAC_DHR12L2 register *****************
#define DAC_DHR12L2_DACC2DHR 0xFFF0 // DAC channel2 12-bit Left aligned data
//***************** Bit definition for DAC_DHR8R2 register *****************
#define DAC_DHR8R2_DACC2DHR 0xFF // DAC channel2 8-bit Right aligned data
//**************** Bit definition for DAC_DHR12RD register *****************
#define DAC_DHR12RD_DACC1DHR 0x00000FFF // DAC channel1 12-bit Right aligned data
#define DAC_DHR12RD_DACC2DHR 0x0FFF0000 // DAC channel2 12-bit Right aligned data
//**************** Bit definition for DAC_DHR12LD register *****************
#define DAC_DHR12LD_DACC1DHR 0x0000FFF0 // DAC channel1 12-bit Left aligned data
#define DAC_DHR12LD_DACC2DHR 0xFFF00000 // DAC channel2 12-bit Left aligned data
//***************** Bit definition for DAC_DHR8RD register *****************
#define DAC_DHR8RD_DACC1DHR 0x00FF // DAC channel1 8-bit Right aligned data
#define DAC_DHR8RD_DACC2DHR 0xFF00 // DAC channel2 8-bit Right aligned data
//****************** Bit definition for DAC_DOR1 register ******************
#define DAC_DOR1_DACC1DOR 0x0FFF // DAC channel1 data output
//****************** Bit definition for DAC_DOR2 register ******************
#define DAC_DOR2_DACC2DOR 0x0FFF // DAC channel2 data output
//******************* Bit definition for DAC_SR register *******************
#define DAC_SR_DMAUDR1 0x00002000 // DAC channel1 DMA underrun flag
#define DAC_SR_DMAUDR2 0x20000000 // DAC channel2 DMA underrun flag

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lib/defs_dma.h
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#pragma once
#include "common.h"
// AUTHOR : Ondrej Hruska
// DATE : 12/2015
// DESCR : Control registers and bit masks for DMA (Direct memory access)
//****************************************************************************
//*
//* REGISTERS
//*
//****************************************************************************
// DMA 1
// Status registers
#define DMA1_ISR MMIO32(_DMA1 + 0x00) // DMA interrupt status register,
#define DMA1_IFCR MMIO32(_DMA1 + 0x04) // DMA interrupt flag clear register,
// Channel bases
#define DMA1_CH1 (_DMA1 + 0x0008)
#define DMA1_CH2 (_DMA1 + 0x001C)
#define DMA1_CH3 (_DMA1 + 0x0030)
#define DMA1_CH4 (_DMA1 + 0x0044)
#define DMA1_CH5 (_DMA1 + 0x0058)
#define DMA1_CH6 (_DMA1 + 0x006C)
#define DMA1_CH7 (_DMA1 + 0x0080)
// offsets
#define DMA_CCR_offs 0x00 // DMA channel x configuration register
#define DMA_CNDTR_offs 0x04 // DMA channel x number of data register
#define DMA_CPAR_offs 0x08 // DMA channel x peripheral address register
#define DMA_CMAR_offs 0x0C // DMA channel x memory address register
#define DMA1_CH1_CCR MMIO32(DMA1_CH1 + 0x00) // DMA channel x configuration register
#define DMA1_CH1_CNDTR MMIO32(DMA1_CH1 + 0x04) // DMA channel x number of data register
#define DMA1_CH1_CPAR MMIO32(DMA1_CH1 + 0x08) // DMA channel x peripheral address register
#define DMA1_CH1_CMAR MMIO32(DMA1_CH1 + 0x0C) // DMA channel x memory address register
#define DMA1_CH2_CCR MMIO32(DMA1_CH2 + 0x00) // DMA channel x configuration register
#define DMA1_CH2_CNDTR MMIO32(DMA1_CH2 + 0x04) // DMA channel x number of data register
#define DMA1_CH2_CPAR MMIO32(DMA1_CH2 + 0x08) // DMA channel x peripheral address register
#define DMA1_CH2_CMAR MMIO32(DMA1_CH2 + 0x0C) // DMA channel x memory address register
#define DMA1_CH3_CCR MMIO32(DMA1_CH3 + 0x00) // DMA channel x configuration register
#define DMA1_CH3_CNDTR MMIO32(DMA1_CH3 + 0x04) // DMA channel x number of data register
#define DMA1_CH3_CPAR MMIO32(DMA1_CH3 + 0x08) // DMA channel x peripheral address register
#define DMA1_CH3_CMAR MMIO32(DMA1_CH3 + 0x0C) // DMA channel x memory address register
#define DMA1_CH4_CCR MMIO32(DMA1_CH4 + 0x00) // DMA channel x configuration register
#define DMA1_CH4_CNDTR MMIO32(DMA1_CH4 + 0x04) // DMA channel x number of data register
#define DMA1_CH4_CPAR MMIO32(DMA1_CH4 + 0x08) // DMA channel x peripheral address register
#define DMA1_CH4_CMAR MMIO32(DMA1_CH4 + 0x0C) // DMA channel x memory address register
#define DMA1_CH5_CCR MMIO32(DMA1_CH5 + 0x00) // DMA channel x configuration register
#define DMA1_CH5_CNDTR MMIO32(DMA1_CH5 + 0x04) // DMA channel x number of data register
#define DMA1_CH5_CPAR MMIO32(DMA1_CH5 + 0x08) // DMA channel x peripheral address register
#define DMA1_CH5_CMAR MMIO32(DMA1_CH5 + 0x0C) // DMA channel x memory address register
#define DMA1_CH6_CCR MMIO32(DMA1_CH6 + 0x00) // DMA channel x configuration register
#define DMA1_CH6_CNDTR MMIO32(DMA1_CH6 + 0x04) // DMA channel x number of data register
#define DMA1_CH6_CPAR MMIO32(DMA1_CH6 + 0x08) // DMA channel x peripheral address register
#define DMA1_CH6_CMAR MMIO32(DMA1_CH6 + 0x0C) // DMA channel x memory address register
#define DMA1_CH7_CCR MMIO32(DMA1_CH7 + 0x00) // DMA channel x configuration register
#define DMA1_CH7_CNDTR MMIO32(DMA1_CH7 + 0x04) // DMA channel x number of data register
#define DMA1_CH7_CPAR MMIO32(DMA1_CH7 + 0x08) // DMA channel x peripheral address register
#define DMA1_CH7_CMAR MMIO32(DMA1_CH7 + 0x0C) // DMA channel x memory address register
// DMA 2
// Status registers
#define DMA2_ISR (_DMA2 + 0x00) // DMA interrupt status register,
#define DMA2_IFCR (_DMA2 + 0x04) // DMA interrupt flag clear register,
// Channel bases
#define DMA2_CH1 (_DMA2 + 0x0008)
#define DMA2_CH2 (_DMA2 + 0x001C)
#define DMA2_CH3 (_DMA2 + 0x0030)
#define DMA2_CH4 (_DMA2 + 0x0044)
#define DMA2_CH5 (_DMA2 + 0x0058)
#define DMA2_CH1_CCR MMIO32(DMA2_CH1 + 0x00) // DMA channel x configuration register
#define DMA2_CH1_CNDTR MMIO32(DMA2_CH1 + 0x04) // DMA channel x number of data register
#define DMA2_CH1_CPAR MMIO32(DMA2_CH1 + 0x08) // DMA channel x peripheral address register
#define DMA2_CH1_CMAR MMIO32(DMA2_CH1 + 0x0C) // DMA channel x memory address register
#define DMA2_CH2_CCR MMIO32(DMA2_CH2 + 0x00) // DMA channel x configuration register
#define DMA2_CH2_CNDTR MMIO32(DMA2_CH2 + 0x04) // DMA channel x number of data register
#define DMA2_CH2_CPAR MMIO32(DMA2_CH2 + 0x08) // DMA channel x peripheral address register
#define DMA2_CH2_CMAR MMIO32(DMA2_CH2 + 0x0C) // DMA channel x memory address register
#define DMA2_CH3_CCR MMIO32(DMA2_CH3 + 0x00) // DMA channel x configuration register
#define DMA2_CH3_CNDTR MMIO32(DMA2_CH3 + 0x04) // DMA channel x number of data register
#define DMA2_CH3_CPAR MMIO32(DMA2_CH3 + 0x08) // DMA channel x peripheral address register
#define DMA2_CH3_CMAR MMIO32(DMA2_CH3 + 0x0C) // DMA channel x memory address register
#define DMA2_CH4_CCR MMIO32(DMA2_CH4 + 0x00) // DMA channel x configuration register
#define DMA2_CH4_CNDTR MMIO32(DMA2_CH4 + 0x04) // DMA channel x number of data register
#define DMA2_CH4_CPAR MMIO32(DMA2_CH4 + 0x08) // DMA channel x peripheral address register
#define DMA2_CH4_CMAR MMIO32(DMA2_CH4 + 0x0C) // DMA channel x memory address register
#define DMA2_CH5_CCR MMIO32(DMA2_CH5 + 0x00) // DMA channel x configuration register
#define DMA2_CH5_CNDTR MMIO32(DMA2_CH5 + 0x04) // DMA channel x number of data register
#define DMA2_CH5_CPAR MMIO32(DMA2_CH5 + 0x08) // DMA channel x peripheral address register
#define DMA2_CH5_CMAR MMIO32(DMA2_CH5 + 0x0C) // DMA channel x memory address register
//****************************************************************************
//*
//* BIT MASKS AND DEFINITIONS
//*
//****************************************************************************
//****************** Bit definition for DMA_ISR register *******************
#define DMA_ISR_GIF1 0x00000001 // Channel 1 Global interrupt flag
#define DMA_ISR_TCIF1 0x00000002 // Channel 1 Transfer Complete flag
#define DMA_ISR_HTIF1 0x00000004 // Channel 1 Half Transfer flag
#define DMA_ISR_TEIF1 0x00000008 // Channel 1 Transfer Error flag
#define DMA_ISR_GIF2 0x00000010 // Channel 2 Global interrupt flag
#define DMA_ISR_TCIF2 0x00000020 // Channel 2 Transfer Complete flag
#define DMA_ISR_HTIF2 0x00000040 // Channel 2 Half Transfer flag
#define DMA_ISR_TEIF2 0x00000080 // Channel 2 Transfer Error flag
#define DMA_ISR_GIF3 0x00000100 // Channel 3 Global interrupt flag
#define DMA_ISR_TCIF3 0x00000200 // Channel 3 Transfer Complete flag
#define DMA_ISR_HTIF3 0x00000400 // Channel 3 Half Transfer flag
#define DMA_ISR_TEIF3 0x00000800 // Channel 3 Transfer Error flag
#define DMA_ISR_GIF4 0x00001000 // Channel 4 Global interrupt flag
#define DMA_ISR_TCIF4 0x00002000 // Channel 4 Transfer Complete flag
#define DMA_ISR_HTIF4 0x00004000 // Channel 4 Half Transfer flag
#define DMA_ISR_TEIF4 0x00008000 // Channel 4 Transfer Error flag
#define DMA_ISR_GIF5 0x00010000 // Channel 5 Global interrupt flag
#define DMA_ISR_TCIF5 0x00020000 // Channel 5 Transfer Complete flag
#define DMA_ISR_HTIF5 0x00040000 // Channel 5 Half Transfer flag
#define DMA_ISR_TEIF5 0x00080000 // Channel 5 Transfer Error flag
#define DMA_ISR_GIF6 0x00100000 // Channel 6 Global interrupt flag
#define DMA_ISR_TCIF6 0x00200000 // Channel 6 Transfer Complete flag
#define DMA_ISR_HTIF6 0x00400000 // Channel 6 Half Transfer flag
#define DMA_ISR_TEIF6 0x00800000 // Channel 6 Transfer Error flag
#define DMA_ISR_GIF7 0x01000000 // Channel 7 Global interrupt flag
#define DMA_ISR_TCIF7 0x02000000 // Channel 7 Transfer Complete flag
#define DMA_ISR_HTIF7 0x04000000 // Channel 7 Half Transfer flag
#define DMA_ISR_TEIF7 0x08000000 // Channel 7 Transfer Error flag
//****************** Bit definition for DMA_IFCR register ******************
#define DMA_IFCR_CGIF1 0x00000001 // Channel 1 Global interrupt clearr
#define DMA_IFCR_CTCIF1 0x00000002 // Channel 1 Transfer Complete clear
#define DMA_IFCR_CHTIF1 0x00000004 // Channel 1 Half Transfer clear
#define DMA_IFCR_CTEIF1 0x00000008 // Channel 1 Transfer Error clear
#define DMA_IFCR_CGIF2 0x00000010 // Channel 2 Global interrupt clear
#define DMA_IFCR_CTCIF2 0x00000020 // Channel 2 Transfer Complete clear
#define DMA_IFCR_CHTIF2 0x00000040 // Channel 2 Half Transfer clear
#define DMA_IFCR_CTEIF2 0x00000080 // Channel 2 Transfer Error clear
#define DMA_IFCR_CGIF3 0x00000100 // Channel 3 Global interrupt clear
#define DMA_IFCR_CTCIF3 0x00000200 // Channel 3 Transfer Complete clear
#define DMA_IFCR_CHTIF3 0x00000400 // Channel 3 Half Transfer clear
#define DMA_IFCR_CTEIF3 0x00000800 // Channel 3 Transfer Error clear
#define DMA_IFCR_CGIF4 0x00001000 // Channel 4 Global interrupt clear
#define DMA_IFCR_CTCIF4 0x00002000 // Channel 4 Transfer Complete clear
#define DMA_IFCR_CHTIF4 0x00004000 // Channel 4 Half Transfer clear
#define DMA_IFCR_CTEIF4 0x00008000 // Channel 4 Transfer Error clear
#define DMA_IFCR_CGIF5 0x00010000 // Channel 5 Global interrupt clear
#define DMA_IFCR_CTCIF5 0x00020000 // Channel 5 Transfer Complete clear
#define DMA_IFCR_CHTIF5 0x00040000 // Channel 5 Half Transfer clear
#define DMA_IFCR_CTEIF5 0x00080000 // Channel 5 Transfer Error clear
#define DMA_IFCR_CGIF6 0x00100000 // Channel 6 Global interrupt clear
#define DMA_IFCR_CTCIF6 0x00200000 // Channel 6 Transfer Complete clear
#define DMA_IFCR_CHTIF6 0x00400000 // Channel 6 Half Transfer clear
#define DMA_IFCR_CTEIF6 0x00800000 // Channel 6 Transfer Error clear
#define DMA_IFCR_CGIF7 0x01000000 // Channel 7 Global interrupt clear
#define DMA_IFCR_CTCIF7 0x02000000 // Channel 7 Transfer Complete clear
#define DMA_IFCR_CHTIF7 0x04000000 // Channel 7 Half Transfer clear
#define DMA_IFCR_CTEIF7 0x08000000 // Channel 7 Transfer Error clear
//****************** Bit definition for DMA_CCR1 register ******************
#define DMA_CCR1_EN 0x0001 // Channel enable
#define DMA_CCR1_TCIE 0x0002 // Transfer complete interrupt enable
#define DMA_CCR1_HTIE 0x0004 // Half Transfer interrupt enable
#define DMA_CCR1_TEIE 0x0008 // Transfer error interrupt enable
#define DMA_CCR1_DIR 0x0010 // Data transfer direction
#define DMA_CCR1_CIRC 0x0020 // Circular mode
#define DMA_CCR1_PINC 0x0040 // Peripheral increment mode
#define DMA_CCR1_MINC 0x0080 // Memory increment mode
#define DMA_CCR1_PSIZE 0x0300 // PSIZE[1:0] bits (Peripheral size)
#define DMA_CCR1_PSIZE_0 0x0100 // Bit 0
#define DMA_CCR1_PSIZE_1 0x0200 // Bit 1
#define DMA_CCR1_MSIZE 0x0C00 // MSIZE[1:0] bits (Memory size)
#define DMA_CCR1_MSIZE_0 0x0400 // Bit 0
#define DMA_CCR1_MSIZE_1 0x0800 // Bit 1
#define DMA_CCR1_PL 0x3000 // PL[1:0] bits(Channel Priority level)
#define DMA_CCR1_PL_0 0x1000 // Bit 0
#define DMA_CCR1_PL_1 0x2000 // Bit 1
#define DMA_CCR1_MEM2MEM 0x4000 // Memory to memory mode
//****************** Bit definition for DMA_CCR2 register ******************
#define DMA_CCR2_EN 0x0001 // Channel enable
#define DMA_CCR2_TCIE 0x0002 // ransfer complete interrupt enable
#define DMA_CCR2_HTIE 0x0004 // Half Transfer interrupt enable
#define DMA_CCR2_TEIE 0x0008 // Transfer error interrupt enable
#define DMA_CCR2_DIR 0x0010 // Data transfer direction
#define DMA_CCR2_CIRC 0x0020 // Circular mode
#define DMA_CCR2_PINC 0x0040 // Peripheral increment mode
#define DMA_CCR2_MINC 0x0080 // Memory increment mode
#define DMA_CCR2_PSIZE 0x0300 // PSIZE[1:0] bits (Peripheral size)
#define DMA_CCR2_PSIZE_0 0x0100 // Bit 0
#define DMA_CCR2_PSIZE_1 0x0200 // Bit 1
#define DMA_CCR2_MSIZE 0x0C00 // MSIZE[1:0] bits (Memory size)
#define DMA_CCR2_MSIZE_0 0x0400 // Bit 0
#define DMA_CCR2_MSIZE_1 0x0800 // Bit 1
#define DMA_CCR2_PL 0x3000 // PL[1:0] bits (Channel Priority level)
#define DMA_CCR2_PL_0 0x1000 // Bit 0
#define DMA_CCR2_PL_1 0x2000 // Bit 1
#define DMA_CCR2_MEM2MEM 0x4000 // Memory to memory mode
//****************** Bit definition for DMA_CCR3 register ******************
#define DMA_CCR3_EN 0x0001 // Channel enable
#define DMA_CCR3_TCIE 0x0002 // Transfer complete interrupt enable
#define DMA_CCR3_HTIE 0x0004 // Half Transfer interrupt enable
#define DMA_CCR3_TEIE 0x0008 // Transfer error interrupt enable
#define DMA_CCR3_DIR 0x0010 // Data transfer direction
#define DMA_CCR3_CIRC 0x0020 // Circular mode
#define DMA_CCR3_PINC 0x0040 // Peripheral increment mode
#define DMA_CCR3_MINC 0x0080 // Memory increment mode
#define DMA_CCR3_PSIZE 0x0300 // PSIZE[1:0] bits (Peripheral size)
#define DMA_CCR3_PSIZE_0 0x0100 // Bit 0
#define DMA_CCR3_PSIZE_1 0x0200 // Bit 1
#define DMA_CCR3_MSIZE 0x0C00 // MSIZE[1:0] bits (Memory size)
#define DMA_CCR3_MSIZE_0 0x0400 // Bit 0
#define DMA_CCR3_MSIZE_1 0x0800 // Bit 1
#define DMA_CCR3_PL 0x3000 // PL[1:0] bits (Channel Priority level)
#define DMA_CCR3_PL_0 0x1000 // Bit 0
#define DMA_CCR3_PL_1 0x2000 // Bit 1
#define DMA_CCR3_MEM2MEM 0x4000 // Memory to memory mode
// ****************** Bit definition for DMA_CCR4 register ******************
#define DMA_CCR4_EN 0x0001 // Channel enable
#define DMA_CCR4_TCIE 0x0002 // Transfer complete interrupt enable
#define DMA_CCR4_HTIE 0x0004 // Half Transfer interrupt enable
#define DMA_CCR4_TEIE 0x0008 // Transfer error interrupt enable
#define DMA_CCR4_DIR 0x0010 // Data transfer direction
#define DMA_CCR4_CIRC 0x0020 // Circular mode
#define DMA_CCR4_PINC 0x0040 // Peripheral increment mode
#define DMA_CCR4_MINC 0x0080 // Memory increment mode
#define DMA_CCR4_PSIZE 0x0300 // PSIZE[1:0] bits (Peripheral size)
#define DMA_CCR4_PSIZE_0 0x0100 // Bit 0
#define DMA_CCR4_PSIZE_1 0x0200 // Bit 1
#define DMA_CCR4_MSIZE 0x0C00 // MSIZE[1:0] bits (Memory size)
#define DMA_CCR4_MSIZE_0 0x0400 // Bit 0
#define DMA_CCR4_MSIZE_1 0x0800 // Bit 1
#define DMA_CCR4_PL 0x3000 // PL[1:0] bits (Channel Priority level)
#define DMA_CCR4_PL_0 0x1000 // Bit 0
#define DMA_CCR4_PL_1 0x2000 // Bit 1
#define DMA_CCR4_MEM2MEM 0x4000 // Memory to memory mode
//***************** Bit definition for DMA_CCR5 register ******************
#define DMA_CCR5_EN 0x0001 // Channel enable
#define DMA_CCR5_TCIE 0x0002 // Transfer complete interrupt enable
#define DMA_CCR5_HTIE 0x0004 // Half Transfer interrupt enable
#define DMA_CCR5_TEIE 0x0008 // Transfer error interrupt enable
#define DMA_CCR5_DIR 0x0010 // Data transfer direction
#define DMA_CCR5_CIRC 0x0020 // Circular mode
#define DMA_CCR5_PINC 0x0040 // Peripheral increment mode
#define DMA_CCR5_MINC 0x0080 // Memory increment mode
#define DMA_CCR5_PSIZE 0x0300 // PSIZE[1:0] bits (Peripheral size)
#define DMA_CCR5_PSIZE_0 0x0100 // Bit 0
#define DMA_CCR5_PSIZE_1 0x0200 // Bit 1
#define DMA_CCR5_MSIZE 0x0C00 // MSIZE[1:0] bits (Memory size)
#define DMA_CCR5_MSIZE_0 0x0400 // Bit 0
#define DMA_CCR5_MSIZE_1 0x0800 // Bit 1
#define DMA_CCR5_PL 0x3000 // PL[1:0] bits (Channel Priority level)
#define DMA_CCR5_PL_0 0x1000 // Bit 0
#define DMA_CCR5_PL_1 0x2000 // Bit 1
#define DMA_CCR5_MEM2MEM 0x4000 // Memory to memory mode enable
//****************** Bit definition for DMA_CCR6 register ******************
#define DMA_CCR6_EN 0x0001 // Channel enable
#define DMA_CCR6_TCIE 0x0002 // Transfer complete interrupt enable
#define DMA_CCR6_HTIE 0x0004 // Half Transfer interrupt enable
#define DMA_CCR6_TEIE 0x0008 // Transfer error interrupt enable
#define DMA_CCR6_DIR 0x0010 // Data transfer direction
#define DMA_CCR6_CIRC 0x0020 // Circular mode
#define DMA_CCR6_PINC 0x0040 // Peripheral increment mode
#define DMA_CCR6_MINC 0x0080 // Memory increment mode
#define DMA_CCR6_PSIZE 0x0300 // PSIZE[1:0] bits (Peripheral size)
#define DMA_CCR6_PSIZE_0 0x0100 // Bit 0
#define DMA_CCR6_PSIZE_1 0x0200 // Bit 1
#define DMA_CCR6_MSIZE 0x0C00 // MSIZE[1:0] bits (Memory size)
#define DMA_CCR6_MSIZE_0 0x0400 // Bit 0
#define DMA_CCR6_MSIZE_1 0x0800 // Bit 1
#define DMA_CCR6_PL 0x3000 // PL[1:0] bits (Channel Priority level)
#define DMA_CCR6_PL_0 0x1000 // Bit 0
#define DMA_CCR6_PL_1 0x2000 // Bit 1
#define DMA_CCR6_MEM2MEM 0x4000 // Memory to memory mode
//****************** Bit definition for DMA_CCR7 register ******************
#define DMA_CCR7_EN 0x0001 // Channel enable
#define DMA_CCR7_TCIE 0x0002 // Transfer complete interrupt enable
#define DMA_CCR7_HTIE 0x0004 // Half Transfer interrupt enable
#define DMA_CCR7_TEIE 0x0008 // Transfer error interrupt enable
#define DMA_CCR7_DIR 0x0010 // Data transfer direction
#define DMA_CCR7_CIRC 0x0020 // Circular mode
#define DMA_CCR7_PINC 0x0040 // Peripheral increment mode
#define DMA_CCR7_MINC 0x0080 // Memory increment mode
#define DMA_CCR7_PSIZE 0x0300 // PSIZE[1:0] bits (Peripheral size)
#define DMA_CCR7_PSIZE_0 0x0100 // Bit 0
#define DMA_CCR7_PSIZE_1 0x0200 // Bit 1
#define DMA_CCR7_MSIZE 0x0C00 // MSIZE[1:0] bits (Memory size)
#define DMA_CCR7_MSIZE_0 0x0400 // Bit 0
#define DMA_CCR7_MSIZE_1 0x0800 // Bit 1
#define DMA_CCR7_PL 0x3000 // PL[1:0] bits (Channel Priority level)
#define DMA_CCR7_PL_0 0x1000 // Bit 0
#define DMA_CCR7_PL_1 0x2000 // Bit 1
#define DMA_CCR7_MEM2MEM 0x4000 // Memory to memory mode enable
//***************** Bit definition for DMA_CNDTR1 register *****************
#define DMA_CNDTR1_NDT 0xFFFF // Number of data to Transfer
//***************** Bit definition for DMA_CNDTR2 register *****************
#define DMA_CNDTR2_NDT 0xFFFF // Number of data to Transfer
//***************** Bit definition for DMA_CNDTR3 register *****************
#define DMA_CNDTR3_NDT 0xFFFF // Number of data to Transfer
//***************** Bit definition for DMA_CNDTR4 register *****************
#define DMA_CNDTR4_NDT 0xFFFF // Number of data to Transfer
//***************** Bit definition for DMA_CNDTR5 register *****************
#define DMA_CNDTR5_NDT 0xFFFF // Number of data to Transfer
//***************** Bit definition for DMA_CNDTR6 register *****************
#define DMA_CNDTR6_NDT 0xFFFF // Number of data to Transfer
//***************** Bit definition for DMA_CNDTR7 register *****************
#define DMA_CNDTR7_NDT 0xFFFF // Number of data to Transfer
//***************** Bit definition for DMA_CPAR1 register ******************
#define DMA_CPAR1_PA 0xFFFFFFFF // Peripheral Address
//***************** Bit definition for DMA_CPAR2 register ******************
#define DMA_CPAR2_PA 0xFFFFFFFF // Peripheral Address
//***************** Bit definition for DMA_CPAR3 register ******************
#define DMA_CPAR3_PA 0xFFFFFFFF // Peripheral Address
//***************** Bit definition for DMA_CPAR4 register ******************
#define DMA_CPAR4_PA 0xFFFFFFFF // Peripheral Address
//***************** Bit definition for DMA_CPAR5 register ******************
#define DMA_CPAR5_PA 0xFFFFFFFF // Peripheral Address
//***************** Bit definition for DMA_CPAR6 register ******************
#define DMA_CPAR6_PA 0xFFFFFFFF // Peripheral Address
//***************** Bit definition for DMA_CPAR7 register ******************
#define DMA_CPAR7_PA 0xFFFFFFFF // Peripheral Address
//***************** Bit definition for DMA_CMAR1 register ******************
#define DMA_CMAR1_MA 0xFFFFFFFF // Memory Address
//***************** Bit definition for DMA_CMAR2 register ******************
#define DMA_CMAR2_MA 0xFFFFFFFF // Memory Address
//***************** Bit definition for DMA_CMAR3 register ******************
#define DMA_CMAR3_MA 0xFFFFFFFF // Memory Address
//***************** Bit definition for DMA_CMAR4 register ******************
#define DMA_CMAR4_MA 0xFFFFFFFF // Memory Address
//***************** Bit definition for DMA_CMAR5 register ******************
#define DMA_CMAR5_MA 0xFFFFFFFF // Memory Address
//***************** Bit definition for DMA_CMAR6 register ******************
#define DMA_CMAR6_MA 0xFFFFFFFF // Memory Address
//***************** Bit definition for DMA_CMAR7 register ******************
#define DMA_CMAR7_MA 0xFFFFFFFF // Memory Address

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lib/defs_flash.h
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#pragma once
#include "common.h"
// AUTHOR : Ondrej Hruska

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lib/defs_gpio.h
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#pragma once
#include "common.h"
// AUTHOR : Ondrej Hruska

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lib/defs_i2c.h
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#pragma once
#include "common.h"
// AUTHOR : Ondrej Hruska
// DATE : 12/2015
// DESCR : Control registers and bit masks for I2C
//****************************************************************************
//*
//* REGISTERS
//*
//****************************************************************************
// offsets
#define I2C_CR1_offs 0x00 // I2C Control register 1
#define I2C_CR2_offs 0x04 // I2C Control register 2
#define I2C_OAR1_offs 0x08 // I2C Own address register 1
#define I2C_OAR2_offs 0x0C // I2C Own address register 2
#define I2C_DR_offs 0x10 // I2C Data register
#define I2C_SR1_offs 0x14 // I2C Status register 1
#define I2C_SR2_offs 0x18 // I2C Status register 2
#define I2C_CCR_offs 0x1C // I2C Clock control register
#define I2C_TRISE_offs 0x20 // I2C TRISE register
// I2C 1
#define I2C1_CR1 MMIO32(I2C1 + 0x00) // I2C1 Control register 1,
#define I2C1_CR2 MMIO32(I2C1 + 0x04) // I2C1 Control register 2,
#define I2C1_OAR1 MMIO32(I2C1 + 0x08) // I2C1 Own address register 1,
#define I2C1_OAR2 MMIO32(I2C1 + 0x0C) // I2C1 Own address register 2,
#define I2C1_DR MMIO32(I2C1 + 0x10) // I2C1 Data register,
#define I2C1_SR1 MMIO32(I2C1 + 0x14) // I2C1 Status register 1,
#define I2C1_SR2 MMIO32(I2C1 + 0x18) // I2C1 Status register 2,
#define I2C1_CCR MMIO32(I2C1 + 0x1C) // I2C1 Clock control register,
#define I2C1_TRISE MMIO32(I2C1 + 0x20) // I2C1 TRISE register,
// I2C 2
#define I2C2_CR1 MMIO32(I2C2 + 0x00) // I2C2 Control register 1,
#define I2C2_CR2 MMIO32(I2C2 + 0x04) // I2C2 Control register 2,
#define I2C2_OAR1 MMIO32(I2C2 + 0x08) // I2C2 Own address register 1,
#define I2C2_OAR2 MMIO32(I2C2 + 0x0C) // I2C2 Own address register 2,
#define I2C2_DR MMIO32(I2C2 + 0x10) // I2C2 Data register,
#define I2C2_SR1 MMIO32(I2C2 + 0x14) // I2C2 Status register 1,
#define I2C2_SR2 MMIO32(I2C2 + 0x18) // I2C2 Status register 2,
#define I2C2_CCR MMIO32(I2C2 + 0x1C) // I2C2 Clock control register,
#define I2C2_TRISE MMIO32(I2C2 + 0x20) // I2C2 TRISE register,
//****************************************************************************
//*
//* BIT MASKS AND DEFINITIONS
//*
//****************************************************************************
//****************** Bit definition for I2C_CR1 register *******************
#define I2C_CR1_PE 0x0001 // Peripheral Enable
#define I2C_CR1_SMBUS 0x0002 // SMBus Mode
#define I2C_CR1_SMBTYPE 0x0008 // SMBus Type
#define I2C_CR1_ENARP 0x0010 // ARP Enable
#define I2C_CR1_ENPEC 0x0020 // PEC Enable
#define I2C_CR1_ENGC 0x0040 // General Call Enable
#define I2C_CR1_NOSTRETCH 0x0080 // Clock Stretching Disable (Slave mode)
#define I2C_CR1_START 0x0100 // Start Generation
#define I2C_CR1_STOP 0x0200 // Stop Generation
#define I2C_CR1_ACK 0x0400 // Acknowledge Enable
#define I2C_CR1_POS 0x0800 // Acknowledge/PEC Position (for data reception)
#define I2C_CR1_PEC 0x1000 // Packet Error Checking
#define I2C_CR1_ALERT 0x2000 // SMBus Alert
#define I2C_CR1_SWRST 0x8000 // Software Reset
//****************** Bit definition for I2C_CR2 register *******************
#define I2C_CR2_FREQ 0x003F // FREQ[5:0] bits (Peripheral Clock Frequency)
#define I2C_CR2_FREQ_0 0x0001 // Bit 0
#define I2C_CR2_FREQ_1 0x0002 // Bit 1
#define I2C_CR2_FREQ_2 0x0004 // Bit 2
#define I2C_CR2_FREQ_3 0x0008 // Bit 3
#define I2C_CR2_FREQ_4 0x0010 // Bit 4
#define I2C_CR2_FREQ_5 0x0020 // Bit 5
#define I2C_CR2_ITERREN 0x0100 // Error Interrupt Enable
#define I2C_CR2_ITEVTEN 0x0200 // Event Interrupt Enable
#define I2C_CR2_ITBUFEN 0x0400 // Buffer Interrupt Enable
#define I2C_CR2_DMAEN 0x0800 // DMA Requests Enable
#define I2C_CR2_LAST 0x1000 // DMA Last Transfer
//****************** Bit definition for I2C_OAR1 register ******************
#define I2C_OAR1_ADD1_7 0x00FE // Interface Address
#define I2C_OAR1_ADD8_9 0x0300 // Interface Address
#define I2C_OAR1_ADD0 0x0001 // Bit 0
#define I2C_OAR1_ADD1 0x0002 // Bit 1
#define I2C_OAR1_ADD2 0x0004 // Bit 2
#define I2C_OAR1_ADD3 0x0008 // Bit 3
#define I2C_OAR1_ADD4 0x0010 // Bit 4
#define I2C_OAR1_ADD5 0x0020 // Bit 5
#define I2C_OAR1_ADD6 0x0040 // Bit 6
#define I2C_OAR1_ADD7 0x0080 // Bit 7
#define I2C_OAR1_ADD8 0x0100 // Bit 8
#define I2C_OAR1_ADD9 0x0200 // Bit 9
#define I2C_OAR1_ADDMODE 0x8000 // Addressing Mode (Slave mode)
//****************** Bit definition for I2C_OAR2 register ******************
#define I2C_OAR2_ENDUAL 0x01 // Dual addressing mode enable
#define I2C_OAR2_ADD2 0xFE // Interface address
//******************* Bit definition for I2C_DR register *******************
#define I2C_DR_DR 0xFF // 8-bit Data Register
//****************** Bit definition for I2C_SR1 register *******************
#define I2C_SR1_SB 0x0001 // Start Bit (Master mode)
#define I2C_SR1_ADDR 0x0002 // Address sent (master mode)/matched (slave mode)
#define I2C_SR1_BTF 0x0004 // Byte Transfer Finished
#define I2C_SR1_ADD10 0x0008 // 10-bit header sent (Master mode)
#define I2C_SR1_STOPF 0x0010 // Stop detection (Slave mode)
#define I2C_SR1_RXNE 0x0040 // Data Register not Empty (receivers)
#define I2C_SR1_TXE 0x0080 // Data Register Empty (transmitters)
#define I2C_SR1_BERR 0x0100 // Bus Error
#define I2C_SR1_ARLO 0x0200 // Arbitration Lost (master mode)
#define I2C_SR1_AF 0x0400 // Acknowledge Failure
#define I2C_SR1_OVR 0x0800 // Overrun/Underrun
#define I2C_SR1_PECERR 0x1000 // PEC Error in reception
#define I2C_SR1_TIMEOUT 0x4000 // Timeout or Tlow Error
#define I2C_SR1_SMBALERT 0x8000 // SMBus Alert
//****************** Bit definition for I2C_SR2 register *******************
#define I2C_SR2_MSL 0x0001 // Master/Slave
#define I2C_SR2_BUSY 0x0002 // Bus Busy
#define I2C_SR2_TRA 0x0004 // Transmitter/Receiver
#define I2C_SR2_GENCALL 0x0010 // General Call Address (Slave mode)
#define I2C_SR2_SMBDEFAULT 0x0020 // SMBus Device Default Address (Slave mode)
#define I2C_SR2_SMBHOST 0x0040 // SMBus Host Header (Slave mode)
#define I2C_SR2_DUALF 0x0080 // Dual Flag (Slave mode)
#define I2C_SR2_PEC 0xFF00 // Packet Error Checking Register
//****************** Bit definition for I2C_CCR register *******************
#define I2C_CCR_CCR 0x0FFF // Clock Control Register in Fast/Standard mode (Master mode)
#define I2C_CCR_DUTY 0x4000 // Fast Mode Duty Cycle
#define I2C_CCR_FS 0x8000 // I2C Master Mode Selection
//***************** Bit definition for I2C_TRISE register ******************
#define I2C_TRISE_TRISE 0x3F // Maximum Rise Time in Fast/Standard mode (Master mode)

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lib/defs_rcc.h
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#pragma once
#include "common.h"
// RCC registers

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lib/defs_spi.h
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#pragma once
#include "common.h"
// AUTHOR : Ondrej Hruska
// DATE : 12/2015
// DESCR : Control registers and bit masks for SPI
//****************************************************************************
//*
//* REGISTERS
//*
//****************************************************************************
// offsets
#define SPI_CR1_offs 0x00 // SPI1 control register 1 (not used in I2S mode)
#define SPI_CR2_offs 0x04 // SPI1 control register 2
#define SPI_SR_offs 0x08 // SPI1 status register
#define SPI_DR_offs 0x0C // SPI1 data register
#define SPI_CRCPR_offs 0x10 // SPI1 CRC polynomial register (not used in I2S mode)
#define SPI_RXCRCR_offs 0x14 // SPI1 RX CRC register (not used in I2S mode)
#define SPI_TXCRCR_offs 0x18 // SPI1 TX CRC register (not used in I2S mode)
#define SPI_I2SCFGR_offs 0x1C // SPI1_I2S configuration register
#define SPI_I2SPR_offs 0x20 // SPI1_I2S prescaler register
// SPI 1
#define SPI1_CR1 MMIO32(SPI1 + 0x00) // SPI1 control register 1 (not used in I2S mode),
#define SPI1_CR2 MMIO32(SPI1 + 0x04) // SPI1 control register 2,
#define SPI1_SR MMIO32(SPI1 + 0x08) // SPI1 status register,
#define SPI1_DR MMIO32(SPI1 + 0x0C) // SPI1 data register,
#define SPI1_CRCPR MMIO32(SPI1 + 0x10) // SPI1 CRC polynomial register (not used in I2S mode),
#define SPI1_RXCRCR MMIO32(SPI1 + 0x14) // SPI1 RX CRC register (not used in I2S mode),
#define SPI1_TXCRCR MMIO32(SPI1 + 0x18) // SPI1 TX CRC register (not used in I2S mode),
#define SPI1_I2SCFGR MMIO32(SPI1 + 0x1C) // SPI1_I2S configuration register,
#define SPI1_I2SPR MMIO32(SPI1 + 0x20) // SPI1_I2S prescaler register,
// SPI 2
#define SPI2_CR1 MMIO32(SPI2 + 0x00) // SPI2 control register 1 (not used in I2S mode),
#define SPI2_CR2 MMIO32(SPI2 + 0x04) // SPI2 control register 2,
#define SPI2_SR MMIO32(SPI2 + 0x08) // SPI2 status register,
#define SPI2_DR MMIO32(SPI2 + 0x0C) // SPI2 data register,
#define SPI2_CRCPR MMIO32(SPI2 + 0x10) // SPI2 CRC polynomial register (not used in I2S mode),
#define SPI2_RXCRCR MMIO32(SPI2 + 0x14) // SPI2 RX CRC register (not used in I2S mode),
#define SPI2_TXCRCR MMIO32(SPI2 + 0x18) // SPI2 TX CRC register (not used in I2S mode),
#define SPI2_I2SCFGR MMIO32(SPI2 + 0x1C) // SPI2_I2S configuration register,
#define SPI2_I2SPR MMIO32(SPI2 + 0x20) // SPI2_I2S prescaler register,
// SPI 3
#define SPI3_CR1 MMIO32(SPI3 + 0x00) // SPI3 control register 1 (not used in I2S mode),
#define SPI3_CR2 MMIO32(SPI3 + 0x04) // SPI3 control register 2,
#define SPI3_SR MMIO32(SPI3 + 0x08) // SPI3 status register,
#define SPI3_DR MMIO32(SPI3 + 0x0C) // SPI3 data register,
#define SPI3_CRCPR MMIO32(SPI3 + 0x10) // SPI3 CRC polynomial register (not used in I2S mode),
#define SPI3_RXCRCR MMIO32(SPI3 + 0x14) // SPI3 RX CRC register (not used in I2S mode),
#define SPI3_TXCRCR MMIO32(SPI3 + 0x18) // SPI3 TX CRC register (not used in I2S mode),
#define SPI3_I2SCFGR MMIO32(SPI3 + 0x1C) // SPI3_I2S configuration register,
#define SPI3_I2SPR MMIO32(SPI3 + 0x20) // SPI3_I2S prescaler register,
//****************************************************************************
//*
//* BIT MASKS AND DEFINITIONS
//*
//****************************************************************************
//****************** Bit definition for SPI_CR1 register *******************
#define SPI_CR1_CPHA 0x0001 // Clock Phase
#define SPI_CR1_CPOL 0x0002 // Clock Polarity
#define SPI_CR1_MSTR 0x0004 // Master Selection
#define SPI_CR1_BR 0x0038 // BR[2:0] bits (Baud Rate Control)
#define SPI_CR1_BR_0 0x0008 // Bit 0
#define SPI_CR1_BR_1 0x0010 // Bit 1
#define SPI_CR1_BR_2 0x0020 // Bit 2
#define SPI_CR1_SPE 0x0040 // SPI Enable
#define SPI_CR1_LSBFIRST 0x0080 // Frame Format
#define SPI_CR1_SSI 0x0100 // Internal slave select
#define SPI_CR1_SSM 0x0200 // Software slave management
#define SPI_CR1_RXONLY 0x0400 // Receive only
#define SPI_CR1_DFF 0x0800 // Data Frame Format
#define SPI_CR1_CRCNEXT 0x1000 // Transmit CRC next
#define SPI_CR1_CRCEN 0x2000 // Hardware CRC calculation enable
#define SPI_CR1_BIDIOE 0x4000 // Output enable in bidirectional mode
#define SPI_CR1_BIDIMODE 0x8000 // Bidirectional data mode enable
//****************** Bit definition for SPI_CR2 register *******************
#define SPI_CR2_RXDMAEN 0x01 // Rx Buffer DMA Enable
#define SPI_CR2_TXDMAEN 0x02 // Tx Buffer DMA Enable
#define SPI_CR2_SSOE 0x04 // SS Output Enable
#define SPI_CR2_FRF 0x08 // Frame format
#define SPI_CR2_ERRIE 0x20 // Error Interrupt Enable
#define SPI_CR2_RXNEIE 0x40 // RX buffer Not Empty Interrupt Enable
#define SPI_CR2_TXEIE 0x80 // Tx buffer Empty Interrupt Enable
//******************* Bit definition for SPI_SR register *******************
#define SPI_SR_RXNE 0x01 // Receive buffer Not Empty
#define SPI_SR_TXE 0x02 // Transmit buffer Empty
#define SPI_SR_CHSIDE 0x04 // Channel side
#define SPI_SR_UDR 0x08 // Underrun flag
#define SPI_SR_CRCERR 0x10 // CRC Error flag
#define SPI_SR_MODF 0x20 // Mode fault
#define SPI_SR_OVR 0x40 // Overrun flag
#define SPI_SR_BSY 0x80 // Busy flag
//******************* Bit definition for SPI_DR register *******************
#define SPI_DR_DR 0xFFFF // Data Register
//****************** Bit definition for SPI_CRCPR register *****************
#define SPI_CRCPR_CRCPOLY 0xFFFF // CRC polynomial register
//***************** Bit definition for SPI_RXCRCR register *****************
#define SPI_RXCRCR_RXCRC 0xFFFF // Rx CRC Register
//***************** Bit definition for SPI_TXCRCR register *****************
#define SPI_TXCRCR_TXCRC 0xFFFF // Tx CRC Register
//***************** Bit definition for SPI_I2SCFGR register ****************
#define SPI_I2SCFGR_CHLEN 0x0001 // Channel length (number of bits per audio channel)
#define SPI_I2SCFGR_DATLEN 0x0006 // DATLEN[1:0] bits (Data length to be transferred)
#define SPI_I2SCFGR_DATLEN_0 0x0002 // Bit 0
#define SPI_I2SCFGR_DATLEN_1 0x0004 // Bit 1
#define SPI_I2SCFGR_CKPOL 0x0008 // steady state clock polarity
#define SPI_I2SCFGR_I2SSTD 0x0030 // I2SSTD[1:0] bits (I2S standard selection)
#define SPI_I2SCFGR_I2SSTD_0 0x0010 // Bit 0
#define SPI_I2SCFGR_I2SSTD_1 0x0020 // Bit 1
#define SPI_I2SCFGR_PCMSYNC 0x0080 // PCM frame synchronization
#define SPI_I2SCFGR_I2SCFG 0x0300 // I2SCFG[1:0] bits (I2S configuration mode)
#define SPI_I2SCFGR_I2SCFG_0 0x0100 // Bit 0
#define SPI_I2SCFGR_I2SCFG_1 0x0200 // Bit 1
#define SPI_I2SCFGR_I2SE 0x0400 // I2S Enable
#define SPI_I2SCFGR_I2SMOD 0x0800 // I2S mode selection
//***************** Bit definition for SPI_I2SPR register ******************
#define SPI_I2SPR_I2SDIV 0x00FF // I2S Linear prescaler
#define SPI_I2SPR_ODD 0x0100 // Odd factor for the prescaler
#define SPI_I2SPR_MCKOE 0x0200 // Master Clock Output Enable

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lib/defs_timers.h
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#pragma once
#include "common.h"
// AUTHOR : Ondrej Hruska
// DATE : 12/2015
// DESCR : Control registers and bit masks for TIM (timers)
//****************************************************************************
//*
//* REGISTERS
//*
//****************************************************************************
// offsets
#define TIM_CR1_offs 0x00 // TIM control register 1
#define TIM_CR2_offs 0x04 // TIM control register 2
#define TIM_SMCR_offs 0x08 // TIM slave mode control register
#define TIM_DIER_offs 0x0C // TIM DMA/interrupt enable register
#define TIM_SR_offs 0x10 // TIM status register
#define TIM_EGR_offs 0x14 // TIM event generation register
#define TIM_CCMR1_offs 0x18 // TIM capture/compare mode register 1
#define TIM_CCMR2_offs 0x1C // TIM capture/compare mode register 2
#define TIM_CCER_offs 0x20 // TIM capture/compare enable register
#define TIM_CNT_offs 0x24 // TIM counter register
#define TIM_PSC_offs 0x28 // TIM prescaler
#define TIM_ARR_offs 0x2C // TIM auto-reload register
#define TIM_CCR1_offs 0x34 // TIM capture/compare register 1
#define TIM_CCR2_offs 0x38 // TIM capture/compare register 2
#define TIM_CCR3_offs 0x3C // TIM capture/compare register 3
#define TIM_CCR4_offs 0x40 // TIM capture/compare register 4
#define TIM_DCR_offs 0x48 // TIM DMA control register
#define TIM_DMAR_offs 0x4C // TIM DMA address for full transfer
#define TIM_OR_offs 0x50 // TIM option register
// Timer 2
#define TIM2_CR1 MMIO32(TIM2 + 0x00) // TIM control register 1,
#define TIM2_CR2 MMIO32(TIM2 + 0x04) // TIM control register 2,
#define TIM2_SMCR MMIO32(TIM2 + 0x08) // TIM slave mode control register,
#define TIM2_DIER MMIO32(TIM2 + 0x0C) // TIM DMA/interrupt enable register,
#define TIM2_SR MMIO32(TIM2 + 0x10) // TIM status register,
#define TIM2_EGR MMIO32(TIM2 + 0x14) // TIM event generation register,
#define TIM2_CCMR1 MMIO32(TIM2 + 0x18) // TIM capture/compare mode register 1,
#define TIM2_CCMR2 MMIO32(TIM2 + 0x1C) // TIM capture/compare mode register 2,
#define TIM2_CCER MMIO32(TIM2 + 0x20) // TIM capture/compare enable register,
#define TIM2_CNT MMIO32(TIM2 + 0x24) // TIM counter register,
#define TIM2_PSC MMIO32(TIM2 + 0x28) // TIM prescaler,
#define TIM2_ARR MMIO32(TIM2 + 0x2C) // TIM auto-reload register,
#define TIM2_CCR1 MMIO32(TIM2 + 0x34) // TIM capture/compare register 1,
#define TIM2_CCR2 MMIO32(TIM2 + 0x38) // TIM capture/compare register 2,
#define TIM2_CCR3 MMIO32(TIM2 + 0x3C) // TIM capture/compare register 3,
#define TIM2_CCR4 MMIO32(TIM2 + 0x40) // TIM capture/compare register 4,
#define TIM2_DCR MMIO32(TIM2 + 0x48) // TIM DMA control register,
#define TIM2_DMAR MMIO32(TIM2 + 0x4C) // TIM DMA address for full transfer,
#define TIM2_OR MMIO32(TIM2 + 0x50) // TIM option register,
// Timer 3
#define TIM3_CR1 MMIO32(TIM3 + 0x00) // TIM control register 1,
#define TIM3_CR2 MMIO32(TIM3 + 0x04) // TIM control register 2,
#define TIM3_SMCR MMIO32(TIM3 + 0x08) // TIM slave mode control register,
#define TIM3_DIER MMIO32(TIM3 + 0x0C) // TIM DMA/interrupt enable register,
#define TIM3_SR MMIO32(TIM3 + 0x10) // TIM status register,
#define TIM3_EGR MMIO32(TIM3 + 0x14) // TIM event generation register,
#define TIM3_CCMR1 MMIO32(TIM3 + 0x18) // TIM capture/compare mode register 1,
#define TIM3_CCMR2 MMIO32(TIM3 + 0x1C) // TIM capture/compare mode register 2,
#define TIM3_CCER MMIO32(TIM3 + 0x20) // TIM capture/compare enable register,
#define TIM3_CNT MMIO32(TIM3 + 0x24) // TIM counter register,
#define TIM3_PSC MMIO32(TIM3 + 0x28) // TIM prescaler,
#define TIM3_ARR MMIO32(TIM3 + 0x2C) // TIM auto-reload register,
#define TIM3_CCR1 MMIO32(TIM3 + 0x34) // TIM capture/compare register 1,
#define TIM3_CCR2 MMIO32(TIM3 + 0x38) // TIM capture/compare register 2,
#define TIM3_CCR3 MMIO32(TIM3 + 0x3C) // TIM capture/compare register 3,
#define TIM3_CCR4 MMIO32(TIM3 + 0x40) // TIM capture/compare register 4,
#define TIM3_DCR MMIO32(TIM3 + 0x48) // TIM DMA control register,
#define TIM3_DMAR MMIO32(TIM3 + 0x4C) // TIM DMA address for full transfer,
#define TIM3_OR MMIO32(TIM3 + 0x50) // TIM option register,
// Timer 4
#define TIM4_CR1 MMIO32(TIM4 + 0x00) // TIM control register 1,
#define TIM4_CR2 MMIO32(TIM4 + 0x04) // TIM control register 2,
#define TIM4_SMCR MMIO32(TIM4 + 0x08) // TIM slave mode control register,
#define TIM4_DIER MMIO32(TIM4 + 0x0C) // TIM DMA/interrupt enable register,
#define TIM4_SR MMIO32(TIM4 + 0x10) // TIM status register,
#define TIM4_EGR MMIO32(TIM4 + 0x14) // TIM event generation register,
#define TIM4_CCMR1 MMIO32(TIM4 + 0x18) // TIM capture/compare mode register 1,
#define TIM4_CCMR2 MMIO32(TIM4 + 0x1C) // TIM capture/compare mode register 2,
#define TIM4_CCER MMIO32(TIM4 + 0x20) // TIM capture/compare enable register,
#define TIM4_CNT MMIO32(TIM4 + 0x24) // TIM counter register,
#define TIM4_PSC MMIO32(TIM4 + 0x28) // TIM prescaler,
#define TIM4_ARR MMIO32(TIM4 + 0x2C) // TIM auto-reload register,
#define TIM4_CCR1 MMIO32(TIM4 + 0x34) // TIM capture/compare register 1,
#define TIM4_CCR2 MMIO32(TIM4 + 0x38) // TIM capture/compare register 2,
#define TIM4_CCR3 MMIO32(TIM4 + 0x3C) // TIM capture/compare register 3,
#define TIM4_CCR4 MMIO32(TIM4 + 0x40) // TIM capture/compare register 4,
#define TIM4_DCR MMIO32(TIM4 + 0x48) // TIM DMA control register,
#define TIM4_DMAR MMIO32(TIM4 + 0x4C) // TIM DMA address for full transfer,
#define TIM4_OR MMIO32(TIM4 + 0x50) // TIM option register,
// Timer 5
#define TIM5_CR1 MMIO32(TIM5 + 0x00) // TIM control register 1,
#define TIM5_CR2 MMIO32(TIM5 + 0x04) // TIM control register 2,
#define TIM5_SMCR MMIO32(TIM5 + 0x08) // TIM slave mode control register,
#define TIM5_DIER MMIO32(TIM5 + 0x0C) // TIM DMA/interrupt enable register,
#define TIM5_SR MMIO32(TIM5 + 0x10) // TIM status register,
#define TIM5_EGR MMIO32(TIM5 + 0x14) // TIM event generation register,
#define TIM5_CCMR1 MMIO32(TIM5 + 0x18) // TIM capture/compare mode register 1,
#define TIM5_CCMR2 MMIO32(TIM5 + 0x1C) // TIM capture/compare mode register 2,
#define TIM5_CCER MMIO32(TIM5 + 0x20) // TIM capture/compare enable register,
#define TIM5_CNT MMIO32(TIM5 + 0x24) // TIM counter register,
#define TIM5_PSC MMIO32(TIM5 + 0x28) // TIM prescaler,
#define TIM5_ARR MMIO32(TIM5 + 0x2C) // TIM auto-reload register,
#define TIM5_CCR1 MMIO32(TIM5 + 0x34) // TIM capture/compare register 1,
#define TIM5_CCR2 MMIO32(TIM5 + 0x38) // TIM capture/compare register 2,
#define TIM5_CCR3 MMIO32(TIM5 + 0x3C) // TIM capture/compare register 3,
#define TIM5_CCR4 MMIO32(TIM5 + 0x40) // TIM capture/compare register 4,
#define TIM5_DCR MMIO32(TIM5 + 0x48) // TIM DMA control register,
#define TIM5_DMAR MMIO32(TIM5 + 0x4C) // TIM DMA address for full transfer,
#define TIM5_OR MMIO32(TIM5 + 0x50) // TIM option register,
// Timer 6
#define TIM6_CR1 MMIO32(TIM6 + 0x00) // TIM control register 1,
#define TIM6_CR2 MMIO32(TIM6 + 0x04) // TIM control register 2,
#define TIM6_SMCR MMIO32(TIM6 + 0x08) // TIM slave mode control register,
#define TIM6_DIER MMIO32(TIM6 + 0x0C) // TIM DMA/interrupt enable register,
#define TIM6_SR MMIO32(TIM6 + 0x10) // TIM status register,
#define TIM6_EGR MMIO32(TIM6 + 0x14) // TIM event generation register,
#define TIM6_CCMR1 MMIO32(TIM6 + 0x18) // TIM capture/compare mode register 1,
#define TIM6_CCMR2 MMIO32(TIM6 + 0x1C) // TIM capture/compare mode register 2,
#define TIM6_CCER MMIO32(TIM6 + 0x20) // TIM capture/compare enable register,
#define TIM6_CNT MMIO32(TIM6 + 0x24) // TIM counter register,
#define TIM6_PSC MMIO32(TIM6 + 0x28) // TIM prescaler,
#define TIM6_ARR MMIO32(TIM6 + 0x2C) // TIM auto-reload register,
#define TIM6_CCR1 MMIO32(TIM6 + 0x34) // TIM capture/compare register 1,
#define TIM6_CCR2 MMIO32(TIM6 + 0x38) // TIM capture/compare register 2,
#define TIM6_CCR3 MMIO32(TIM6 + 0x3C) // TIM capture/compare register 3,
#define TIM6_CCR4 MMIO32(TIM6 + 0x40) // TIM capture/compare register 4,
#define TIM6_DCR MMIO32(TIM6 + 0x48) // TIM DMA control register,
#define TIM6_DMAR MMIO32(TIM6 + 0x4C) // TIM DMA address for full transfer,
#define TIM6_OR MMIO32(TIM6 + 0x50) // TIM option register,
// Timer 7
#define TIM7_CR1 MMIO32(TIM7 + 0x00) // TIM control register 1,
#define TIM7_CR2 MMIO32(TIM7 + 0x04) // TIM control register 2,
#define TIM7_SMCR MMIO32(TIM7 + 0x08) // TIM slave mode control register,
#define TIM7_DIER MMIO32(TIM7 + 0x0C) // TIM DMA/interrupt enable register,
#define TIM7_SR MMIO32(TIM7 + 0x10) // TIM status register,
#define TIM7_EGR MMIO32(TIM7 + 0x14) // TIM event generation register,
#define TIM7_CCMR1 MMIO32(TIM7 + 0x18) // TIM capture/compare mode register 1,
#define TIM7_CCMR2 MMIO32(TIM7 + 0x1C) // TIM capture/compare mode register 2,
#define TIM7_CCER MMIO32(TIM7 + 0x20) // TIM capture/compare enable register,
#define TIM7_CNT MMIO32(TIM7 + 0x24) // TIM counter register,
#define TIM7_PSC MMIO32(TIM7 + 0x28) // TIM prescaler,
#define TIM7_ARR MMIO32(TIM7 + 0x2C) // TIM auto-reload register,
#define TIM7_CCR1 MMIO32(TIM7 + 0x34) // TIM capture/compare register 1,
#define TIM7_CCR2 MMIO32(TIM7 + 0x38) // TIM capture/compare register 2,
#define TIM7_CCR3 MMIO32(TIM7 + 0x3C) // TIM capture/compare register 3,
#define TIM7_CCR4 MMIO32(TIM7 + 0x40) // TIM capture/compare register 4,
#define TIM7_DCR MMIO32(TIM7 + 0x48) // TIM DMA control register,
#define TIM7_DMAR MMIO32(TIM7 + 0x4C) // TIM DMA address for full transfer,
#define TIM7_OR MMIO32(TIM7 + 0x50) // TIM option register,
// Timer 9
#define TIM9_CR1 MMIO32(TIM9 + 0x00) // TIM control register 1,
#define TIM9_CR2 MMIO32(TIM9 + 0x04) // TIM control register 2,
#define TIM9_SMCR MMIO32(TIM9 + 0x08) // TIM slave mode control register,
#define TIM9_DIER MMIO32(TIM9 + 0x0C) // TIM DMA/interrupt enable register,
#define TIM9_SR MMIO32(TIM9 + 0x10) // TIM status register,
#define TIM9_EGR MMIO32(TIM9 + 0x14) // TIM event generation register,
#define TIM9_CCMR1 MMIO32(TIM9 + 0x18) // TIM capture/compare mode register 1,
#define TIM9_CCMR2 MMIO32(TIM9 + 0x1C) // TIM capture/compare mode register 2,
#define TIM9_CCER MMIO32(TIM9 + 0x20) // TIM capture/compare enable register,
#define TIM9_CNT MMIO32(TIM9 + 0x24) // TIM counter register,
#define TIM9_PSC MMIO32(TIM9 + 0x28) // TIM prescaler,
#define TIM9_ARR MMIO32(TIM9 + 0x2C) // TIM auto-reload register,
#define TIM9_CCR1 MMIO32(TIM9 + 0x34) // TIM capture/compare register 1,
#define TIM9_CCR2 MMIO32(TIM9 + 0x38) // TIM capture/compare register 2,
#define TIM9_CCR3 MMIO32(TIM9 + 0x3C) // TIM capture/compare register 3,
#define TIM9_CCR4 MMIO32(TIM9 + 0x40) // TIM capture/compare register 4,
#define TIM9_DCR MMIO32(TIM9 + 0x48) // TIM DMA control register,
#define TIM9_DMAR MMIO32(TIM9 + 0x4C) // TIM DMA address for full transfer,
#define TIM9_OR MMIO32(TIM9 + 0x50) // TIM option register,
// Timer 10
#define TIM10_CR1 MMIO32(TIM10 + 0x00) // TIM control register 1,
#define TIM10_CR2 MMIO32(TIM10 + 0x04) // TIM control register 2,
#define TIM10_SMCR MMIO32(TIM10 + 0x08) // TIM slave mode control register,
#define TIM10_DIER MMIO32(TIM10 + 0x0C) // TIM DMA/interrupt enable register,
#define TIM10_SR MMIO32(TIM10 + 0x10) // TIM status register,
#define TIM10_EGR MMIO32(TIM10 + 0x14) // TIM event generation register,
#define TIM10_CCMR1 MMIO32(TIM10 + 0x18) // TIM capture/compare mode register 1,
#define TIM10_CCMR2 MMIO32(TIM10 + 0x1C) // TIM capture/compare mode register 2,
#define TIM10_CCER MMIO32(TIM10 + 0x20) // TIM capture/compare enable register,
#define TIM10_CNT MMIO32(TIM10 + 0x24) // TIM counter register,
#define TIM10_PSC MMIO32(TIM10 + 0x28) // TIM prescaler,
#define TIM10_ARR MMIO32(TIM10 + 0x2C) // TIM auto-reload register,
#define TIM10_CCR1 MMIO32(TIM10 + 0x34) // TIM capture/compare register 1,
#define TIM10_CCR2 MMIO32(TIM10 + 0x38) // TIM capture/compare register 2,
#define TIM10_CCR3 MMIO32(TIM10 + 0x3C) // TIM capture/compare register 3,
#define TIM10_CCR4 MMIO32(TIM10 + 0x40) // TIM capture/compare register 4,
#define TIM10_DCR MMIO32(TIM10 + 0x48) // TIM DMA control register,
#define TIM10_DMAR MMIO32(TIM10 + 0x4C) // TIM DMA address for full transfer,
#define TIM10_OR MMIO32(TIM10 + 0x50) // TIM option register,
// Timer 11
#define TIM11_CR1 MMIO32(TIM11 + 0x00) // TIM control register 1,
#define TIM11_CR2 MMIO32(TIM11 + 0x04) // TIM control register 2,
#define TIM11_SMCR MMIO32(TIM11 + 0x08) // TIM slave mode control register,
#define TIM11_DIER MMIO32(TIM11 + 0x0C) // TIM DMA/interrupt enable register,
#define TIM11_SR MMIO32(TIM11 + 0x10) // TIM status register,
#define TIM11_EGR MMIO32(TIM11 + 0x14) // TIM event generation register,
#define TIM11_CCMR1 MMIO32(TIM11 + 0x18) // TIM capture/compare mode register 1,
#define TIM11_CCMR2 MMIO32(TIM11 + 0x1C) // TIM capture/compare mode register 2,
#define TIM11_CCER MMIO32(TIM11 + 0x20) // TIM capture/compare enable register,
#define TIM11_CNT MMIO32(TIM11 + 0x24) // TIM counter register,
#define TIM11_PSC MMIO32(TIM11 + 0x28) // TIM prescaler,
#define TIM11_ARR MMIO32(TIM11 + 0x2C) // TIM auto-reload register,
#define TIM11_CCR1 MMIO32(TIM11 + 0x34) // TIM capture/compare register 1,
#define TIM11_CCR2 MMIO32(TIM11 + 0x38) // TIM capture/compare register 2,
#define TIM11_CCR3 MMIO32(TIM11 + 0x3C) // TIM capture/compare register 3,
#define TIM11_CCR4 MMIO32(TIM11 + 0x40) // TIM capture/compare register 4,
#define TIM11_DCR MMIO32(TIM11 + 0x48) // TIM DMA control register,
#define TIM11_DMAR MMIO32(TIM11 + 0x4C) // TIM DMA address for full transfer,
#define TIM11_OR MMIO32(TIM11 + 0x50) // TIM option register,
//****************************************************************************
//*
//* BIT MASKS AND DEFINITIONS
//*
//****************************************************************************
//****************** Bit definition for TIM_CR1 register *******************
#define TIM_CR1_CEN 0x0001 // Counter enable
#define TIM_CR1_UDIS 0x0002 // Update disable
#define TIM_CR1_URS 0x0004 // Update request source
#define TIM_CR1_OPM 0x0008 // One pulse mode
#define TIM_CR1_DIR 0x0010 // Direction
#define TIM_CR1_CMS 0x0060 // CMS[1:0] bits (Center-aligned mode selection)
#define TIM_CR1_CMS_0 0x0020 // Bit 0
#define TIM_CR1_CMS_1 0x0040 // Bit 1
#define TIM_CR1_ARPE 0x0080 // Auto-reload preload enable
#define TIM_CR1_CKD 0x0300 // CKD[1:0] bits (clock division)
#define TIM_CR1_CKD_0 0x0100 // Bit 0
#define TIM_CR1_CKD_1 0x0200 // Bit 1
//****************** Bit definition for TIM_CR2 register *******************
#define TIM_CR2_CCDS 0x0008 // Capture/Compare DMA Selection
#define TIM_CR2_MMS 0x0070 // MMS[2:0] bits (Master Mode Selection)
#define TIM_CR2_MMS_0 0x0010 // Bit 0
#define TIM_CR2_MMS_1 0x0020 // Bit 1
#define TIM_CR2_MMS_2 0x0040 // Bit 2
#define TIM_CR2_TI1S 0x0080 // TI1 Selection
//****************** Bit definition for TIM_SMCR register ******************
#define TIM_SMCR_SMS 0x0007 // SMS[2:0] bits (Slave mode selection)
#define TIM_SMCR_SMS_0 0x0001 // Bit 0
#define TIM_SMCR_SMS_1 0x0002 // Bit 1
#define TIM_SMCR_SMS_2 0x0004 // Bit 2
#define TIM_SMCR_OCCS 0x0008 // OCCS bits (OCref Clear Selection)
#define TIM_SMCR_TS 0x0070 // TS[2:0] bits (Trigger selection)
#define TIM_SMCR_TS_0 0x0010 // Bit 0
#define TIM_SMCR_TS_1 0x0020 // Bit 1
#define TIM_SMCR_TS_2 0x0040 // Bit 2
#define TIM_SMCR_MSM 0x0080 // Master/slave mode
#define TIM_SMCR_ETF 0x0F00 // ETF[3:0] bits (External trigger filter)
#define TIM_SMCR_ETF_0 0x0100 // Bit 0
#define TIM_SMCR_ETF_1 0x0200 // Bit 1
#define TIM_SMCR_ETF_2 0x0400 // Bit 2
#define TIM_SMCR_ETF_3 0x0800 // Bit 3
#define TIM_SMCR_ETPS 0x3000 // ETPS[1:0] bits (External trigger prescaler)
#define TIM_SMCR_ETPS_0 0x1000 // Bit 0
#define TIM_SMCR_ETPS_1 0x2000 // Bit 1
#define TIM_SMCR_ECE 0x4000 // External clock enable
#define TIM_SMCR_ETP 0x8000 // External trigger polarity
//****************** Bit definition for TIM_DIER register ******************
#define TIM_DIER_UIE 0x0001 // Update interrupt enable
#define TIM_DIER_CC1IE 0x0002 // Capture/Compare 1 interrupt enable
#define TIM_DIER_CC2IE 0x0004 // Capture/Compare 2 interrupt enable
#define TIM_DIER_CC3IE 0x0008 // Capture/Compare 3 interrupt enable
#define TIM_DIER_CC4IE 0x0010 // Capture/Compare 4 interrupt enable
#define TIM_DIER_TIE 0x0040 // Trigger interrupt enable
#define TIM_DIER_UDE 0x0100 // Update DMA request enable
#define TIM_DIER_CC1DE 0x0200 // Capture/Compare 1 DMA request enable
#define TIM_DIER_CC2DE 0x0400 // Capture/Compare 2 DMA request enable
#define TIM_DIER_CC3DE 0x0800 // Capture/Compare 3 DMA request enable
#define TIM_DIER_CC4DE 0x1000 // Capture/Compare 4 DMA request enable
#define TIM_DIER_TDE 0x4000 // Trigger DMA request enable
//******************* Bit definition for TIM_SR register *******************
#define TIM_SR_UIF 0x0001 // Update interrupt Flag
#define TIM_SR_CC1IF 0x0002 // Capture/Compare 1 interrupt Flag
#define TIM_SR_CC2IF 0x0004 // Capture/Compare 2 interrupt Flag
#define TIM_SR_CC3IF 0x0008 // Capture/Compare 3 interrupt Flag
#define TIM_SR_CC4IF 0x0010 // Capture/Compare 4 interrupt Flag
#define TIM_SR_TIF 0x0040 // Trigger interrupt Flag
#define TIM_SR_CC1OF 0x0200 // Capture/Compare 1 Overcapture Flag
#define TIM_SR_CC2OF 0x0400 // Capture/Compare 2 Overcapture Flag
#define TIM_SR_CC3OF 0x0800 // Capture/Compare 3 Overcapture Flag
#define TIM_SR_CC4OF 0x1000 // Capture/Compare 4 Overcapture Flag
//****************** Bit definition for TIM_EGR register *******************
#define TIM_EGR_UG 0x01 // Update Generation
#define TIM_EGR_CC1G 0x02 // Capture/Compare 1 Generation
#define TIM_EGR_CC2G 0x04 // Capture/Compare 2 Generation
#define TIM_EGR_CC3G 0x08 // Capture/Compare 3 Generation
#define TIM_EGR_CC4G 0x10 // Capture/Compare 4 Generation
#define TIM_EGR_TG 0x40 // Trigger Generation
//***************** Bit definition for TIM_CCMR1 register ******************
#define TIM_CCMR1_CC1S 0x0003 // CC1S[1:0] bits (Capture/Compare 1 Selection)
#define TIM_CCMR1_CC1S_0 0x0001 // Bit 0
#define TIM_CCMR1_CC1S_1 0x0002 // Bit 1
#define TIM_CCMR1_OC1FE 0x0004 // Output Compare 1 Fast enable
#define TIM_CCMR1_OC1PE 0x0008 // Output Compare 1 Preload enable
#define TIM_CCMR1_OC1M 0x0070 // OC1M[2:0] bits (Output Compare 1 Mode)
#define TIM_CCMR1_OC1M_0 0x0010 // Bit 0
#define TIM_CCMR1_OC1M_1 0x0020 // Bit 1
#define TIM_CCMR1_OC1M_2 0x0040 // Bit 2
#define TIM_CCMR1_OC1CE 0x0080 // Output Compare 1Clear Enable
#define TIM_CCMR1_CC2S 0x0300 // CC2S[1:0] bits (Capture/Compare 2 Selection)
#define TIM_CCMR1_CC2S_0 0x0100 // Bit 0
#define TIM_CCMR1_CC2S_1 0x0200 // Bit 1
#define TIM_CCMR1_OC2FE 0x0400 // Output Compare 2 Fast enable
#define TIM_CCMR1_OC2PE 0x0800 // Output Compare 2 Preload enable
#define TIM_CCMR1_OC2M 0x7000 // OC2M[2:0] bits (Output Compare 2 Mode)
#define TIM_CCMR1_OC2M_0 0x1000 // Bit 0
#define TIM_CCMR1_OC2M_1 0x2000 // Bit 1
#define TIM_CCMR1_OC2M_2 0x4000 // Bit 2
#define TIM_CCMR1_OC2CE 0x8000 // Output Compare 2 Clear Enable
//----------------------------------------------------------------------------
#define TIM_CCMR1_IC1PSC 0x000C // IC1PSC[1:0] bits (Input Capture 1 Prescaler)
#define TIM_CCMR1_IC1PSC_0 0x0004 // Bit 0
#define TIM_CCMR1_IC1PSC_1 0x0008 // Bit 1
#define TIM_CCMR1_IC1F 0x00F0 // IC1F[3:0] bits (Input Capture 1 Filter)
#define TIM_CCMR1_IC1F_0 0x0010 // Bit 0
#define TIM_CCMR1_IC1F_1 0x0020 // Bit 1
#define TIM_CCMR1_IC1F_2 0x0040 // Bit 2
#define TIM_CCMR1_IC1F_3 0x0080 // Bit 3
#define TIM_CCMR1_IC2PSC 0x0C00 // IC2PSC[1:0] bits (Input Capture 2 Prescaler)
#define TIM_CCMR1_IC2PSC_0 0x0400 // Bit 0
#define TIM_CCMR1_IC2PSC_1 0x0800 // Bit 1
#define TIM_CCMR1_IC2F 0xF000 // IC2F[3:0] bits (Input Capture 2 Filter)
#define TIM_CCMR1_IC2F_0 0x1000 // Bit 0
#define TIM_CCMR1_IC2F_1 0x2000 // Bit 1
#define TIM_CCMR1_IC2F_2 0x4000 // Bit 2
#define TIM_CCMR1_IC2F_3 0x8000 // Bit 3
//***************** Bit definition for TIM_CCMR2 register ******************
#define TIM_CCMR2_CC3S 0x0003 // CC3S[1:0] bits (Capture/Compare 3 Selection)
#define TIM_CCMR2_CC3S_0 0x0001 // Bit 0
#define TIM_CCMR2_CC3S_1 0x0002 // Bit 1
#define TIM_CCMR2_OC3FE 0x0004 // Output Compare 3 Fast enable
#define TIM_CCMR2_OC3PE 0x0008 // Output Compare 3 Preload enable
#define TIM_CCMR2_OC3M 0x0070 // OC3M[2:0] bits (Output Compare 3 Mode)
#define TIM_CCMR2_OC3M_0 0x0010 // Bit 0
#define TIM_CCMR2_OC3M_1 0x0020 // Bit 1
#define TIM_CCMR2_OC3M_2 0x0040 // Bit 2
#define TIM_CCMR2_OC3CE 0x0080 // Output Compare 3 Clear Enable
#define TIM_CCMR2_CC4S 0x0300 // CC4S[1:0] bits (Capture/Compare 4 Selection)
#define TIM_CCMR2_CC4S_0 0x0100 // Bit 0
#define TIM_CCMR2_CC4S_1 0x0200 // Bit 1
#define TIM_CCMR2_OC4FE 0x0400 // Output Compare 4 Fast enable
#define TIM_CCMR2_OC4PE 0x0800 // Output Compare 4 Preload enable
#define TIM_CCMR2_OC4M 0x7000 // OC4M[2:0] bits (Output Compare 4 Mode)
#define TIM_CCMR2_OC4M_0 0x1000 // Bit 0
#define TIM_CCMR2_OC4M_1 0x2000 // Bit 1
#define TIM_CCMR2_OC4M_2 0x4000 // Bit 2
#define TIM_CCMR2_OC4CE 0x8000 // Output Compare 4 Clear Enable
//----------------------------------------------------------------------------
#define TIM_CCMR2_IC3PSC 0x000C // IC3PSC[1:0] bits (Input Capture 3 Prescaler)
#define TIM_CCMR2_IC3PSC_0 0x0004 // Bit 0
#define TIM_CCMR2_IC3PSC_1 0x0008 // Bit 1
#define TIM_CCMR2_IC3F 0x00F0 // IC3F[3:0] bits (Input Capture 3 Filter)
#define TIM_CCMR2_IC3F_0 0x0010 // Bit 0
#define TIM_CCMR2_IC3F_1 0x0020 // Bit 1
#define TIM_CCMR2_IC3F_2 0x0040 // Bit 2
#define TIM_CCMR2_IC3F_3 0x0080 // Bit 3
#define TIM_CCMR2_IC4PSC 0x0C00 // IC4PSC[1:0] bits (Input Capture 4 Prescaler)
#define TIM_CCMR2_IC4PSC_0 0x0400 // Bit 0
#define TIM_CCMR2_IC4PSC_1 0x0800 // Bit 1
#define TIM_CCMR2_IC4F 0xF000 // IC4F[3:0] bits (Input Capture 4 Filter)
#define TIM_CCMR2_IC4F_0 0x1000 // Bit 0
#define TIM_CCMR2_IC4F_1 0x2000 // Bit 1
#define TIM_CCMR2_IC4F_2 0x4000 // Bit 2
#define TIM_CCMR2_IC4F_3 0x8000 // Bit 3
//****************** Bit definition for TIM_CCER register ******************
#define TIM_CCER_CC1E 0x0001 // Capture/Compare 1 output enable
#define TIM_CCER_CC1P 0x0002 // Capture/Compare 1 output Polarity
#define TIM_CCER_CC1NP 0x0008 // Capture/Compare 1 Complementary output Polarity
#define TIM_CCER_CC2E 0x0010 // Capture/Compare 2 output enable
#define TIM_CCER_CC2P 0x0020 // Capture/Compare 2 output Polarity
#define TIM_CCER_CC2NP 0x0080 // Capture/Compare 2 Complementary output Polarity
#define TIM_CCER_CC3E 0x0100 // Capture/Compare 3 output enable
#define TIM_CCER_CC3P 0x0200 // Capture/Compare 3 output Polarity
#define TIM_CCER_CC3NP 0x0800 // Capture/Compare 3 Complementary output Polarity
#define TIM_CCER_CC4E 0x1000 // Capture/Compare 4 output enable
#define TIM_CCER_CC4P 0x2000 // Capture/Compare 4 output Polarity
#define TIM_CCER_CC4NP 0x8000 // Capture/Compare 4 Complementary output Polarity
//****************** Bit definition for TIM_CNT register *******************
#define TIM_CNT_CNT 0xFFFF // Counter Value
//****************** Bit definition for TIM_PSC register *******************
#define TIM_PSC_PSC 0xFFFF // Prescaler Value
//****************** Bit definition for TIM_ARR register *******************
#define TIM_ARR_ARR 0xFFFF // actual auto-reload Value
//****************** Bit definition for TIM_CCR1 register ******************
#define TIM_CCR1_CCR1 0xFFFF // Capture/Compare 1 Value
//****************** Bit definition for TIM_CCR2 register ******************
#define TIM_CCR2_CCR2 0xFFFF // Capture/Compare 2 Value
//****************** Bit definition for TIM_CCR3 register ******************
#define TIM_CCR3_CCR3 0xFFFF // Capture/Compare 3 Value
//****************** Bit definition for TIM_CCR4 register ******************
#define TIM_CCR4_CCR4 0xFFFF // Capture/Compare 4 Value
//****************** Bit definition for TIM_DCR register *******************
#define TIM_DCR_DBA 0x001F // DBA[4:0] bits (DMA Base Address)
#define TIM_DCR_DBA_0 0x0001 // Bit 0
#define TIM_DCR_DBA_1 0x0002 // Bit 1
#define TIM_DCR_DBA_2 0x0004 // Bit 2
#define TIM_DCR_DBA_3 0x0008 // Bit 3
#define TIM_DCR_DBA_4 0x0010 // Bit 4
#define TIM_DCR_DBL 0x1F00 // DBL[4:0] bits (DMA Burst Length)
#define TIM_DCR_DBL_0 0x0100 // Bit 0
#define TIM_DCR_DBL_1 0x0200 // Bit 1
#define TIM_DCR_DBL_2 0x0400 // Bit 2
#define TIM_DCR_DBL_3 0x0800 // Bit 3
#define TIM_DCR_DBL_4 0x1000 // Bit 4
//****************** Bit definition for TIM_DMAR register ******************
#define TIM_DMAR_DMAB 0xFFFF // DMA register for burst accesses
//****************** Bit definition for TIM_OR register ********************
#define TIM_OR_TI1RMP 0x0003 // Option register for TI1 Remapping
#define TIM_OR_TI1RMP_0 0x0001 // Bit 0
#define TIM_OR_TI1RMP_1 0x0002 // Bit 1

3
lib/defs_usart.h
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@ -1,3 +1,6 @@
#pragma once
#include "common.h"
// AUTHOR : Ondrej Hruska
// DATE : 12/2015
// DESCR : Control registers and bit masks for USART

7
main.c
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@ -7,25 +7,22 @@
#include "init.h"
#include "blink.h"
// called every 1s
void say_hello(void)
{
usart_tx_string(USART3, "HELLO\r\n");
}
/** Called before main() */
/** Called by startup script, before main() */
void SystemInit(void)
{
init_clock();
init_systick();
init_gpios();
init_usart();
init_adc();
register_periodic_task(green_toggle, 1000);
register_periodic_task(blink_blue, 5000);
}

11
proj.pro
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@ -14,7 +14,8 @@ DISTFILES += \
Makefile \
style.astylerc \
startup_stm32l100xc.s \
stm32l100rc.ld
stm32l100rc.ld \
.gitignore
SOURCES += \
main.c \
@ -47,5 +48,11 @@ HEADERS += \
utils/timebase.h \
utils/usart.h \
utils/debounce.h \
blink.h
blink.h \
lib/defs_adc.h \
lib/defs_dac.h \
lib/defs_dma.h \
lib/defs_i2c.h \
lib/defs_spi.h \
lib/defs_timers.h

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