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142 lines
6.1 KiB
142 lines
6.1 KiB
#pragma once
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#include "common.h"
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// AUTHOR : Ondrej Hruska
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// DATE : 12/2015
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// DESCR : Base library file. This file must be included before any other library
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// files. This file defines memory map and base addresses of peripherals.
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#define FLASH_BASE 0x08000000 // FLASH base address in the alias region
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#define SRAM_BASE 0x20000000 // SRAM base address in the alias region
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#define PERIPH_BASE 0x40000000 // Peripheral base address in the alias region
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#define SRAM_BB_BASE (SRAM_BASE + 0x02000000) // SRAM base address in the bit-band region
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#define PERIPH_BB_BASE (PERIPH_BASE + 0x02000000) // Peripheral base address in the bit-band region
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// ------------------------- System Config Blocks -----------------------------
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#define SCS_BASE 0xE000E000 // System Control Space base
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#define SCB (SCS_BASE + 0x0D00) // System Control Block base
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#define NVIC (SCS_BASE + 0x0100) // Nested Interrupt Vector Controller base
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#define OB_CTRL 0x1FF80000 // FLASH Option Bytes base address
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#define AES_BASE 0x50060000 // Encryption module
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#define FSMC_BASE 0xA0000000 // External Memory Control base
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#define DBGMCU_BASE 0xE0042000 // Debug MCU registers base address
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#define INFO_BASE (0x1ff00000U)
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// ----------------------------- Peripherals ----------------------------------
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// *** Peripheral bus bases ***
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#define APB1_BASE PERIPH_BASE // Advanced Peripheral Bus 1 base
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#define APB2_BASE (PERIPH_BASE + 0x10000) // Advanced Peripheral Bus 2 base
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#define AHB_BASE (PERIPH_BASE + 0x20000) // Advanced High-speed Bus base
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// *** Peripheral Bus 1 devices ***
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#define TIM2 (APB1_BASE + 0x0000) // Timer bases
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#define TIM3 (APB1_BASE + 0x0400)
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#define TIM4 (APB1_BASE + 0x0800)
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#define TIM5 (APB1_BASE + 0x0C00)
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#define TIM6 (APB1_BASE + 0x1000)
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#define TIM7 (APB1_BASE + 0x1400)
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#define LCD (APB1_BASE + 0x2400) // LCD controller base
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#define RTC (APB1_BASE + 0x2800) // RTC base
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#define WWDG (APB1_BASE + 0x2C00) // Window Watchdog base
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#define IWDG (APB1_BASE + 0x3000) // Independent Watchdog base
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#define SPI2 (APB1_BASE + 0x3800) // SPI base
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#define SPI3 (APB1_BASE + 0x3C00)
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#define USART2 (APB1_BASE + 0x4400) // USART base
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#define USART3 (APB1_BASE + 0x4800)
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#define UART4 (APB1_BASE + 0x4C00) // UART base (?)
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#define UART5 (APB1_BASE + 0x5000)
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#define I2C1 (APB1_BASE + 0x5400) // I2C base
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#define I2C2 (APB1_BASE + 0x5800)
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#define PWR_CTRL (APB1_BASE + 0x7000) // Power Control block base
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#define DAC_BASE (APB1_BASE + 0x7400) // D/A config base
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#define COMP_BASE (APB1_BASE + 0x7C00) // Analog Comparator base
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#define RI_BASE (APB1_BASE + 0x7C04) // Routing Interface base (analog pin connections)
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#define OPAMP_BASE (APB1_BASE + 0x7C5C) // OpAmp config base
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#define USB_BASE (APB1_BASE + 0x5C00) // USB registers base
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// *** Peripheral Bus 2 devices ***
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#define TIM9 (APB2_BASE + 0x0800) // Timer base
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#define TIM10 (APB2_BASE + 0x0C00)
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#define TIM11 (APB2_BASE + 0x1000)
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#define SYSCFG_BASE (APB2_BASE + 0x0000) // System config block base
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#define EXTI_BASE (APB2_BASE + 0x0400) // External interrupt settings base
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#define ADC1_BASE (APB2_BASE + 0x2400) // A/D 1
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#define ADCC_BASE (APB2_BASE + 0x2700) // common A/D registers base
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#define SDIO (APB2_BASE + 0x2C00) // SD host
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#define SPI1 (APB2_BASE + 0x3000) // SPI
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#define USART1 (APB2_BASE + 0x3800)
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// *** High Speed Bus devices ***
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#define GPIO_BASE (AHB_BASE + 0x0000) // GPIO block base
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#define CRC_BASE (AHB_BASE + 0x3000) // CRC module base
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#define RCC_BASE (AHB_BASE + 0x3800) // Reset and Clock Config base
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#define DMA1 (AHB_BASE + 0x6000) // DMA control base
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#define DMA2 (AHB_BASE + 0x6400)
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#define FLASH_CTRL (AHB_BASE + 0x3C00) // FLASH control base
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/* MPU: Memory protection unit */
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#define MPU_BASE (SCS_BASE + 0x0D90)
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// ----
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/* Device Electronic Signature */
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#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x8004C)
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#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x80050)
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#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
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#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
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#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)
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/* ST provided factory calibration values @ 3.0V */
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#define ST_VREFINT_CAL MMIO16(0x1FF80078)
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#define ST_TSENSE_CAL1_30C MMIO16(0x1FF8007A)
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#define ST_TSENSE_CAL2_110C MMIO16(0x1FF8007E)
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// ---- ARMv7M+ only ----
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#define PPBI_BASE (0xE0000000U)
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/* STE: Software Trigger Interrupt Register */
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#define STIR_BASE (SCS_BASE + 0x0F00)
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/* ID: ID space */
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#define ID_BASE (SCS_BASE + 0x0FD0)
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/* ITR: Interrupt Type Register */
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#define ITR_BASE (SCS_BASE + 0x0000)
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/* ITM: Instrumentation Trace Macrocell */
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#define ITM_BASE (PPBI_BASE + 0x0000)
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/* DWT: Data Watchpoint and Trace unit */
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#define DWT_BASE (PPBI_BASE + 0x1000)
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/* FPB: Flash Patch and Breakpoint unit */
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#define FPB_BASE (PPBI_BASE + 0x2000)
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#define TPIU_BASE (PPBI_BASE + 0x40000)
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