gex
/
gex-thesis
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

added appendices

Browse Source
master
Ondřej Hruška 8 years ago
parent d1ecdbd405
commit 2cd96c0fb2
Signed by: MightyPork
GPG Key ID: 2C5FD5035250423D
11 changed files with 69 additions and 12 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 7
      ch.hardware_realization.tex
  2. 13
      document_config.tex
  3. BIN
      schema/GexHubSchemRev1.pdf
  4. BIN
      schema/GexHubSchemRev2.pdf
  5. BIN
      schema/GexRadioSchemRev1.pdf
  6. BIN
      schema/GexZeroSchemRev1.pdf
  7. BIN
      schema/GexZeroSchemRev2.pdf
  8. 50
      thesis.appendices.tex
  9. 2
      thesis.bib
  10. BIN
      thesis.pdf
  11. 9
      thesis.tex

7
ch.hardware_realization.tex
Unescape View File

@ -24,7 +24,7 @@ An accelerometer \gls{IC} L3GD20 is fitted on the board, attached to SPI2 on pin
\section{GEX Hub} \section{GEX Hub}
GEX Hub was the first custom \gls{PCB} designed for GEX. It uses the same microcontroller as the Discovery board, thus the firmware modifications needed to make it work with this new platform were minimal. GEX Hub was the first custom \gls{PCB} designed for GEX. It uses the same microcontroller as the Discovery board, thus the firmware modifications needed to make it work with this new platform were minimal. The schematic diagram is attached in \hyperref[apx:gex_hub]{Appendix A}.
The Hub board provides access to all the \gls{GPIO} pins\footnote{With the exception of pins used by USB and the Lock button.} through three flat-cable connectors, one for each port; they also contain a ground and power supply connection to make the attachment of external boards or a breadboard easier, requiring just one cable. The use of flat cables, however, is not mandatory---the flat cable connectors are based on the standard 2.54\,mm-pitch pin headers, allowing the user to use widely available ``jumper wires''. The Hub board provides access to all the \gls{GPIO} pins\footnote{With the exception of pins used by USB and the Lock button.} through three flat-cable connectors, one for each port; they also contain a ground and power supply connection to make the attachment of external boards or a breadboard easier, requiring just one cable. The use of flat cables, however, is not mandatory---the flat cable connectors are based on the standard 2.54\,mm-pitch pin headers, allowing the user to use widely available ``jumper wires''.
@ -241,7 +241,7 @@ Like our STM32 microcontroller, the Broadcom processor on the RPi multiplexes it
\end{table} \end{table}
} }
The GEX Zero pin header's alternate functions should match those on the RPi Zero header, so that the existing add-on boards can be used without modifications. By inspecting the alternate function tables in the STM32F072 datasheet~\cite{f072-ds}, we found a layout that fulfills this requirement almost perfectly. The final assignment is shown in \cref{tbl:gz_rpi_compare}. The GEX Zero pin header's alternate functions should match those on the RPi Zero header, so that the existing add-on boards can be used without modifications. By inspecting the alternate function tables in the STM32F072 datasheet~\cite{f072-ds}, we found a layout that fulfills this requirement almost perfectly. The final assignment is shown in \cref{tbl:gz_rpi_compare}, and the full schematic diagram is attached in \hyperref[apx:gex_zero]{Appendix B}.
\gls{GPIO} ports A and B are fully exposed in the header, with the exception of pins PA11 and PA12 that are routed to the USB connector. The remaining positions were filled pith pins from port C. The omitted ``ID \IIC'' port on pins 27 and 28 is used by the RPi Zero to read configuration from an EEPROM chip on some add-on boards. As this is the only use of the \IIC port, its lack is not a big limitation. \gls{GPIO} ports A and B are fully exposed in the header, with the exception of pins PA11 and PA12 that are routed to the USB connector. The remaining positions were filled pith pins from port C. The omitted ``ID \IIC'' port on pins 27 and 28 is used by the RPi Zero to read configuration from an EEPROM chip on some add-on boards. As this is the only use of the \IIC port, its lack is not a big limitation.
@ -319,10 +319,11 @@ Unfortunately, neither the GEX Zero \gls{PCB} was flawless in the first revision
\section{Wireless Gateway} \label{sec:rfgateway} \section{Wireless Gateway} \label{sec:rfgateway}
The wireless gateway was designed as a ``\gls{USB} dongle'', using the USB-A connector (\cref{fig:gwxgw}). It is fitted with a STM32F103 microcontroller, selected for its low cost and availability in small packages (in this case LQFP48). The nRF24L01+ module is partly sticking outside the board outline, allowing the \gls{PCB} to be smaller (and thus cheaper to manufacture), while reducing interference between components and copper plating on the board and the antenna. The wireless gateway was designed as a ``\gls{USB} dongle'', using the \gls{USB} type A connector (\cref{fig:gwxgw}). It is fitted with a STM32F103 microcontroller, selected for its low cost and availability in small packages (in this case LQFP48). The nRF24L01+ module is partly sticking outside the board outline, allowing the \gls{PCB} to be smaller (and thus cheaper to manufacture), while reducing interference between components and copper plating on the board and the antenna. The schematic diagram of the wireless gateway is attached in \hyperref[apx:gex_wgw]{Appendix C}.
Beyond the use with GEX, the gateway is a versatile tool which could be programmed with a different firmware and serve other purposes, e.g., as a wireless connection between two computers, to scan the radio spectrum for interference in order to find a clear channel, or to communicate with other devices that use the nRF24L01+ transceiver. The chosen microcontroller, unfortunately, does not include a USB bootloader, so a SWD programmer is required to change the firmware; SWD is routed to the pin header next to the wireless module. Beyond the use with GEX, the gateway is a versatile tool which could be programmed with a different firmware and serve other purposes, e.g., as a wireless connection between two computers, to scan the radio spectrum for interference in order to find a clear channel, or to communicate with other devices that use the nRF24L01+ transceiver. The chosen microcontroller, unfortunately, does not include a USB bootloader, so a SWD programmer is required to change the firmware; SWD is routed to the pin header next to the wireless module.
\begin{figure}[h] \begin{figure}[h]
\centering \centering
\includegraphics[width=.9\textwidth]{img/photo-rfdongle.jpg} \includegraphics[width=.9\textwidth]{img/photo-rfdongle.jpg}

13
document_config.tex
Unescape View File

@ -94,3 +94,16 @@
\input{pre.gex_command_tables} \input{pre.gex_command_tables}
% custom style for the appendix
\fancyfoot[LE,RO]{\thepage} % Left side on Even pages; Right side on Odd pages
\fancypagestyle{appendix}{%
\fancyfootoffset[lef,rof]{60pt}
\fancyfootoffset[leh,roh]{60pt}
\renewcommand{\headrulewidth}{0pt}%
\fancyhf{}%
\fancyhf[leh,roh]{\vspace{.9cm}\leftmark}%
\fancyhf[lef,rof]{\thepage}%
}

BIN
schema/GexHubSchemRev1.pdf
View File

Binary file not shown.

BIN
schema/GexHubSchemRev2.pdf
View File

Binary file not shown.

BIN
schema/GexRadioSchemRev1.pdf
View File

Binary file not shown.

BIN
schema/GexZeroSchemRev1.pdf
View File

Binary file not shown.

BIN
schema/GexZeroSchemRev2.pdf
View File

Binary file not shown.

50
thesis.appendices.tex
Unescape View File

@ -0,0 +1,50 @@
\appendix % začátek příloh
% hacks to remove the header and move page numbers into the margin
\pagestyle{appendix}
\newgeometry{textheight=760pt}
% ok so this is ugly as sin, but \leftmark and \rightmark didn't work with
% the phantom sections, so we redefine leftmark manually and use it on both sides
\renewcommand{\leftmark}{Appendix A: GEX Hub Schematics, Revision 1}
\includepdf[angle=90,pagecommand={%
\phantomsection\addcontentsline{toc}{chapter}{A{\enspace}GEX Hub Schematics}%
\label{apx:gex_hub}%
\phantomsection\addcontentsline{toc}{section}{A.1 GEX Hub Revision 1}%
\label{apx:gex_hub1}%
}]{schema/GexHubSchemRev1.pdf}
\renewcommand{\leftmark}{Appendix A: GEX Hub Schematics, Revision 2}
\includepdf[angle=90,pagecommand={%
\phantomsection\addcontentsline{toc}{section}{A.2 GEX Hub Revision 2}%
\label{apx:gex_hub2}%
}]{schema/GexHubSchemRev2.pdf}
\renewcommand{\leftmark}{Appendix B: GEX Zero Schematics, Revision 1}
\includepdf[angle=90,pagecommand={%
\phantomsection\addcontentsline{toc}{chapter}{B{\enspace}GEX Zero Schematics}%
\label{apx:gex_zero}%
\phantomsection\addcontentsline{toc}{section}{B.1 GEX Zero Revision 1}%
\label{apx:gex_zero1}%
}]{schema/GexZeroSchemRev1.pdf}
\renewcommand{\leftmark}{Appendix B: GEX Zero Schematics, Revision 2}
\includepdf[angle=90,pagecommand={%
\phantomsection\addcontentsline{toc}{section}{B.2 GEX Zero Revision 2}%
\label{apx:gex_zero2}%
}]{schema/GexZeroSchemRev2.pdf}
\renewcommand{\leftmark}{Appendix C: Wireless Gateway Schematics, Revision 1}
\includepdf[angle=90,pagecommand={%
\phantomsection\addcontentsline{toc}{chapter}{C{\enspace}Wireless Gateway Schematics}%
\label{apx:gex_wgw}%
\phantomsection\addcontentsline{toc}{section}{C.1 Wireless Gateway Revision 1}%
\label{apx:gex_wgw1}%
}]{schema/GexRadioSchemRev1.pdf}
% ... appendices

2
thesis.bib
Unescape View File

@ -389,7 +389,7 @@
@online{eev-gpio-pu, @online{eev-gpio-pu,
author = {{EEVblog Electronics Community Forum}}, author = {{EEVblog Electronics Community Forum}},
title = {pid.codes, a registry of USB PID codes for open source hardware projects}, title = {Driving the 1K5 USB pull-up resistor on D+},
url = {https://www.eevblog.com/forum/projects/driving-the-1k5-usb-pull-up-resistor-on-d/}, url = {https://www.eevblog.com/forum/projects/driving-the-1k5-usb-pull-up-resistor-on-d/},
urldate = {2018-05-12} urldate = {2018-05-12}
} }

BIN
thesis.pdf
View File

Binary file not shown.

9
thesis.tex
Unescape View File

@ -49,14 +49,7 @@
\input{ch.conclusion} \input{ch.conclusion}
\printbibliography \printbibliography
\appendix % začátek příloh
% seznam bibliografie \input{thesis.appendices}
\newpage
\todo[inline]{Schematics here ....}
% ... appendices
\end{document} \end{document}

Write Preview
Loading…
Cancel
Save