10 Commits
Author SHA1 Message Date
MightyPork 6fbd48c718 submodule sync 2018-04-23 16:11:57 +02:00
MightyPork ad0bb1cb86 update the submodule ref 2018-04-19 21:36:59 +02:00
MightyPork abec5a3c76 update submodule ref to 0.2.0 2018-04-01 20:26:45 +02:00
MightyPork 9c4c65cfe0 updated submodule ref 2018-03-18 22:34:21 +01:00
MightyPork 7d505a3a40 bump user 2018-03-18 21:03:29 +01:00
MightyPork 9954995fa3 fixes for oscillator fallback 2018-03-15 23:23:11 +01:00
MightyPork 0657a11e48 bump 2018-03-11 00:05:17 +01:00
MightyPork 374e5a2df9 compat with f072hub 2018-03-07 22:04:40 +01:00
MightyPork 4f34d43b3a Fix a bug in multi-part PCD transmit 2018-03-05 10:20:52 +01:00
MightyPork b76f9f66b3 fixes .. 2018-03-04 22:05:08 +01:00
8 changed files with 80 additions and 104 deletions
+1
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@@ -84,3 +84,4 @@ cmake-build-*
/main.flash.map /main.flash.map
/disassembly.lst /disassembly.lst
/main.ram.map /main.ram.map
build/*
+1 -1
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@@ -1,3 +1,3 @@
[submodule "User"] [submodule "User"]
path = User path = User
url = git@github.com:MightyPork/gex-core url = git@github.com:gexpander/gex-core
+1 -1
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@@ -18,7 +18,7 @@ add_definitions(
-DVERBOSE_HARDFAULT=1 -DVERBOSE_HARDFAULT=1
-DUSE_STACK_MONITOR=1 -DUSE_STACK_MONITOR=1
-DUSE_DEBUG_UART=1 -DUSE_DEBUG_UART=1
-DGEX_PLAT_F072_DISCOVERY -DGEX_PLAT_F072_HUB
-DHAL_TSC_MODULE_ENABLED -DHAL_TSC_MODULE_ENABLED
) )
@@ -70,24 +70,12 @@
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include <utils/hexdump.h>
#include "stm32f0xx_hal.h" #include "stm32f0xx_hal.h"
#include "stdbool.h"
/** @addtogroup STM32F0xx_HAL_Driver /** @addtogroup STM32F0xx_HAL_Driver
* @{ * @{
*/ */
static inline void dbgShowTog(PCD_HandleTypeDef *hpcd, bool strobe)
{
PCD_EPTypeDef *ep = &hpcd->IN_ep[2];
uint32_t v = (GPIOB->ODR & ~0b111);
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX) v |= 1;
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX) v |= 2;
GPIOB->ODR = v;
}
#ifdef HAL_PCD_MODULE_ENABLED #ifdef HAL_PCD_MODULE_ENABLED
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6) #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
@@ -750,16 +738,12 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
/* Clear the data toggle bits for the endpoint IN/OUT*/ /* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num) PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num) PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
PCD_RX_DTOG(hpcd->Instance, ep->num); PCD_RX_DTOG(hpcd->Instance, ep->num);
/* Configure DISABLE status for the Endpoint*/ /* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS) PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
} }
} }
dbgShowTog(hpcd, false);
__HAL_UNLOCK(hpcd); __HAL_UNLOCK(hpcd);
return ret; return ret;
@@ -919,12 +903,12 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
ep->xfer_count = 0U; ep->xfer_count = 0U;
ep->is_in = 1U; ep->is_in = 1U;
ep->num = ep_addr & 0x7FU; ep->num = ep_addr & 0x7FU;
/*Multi packet transfer*/ /*Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket) if (ep->xfer_len > ep->maxpacket)
{ {
len=ep->maxpacket; len=ep->maxpacket;
ep->xfer_len-=len; ep->xfer_len-=len;
} }
else else
{ {
@@ -941,25 +925,23 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
else else
{ {
/*Write the data to the USB endpoint*/ /*Write the data to the USB endpoint*/
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX) if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
{ {
/*Set the Double buffer counter for pmabuffer0*/ /*Set the Double buffer counter for pmabuffer1*/
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len) PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len)
pmabuffer = ep->pmaaddr0; pmabuffer = ep->pmaaddr1;
} }
else else
{ {
/*Set the Double buffer counter for pmabuffer1*/ /*Set the Double buffer counter for pmabuffer0*/
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len) PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len)
pmabuffer = ep->pmaaddr1; pmabuffer = ep->pmaaddr0;
} }
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, (uint16_t) len); PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in) PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in)
} }
dbgShowTog(hpcd, false);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID) PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
return HAL_OK; return HAL_OK;
@@ -1139,6 +1121,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
* @} * @}
*/ */
#pragma GCC push_options //GEX addition
#pragma GCC optimize ("O2")
/** @addtogroup PCD_Private_Functions /** @addtogroup PCD_Private_Functions
* @{ * @{
*/ */
@@ -1197,6 +1181,7 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui
*pbUsrBuf++ = ((temp >> 0) & 0xFF); *pbUsrBuf++ = ((temp >> 0) & 0xFF);
} }
} }
#pragma GCC pop_options //GEX addition
/** /**
* @brief This function handles PCD Endpoint interrupt request. * @brief This function handles PCD Endpoint interrupt request.
@@ -1210,14 +1195,10 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
uint8_t EPindex; uint8_t EPindex;
__IO uint16_t wIstr; __IO uint16_t wIstr;
__IO uint16_t wEPVal = 0U; __IO uint16_t wEPVal = 0U;
GPIOB->ODR |= 4;
for(volatile i=0;i<20;i++);
GPIOB->ODR &= ~4;
/* stay in loop while pending interrupts */ /* stay in loop while pending interrupts */
while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U) while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U)
{ {
/* extract highest priority endpoint number */ /* extract highest priority endpoint number */
EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
@@ -1357,19 +1338,15 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
/* clear int flag */ /* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex); PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
// This function is full of strange code that causes the double buffered mode to not work /* IN double Buffering*/
#define WANT_HAL_BUGS 0
#if WANT_HAL_BUGS
/* IN double Buffering*/
if (ep->doublebuffer == 0U) if (ep->doublebuffer == 0U)
{ {
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
if (ep->xfer_count != 0) // if (ep->xfer_count != 0)
{ // {
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); // PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); // GEX FIX
} // }
} }
else else
{ {
@@ -1391,50 +1368,13 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
} }
} }
PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN) PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN)
} }
/*multi-packet on the NON control IN endpoint*/ /*multi-packet on the NON control IN endpoint*/
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); // ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); // GEX FIX
#else
uint8_t tmpbuf[64];
/* IN double Buffering*/
if (ep->doublebuffer == 0U)
{
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
}
else
{
// NOTE: DTOG is inverted by the device at the end of a transaction
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
{
/*read from endpoint BUF0Addr buffer*/
ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
// PCD_ReadPMA(hpcd->Instance, tmpbuf, ep->pmaaddr0, ep->xfer_count);
// hexDump("buf0", tmpbuf, ep->xfer_count);
}
else
{
/*read from endpoint BUF1Addr buffer*/
ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
// PCD_ReadPMA(hpcd->Instance, tmpbuf, ep->pmaaddr1, ep->xfer_count);
// hexDump("buf1", tmpbuf, ep->xfer_count);
}
}
#endif
// dbg("ISR: ep %02x Xferd %db, remain %d", ep->num, ep->xfer_count, ep->xfer_len);
ep->xfer_buff+=ep->xfer_count; ep->xfer_buff+=ep->xfer_count;
/* Zero Length Packet? */
if(ep->num==2) dbgShowTog(hpcd, true);
/* Zero Length Packet? <- what? */
if (ep->xfer_len == 0U) if (ep->xfer_len == 0U)
{ {
/* TX COMPLETE */ /* TX COMPLETE */
@@ -1442,7 +1382,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
} }
else else
{ {
trap("multipart!");
HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
} }
} }
+1 -1
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@@ -43,7 +43,7 @@
#include "main.h" #include "main.h"
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
#define USBD_NUM_ENDPOINTS 4 #define USBD_NUM_ENDPOINTS 3
/* ########################## Module Selection ############################## */ /* ########################## Module Selection ############################## */
/** /**
+10 -1
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@@ -15,7 +15,8 @@ DISABLE_MSC := 0
CDC_LOOPBACK_TEST := 0 CDC_LOOPBACK_TEST := 0
include User/gex.mk include User/gex.mk
GEX_PLAT=F072_DISCOVERY GEX_PLAT=F072_HUB
#GEX_PLAT=F072_DISCOVERY
###################################### ######################################
# target # target
@@ -242,6 +243,14 @@ flash: $(BUILD_DIR)/$(TARGET).bin
@printf " FLASH $<\n" @printf " FLASH $<\n"
@st-flash write $< 0x8000000 @st-flash write $< 0x8000000
$(BUILD_DIR)/$(TARGET).dfu: $(BUILD_DIR)/$(TARGET).hex
@printf " DFU-GEN $<\n"
dfu-convert -i $< $@
dfu: $(BUILD_DIR)/$(TARGET).dfu
@printf " DFU UPLOAD $<\n"
dfu-util -a 0 -D $<
patch: patch:
@./cubepatch.sh @./cubepatch.sh
+40 -13
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@@ -47,10 +47,10 @@
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include <stm32f0xx_ll_gpio.h>
#include "main.h" #include "main.h"
#include "stm32f0xx_hal.h" #include "stm32f0xx_hal.h"
#include "cmsis_os.h" #include "cmsis_os.h"
#include <stdbool.h>
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
#include "gex_hooks.h" #include "gex_hooks.h"
@@ -150,23 +150,50 @@ void SystemClock_Config(void)
_Error_Handler(__FILE__, __LINE__); _Error_Handler(__FILE__, __LINE__);
} }
#else #else
volatile uint32_t counter;
/* Set FLASH latency */ /* Set FLASH latency */
LL_FLASH_SetLatency(LL_FLASH_LATENCY_1); LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
#if !PLAT_FULL_XTAL
LL_RCC_HSE_EnableBypass(); LL_RCC_HSE_EnableBypass();
#endif
LL_RCC_HSE_Enable(); LL_RCC_HSE_Enable();
while(LL_RCC_HSE_IsReady() != 1) {} counter = 0;
while(LL_RCC_HSE_IsReady() != 1 && counter < 10000) {
counter++;
}
/* Main PLL configuration and activation */ bool has_pll = 0;
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLL_MUL_6, LL_RCC_PREDIV_DIV_1); if (LL_RCC_HSE_IsReady() == 0) {
LL_RCC_PLL_Enable(); // Looks like HSE xtal doesn't work - use HSI48
while(LL_RCC_PLL_IsReady() != 1) {} LL_RCC_HSI48_Enable();
while(LL_RCC_HSI48_IsReady() != 1) {}
/* Sysclk activation on the main PLL */ LL_CRS_EnableAutoTrimming(); // crystalless USB
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {} LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI48);
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI48) {}
} else {
// external 8 MHz xtal
/* Main PLL configuration and activation */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLL_MUL_6, LL_RCC_PREDIV_DIV_1);
LL_RCC_PLL_Enable();
while(LL_RCC_PLL_IsReady() != 1) {}
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}
has_pll = true;
}
/* Set APB1 prescaler */ /* Set APB1 prescaler */
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
@@ -175,12 +202,12 @@ void SystemClock_Config(void)
LL_SetSystemCoreClock(48000000); LL_SetSystemCoreClock(48000000);
#endif #endif
// TODO this can be rewritten using LL while greatly reducing code size
/**Initializes the CPU, AHB and APB busses clocks /**Initializes the CPU, AHB and APB busses clocks
*/ */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1;
|RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = has_pll ? RCC_SYSCLKSOURCE_PLLCLK : RCC_SYSCLKSOURCE_HSI48;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+1 -1
Submodule User updated: c4efa5ddaa...30d1762710