compat with f072hub

.gitignore

@@ -84,3 +84,4 @@ cmake-build-*
 /main.flash.map
 /disassembly.lst
 /main.ram.map
+build/*

CMakeLists.txt

@@ -18,7 +18,7 @@ add_definitions(
         -DVERBOSE_HARDFAULT=1
         -DUSE_STACK_MONITOR=1
         -DUSE_DEBUG_UART=1
-        -DGEX_PLAT_F072_DISCOVERY
+        -DGEX_PLAT_F072_HUB
         -DHAL_TSC_MODULE_ENABLED
 )
 

Makefile

@@ -15,6 +15,7 @@ DISABLE_MSC   := 0
 CDC_LOOPBACK_TEST := 0
 
 include User/gex.mk
+#GEX_PLAT=F072_HUB
 GEX_PLAT=F072_DISCOVERY
 
 ######################################
@@ -242,6 +243,14 @@ flash: $(BUILD_DIR)/$(TARGET).bin
 	@printf "  FLASH  $<\n"
 	@st-flash write $< 0x8000000
 
+$(BUILD_DIR)/$(TARGET).dfu: $(BUILD_DIR)/$(TARGET).hex
+	@printf "  DFU-GEN  $<\n"
+	dfu-convert -i $< $@
+
+dfu: $(BUILD_DIR)/$(TARGET).dfu
+	@printf "  DFU UPLOAD  $<\n"
+	dfu-util -a 0 -D $<
+
 patch:
 	@./cubepatch.sh
 

Src/main.c

@@ -47,7 +47,6 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include <stm32f0xx_ll_gpio.h>
 #include "main.h"
 #include "stm32f0xx_hal.h"
 #include "cmsis_os.h"
@@ -150,23 +149,46 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 #else
+  volatile uint32_t counter;
+
   /* Set FLASH latency */
   LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
 
+#if !PLAT_FULL_XTAL
   LL_RCC_HSE_EnableBypass();
+#endif
+
   LL_RCC_HSE_Enable();
-  while(LL_RCC_HSE_IsReady() != 1) {}
+  counter = 0;
+  while(LL_RCC_HSE_IsReady() != 1 && counter < 10000) {
+    counter++;
+  }
+
+  if (LL_RCC_HSE_IsReady() == 0) {
+    // Looks like HSE xtal doesn't work - use HSI48
+    LL_RCC_HSI48_Enable();
+    while(LL_RCC_HSI48_IsReady() != 1) {}
 
-  /* Main PLL configuration and activation */
-  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLL_MUL_6, LL_RCC_PREDIV_DIV_1);
+    LL_CRS_EnableAutoTrimming(); // crystalless USB
 
-  LL_RCC_PLL_Enable();
-  while(LL_RCC_PLL_IsReady() != 1) {}
+    LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI48);
+    while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}
 
-  /* Sysclk activation on the main PLL */
-  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
-  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
-  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}
+  } else {
+    // external 8 MHz xtal
+
+    /* Main PLL configuration and activation */
+    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLL_MUL_6, LL_RCC_PREDIV_DIV_1);
+
+    LL_RCC_PLL_Enable();
+    while(LL_RCC_PLL_IsReady() != 1) {}
+
+    /* Sysclk activation on the main PLL */
+    LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+    while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}
+  }
 
   /* Set APB1 prescaler */
   LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
@@ -175,11 +197,11 @@ void SystemClock_Config(void)
   LL_SetSystemCoreClock(48000000);
 #endif
 
+  // TODO this can be rewritten using LL while greatly reducing code size
 
     /**Initializes the CPU, AHB and APB busses clocks 
     */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-                              |RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;

User

@@ -1 +1 @@
-Subproject commit da330b4b73af17f12a45a614ee61ebfcd0559a72
+Subproject commit 274f2be6e072ee0ed109b6bb9c32ffca8c8ef7cb