11 Commits
32 changed files with 1201 additions and 459 deletions
+4 -3
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@@ -90,7 +90,8 @@
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
#include <stdint.h>
#include "main.h"
extern uint32_t SystemCoreClock;
#include "plat_compat.h"
extern uint32_t SystemCoreClock;
#endif
#define configUSE_PREEMPTION 1
@@ -110,11 +111,11 @@
#define configENABLE_BACKWARD_COMPATIBILITY 0
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY 4 // above normal
#define configTIMER_TASK_PRIORITY TSK_TIMERS_PRIO // above normal
#define configTIMER_TASK_STACK_DEPTH TSK_STACK_TIMERS //128
#define configTIMER_QUEUE_LENGTH 4
#define configTOTAL_HEAP_SIZE 4096
#define configTOTAL_HEAP_SIZE PLAT_HEAP_SIZE
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
+3 -5
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@@ -7,7 +7,6 @@
#include "platform.h"
#include "task_main.h"
#include "utils/hexdump.h"
#include "USB/usbd_cdc_if.h"
#include "TinyFrame.h"
@@ -20,13 +19,13 @@ void TF_WriteImpl(TinyFrame *tf, const uint8_t *buff, uint32_t len)
#define CHUNK 64 // same as TF_SENDBUF_LEN, so we should always have only one run of the loop
int32_t total = (int32_t) len;
while (total > 0) {
int32_t mxStatus = osSemaphoreWait(semVcomTxReadyHandle, 250);
const int32_t mxStatus = osSemaphoreWait(semVcomTxReadyHandle, 100);
if (mxStatus != osOK) {
TF_Error("Tx stalled");
return;
}
uint16_t chunksize = (uint16_t) MIN(total, CHUNK);
const uint16_t chunksize = (uint16_t) MIN(total, CHUNK);
assert_param(USBD_OK == CDC_Transmit_FS((uint8_t *) buff, chunksize));
buff += chunksize;
@@ -38,11 +37,10 @@ void TF_WriteImpl(TinyFrame *tf, const uint8_t *buff, uint32_t len)
bool TF_ClaimTx(TinyFrame *tf)
{
(void) tf;
assert_param(osThreadGetId() != tskMainHandle);
// assert_param(osThreadGetId() != tskMainHandle);
assert_param(!inIRQ());
assert_param(osOK == osMutexWait(mutTinyFrameTxHandle, 5000));
return true;
}
@@ -9,6 +9,7 @@
#include "usbd_msc.h"
#include "usbd_cdc.h"
#include "usbd_msc_cdc.h"
#include "USB/usb_device.h"
#define USBD_MSC_CDC_CONFIG_DESC_SIZ 98
/* USB Mass storage device Configuration Descriptor */
@@ -112,7 +113,7 @@ __ALIGN_BEGIN uint8_t USBD_MSC_CDC_CfgFSDesc[USBD_MSC_CDC_CONFIG_DESC_SIZ] __AL
0x03, /* bmAttributes: Interrupt */
LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: TODO: 2?*/
HIBYTE(CDC_CMD_PACKET_SIZE),
0x10, //0xFF, /* bInterval: TODO was 0x10?*/
0xFF, /* bInterval: TODO was 0x10?*/
/********** CDC Data Class Interface Descriptor ***********/
/*75*/ 0x09, /* bLength: Endpoint Descriptor size */
@@ -232,6 +233,13 @@ static uint8_t USBD_MSC_CDC_EP0_RxReady(struct _USBD_HandleTypeDef *pdev)
static uint8_t USBD_MSC_CDC_DataIn(struct _USBD_HandleTypeDef *pdev, uint8_t epnum)
{
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
// This is a notification about data been Tx'd - avoid the bounce via main thread.
if (epnum == (CDC_IN_EP&0x7)) {
USBD_CDC_DataIn(&hUsbDeviceFS, CDC_IN_EP);
return USBD_OK;
}
xTaskNotifyFromISR(tskMainHandle, USBEVT_FLAG_EPx_IN(epnum), eSetBits, &xHigherPriorityTaskWoken);
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
// if (epnum == MSC_EPIN_ADDR||epnum==MSC_EPOUT_ADDR) USBD_MSC_DataIn(pdev, epnum);
+7 -2
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@@ -306,11 +306,16 @@ uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
/* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */
void USBD_CDC_TransmitDone(USBD_HandleTypeDef *pdev)
{
assert_param(xTaskGetCurrentTaskHandle() == tskMainHandle);
// This is called from the ISR directly, unlike the other functions - that's because
// all this does is notify the TF write impl that the Tx EP is ready via a semaphore.
// Notify the semaphore that we're ready to transmit more
assert_param(semVcomTxReadyHandle != NULL);
xSemaphoreGive(semVcomTxReadyHandle);
assert_param(inIRQ());
portBASE_TYPE taskWoken = pdFALSE;
assert_param(xSemaphoreGiveFromISR(semVcomTxReadyHandle, &taskWoken) == pdTRUE);
portYIELD_FROM_ISR(taskWoken);
}
/* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */
+2 -1
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@@ -71,6 +71,7 @@ static void settings_bulkread_cb(BulkRead *bulk, uint32_t chunk, uint8_t *buffer
if (bulk->offset == 0) iw_begin();
IniWriter iw = iw_init((char *)buffer, bulk->offset, chunk);
iw.tag = 1;
settings_build_units_ini(&iw);
}
@@ -85,7 +86,7 @@ static TF_Result lst_ini_export(TinyFrame *tf, TF_Msg *msg)
assert_param(bulk != NULL);
bulk->frame_id = msg->frame_id;
bulk->len = iw_measure_total(settings_build_units_ini);
bulk->len = iw_measure_total(settings_build_units_ini, 1);
bulk->read = settings_bulkread_cb;
bulk->userdata = NULL;
+4 -2
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@@ -229,7 +229,6 @@ static void gex_file_preamble(IniWriter *iw, const char *filename)
iw_hdr_comment(iw, filename);
iw_hdr_comment(iw, "GEX v%s on %s", GEX_VERSION, GEX_PLATFORM);
iw_hdr_comment(iw, "built %s at %s", __DATE__, __TIME__);
iw_cmt_newline(iw);
}
/** Generate a config file header (write instructions) */
@@ -237,12 +236,15 @@ static void ini_preamble(IniWriter *iw, const char *filename)
{
gex_file_preamble(iw, filename);
if (iw->tag == 0) { // tag 1 is set when exporting via the API
iw_cmt_newline(iw);
iw_comment(iw, "Overwrite this file to change settings.");
#if PLAT_LOCK_BTN
iw_comment(iw, "Press the LOCK button to save them to Flash.");
#else
iw_comment(iw, "Close the LOCK jumper to save them to Flash.");
#endif
}
}
// --- UNITS.INI ---
@@ -284,7 +286,7 @@ extern void plat_print_system_pinout(IniWriter *iw);
void settings_build_pinout_txt(IniWriter *iw)
{
gex_file_preamble(iw, "PINOUT.TXT");
iw_cmt_newline(iw);
rsc_print_all_available(iw);
ureg_print_unit_resources(iw);
plat_print_system_pinout(iw);
+16 -9
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@@ -340,19 +340,26 @@ bool ureg_finalize_all_init(void)
} else {
pUnit->status = pUnit->driver->init(pUnit);
if (pUnit->status != E_SUCCESS) {
dbg("!!! error initing unit %s: %s", pUnit->name,
error_get_message(pUnit->status));
dbg("!!! error initing unit %s: %s", pUnit->name, error_get_message(pUnit->status));
}
// try to assign unique callsigns
// FIXME this is wrong, sometimes leads to duplicate CS
if (pUnit->callsign == 0) {
pUnit->callsign = callsign++;
// this is very inefficient but should be reliable
bool change = false;
do {
UlistEntry *xli = ulist_head;
while (xli != NULL) {
if (xli->unit.callsign != 0) {
if (xli->unit.callsign == callsign) {
change = true;
callsign++;
}
else {
if (pUnit->callsign >= callsign) {
callsign = (uint8_t) (pUnit->callsign + 1);
}
xli = xli->next;
}
} while (change && callsign < 255);
pUnit->callsign = callsign;
}
}
@@ -398,8 +405,9 @@ void ureg_build_ini(IniWriter *iw)
// Unit list
iw_section(iw, "UNITS");
iw_comment(iw, "Create units by adding their names next to a type (e.g. PIN=A,B),");
iw_comment(iw, "Create units by adding their names next to a type (e.g. DO=A,B),");
iw_comment(iw, "remove the same way. Reload to update the unit sections below.");
iw_cmt_newline(iw);
// This could certainly be done in some more efficient way ...
re = ureg_head;
@@ -412,7 +420,6 @@ void ureg_build_ini(IniWriter *iw)
const UnitDriver *const pDriver = re->driver;
iw_cmt_newline(iw);
iw_comment(iw, pDriver->description);
iw_string(iw, pDriver->name);
iw_string(iw, "=");
+2 -2
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@@ -178,11 +178,11 @@ void MX_FREERTOS_Init(void) {
/* Create the thread(s) */
/* definition and creation of tskMain */
osThreadStaticDef(tskMain, TaskMain, osPriorityHigh, 0, TSK_STACK_MAIN, mainTaskStack, &mainTaskControlBlock);
osThreadStaticDef(tskMain, TaskMain, TSK_MAIN_PRIO, 0, TSK_STACK_MAIN, mainTaskStack, &mainTaskControlBlock);
tskMainHandle = osThreadCreate(osThread(tskMain), NULL);
/* definition and creation of TaskMessaging */
osThreadStaticDef(tskMsg, TaskMsgJob, osPriorityNormal, 0, TSK_STACK_MSG, msgJobQueTaskStack, &msgJobQueTaskControlBlock);
osThreadStaticDef(tskMsg, TaskMsgJob, TSK_JOBS_PRIO, 0, TSK_STACK_MSG, msgJobQueTaskStack, &msgJobQueTaskControlBlock);
tskMsgJobHandle = osThreadCreate(osThread(tskMsg), NULL);
/* USER CODE BEGIN RTOS_THREADS */
+1
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@@ -14,6 +14,7 @@ GEX_SRC_DIR = \
User/units/i2c \
User/units/spi \
User/units/adc \
User/units/sipo \
User/TinyFrame \
User/CWPack \
User/tasks
+39 -24
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@@ -86,7 +86,7 @@ bool parse_port_name(const char *value, char *targetName)
}
/** Parse a list of pin numbers with ranges and commans/semicolons to a bitmask */
uint16_t parse_pinmask(const char *value, bool *suc)
uint32_t parse_pinmask(const char *value, bool *suc)
{
uint32_t bits = 0;
uint32_t acu = 0;
@@ -116,7 +116,10 @@ uint16_t parse_pinmask(const char *value, bool *suc)
rangestart = swp;
}
for(uint32_t i=rangestart; i<=acu; i++) {
if (rangestart > 31) rangestart = 31;
if (acu > 31) acu = 31;
for(uint32_t i=rangestart; i <= acu; i++) {
bits |= 1<<i;
}
@@ -133,13 +136,11 @@ uint16_t parse_pinmask(const char *value, bool *suc)
}
} while (c != 0);
if (bits > 0xFFFF) *suc = false;
return (uint16_t) bits;
return bits;
}
/** Convert a pin bitmask to the ASCII format understood by str_parse_pinmask() */
char * pinmask2str(uint16_t pins, char *buffer)
char * pinmask2str(uint32_t pins, char *buffer)
{
char *b = buffer;
uint32_t start = 0;
@@ -152,13 +153,13 @@ char * pinmask2str(uint16_t pins, char *buffer)
return buffer;
}
for (int32_t i = 15; i >= -1; i--) {
for (int32_t i = 31; i >= -1; i--) {
bool bit;
if (i == -1) {
bit = false;
} else {
bit = 0 != (pins & 0x8000);
bit = 0 != (pins & 0x80000000);
pins <<= 1;
}
@@ -189,7 +190,7 @@ char * pinmask2str(uint16_t pins, char *buffer)
return buffer;
}
char * pinmask2str_up(uint16_t pins, char *buffer)
char * pinmask2str_up(uint32_t pins, char *buffer)
{
char *b = buffer;
uint32_t start = 0;
@@ -202,10 +203,10 @@ char * pinmask2str_up(uint16_t pins, char *buffer)
return buffer;
}
for (int32_t i = 0; i <= 16; i++) {
for (int32_t i = 0; i <= 32; i++) {
bool bit;
if (i == 16) {
if (i == 32) {
bit = false;
} else {
bit = 0 != (pins & 1);
@@ -239,43 +240,56 @@ char * pinmask2str_up(uint16_t pins, char *buffer)
return buffer;
}
/** Spread packed port pins using a mask */
uint16_t pinmask_spread(uint16_t packed, uint16_t mask)
#pragma GCC push_options
#pragma GCC optimize ("O2")
/** spread a packed pinfield using a mask */
uint32_t pinmask_spread_32(uint32_t packed, uint32_t mask)
{
uint16_t result = 0;
uint16_t poke = 1;
for (int i = 0; i<16; i++) {
if (mask & (1<<i)) {
uint32_t result = 0;
uint32_t poke = 1;
if(packed == 0) return 0;
for (int i = 0; i < 32; i++) {
if (mask & 1) {
if (packed & poke) {
result |= 1<<i;
packed ^= poke;
if (packed == 0) break;
}
poke <<= 1;
}
mask >>= 1;
// if (mask == 0) break;
}
return result;
}
/** Pack spread port pins using a mask */
uint16_t pinmask_pack(uint16_t spread, uint16_t mask)
uint32_t pinmask_pack_32(uint32_t spread, uint32_t mask)
{
uint16_t result = 0;
uint16_t poke = 1;
for (int i = 0; i<16; i++) {
if (mask & (1<<i)) {
uint32_t result = 0;
uint32_t poke = 1;
for (int i = 0; i<32; i++) {
if (mask & 1) {
if (spread & (1<<i)) {
result |= poke;
spread ^= (1<<i);
if (spread == 0) break;
}
poke <<= 1;
}
mask >>= 1;
// if (mask == 0) break;
}
return result;
}
/** Convert spread port pin number to a packed index using a mask */
uint8_t pinmask_translate(uint16_t mask, uint8_t index)
uint8_t pinmask_translate(uint32_t mask, uint8_t index)
{
int cnt = 0;
for (int i = 0; i<16; i++) {
for (int i = 0; i<32; i++) {
if (mask & (1<<i)) {
if (i == index) return (uint8_t) cnt;
cnt++;
@@ -283,6 +297,7 @@ uint8_t pinmask_translate(uint16_t mask, uint8_t index)
}
return 0;
}
#pragma GCC pop_options
/** Configure unit pins as analog (part of unit teardown) */
void hw_deinit_unit_pins(Unit *unit)
+18 -6
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@@ -69,7 +69,7 @@ bool parse_port_name(const char *value, char *targetName);
* @param suc - set to False if parsing failed
* @return the resulting bitmap
*/
uint16_t parse_pinmask(const char *value, bool *suc);
uint32_t parse_pinmask(const char *value, bool *suc);
/**
* Convert a pin bitmap to the ASCII format understood by str_parse_pinmask()
@@ -79,7 +79,7 @@ uint16_t parse_pinmask(const char *value, bool *suc);
* @param buffer - output string buffer
* @return the output buffer
*/
char * pinmask2str(uint16_t pins, char *buffer);
char * pinmask2str(uint32_t pins, char *buffer);
/**
* Convert a pin bitmap to the ASCII format understood by str_parse_pinmask()
@@ -89,7 +89,7 @@ char * pinmask2str(uint16_t pins, char *buffer);
* @param buffer - output string buffer
* @return the output buffer
*/
char * pinmask2str_up(uint16_t pins, char *buffer);
char * pinmask2str_up(uint32_t pins, char *buffer);
/**
* Spread packed port pins using a mask
@@ -98,7 +98,13 @@ char * pinmask2str_up(uint16_t pins, char *buffer);
* @param mask - positions of the bits (eg. 0x8803)
* @return - bits spread to their positions (always counting from right)
*/
uint16_t pinmask_spread(uint16_t packed, uint16_t mask);
uint32_t pinmask_spread_32(uint32_t packed, uint32_t mask);
/** Spread packed port pins using a mask - 16-bit version */
static inline uint16_t pinmask_spread(uint16_t packed, uint16_t mask)
{
return (uint16_t) pinmask_spread_32(packed, mask);
}
/**
* Pack spread port pins using a mask
@@ -107,14 +113,20 @@ uint16_t pinmask_spread(uint16_t packed, uint16_t mask);
* @param mask - mask of the bits we want to pack (eg. 0x8803)
* @return - packed bits, right aligned (eg. 0b1110)
*/
uint16_t pinmask_pack(uint16_t spread, uint16_t mask);
uint32_t pinmask_pack_32(uint32_t spread, uint32_t mask);
/** Pack spread port pins using a mask - 16-bit version */
static inline uint16_t pinmask_pack(uint32_t spread, uint32_t mask)
{
return (uint16_t) pinmask_pack_32(spread, mask);
}
/**
* Convert spread port pin number to a packed index using a mask
*
* eg. with a mask 0b1010 and index 3, the result is 1 (bit 1 of the packed - 0bX0)
*/
uint8_t pinmask_translate(uint16_t mask, uint8_t index);
uint8_t pinmask_translate(uint32_t mask, uint8_t index);
/**
* Set all GPIO resources held by unit to analog.
+9 -2
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@@ -7,6 +7,11 @@
#define VFS_DRIVE_NAME "GEX"
// -------- Priorities -------------
#define TSK_MAIN_PRIO osPriorityNormal
#define TSK_JOBS_PRIO osPriorityHigh
#define TSK_TIMERS_PRIO 4 // this must be in the 0-7 range
// -------- Static buffers ---------
// USB / VFS task stack size
#if DISABLE_MSC
@@ -17,10 +22,12 @@
// 180 is normally enough if not doing extensive debug logging
#define TSK_STACK_MSG 200 // TF message handler task stack size (all unit commands run on this thread)
#define TSK_STACK_IDLE 64 //configMINIMAL_STACK_SIZE
#define TSK_STACK_TIMERS 64 //configTIMER_TASK_STACK_DEPTH
#define PLAT_HEAP_SIZE 4096
#define BULK_READ_BUF_LEN 256 // Buffer for TF bulk reads
#define UNIT_TMP_LEN 512 // Buffer for internal unit operations
@@ -28,7 +35,7 @@
#define FLASH_SAVE_BUF_LEN 128 // Malloc'd buffer for saving to flash
#define MSG_QUE_SLOT_SIZE 64 // FIXME this should be possible to lower, but there's some bug with bulk transfer / INI parser
#define RX_QUE_CAPACITY 36 // TinyFrame rx queue size (64 bytes each)
#define RX_QUE_CAPACITY 16 // TinyFrame rx queue size (64 bytes each)
#define TF_MAX_PAYLOAD_RX 512 // TF max Rx payload
#define TF_SENDBUF_LEN 64 // TF transmit buffer (can be less than a full frame)
+2
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@@ -17,6 +17,7 @@
#include "units/test/unit_test.h"
#include "units/usart/unit_usart.h"
#include "units/spi/unit_spi.h"
#include "units/sipo/unit_sipo.h"
#include "hw_utils.h"
void plat_init_resources(void)
@@ -86,6 +87,7 @@ void plat_init_resources(void)
ureg_add_type(&UNIT_USART);
ureg_add_type(&UNIT_1WIRE);
ureg_add_type(&UNIT_ADC);
ureg_add_type(&UNIT_SIPO);
// Free all present resources
{
+3 -3
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@@ -81,9 +81,9 @@ void TaskMain(void const * argument)
#endif
// CDC - config packets and data in/out
if (msg & (USBEVT_FLAG_EPx_IN(CDC_IN_EP))) {
USBD_CDC_DataIn(&hUsbDeviceFS, CDC_IN_EP);
}
// if (msg & (USBEVT_FLAG_EPx_IN(CDC_IN_EP))) {
// USBD_CDC_DataIn(&hUsbDeviceFS, CDC_IN_EP);
// }
if (msg & (USBEVT_FLAG_EPx_IN(CDC_CMD_EP))) {
USBD_CDC_DataIn(&hUsbDeviceFS, CDC_CMD_EP);
}
+2 -6
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@@ -11,13 +11,12 @@ volatile uint32_t msgQueHighWaterMark = 0;
static bool que_safe_post(struct rx_sched_combined_que_item *slot)
{
uint32_t count = 0;
assert_param(slot != NULL);
if (inIRQ()) {
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
BaseType_t status = xQueueSendFromISR(queMsgJobHandle, slot, &xHigherPriorityTaskWoken);
if (pdPASS != status) {
dbg("! Que post from ISR failed");
dbg("(!) Que post from ISR failed");
return false;
}
@@ -29,7 +28,7 @@ static bool que_safe_post(struct rx_sched_combined_que_item *slot)
} else {
BaseType_t status = xQueueSend(queMsgJobHandle, slot, MSG_QUE_POST_TIMEOUT);
if (pdPASS != status) {
dbg("! Que post failed");
dbg("(!) Que post failed");
return false;
}
@@ -80,12 +79,9 @@ void TaskMsgJob(const void *argument)
xQueueReceive(queMsgJobHandle, &slot, osWaitForever);
if (slot.is_job) {
assert_param(slot.job.cb != NULL);
slot.job.cb(&slot.job);
}
else {
assert_param(slot.msg.len > 0 && slot.msg.len <= MSG_QUE_SLOT_SIZE); // check the len is within bounds
#if CDC_LOOPBACK_TEST
TF_WriteImpl(comm, slot.msg.data, slot.msg.len);
#else
-29
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@@ -1,29 +0,0 @@
//
// Created by MightyPork on 2018/02/03.
//
#include "platform.h"
#include "unit_base.h"
#include "unit_adc.h"
#define ADC_INTERNAL
#include "_adc_internal.h"
error_t UU_ADC_AbortCapture(Unit *unit)
{
CHECK_TYPE(unit, &UNIT_ADC);
struct priv *priv = unit->data;
enum uadc_opmode old_opmode = priv->opmode;
priv->auto_rearm = false;
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
if (old_opmode == ADC_OPMODE_BLCAP ||
old_opmode == ADC_OPMODE_STREAM ||
old_opmode == ADC_OPMODE_TRIGD) {
UADC_ReportEndOfStream(unit);
}
return E_SUCCESS;
}
+231 -146
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@@ -1,6 +1,8 @@
//
// Created by MightyPork on 2018/02/04.
//
// The core functionality of the ADC unit is defined here.
//
#include "platform.h"
#include "unit_base.h"
@@ -9,65 +11,83 @@
#define ADC_INTERNAL
#include "_adc_internal.h"
#define DMA_POS(priv) ((priv)->dma_buffer_itemcount - (priv)->DMA_CHx->CNDTR)
volatile bool emergency = false;
//#define CRUMB() if(emergency) trap("crumb")
#define DMA_POS(priv) ((priv)->buf_itemcount - (priv)->DMA_CHx->CNDTR)
/**
* Async job to send a chunk of the DMA buffer to PC.
* This can't be done directly because the interrupt couldn't wait for the TinyFrame mutex.
*
* unit - unit
* data1 - start index
* data2 - number of samples to send
* data3 - bit flags: 0x80 if this is the last sample and we should close
* 0x01 if this was the TC interrupt (otherwise it's HT)
*/
static void UADC_JobSendBlockChunk(Job *job)
{
Unit *unit = job->unit;
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
uint32_t start = job->data1;
uint32_t count = job->data2;
bool close = (bool) job->data3;
const uint32_t start = job->data1;
const uint32_t count = job->data2;
const bool close = (bool) (job->data3 & 0x80);
const bool tc = (bool) (job->data3 & 0x01);
// dbg("Send indices [%d -> %d)", (int)start, (int)(start+count));
TF_TYPE type = close ? EVT_CAPT_DONE : EVT_CAPT_MORE;
const TF_TYPE type = close ? EVT_CAPT_DONE : EVT_CAPT_MORE;
TF_Msg msg = {
.frame_id = priv->stream_frame_id,
.len = (TF_LEN) (1 + count*sizeof(uint16_t)),
.len = (TF_LEN) (1 /*seq*/ + count * sizeof(uint16_t)),
.type = type,
};
TF_Respond_Multipart(comm, &msg);
TF_Multipart_Payload(comm, &priv->stream_serial, 1);
TF_Multipart_Payload(comm, (uint8_t *) (priv->dma_buffer + start), count * sizeof(uint16_t));
TF_Multipart_Close(comm);
// Clear the "busy" flags - those are checked in the DMA ISR to detect overrun
if (tc) priv->tc_pending = false;
else priv->ht_pending = false;
priv->stream_serial++;
}
/**
* Async job to send the trigger header.
* The header includes info about the trigger + the pre-trigger buffer.
*
* data1 - index in the DMA buffer at which the captured data willl start
* data2 - edge type - 1 rise, 2 fall, 3 forced
* timestamp - event stamp
* unit - unit
*/
static void UADC_JobSendTriggerCaptureHeader(Job *job)
{
Unit *unit = job->unit;
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
EventReport er = {
.unit = unit,
.type = EVT_CAPT_START,
.timestamp = job->timestamp,
.length = (priv->pretrig_len+1)*priv->nb_channels*sizeof(uint16_t) + 2 /*pretrig len*/ + 1 /*edge*/ + 1 /* seq */
.length = (priv->pretrig_len + 1) * // see below why +1
priv->nb_channels *
sizeof(uint16_t) +
4 /*pretrig len*/ +
1 /*edge*/ +
1 /* seq */
};
uint16_t index_trigd = (uint16_t) job->data1;
uint32_t index_trigd = job->data1;
uint8_t edge = (uint8_t) job->data2;
EventReport_Start(&er);
priv->stream_frame_id = er.sent_msg_id;
// dbg("Sending TRIG HEADER with id %d (idx %d)", (int)er.sent_msg_id, (int)index_trigd);
{
// preamble
uint8_t buf[4];
PayloadBuilder pb = pb_start(buf, 4, NULL);
pb_u16(&pb, priv->pretrig_len);
pb_u32(&pb, priv->pretrig_len);
pb_u8(&pb, edge);
pb_u8(&pb, priv->stream_serial++); // This is the serial counter for the first chunk
// (containing the pre-trigger, or empty if no pretrig configured)
@@ -75,35 +95,25 @@ static void UADC_JobSendTriggerCaptureHeader(Job *job)
if (priv->pretrig_len > 0) {
// pretrig
uint16_t pretrig_remain = (uint16_t) ((priv->pretrig_len + 1) * priv->nb_channels); // +1 because we want pretrig 0 to exactly start with the triggering sample
assert_param(index_trigd <= priv->dma_buffer_itemcount);
// +1 because we want pretrig 0 to exactly start with the triggering sample
uint32_t pretrig_remain = (priv->pretrig_len + 1) * priv->nb_channels;
assert_param(index_trigd <= priv->buf_itemcount);
// this is one past the last entry of the triggering capture group
if (pretrig_remain > index_trigd) {
// used items in the wrap-around part of the buffer
uint16_t items_from_end = pretrig_remain - index_trigd;
assert_param(priv->dma_buffer_itemcount - items_from_end >= index_trigd);
uint32_t items_from_end = pretrig_remain - index_trigd;
assert_param(priv->buf_itemcount - items_from_end >= index_trigd);
// dbg("Pretrig wraparound part: start %d, len %d",
// (int) (priv->dma_buffer_itemcount - items_from_end),
// (int) items_from_end
// );
EventReport_Data(
(uint8_t *) &priv->dma_buffer[priv->dma_buffer_itemcount -
items_from_end],
EventReport_Data((uint8_t *) &priv->dma_buffer[priv->buf_itemcount - items_from_end],
items_from_end * sizeof(uint16_t));
assert_param(items_from_end <= pretrig_remain);
pretrig_remain -= items_from_end;
}
// dbg("Pretrig front part: start %d, len %d",
// (int) (index_trigd - pretrig_remain),
// (int) pretrig_remain
// );
assert_param(pretrig_remain <= index_trigd);
EventReport_Data((uint8_t *) &priv->dma_buffer[index_trigd - pretrig_remain],
pretrig_remain * sizeof(uint16_t));
@@ -112,13 +122,11 @@ static void UADC_JobSendTriggerCaptureHeader(Job *job)
EventReport_End();
}
/**
* Async job to notify about end of stream
*/
static void UADC_JobSendEndOfStreamMsg(Job *job)
{
Unit *unit = job->unit;
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
TF_Msg msg = {
.type = EVT_CAPT_DONE,
.frame_id = (TF_ID) job->data1
@@ -126,25 +134,36 @@ static void UADC_JobSendEndOfStreamMsg(Job *job)
TF_Respond(comm, &msg);
}
/**
* Schedule sending a event report to the PC that the current stream has ended.
* The client library should handle this appropriately.
*/
void UADC_ReportEndOfStream(Unit *unit)
{
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
Job j = {
.unit = unit,
.data1 = priv->stream_frame_id,
.data1 = priv->stream_frame_id, // copy the ID, it may be invalid by the time the cb gets executed
.cb = UADC_JobSendEndOfStreamMsg
};
scheduleJob(&j);
}
/**
* This is a helper function for the ADC DMA interrupt for handing the different interrupt types (half / full transfer).
* It sends the part of the buffer that was just captured via an async job, or aborts on overrun.
*
* It's split off here to allow calling it for the different flags without repeating code.
*
* @param unit
* @param tc - true if this is the TC interrupt, else HT
*/
static void handle_httc(Unit *unit, bool tc)
{
struct priv *priv = unit->data;
uint16_t start = priv->stream_startpos;
uint16_t end;
uint32_t start = priv->stream_startpos;
uint32_t end;
const bool ht = !tc;
const bool m_trigd = priv->opmode == ADC_OPMODE_TRIGD;
@@ -152,24 +171,18 @@ static void handle_httc(Unit *unit, bool tc)
const bool m_fixcpt = priv->opmode == ADC_OPMODE_BLCAP;
if (ht) {
// dbg("HT");
end = (uint16_t) (priv->dma_buffer_itemcount / 2);
LL_DMA_ClearFlag_HT(priv->DMAx, priv->dma_chnum);
end = (priv->buf_itemcount / 2);
}
else {
// dbg("TC");
end = (uint16_t) priv->dma_buffer_itemcount;
LL_DMA_ClearFlag_TC(priv->DMAx, priv->dma_chnum);
end = priv->buf_itemcount;
}
if (ht == tc) {
// This shouldn't happen - looks like we missed the TC flag
dbg("!! %d -> %d", (int) start, (int) end);
// TODO we could try to catch up. for now, just take what is easy to grab and hope it doesnt matter
if (end == 64) start = 0;
if (start != end) { // this sometimes happened after a trigger, may be unnecessary now
if (end < start) {
// this was a trap for a bug with missed TC irq, it's hopefully fixed now
trap("end < start! %d < %d, tc %d", (int)end, (int)start, (int)tc);
}
if (start != end) {
uint32_t sgcount = (end - start) / priv->nb_channels;
if (m_trigd || m_fixcpt) {
@@ -177,111 +190,143 @@ static void handle_httc(Unit *unit, bool tc)
priv->trig_stream_remain -= sgcount;
}
bool close = !m_stream && priv->trig_stream_remain == 0;
// Check for the closing condition
const bool close = !m_stream && priv->trig_stream_remain == 0;
if ((tc && priv->tc_pending) || (ht && priv->ht_pending)) {
dbg("(!) ADC DMA not handled in time, abort capture");
UADC_SwitchMode(unit, ADC_OPMODE_EMERGENCY_SHUTDOWN);
return;
}
// Here we set the tc/ht pending flags for detecting overrun
Job j = {
.unit = unit,
.data1 = start,
.data2 = sgcount * priv->nb_channels,
.data3 = (uint32_t) close,
.data3 = (uint32_t) (close*0x80) | (tc*1), // bitfields to indicate what's happening
.cb = UADC_JobSendBlockChunk
};
if (tc)
priv->tc_pending = true;
else
priv->ht_pending = true;
if (!scheduleJob(&j)) {
// Abort if we can't queue - the stream would tear and we'd hog the system with error messages
dbg("(!) Buffers overflow, abort capture");
emergency = true;
UADC_SwitchMode(unit, ADC_OPMODE_EMERGENCY_SHUTDOWN);
return;
}
if (close) {
// dbg("End of capture");
// If auto-arm enabled, we need to re-arm again.
// However, EOS irq is disabled during the capture.
// We have to wait for the next EOS interrupt to occur.
// TODO verify if keeping the EOS irq enabled during capture has significant performance penalty. If not, we can leave it enabled.
// If auto-arm is enabled, we need to re-arm again.
// However, EOS irq is disabled during the capture so the trigger edge detection would
// work on stale data from before this trigger. We have to wait for the next full
// conversion (EOS) before arming.
UADC_SwitchMode(unit, (priv->auto_rearm && m_trigd) ? ADC_OPMODE_REARM_PENDING : ADC_OPMODE_IDLE);
}
} else {
// dbg("start==end, skip this irq");
}
// Advance the starting position
if (tc) {
priv->stream_startpos = 0;
}
else {
priv->stream_startpos = end;
priv->stream_startpos = priv->buf_itemcount / 2;
}
}
/**
* IRQ handler for the DMA flags.
*
* We handle flags:
* TC - transfer complete
* HT - half transfer
* TE - transfer error (this should never happen unless there's a bug)
*
* The buffer works in a circular mode, so we always handle the previous half
* or what of it should be sent (if capture started somewhere inside).
*
* @param arg - the unit, passed via the irq dispatcher
*/
void UADC_DMA_Handler(void *arg)
{
Unit *unit = arg;
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
// First thing, grab the flags. They may change during the function.
// Working on the live register might cause race conditions.
const uint32_t isrsnapshot = priv->DMAx->ISR;
if (priv->opmode == ADC_OPMODE_UNINIT) {
// the IRQ occured while switching mode, clear flags and do nothing else
LL_DMA_ClearFlag_HT(priv->DMAx, priv->dma_chnum);
LL_DMA_ClearFlag_TC(priv->DMAx, priv->dma_chnum);
LL_DMA_ClearFlag_TE(priv->DMAx, priv->dma_chnum);
return;
}
const uint32_t isrsnapshot = priv->DMAx->ISR;
if (LL_DMA_IsActiveFlag_G(isrsnapshot, priv->dma_chnum)) {
// we have some flags set - check which
const bool tc = LL_DMA_IsActiveFlag_TC(isrsnapshot, priv->dma_chnum);
const bool ht = LL_DMA_IsActiveFlag_HT(isrsnapshot, priv->dma_chnum);
const bool te = LL_DMA_IsActiveFlag_TE(isrsnapshot, priv->dma_chnum);
if (ht) LL_DMA_ClearFlag_HT(priv->DMAx, priv->dma_chnum);
if (tc) LL_DMA_ClearFlag_TC(priv->DMAx, priv->dma_chnum);
if (te) {
// this shouldn't happen - error
adc_dbg("ADC DMA TE!");
LL_DMA_ClearFlag_TE(priv->DMAx, priv->dma_chnum);
return;
}
// check what mode we're in
const bool m_trigd = priv->opmode == ADC_OPMODE_TRIGD;
const bool m_stream = priv->opmode == ADC_OPMODE_STREAM;
const bool m_fixcpt = priv->opmode == ADC_OPMODE_BLCAP;
if (m_trigd || m_stream || m_fixcpt) {
if (ht || tc) {
const uint32_t half = (uint32_t) (priv->buf_itemcount / 2);
if (ht && tc) {
uint16_t half = (uint16_t) (priv->dma_buffer_itemcount / 2);
// dual event interrupt - may happen if we missed both and they were pending after
// interrupts became enabled again (this can happen due to the EOS or other higher prio irq's)
if (priv->stream_startpos > half) {
handle_httc(unit, true);
handle_httc(unit, false);
handle_httc(unit, true); // TC
handle_httc(unit, false); // HT
} else {
handle_httc(unit, false);
handle_httc(unit, true);
handle_httc(unit, false); // HT
handle_httc(unit, true); // TC
}
} else {
if (ht && priv->stream_startpos > half) {
// We missed the TC interrupt while e.g. setting up the stream / interrupt. catch up!
// This fixes a bug with "negative size" for report.
handle_httc(unit, true); // TC
}
handle_httc(unit, tc);
}
}
} else {
// This shouldn't happen, the interrupt should be disabled in this opmode
dbg("(!) not streaming, DMA IT should be disabled");
if (ht) {
LL_DMA_ClearFlag_HT(priv->DMAx, priv->dma_chnum);
}
else {
LL_DMA_ClearFlag_TC(priv->DMAx, priv->dma_chnum);
}
}
if (te) {
// this shouldn't happen - error
dbg("ADC DMA TE!");
LL_DMA_ClearFlag_TE(priv->DMAx, priv->dma_chnum);
dbg("(!) not streaming, ADC DMA IT should be disabled");
}
}
}
/**
* End of measurement group interrupt handler.
* This interrupt records the measured values and checks for trigger.
*
* @param arg - unit, passed b y irq dispatcher
*/
void UADC_ADC_EOS_Handler(void *arg)
{
Unit *unit = arg;
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
// Normally
uint64_t timestamp = 0;
@@ -291,12 +336,12 @@ void UADC_ADC_EOS_Handler(void *arg)
if (priv->opmode == ADC_OPMODE_UNINIT) return;
// Wait for the DMA to complete copying the last sample
uint16_t dmapos;
hw_wait_while((dmapos = (uint16_t) DMA_POS(priv)) % priv->nb_channels != 0, 100); // XXX this could be changed to reading it from the DR instead
uint32_t dmapos;
hw_wait_while((dmapos = DMA_POS(priv)) % priv->nb_channels != 0, 100); // XXX this could be changed to reading it from the DR instead
uint32_t sample_pos;
if (dmapos == 0) {
sample_pos = (uint32_t) (priv->dma_buffer_itemcount);
sample_pos = (uint32_t) (priv->buf_itemcount);
} else {
sample_pos = dmapos;
}
@@ -305,11 +350,11 @@ void UADC_ADC_EOS_Handler(void *arg)
int cnt = 0; // index of the sample within the group
const bool can_average = priv->real_frequency_int < UADC_MAX_FREQ_FOR_AVERAGING;
const uint32_t channels_mask = priv->extended_channels_mask;
const uint32_t channels_mask = priv->channels_mask;
for (uint8_t i = 0; i < 18; i++) {
if (channels_mask & (1 << i)) {
uint16_t val = priv->dma_buffer[sample_pos+cnt];
const uint16_t val = priv->dma_buffer[sample_pos+cnt];
cnt++;
if (can_average) {
@@ -323,18 +368,15 @@ void UADC_ADC_EOS_Handler(void *arg)
}
if (priv->opmode == ADC_OPMODE_ARMED) {
uint16_t val = priv->last_samples[priv->trigger_source];
const uint16_t val = priv->last_samples[priv->trigger_source];
// dbg("Trig line level %d", (int)val);
if ((priv->trig_prev_level < priv->trig_level) && val >= priv->trig_level && (bool) (priv->trig_edge & 0b01)) {
// dbg("******** Rising edge");
// Rising edge
UADC_HandleTrigger(unit, 1, timestamp);
UADC_HandleTrigger(unit, 0b01, timestamp);
}
else if ((priv->trig_prev_level > priv->trig_level) && val <= priv->trig_level && (bool) (priv->trig_edge & 0b10)) {
// dbg("******** Falling edge");
// Falling edge
UADC_HandleTrigger(unit, 2, timestamp);
UADC_HandleTrigger(unit, 0b10, timestamp);
}
priv->trig_prev_level = val;
}
@@ -352,15 +394,20 @@ void UADC_ADC_EOS_Handler(void *arg)
}
}
/**
* Handle a detected trigger - start capture if we're not in hold-off
*
* @param unit
* @param edge_type - edge type, is included in the report
* @param timestamp - event time
*/
void UADC_HandleTrigger(Unit *unit, uint8_t edge_type, uint64_t timestamp)
{
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
if (priv->opmode == ADC_OPMODE_UNINIT) return;
if (priv->trig_holdoff != 0 && priv->trig_holdoff_remain > 0) {
// dbg("Trig discarded due to holdoff.");
// Trig discarded due to holdoff
return;
}
@@ -371,12 +418,11 @@ void UADC_HandleTrigger(Unit *unit, uint8_t edge_type, uint64_t timestamp)
unit->_tick_cnt = 1;
}
priv->stream_startpos = (uint16_t) DMA_POS(priv);
priv->stream_startpos = DMA_POS(priv);
priv->trig_stream_remain = priv->trig_len;
priv->stream_serial = 0;
// dbg("Trigger condition hit, edge=%d, startpos %d", edge_type, (int)priv->stream_startpos);
// This func may be called from the EOS interrupt, so it's safer to send the header message asynchronously
Job j = {
.unit = unit,
.timestamp = timestamp,
@@ -389,59 +435,86 @@ void UADC_HandleTrigger(Unit *unit, uint8_t edge_type, uint64_t timestamp)
UADC_SwitchMode(unit, ADC_OPMODE_TRIGD);
}
/**
* Abort ongoing capture.
*/
void UADC_AbortCapture(Unit *unit)
{
struct priv *priv = unit->data;
const enum uadc_opmode old_opmode = priv->opmode;
priv->auto_rearm = false;
if (old_opmode == ADC_OPMODE_BLCAP ||
old_opmode == ADC_OPMODE_STREAM ||
old_opmode == ADC_OPMODE_TRIGD) {
UADC_ReportEndOfStream(unit);
}
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
}
/**
* Start a manual block capture.
*
* @param unit
* @param len - number of samples (groups)
* @param frame_id - TF session to re-use for the report (client has a listener set up)
*/
void UADC_StartBlockCapture(Unit *unit, uint32_t len, TF_ID frame_id)
{
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
if (priv->opmode == ADC_OPMODE_UNINIT) return;
priv->stream_frame_id = frame_id;
priv->stream_startpos = (uint16_t) DMA_POS(priv);
priv->stream_startpos = DMA_POS(priv);
priv->trig_stream_remain = len;
priv->stream_serial = 0;
UADC_SwitchMode(unit, ADC_OPMODE_BLCAP);
}
/** Start stream */
/**
* Start a stream
*
* @param frame_id - TF session to re-use for the frames (client has a listener set up)
*/
void UADC_StartStream(Unit *unit, TF_ID frame_id)
{
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
if (priv->opmode == ADC_OPMODE_UNINIT) return;
priv->stream_frame_id = frame_id;
priv->stream_startpos = (uint16_t) DMA_POS(priv);
priv->stream_serial = 0;
UADC_SwitchMode(unit, ADC_OPMODE_STREAM);
}
/** End stream */
/**
* End a stream by user request.
*/
void UADC_StopStream(Unit *unit)
{
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
if (priv->opmode == ADC_OPMODE_UNINIT) return;
UADC_ReportEndOfStream(unit);
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
}
/** Handle unit update tick - expire the trigger hold-off */
/**
* Handle unit update tick - expire the trigger hold-off.
* We also check for the emergency shutdown condition and clear it.
*/
void UADC_updateTick(Unit *unit)
{
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
// Recover from shutdown after a delay
if (priv->opmode == ADC_OPMODE_EMERGENCY_SHUTDOWN) {
dbg("Recovering from emergency shutdown");
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
LL_TIM_EnableCounter(priv->TIMx);
adc_dbg("ADC recovering from emergency shutdown");
UADC_ReportEndOfStream(unit);
LL_TIM_EnableCounter(priv->TIMx);
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
unit->tick_interval = 0;
return;
}
@@ -456,14 +529,17 @@ void UADC_updateTick(Unit *unit)
}
}
/**
* Switch the ADC operational mode.
*
* @param unit
* @param new_mode - mode to set
*/
void UADC_SwitchMode(Unit *unit, enum uadc_opmode new_mode)
{
assert_param(unit);
struct priv *priv = unit->data;
assert_param(priv);
const enum uadc_opmode old_mode = priv->opmode;
if (new_mode == old_mode) return; // nothing to do
// if un-itied, can go only to IDLE
@@ -472,33 +548,37 @@ void UADC_SwitchMode(Unit *unit, enum uadc_opmode new_mode)
priv->opmode = ADC_OPMODE_UNINIT;
if (new_mode == ADC_OPMODE_UNINIT) {
// dbg("ADC switch -> UNINIT");
adc_dbg("ADC switch -> UNINIT");
// Stop the DMA, timer and disable ADC - this is called before tearing down the unit
LL_TIM_DisableCounter(priv->TIMx);
LL_ADC_ClearFlag_EOS(priv->ADCx);
LL_ADC_DisableIT_EOS(priv->ADCx);
// Switch off the ADC
if (LL_ADC_IsEnabled(priv->ADCx)) {
// Cancel ongoing conversion
if (LL_ADC_REG_IsConversionOngoing(priv->ADCx)) {
// dbg("Stopping ADC conv");
LL_ADC_REG_StopConversion(priv->ADCx);
hw_wait_while(LL_ADC_REG_IsStopConversionOngoing(priv->ADCx), 100);
}
LL_ADC_Disable(priv->ADCx);
// dbg("Disabling ADC");
hw_wait_while(LL_ADC_IsDisableOngoing(priv->ADCx), 100);
}
// dbg("Disabling DMA");
LL_DMA_DisableChannel(priv->DMAx, priv->dma_chnum);
LL_DMA_DisableIT_HT(priv->DMAx, priv->dma_chnum);
LL_DMA_DisableIT_TC(priv->DMAx, priv->dma_chnum);
LL_DMA_ClearFlag_HT(priv->DMAx, priv->dma_chnum);
LL_DMA_ClearFlag_TC(priv->DMAx, priv->dma_chnum);
}
else if (new_mode == ADC_OPMODE_IDLE || new_mode == ADC_OPMODE_REARM_PENDING) {
// IDLE and ARMED are identical with the exception that the trigger condition is not checked
// ARMED can be only entered from IDLE, thus we do the init only here.
priv->tc_pending = false;
priv->ht_pending = false;
// In IDLE, we don't need the DMA interrupts
LL_DMA_ClearFlag_HT(priv->DMAx, priv->dma_chnum);
LL_DMA_ClearFlag_TC(priv->DMAx, priv->dma_chnum);
@@ -519,6 +599,7 @@ void UADC_SwitchMode(Unit *unit, enum uadc_opmode new_mode)
}
}
else if (new_mode == ADC_OPMODE_EMERGENCY_SHUTDOWN) {
adc_dbg("ADC switch -> EMERGENCY_STOP");
// Emergency shutdown is used when the job queue overflows and the stream is torn
// This however doesn't help in the case when user sets such a high frequency
// that the whole app becomes unresponsive due to the completion ISR, need to verify the value manually.
@@ -538,17 +619,15 @@ void UADC_SwitchMode(Unit *unit, enum uadc_opmode new_mode)
unit->_tick_cnt = 250; // 1-off
}
else if (new_mode == ADC_OPMODE_ARMED) {
// dbg("ADC switch -> ARMED");
adc_dbg("ADC switch -> ARMED");
assert_param(old_mode == ADC_OPMODE_IDLE || old_mode == ADC_OPMODE_REARM_PENDING);
// avoid firing immediately by the value jumping across the scale
priv->trig_prev_level = priv->last_samples[priv->trigger_source];
}
else if (new_mode == ADC_OPMODE_TRIGD ||
new_mode == ADC_OPMODE_STREAM ||
new_mode == ADC_OPMODE_BLCAP) {
else if (new_mode == ADC_OPMODE_TRIGD || new_mode == ADC_OPMODE_STREAM || new_mode == ADC_OPMODE_BLCAP) {
adc_dbg("ADC switch -> CAPTURE");
// dbg("ADC switch -> TRIG'D / STREAM / BLOCK");
assert_param(old_mode == ADC_OPMODE_ARMED || old_mode == ADC_OPMODE_IDLE);
// during the capture, we disallow direct readout and averaging to reduce overhead
@@ -560,6 +639,12 @@ void UADC_SwitchMode(Unit *unit, enum uadc_opmode new_mode)
LL_DMA_ClearFlag_HT(priv->DMAx, priv->dma_chnum);
LL_DMA_ClearFlag_TC(priv->DMAx, priv->dma_chnum);
// those must be as close as possible to the enabling
// if not trig'd, we don't care for lost samples before (this could cause a DMA irq miss / ht/tc mismatch with the startpos)
if (new_mode != ADC_OPMODE_TRIGD) {
priv->stream_startpos = DMA_POS(priv);
priv->stream_serial = 0;
}
LL_DMA_EnableIT_HT(priv->DMAx, priv->dma_chnum);
LL_DMA_EnableIT_TC(priv->DMAx, priv->dma_chnum);
}
+92 -102
View File
@@ -1,8 +1,9 @@
//
// Created by MightyPork on 2018/02/03.
//
// ADC unit init and de-init functions
//
#include <stm32f072xb.h>
#include "platform.h"
#include "unit_base.h"
@@ -15,13 +16,11 @@ error_t UADC_preInit(Unit *unit)
struct priv *priv = unit->data = calloc_ck(1, sizeof(struct priv));
if (priv == NULL) return E_OUT_OF_MEM;
priv->channels = 1; // PA0
priv->enable_tsense = false;
priv->enable_vref = false;
priv->sample_time = 0b010; // 13.5c
priv->frequency = 1000;
priv->buffer_size = 512;
priv->averaging_factor = 500;
priv->cfg.channels = 1<<16; // Tsense by default - always available, easy testing
priv->cfg.sample_time = 0b010; // 13.5c - good enough and the default 0b00 value really is useless
priv->cfg.frequency = 1000;
priv->cfg.buffer_size = 256; // in half-words
priv->cfg.averaging_factor = 500; // 0.5
priv->opmode = ADC_OPMODE_UNINIT;
@@ -36,14 +35,12 @@ error_t UADC_SetSampleRate(Unit *unit, uint32_t hertz)
uint16_t presc;
uint32_t count;
if (!solve_timer(PLAT_APB1_HZ, hertz, true, &presc, &count,
&priv->real_frequency)) {
if (!solve_timer(PLAT_APB1_HZ, hertz, true, &presc, &count, &priv->real_frequency)) {
dbg("Failed to resolve timer params.");
return E_BAD_VALUE;
}
dbg("Frequency error %d ppm, presc %d, count %d",
(int) lrintf(1000000.0f *
((priv->real_frequency - hertz) / (float) hertz)),
adc_dbg("Frequency error %d ppm, presc %d, count %d",
(int) lrintf(1000000.0f * ((priv->real_frequency - hertz) / (float) hertz)),
(int) presc, (int) count);
LL_TIM_SetPrescaler(priv->TIMx, (uint32_t) (presc - 1));
@@ -54,6 +51,51 @@ error_t UADC_SetSampleRate(Unit *unit, uint32_t hertz)
return E_SUCCESS;
}
/**
* Set up the ADC DMA.
* This is split to its own function because it's also called when the user adjusts the
* enabled channels and we need to re-configure it.
*
* @param unit
*/
void UADC_SetupDMA(Unit *unit)
{
struct priv *priv = unit->data;
adc_dbg("Setting up DMA");
{
uint32_t itemcount = priv->nb_channels * (priv->cfg.buffer_size / (priv->nb_channels));
if (itemcount % 2 == 1) itemcount -= priv->nb_channels; // ensure the count is even
priv->buf_itemcount = itemcount;
adc_dbg("DMA item count is %d (%d bytes), There are %d samples per group.",
(int)priv->buf_itemcount,
(int)(priv->buf_itemcount * sizeof(uint16_t)),
(int)priv->nb_channels);
{
LL_DMA_InitTypeDef init;
LL_DMA_StructInit(&init);
init.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
init.Mode = LL_DMA_MODE_CIRCULAR;
init.NbData = itemcount;
init.PeriphOrM2MSrcAddress = (uint32_t) &priv->ADCx->DR;
init.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_HALFWORD;
init.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
init.MemoryOrM2MDstAddress = (uint32_t) priv->dma_buffer;
init.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_HALFWORD;
init.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
assert_param(SUCCESS == LL_DMA_Init(priv->DMAx, priv->dma_chnum, &init));
}
// LL_DMA_EnableChannel(priv->DMAx, priv->dma_chnum); // this is done in the switch mode func now
}
}
/** Finalize unit set-up */
error_t UADC_init(Unit *unit)
{
@@ -77,8 +119,10 @@ error_t UADC_init(Unit *unit)
{
// Claim and configure all analog pins
priv->nb_channels = 0;
for (uint8_t i = 0; i < 16; i++) {
if (priv->channels & (1 << i)) {
for (uint8_t i = 0; i <= UADC_MAX_CHANNEL; i++) {
if (priv->cfg.channels & (1 << i)) {
priv->nb_channels++;
char c;
uint8_t num;
if (i <= 7) {
@@ -89,9 +133,11 @@ error_t UADC_init(Unit *unit)
c = 'B';
num = (uint8_t) (i - 8);
}
else {
else if (i <= 15) {
c = 'C';
num = (uint8_t) (i - 10);
} else {
break;
}
TRY(rsc_claim_pin(unit, c, num));
@@ -101,23 +147,27 @@ error_t UADC_init(Unit *unit)
LL_GPIO_SetPinPull(port, ll_pin, LL_GPIO_PULL_NO);
LL_GPIO_SetPinMode(port, ll_pin, LL_GPIO_MODE_ANALOG);
priv->nb_channels++;
}
}
if (priv->enable_tsense) priv->nb_channels++;
if (priv->enable_vref) priv->nb_channels++;
if (priv->nb_channels == 0) {
dbg("!! Need at least 1 channel");
dbg("Need at least 1 channel");
return E_BAD_CONFIG;
}
if (priv->buffer_size < priv->nb_channels*2*2) {
// ensure some minimal space is available
if (priv->cfg.buffer_size < priv->nb_channels * 2) {
dbg("Insufficient buf size");
return E_BAD_CONFIG;
}
}
// ---------------- Alloc the buffer ----------------------
adc_dbg("Allocating buffer of size %d half-words", (int)priv->cfg.buffer_size);
priv->dma_buffer = calloc_ck(priv->cfg.buffer_size, sizeof(uint16_t));
if (NULL == priv->dma_buffer) return E_OUT_OF_MEM;
assert_param(((uint32_t) priv->dma_buffer & 3) == 0); // must be aligned
// ------------------- ENABLE CLOCKS --------------------------
{
// enable peripherals clock
@@ -127,22 +177,10 @@ error_t UADC_init(Unit *unit)
}
// ------------------- CONFIGURE THE TIMER --------------------------
dbg("Setting up TIMER");
adc_dbg("Setting up TIMER");
{
TRY(UADC_SetSampleRate(unit, priv->frequency));
// // Find suitable timer values
// uint16_t presc;
// uint32_t count;
// float real_freq;
// if (!solve_timer(PLAT_APB1_HZ, priv->frequency, true, &presc, &count, &real_freq)) {
// dbg("Failed to resolve timer params.");
// return E_BAD_VALUE;
// }
// dbg("Frequency error %d ppm, presc %d, count %d",
// (int) lrintf(1000000.0f * ((real_freq - priv->frequency) / (float)priv->frequency)), (int) presc, (int) count);
//
// LL_TIM_SetPrescaler(priv->TIMx, (uint32_t) (presc - 1));
// LL_TIM_SetAutoReload(priv->TIMx, count - 1);
TRY(UADC_SetSampleRate(unit, priv->cfg.frequency));
LL_TIM_EnableARRPreload(priv->TIMx);
LL_TIM_EnableUpdateEvent(priv->TIMx);
LL_TIM_SetTriggerOutput(priv->TIMx, LL_TIM_TRGO_UPDATE);
@@ -150,101 +188,52 @@ error_t UADC_init(Unit *unit)
}
// --------------------- CONFIGURE THE ADC ---------------------------
dbg("Setting up ADC");
adc_dbg("Setting up ADC");
{
// Calibrate the ADC
dbg("Wait for calib");
adc_dbg("Wait for calib");
LL_ADC_StartCalibration(priv->ADCx);
while (LL_ADC_IsCalibrationOnGoing(priv->ADCx)) {}
dbg("ADC calibrated.");
adc_dbg("ADC calibrated.");
{
uint32_t mask = 0;
if (priv->enable_vref) mask |= LL_ADC_PATH_INTERNAL_VREFINT;
if (priv->enable_tsense) mask |= LL_ADC_PATH_INTERNAL_TEMPSENSOR;
LL_ADC_SetCommonPathInternalCh(priv->ADCx_Common, mask);
}
// Let's just enable the internal channels always - makes toggling them on-line easier
LL_ADC_SetCommonPathInternalCh(priv->ADCx_Common, LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR);
LL_ADC_SetDataAlignment(priv->ADCx, LL_ADC_DATA_ALIGN_RIGHT);
LL_ADC_SetResolution(priv->ADCx, LL_ADC_RESOLUTION_12B);
LL_ADC_REG_SetDMATransfer(priv->ADCx, LL_ADC_REG_DMA_TRANSFER_UNLIMITED);
// configure channels
priv->extended_channels_mask = priv->channels;
if (priv->enable_tsense) priv->extended_channels_mask |= (1<<16);
if (priv->enable_vref) priv->extended_channels_mask |= (1<<17);
priv->channels_mask = priv->cfg.channels;
priv->ADCx->CHSELR = priv->extended_channels_mask;
priv->ADCx->CHSELR = priv->channels_mask;
LL_ADC_REG_SetTriggerSource(priv->ADCx, LL_ADC_REG_TRIG_EXT_TIM15_TRGO);
LL_ADC_SetSamplingTimeCommonChannels(priv->ADCx, LL_ADC_SAMPLETIMES[priv->sample_time]);
LL_ADC_SetSamplingTimeCommonChannels(priv->ADCx, LL_ADC_SAMPLETIMES[priv->cfg.sample_time]);
// LL_ADC_Enable(priv->ADCx);
// will be enabled when switching to INIT mode
}
// --------------------- CONFIGURE DMA -------------------------------
dbg("Setting up DMA");
{
// The length must be a 2*multiple of the number of channels, in bytes
uint16_t itemcount = (uint16_t) ((priv->nb_channels) * (uint16_t) (priv->buffer_size / (2 * priv->nb_channels)));
if (itemcount % 2 == 1) itemcount -= priv->nb_channels;
priv->dma_buffer_itemcount = itemcount;
dbg("DMA item count is %d (%d bytes), There are %d 2-byte samples per group.",
priv->dma_buffer_itemcount,
priv->dma_buffer_itemcount*sizeof(uint16_t),
priv->nb_channels);
priv->dma_buffer = calloc_ck(priv->dma_buffer_itemcount, sizeof(uint16_t));
if (NULL == priv->dma_buffer) return E_OUT_OF_MEM;
assert_param(((uint32_t) priv->dma_buffer & 3) == 0); // must be aligned
{
LL_DMA_InitTypeDef init;
LL_DMA_StructInit(&init);
init.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
init.Mode = LL_DMA_MODE_CIRCULAR;
init.NbData = itemcount;
init.PeriphOrM2MSrcAddress = (uint32_t) &priv->ADCx->DR;
init.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_HALFWORD;
init.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
init.MemoryOrM2MDstAddress = (uint32_t) priv->dma_buffer;
init.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_HALFWORD;
init.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
assert_param(SUCCESS == LL_DMA_Init(priv->DMAx, priv->dma_chnum, &init));
// Interrupt on transfer 1/2 and complete
// We will capture the first and second half and send it while the other half is being filled.
// LL_DMA_EnableIT_HT(priv->DMAx, priv->dma_chnum);
// LL_DMA_EnableIT_TC(priv->DMAx, priv->dma_chnum);
}
LL_DMA_EnableChannel(priv->DMAx, priv->dma_chnum);
}
UADC_SetupDMA(unit);
// prepare the avg factor float for the ISR
if (priv->averaging_factor > 1000) priv->averaging_factor = 1000; // normalize
priv->avg_factor_as_float = priv->averaging_factor/1000.0f;
if (priv->cfg.averaging_factor > 1000) priv->cfg.averaging_factor = 1000; // normalize
priv->avg_factor_as_float = priv->cfg.averaging_factor/1000.0f;
dbg("ADC peripherals configured.");
adc_dbg("ADC peripherals configured.");
irqd_attach(priv->DMA_CHx, UADC_DMA_Handler, unit);
irqd_attach(priv->ADCx, UADC_ADC_EOS_Handler, unit);
dbg("irqs attached");
adc_dbg("irqs attached");
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
dbg("ADC done");
adc_dbg("ADC done");
return E_SUCCESS;
}
/** Tear down the unit */
void UADC_deInit(Unit *unit)
{
@@ -262,10 +251,11 @@ void UADC_deInit(Unit *unit)
irqd_detach(priv->ADCx, UADC_ADC_EOS_Handler);
LL_DMA_DeInit(priv->DMAx, priv->dma_chnum);
free_ck(priv->dma_buffer);
}
// free buffer if not NULL
free_ck(priv->dma_buffer);
// Release all resources, deinit pins
rsc_teardown(unit);
+35 -14
View File
@@ -1,6 +1,8 @@
//
// Created by MightyPork on 2018/02/03.
//
// Defines and prototypes used internally by the ADC unit.
//
#ifndef GEX_F072_ADC_INTERNAL_H
#define GEX_F072_ADC_INTERNAL_H
@@ -11,8 +13,13 @@
#include "unit_base.h"
//#define adc_dbg dbg
#define adc_dbg(...) do {} while(0)
#define UADC_MAX_FREQ_FOR_AVERAGING 20000
#define UADC_MAX_CHANNEL 17
enum uadc_opmode {
ADC_OPMODE_UNINIT, //!< Not yet switched to any mode
ADC_OPMODE_IDLE, //!< Idle. Allows immediate value readout and averaging.
@@ -33,48 +40,56 @@ enum uadc_event {
/** Private data structure */
struct priv {
// settings
uint16_t channels; //!< bit flags (will be recorded in order 0-15)
bool enable_tsense; //!< append a signal from the temperature channel (voltage proportional to Tj)
bool enable_vref; //!< append a signal from the internal voltage reference
struct {
uint32_t channels; //!< bit flags (will be recorded in order 0-15)
uint8_t sample_time; //!< 0-7 (corresponds to 1.5-239.5 cycles) - time for the sampling capacitor to charge
uint32_t frequency; //!< Timer frequency in Hz. Note: not all frequencies can be achieved accurately
uint16_t buffer_size; //!< Buffer size in bytes (count 2 bytes per channel per measurement) - faster sampling freq needs bigger buffer
uint32_t buffer_size; //!< Buffer size in bytes (count 2 bytes per channel per measurement) - faster sampling freq needs bigger buffer
uint16_t averaging_factor; //!< Exponential averaging factor 0-1000
} cfg;
// internal state
float real_frequency;
uint32_t real_frequency_int;
uint32_t extended_channels_mask; //!< channels bitfield including tsense and vref
float avg_factor_as_float;
// Peripherals
ADC_TypeDef *ADCx; //!< The ADC peripheral used
ADC_Common_TypeDef *ADCx_Common; //!< The ADC common control block
TIM_TypeDef *TIMx; //!< ADC timing timer instance
DMA_TypeDef *DMAx; //!< DMA isnatnce used
uint8_t dma_chnum; //!< DMA channel number
DMA_Channel_TypeDef *DMA_CHx; //!< DMA channel instance
// Live config
float real_frequency;
uint32_t real_frequency_int;
uint32_t channels_mask; //!< channels bitfield including tsense and vref
float avg_factor_as_float;
uint16_t *dma_buffer; //!< malloc'd buffer for the samples
uint8_t nb_channels; //!< nbr of enabled adc channels
uint16_t dma_buffer_itemcount; //!< real size of the buffer in samples (adjusted to fit 2x whole multiple of sample group)
uint32_t buf_itemcount; //!< real size of the buffer in samples (adjusted to fit 2x whole multiple of sample group)
// Trigger state
uint32_t trig_stream_remain; //!< Counter of samples remaining to be sent in the post-trigger stream
uint16_t trig_holdoff_remain; //!< Tmp counter for the currently active hold-off
uint16_t trig_prev_level; //!< Value of the previous sample, used to detect trigger edge
uint16_t stream_startpos; //!< Byte offset in the DMA buffer where the next capture for a stream should start.
uint32_t stream_startpos; //!< Byte offset in the DMA buffer where the next capture for a stream should start.
//!< Updated in TH/TC and on trigger (after the preceding data is sent as a pretrig buffer)
enum uadc_opmode opmode; //!< OpMode (state machine state)
float averaging_bins[18]; //!< Averaging buffers, enough space to accommodate all channels (16 external + 2 internal)
uint16_t last_samples[18]; //!< If averaging is disabled, the last captured sample is stored here.
// Trigger config
uint8_t trigger_source; //!< number of the pin selected as a trigger source
uint16_t pretrig_len; //!< Pre-trigger length, nbr of historical samples to report when trigger occurs
uint32_t pretrig_len; //!< Pre-trigger length, nbr of historical samples to report when trigger occurs
uint32_t trig_len; //!< Trigger length, nbr of samples to report AFTER a trigger occurs
uint16_t trig_level; //!< Triggering level in LSB
uint8_t trig_edge; //!< Which edge we want to trigger on. 1-rising, 2-falling, 3-both
bool auto_rearm; //!< Flag that the trigger should be re-armed after the stream finishes
uint16_t trig_holdoff; //!< Trigger hold-off time, set when configuring the trigger
TF_ID stream_frame_id; //!< Session ID for multi-part stream (response or report)
uint8_t stream_serial;
uint8_t stream_serial; //!< Serial nr of a stream frame
bool tc_pending;
bool ht_pending;
};
/** Allocate data structure and set defaults */
@@ -102,6 +117,9 @@ error_t UADC_init(Unit *unit);
/** Tear down the unit */
void UADC_deInit(Unit *unit);
/** Configure DMA (buffer count etc) */
void UADC_SetupDMA(Unit *unit);
// ------------------------------------------------------------------------
/** DMA half/complete handler */
@@ -134,4 +152,7 @@ void UADC_StopStream(Unit *unit);
/** Configure frequency */
error_t UADC_SetSampleRate(Unit *unit, uint32_t hertz);
/** Abort capture */
void UADC_AbortCapture(Unit *unit);
#endif //GEX_F072_ADC_INTERNAL_H
+34 -50
View File
@@ -1,6 +1,8 @@
//
// Created by MightyPork on 2018/02/03.
//
// ADC unit settings reading / parsing
//
#include "platform.h"
#include "unit_base.h"
@@ -16,18 +18,11 @@ void UADC_loadBinary(Unit *unit, PayloadParser *pp)
uint8_t version = pp_u8(pp);
(void)version;
priv->channels = pp_u16(pp);
priv->enable_tsense = pp_bool(pp);
priv->enable_vref = pp_bool(pp);
priv->sample_time = pp_u8(pp);
priv->frequency = pp_u32(pp);
if (version >= 1) {
priv->buffer_size = pp_u16(pp);
}
if (version >= 2) {
priv->averaging_factor = pp_u16(pp);
}
priv->cfg.channels = pp_u32(pp);
priv->cfg.sample_time = pp_u8(pp);
priv->cfg.frequency = pp_u32(pp);
priv->cfg.buffer_size = pp_u32(pp);
priv->cfg.averaging_factor = pp_u16(pp);
}
/** Write to a binary buffer for storing in Flash */
@@ -35,15 +30,13 @@ void UADC_writeBinary(Unit *unit, PayloadBuilder *pb)
{
struct priv *priv = unit->data;
pb_u8(pb, 2); // version
pb_u8(pb, 0); // version
pb_u16(pb, priv->channels);
pb_bool(pb, priv->enable_tsense);
pb_bool(pb, priv->enable_vref);
pb_u8(pb, priv->sample_time);
pb_u32(pb, priv->frequency);
pb_u16(pb, priv->buffer_size);
pb_u16(pb, priv->averaging_factor);
pb_u32(pb, priv->cfg.channels);
pb_u8(pb, priv->cfg.sample_time);
pb_u32(pb, priv->cfg.frequency);
pb_u32(pb, priv->cfg.buffer_size);
pb_u16(pb, priv->cfg.averaging_factor);
}
// ------------------------------------------------------------------------
@@ -55,27 +48,21 @@ error_t UADC_loadIni(Unit *unit, const char *key, const char *value)
struct priv *priv = unit->data;
if (streq(key, "channels")) {
priv->channels = parse_pinmask(value, &suc);
}
else if (streq(key, "enable_tsense")) {
priv->enable_tsense = str_parse_yn(value, &suc);
}
else if (streq(key, "enable_vref")) {
priv->enable_vref = str_parse_yn(value, &suc);
priv->cfg.channels = parse_pinmask(value, &suc);
}
else if (streq(key, "sample_time")) {
priv->sample_time = (uint8_t) avr_atoi(value);
if (priv->sample_time > 7) return E_BAD_VALUE;
priv->cfg.sample_time = (uint8_t) avr_atoi(value);
if (priv->cfg.sample_time > 7) return E_BAD_VALUE;
}
else if (streq(key, "frequency")) {
priv->frequency = (uint32_t) avr_atoi(value);
priv->cfg.frequency = (uint32_t) avr_atoi(value);
}
else if (streq(key, "buffer_size")) {
priv->buffer_size = (uint16_t) avr_atoi(value);
priv->cfg.buffer_size = (uint32_t) avr_atoi(value);
}
else if (streq(key, "avg_factor")) {
priv->averaging_factor = (uint16_t) avr_atoi(value);
if (priv->averaging_factor > 1000) return E_BAD_VALUE;
priv->cfg.averaging_factor = (uint16_t) avr_atoi(value);
if (priv->cfg.averaging_factor > 1000) return E_BAD_VALUE;
}
else {
return E_BAD_KEY;
@@ -91,32 +78,29 @@ void UADC_writeIni(Unit *unit, IniWriter *iw)
struct priv *priv = unit->data;
iw_comment(iw, "Enabled channels, comma separated");
iw_comment(iw, "0-7 = A0-A7, 8-9 = B0-B1, 10-15 = C0-C5");
iw_entry(iw, "channels", "%s", pinmask2str_up(priv->channels, unit_tmp512));
iw_comment(iw, "Enable Tsense channel (#16)");
iw_entry(iw, "enable_tsense", str_yn(priv->enable_tsense));
iw_comment(iw, "Enable Vref channel (#17)");
iw_entry(iw, "enable_vref", str_yn(priv->enable_vref));
iw_comment(iw, " 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17");
iw_comment(iw, "A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 C0 C1 C2 C3 C4 C5 Tsens Vref");
iw_entry(iw, "channels", "%s", pinmask2str_up(priv->cfg.channels, unit_tmp512));
iw_cmt_newline(iw);
iw_comment(iw, "Sampling time (0-7)");
iw_entry(iw, "sample_time", "%d", (int)priv->sample_time);
iw_entry(iw, "sample_time", "%d", (int)priv->cfg.sample_time);
iw_comment(iw, "Sampling frequency (Hz)");
iw_entry(iw, "frequency", "%d", (int)priv->frequency);
iw_entry(iw, "frequency", "%d", (int)priv->cfg.frequency);
iw_comment(iw, "Sample buffer size (bytes, 2 per channels per sample)");
iw_comment(iw, "- a report is sent when 1/2 of the circular buffer is filled");
iw_comment(iw, "- the buffer is shared by all channels");
iw_comment(iw, "- insufficient buffer size can lead to data loss");
iw_entry(iw, "buffer_size", "%d", (int)priv->buffer_size);
iw_cmt_newline(iw);
iw_comment(iw, "Sample buffer size");
iw_comment(iw, "- shared by all enabled channels");
iw_comment(iw, "- defines the maximum pre-trigger size (divide by # of channels)");
iw_comment(iw, "- captured data is sent in half-buffer chunks");
iw_comment(iw, "- buffer overrun aborts the data capture");
iw_entry(iw, "buffer_size", "%d", (int)priv->cfg.buffer_size);
iw_cmt_newline(iw);
iw_comment(iw, "Exponential averaging coefficient (permil, range 0-1000 ~ 0.000-1.000)");
iw_comment(iw, "- used formula: y[t]=(1-k)*y[t-1]+k*u[t]");
iw_comment(iw, "- available only for direct readout (i.e. not used in block capture)");
iw_entry(iw, "avg_factor", "%d", priv->averaging_factor);
iw_comment(iw, "- not available when a capture is running");
iw_entry(iw, "avg_factor", "%d", priv->cfg.averaging_factor);
}
+86 -19
View File
@@ -10,7 +10,7 @@
// ------------------------------------------------------------------------
enum TplCmd_ {
enum AdcCmd_ {
CMD_READ_RAW = 0,
CMD_READ_SMOOTHED = 1,
@@ -27,6 +27,8 @@ enum TplCmd_ {
CMD_STREAM_STOP = 27,
CMD_SET_SMOOTHING_FACTOR = 28,
CMD_SET_SAMPLE_RATE = 29,
CMD_ENABLE_CHANNELS = 30,
CMD_SET_SAMPLE_TIME = 31,
};
/** Handle a request message */
@@ -35,8 +37,6 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
struct priv *priv = unit->data;
PayloadBuilder pb = pb_start(unit_tmp512, UNIT_TMP_LEN, NULL);
// TODO toggling individual channels - would require DMA re-init and various changes in the usage of the struct
switch (command) {
/**
* Get enabled channels.
@@ -44,13 +44,17 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
*/
case CMD_GET_ENABLED_CHANNELS:
for (uint8_t i = 0; i < 18; i++) {
if (priv->extended_channels_mask & (1 << i)) {
if (priv->channels_mask & (1 << i)) {
pb_u8(&pb, i);
}
}
com_respond_pb(frame_id, MSG_SUCCESS, &pb);
return E_SUCCESS;
/**
* Set the sample rate in Hz
* plad: hz:u32
*/
case CMD_SET_SAMPLE_RATE:
{
uint32_t freq = pp_u32(pp);
@@ -81,6 +85,69 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
}
return E_SUCCESS;
/**
* Set sample time
* pld: u8:0-7
*/
case CMD_SET_SAMPLE_TIME:
{
uint8_t tim = pp_u8(pp);
if (tim > 7) return E_BAD_VALUE;
UADC_SwitchMode(unit, ADC_OPMODE_UNINIT);
{
LL_ADC_SetSamplingTimeCommonChannels(priv->ADCx, LL_ADC_SAMPLETIMES[tim]);
}
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
}
return E_SUCCESS;
/**
* Enable channels. The channels must've been configured in the settings (except ch 16 and 17 which are available always)
* pld: u32: bitmap of channels
*/
case CMD_ENABLE_CHANNELS:
{
uint32_t new_channels = pp_u32(pp);
// this tears down the peripherals sufficiently so we can re-configure them. Going back to IDLE re-inits this
UADC_SwitchMode(unit, ADC_OPMODE_UNINIT);
uint32_t illegal_channels = new_channels & ~(priv->cfg.channels | (1<<16) | (1<<17)); // 16 and 17 may be enabled always
if (illegal_channels != 0) {
com_respond_str(MSG_ERROR, frame_id, "Some requested channels not available");
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
return E_FAILURE;
}
uint8_t nb_channels = 0;
// count the enabled channels
for(int i = 0; i < 32; i++) {
if (new_channels & (1<<i)) {
nb_channels++;
}
}
if (nb_channels == 0) {
com_respond_str(MSG_ERROR, frame_id, "Need at least 1 channel");
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
return E_FAILURE;
}
if (priv->cfg.buffer_size < nb_channels * 2) {
com_respond_str(MSG_ERROR, frame_id, "Insufficient buf size");
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
return E_BAD_CONFIG;
}
priv->nb_channels = nb_channels;
priv->ADCx->CHSELR = new_channels; // apply it to the ADC
priv->channels_mask = new_channels;
UADC_SetupDMA(unit);
UADC_SwitchMode(unit, ADC_OPMODE_IDLE);
}
return E_SUCCESS;
/**
* Read raw values from the last measurement.
* Response: interleaved (u8:channel, u16:value) for all channels
@@ -91,7 +158,7 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
}
for (uint8_t i = 0; i < 18; i++) {
if (priv->extended_channels_mask & (1 << i)) {
if (priv->channels_mask & (1 << i)) {
pb_u16(&pb, priv->last_samples[i]);
}
}
@@ -113,7 +180,7 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
}
for (uint8_t i = 0; i < 18; i++) {
if (priv->extended_channels_mask & (1 << i)) {
if (priv->channels_mask & (1 << i)) {
pb_float(&pb, priv->averaging_bins[i]);
}
}
@@ -133,7 +200,7 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
* u8(bool) - auto re-arm after firing and completing the capture
*/
case CMD_SETUP_TRIGGER:
dbg("> Setup trigger");
adc_dbg("> Setup trigger");
if (priv->opmode != ADC_OPMODE_IDLE &&
priv->opmode != ADC_OPMODE_ARMED &&
priv->opmode != ADC_OPMODE_REARM_PENDING) {
@@ -144,17 +211,17 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
const uint8_t source = pp_u8(pp);
const uint16_t level = pp_u16(pp);
const uint8_t edge = pp_u8(pp);
const uint16_t pretrig = pp_u16(pp);
const uint32_t pretrig = pp_u32(pp);
const uint32_t count = pp_u32(pp);
const uint16_t holdoff = pp_u16(pp);
const bool auto_rearm = pp_bool(pp);
if (source > 17) {
if (source > UADC_MAX_CHANNEL) {
com_respond_str(MSG_ERROR, frame_id, "Invalid trig source");
return E_FAILURE;
}
if (0 == (priv->extended_channels_mask & (1 << source))) {
if (0 == (priv->channels_mask & (1 << source))) {
com_respond_str(MSG_ERROR, frame_id, "Channel not enabled");
return E_FAILURE;
}
@@ -170,7 +237,7 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
}
// XXX the max size may be too much
const uint16_t max_pretrig = (priv->dma_buffer_itemcount / priv->nb_channels);
const uint32_t max_pretrig = (priv->buf_itemcount / priv->nb_channels);
if (pretrig > max_pretrig) {
com_respond_snprintf(frame_id, MSG_ERROR,
"Pretrig too large (max %d)", (int) max_pretrig);
@@ -192,7 +259,7 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
* Arm (permissible only if idle and the trigger is configured)
*/
case CMD_ARM:
dbg("> Arm");
adc_dbg("> Arm");
uint8_t sticky = pp_u8(pp);
if(priv->opmode == ADC_OPMODE_ARMED || priv->opmode == ADC_OPMODE_REARM_PENDING) {
@@ -222,7 +289,7 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
* Switches to idle.
*/
case CMD_DISARM:
dbg("> Disarm");
adc_dbg("> Disarm");
priv->auto_rearm = false;
@@ -245,8 +312,8 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
* Abort any ongoing capture and dis-arm.
*/
case CMD_ABORT:;
dbg("> Abort capture");
TRY(UU_ADC_AbortCapture(unit));
adc_dbg("> Abort capture");
UADC_AbortCapture(unit);
return E_SUCCESS;
/**
@@ -254,7 +321,7 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
* The reported edge will be 0b11, here meaning "manual trigger"
*/
case CMD_FORCE_TRIGGER:
dbg("> Force trigger");
adc_dbg("> Force trigger");
// This is similar to block capture, but includes the pre-trig buffer and has fixed size based on trigger config
// FORCE is useful for checking if the trigger is set up correctly
if (priv->opmode != ADC_OPMODE_ARMED &&
@@ -276,7 +343,7 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
* u32 - sample count (for each channel)
*/
case CMD_BLOCK_CAPTURE:
dbg("> Block cpt");
adc_dbg("> Block cpt");
if (priv->opmode != ADC_OPMODE_ARMED &&
priv->opmode != ADC_OPMODE_REARM_PENDING &&
priv->opmode != ADC_OPMODE_IDLE) return E_BUSY;
@@ -291,7 +358,7 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
* The stream can be terminated by the stop command.
*/
case CMD_STREAM_START:
dbg("> Stream ON");
adc_dbg("> Stream ON");
if (priv->opmode != ADC_OPMODE_ARMED &&
priv->opmode != ADC_OPMODE_REARM_PENDING &&
priv->opmode != ADC_OPMODE_IDLE) return E_BUSY;
@@ -303,7 +370,7 @@ static error_t UADC_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, P
* Stop a stream.
*/
case CMD_STREAM_STOP:
dbg("> Stream OFF");
adc_dbg("> Stream OFF");
if (priv->opmode != ADC_OPMODE_STREAM) {
com_respond_str(MSG_ERROR, frame_id, "Not streaming");
return E_FAILURE;
+2 -3
View File
@@ -1,7 +1,8 @@
//
// Created by MightyPork on 2017/11/25.
//
// Digital input unit; single or multiple pin read access on one port (A-F)
// ADC unit with several DSO-like features, like triggering, pre-trigger, block capture,
// streaming, smoothing...
//
#ifndef U_TPL_H
@@ -11,6 +12,4 @@
extern const UnitDriver UNIT_ADC;
error_t UU_ADC_AbortCapture(Unit *unit);
#endif //U_TPL_H
+3 -3
View File
@@ -47,13 +47,13 @@ error_t DOut_loadIni(Unit *unit, const char *key, const char *value)
suc = parse_port_name(value, &priv->port_name);
}
else if (streq(key, "pins")) {
priv->pins = parse_pinmask(value, &suc);
priv->pins = (uint16_t) parse_pinmask(value, &suc);
}
else if (streq(key, "initial")) {
priv->initial = parse_pinmask(value, &suc);
priv->initial = (uint16_t) parse_pinmask(value, &suc);
}
else if (streq(key, "open-drain")) {
priv->open_drain = parse_pinmask(value, &suc);
priv->open_drain = (uint16_t) parse_pinmask(value, &suc);
}
else {
return E_BAD_KEY;
+110
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@@ -0,0 +1,110 @@
//
// Created by MightyPork on 2018/02/03.
//
#include "platform.h"
#include "unit_base.h"
#include "unit_sipo.h"
#define SIPO_INTERNAL
#include "_sipo_internal.h"
static void send_pulse(bool pol, GPIO_TypeDef *port, uint32_t ll)
{
if (pol) {
LL_GPIO_SetOutputPin(port, ll);
}
else {
LL_GPIO_ResetOutputPin(port, ll);
}
__asm_loop(2);
if (pol) {
LL_GPIO_ResetOutputPin(port, ll);
}
else {
LL_GPIO_SetOutputPin(port, ll);
}
}
#pragma GCC push_options
#pragma GCC optimize ("O2")
error_t UU_SIPO_Write(Unit *unit, const uint8_t *buffer, uint16_t buflen, uint16_t terminal_data)
{
CHECK_TYPE(unit, &UNIT_SIPO);
struct priv *priv = unit->data;
if (buflen % priv->data_width != 0) {
dbg("Buflen %d vs width %d", (int)buflen, (int)priv->data_width);
return E_BAD_COUNT; // must be a multiple of the channel count
}
// buffer contains data for the individual data pins, back to back as AAA BBB CCC (whole bytes)
const uint8_t data_width = priv->data_width;
const uint16_t bytelen = buflen / data_width;
const uint16_t mask = priv->data_pins;
uint8_t offsets[16];
for (int i=0; i<16; i++) offsets[i] = (uint8_t) (bytelen * i);
for (int32_t bn = bytelen - 1; bn >= 0; bn--) {
// send the byte
for (int32_t i = 0; i < 8; i++) {
uint16_t packed = 0;
for (int32_t j = data_width - 1; j >= 0; j--) {
packed |= (buffer[bn + offsets[j]] >> i) & 1;
if (j > 0) packed <<= 1;
}
uint16_t spread = pinmask_spread(packed, mask);
priv->data_port->BSRR = spread | (((~spread) & mask) << 16);
// Shift clock pulse
send_pulse(priv->shift_pol, priv->shift_port, priv->shift_ll);
}
}
// load the final data - this may be used by some other circuitry or
// simply to rest the lines at a defined known level
uint16_t spread = pinmask_spread(terminal_data, mask);
priv->data_port->BSRR = spread | (((~spread) & mask) << 16);
send_pulse(priv->store_pol, priv->store_port, priv->store_ll);
return E_SUCCESS;
}
#pragma GCC pop_options
error_t UU_SIPO_DirectData(Unit *unit, uint16_t data_packed)
{
CHECK_TYPE(unit, &UNIT_SIPO);
struct priv *priv = unit->data;
uint16_t spread = pinmask_spread(data_packed, priv->data_pins);
priv->data_port->BSRR = spread | (((~spread) & priv->data_pins) << 16);
return E_SUCCESS;
}
error_t UU_SIPO_DirectClear(Unit *unit)
{
CHECK_TYPE(unit, &UNIT_SIPO);
struct priv *priv = unit->data;
send_pulse(priv->clear_pol, priv->clear_port, priv->clear_ll);
return E_SUCCESS;
}
error_t UU_SIPO_DirectShift(Unit *unit)
{
CHECK_TYPE(unit, &UNIT_SIPO);
struct priv *priv = unit->data;
send_pulse(priv->shift_pol, priv->shift_port, priv->shift_ll);
return E_SUCCESS;
}
error_t UU_SIPO_DirectStore(Unit *unit)
{
CHECK_TYPE(unit, &UNIT_SIPO);
struct priv *priv = unit->data;
send_pulse(priv->store_pol, priv->store_port, priv->store_ll);
return E_SUCCESS;
}
+126
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@@ -0,0 +1,126 @@
//
// Created by MightyPork on 2018/02/03.
//
#include "platform.h"
#include "unit_base.h"
#define SIPO_INTERNAL
#include "_sipo_internal.h"
/** Allocate data structure and set defaults */
error_t USIPO_preInit(Unit *unit)
{
struct priv *priv = unit->data = calloc_ck(1, sizeof(struct priv));
if (priv == NULL) return E_OUT_OF_MEM;
priv->store_pname = 'A';
priv->store_pnum = 0;
priv->store_pol = true;
priv->shift_pname = 'A';
priv->shift_pnum = 1;
priv->shift_pol = true;
priv->clear_pname = 'A';
priv->clear_pnum = 2;
priv->clear_pol = false;
priv->data_pname = 'A';
priv->data_pins = (1<<3);
return E_SUCCESS;
}
/** Finalize unit set-up */
error_t USIPO_init(Unit *unit)
{
bool suc = true;
struct priv *priv = unit->data;
// --- Parse config ---
priv->store_ll = hw_pin2ll(priv->store_pnum, &suc);
priv->store_port = hw_port2periph(priv->store_pname, &suc);
Resource store_rsc = hw_pin2resource(priv->store_pname, priv->store_pnum, &suc);
if (!suc) return E_BAD_CONFIG;
TRY(rsc_claim(unit, store_rsc));
priv->shift_ll = hw_pin2ll(priv->shift_pnum, &suc);
priv->shift_port = hw_port2periph(priv->shift_pname, &suc);
Resource shift_rsc = hw_pin2resource(priv->shift_pname, priv->shift_pnum, &suc);
if (!suc) return E_BAD_CONFIG;
TRY(rsc_claim(unit, shift_rsc));
priv->clear_ll = hw_pin2ll(priv->clear_pnum, &suc);
priv->clear_port = hw_port2periph(priv->clear_pname, &suc);
Resource clear_rsc = hw_pin2resource(priv->clear_pname, priv->clear_pnum, &suc);
if (!suc) return E_BAD_CONFIG;
TRY(rsc_claim(unit, clear_rsc));
// Claim all needed pins
TRY(rsc_claim_gpios(unit, priv->data_pname, priv->data_pins));
priv->data_port = hw_port2periph(priv->data_pname, &suc);
// --- Init hardware ---
priv->data_width = 0;
for (int i = 0; i < 16; i++) {
if (priv->data_pins & (1 << i)) {
uint32_t ll_pin = hw_pin2ll((uint8_t) i, &suc);
LL_GPIO_SetPinMode(priv->data_port, ll_pin, LL_GPIO_MODE_OUTPUT);
LL_GPIO_SetPinOutputType(priv->data_port, ll_pin, LL_GPIO_OUTPUT_PUSHPULL);
LL_GPIO_SetPinSpeed(priv->data_port, ll_pin, LL_GPIO_SPEED_FREQ_HIGH);
priv->data_width++;
}
}
// Set the initial state - zeros
priv->data_port->ODR &= ~priv->data_pins;
// STORE
LL_GPIO_SetPinMode(priv->store_port, priv->store_ll, LL_GPIO_MODE_OUTPUT);
LL_GPIO_SetPinOutputType(priv->store_port, priv->store_ll, LL_GPIO_OUTPUT_PUSHPULL);
LL_GPIO_SetPinSpeed(priv->store_port, priv->store_ll, LL_GPIO_SPEED_FREQ_HIGH);
if (priv->store_pol)
LL_GPIO_ResetOutputPin(priv->store_port, priv->store_ll);
else
LL_GPIO_SetOutputPin(priv->store_port, priv->store_ll);
// SHIFT
LL_GPIO_SetPinMode(priv->shift_port, priv->shift_ll, LL_GPIO_MODE_OUTPUT);
LL_GPIO_SetPinOutputType(priv->shift_port, priv->shift_ll, LL_GPIO_OUTPUT_PUSHPULL);
LL_GPIO_SetPinSpeed(priv->shift_port, priv->shift_ll, LL_GPIO_SPEED_FREQ_HIGH);
if (priv->shift_pol)
LL_GPIO_ResetOutputPin(priv->shift_port, priv->shift_ll);
else
LL_GPIO_SetOutputPin(priv->shift_port, priv->shift_ll);
// CLEAR
LL_GPIO_SetPinMode(priv->clear_port, priv->clear_ll, LL_GPIO_MODE_OUTPUT);
LL_GPIO_SetPinOutputType(priv->clear_port, priv->clear_ll, LL_GPIO_OUTPUT_PUSHPULL);
LL_GPIO_SetPinSpeed(priv->clear_port, priv->clear_ll, LL_GPIO_SPEED_FREQ_HIGH);
if (priv->clear_pol)
LL_GPIO_ResetOutputPin(priv->clear_port, priv->clear_ll);
else
LL_GPIO_SetOutputPin(priv->clear_port, priv->clear_ll);
// initial clear
UU_SIPO_DirectClear(unit);
return E_SUCCESS;
}
/** Tear down the unit */
void USIPO_deInit(Unit *unit)
{
// Release all resources, deinit pins
rsc_teardown(unit);
// Free memory
free_ck(unit->data);
}
+121
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@@ -0,0 +1,121 @@
//
// Created by MightyPork on 2018/02/03.
//
#ifndef GEX_F072_SIPO_INTERNAL_H
#define GEX_F072_SIPO_INTERNAL_H
#ifndef SIPO_INTERNAL
#error bad include!
#endif
#include "unit_base.h"
/** Private data structure */
struct priv {
// settings
char store_pname;
uint8_t store_pnum;
bool store_pol; //!< Store pulse active edge
char shift_pname;
uint8_t shift_pnum;
bool shift_pol; //!< Shift clock active edge
char clear_pname;
uint8_t clear_pnum;
bool clear_pol; //!< Clear signal active level
char data_pname;
uint16_t data_pins;
// live fields
uint32_t store_ll;
uint32_t shift_ll;
uint32_t clear_ll;
GPIO_TypeDef *store_port;
GPIO_TypeDef *shift_port;
GPIO_TypeDef *clear_port;
GPIO_TypeDef *data_port;
uint8_t data_width;
};
/** Allocate data structure and set defaults */
error_t USIPO_preInit(Unit *unit);
/** Load from a binary buffer stored in Flash */
void USIPO_loadBinary(Unit *unit, PayloadParser *pp);
/** Write to a binary buffer for storing in Flash */
void USIPO_writeBinary(Unit *unit, PayloadBuilder *pb);
// ------------------------------------------------------------------------
/** Parse a key-value pair from the INI file */
error_t USIPO_loadIni(Unit *unit, const char *key, const char *value);
/** Generate INI file section for the unit */
void USIPO_writeIni(Unit *unit, IniWriter *iw);
// ------------------------------------------------------------------------
/** Finalize unit set-up */
error_t USIPO_init(Unit *unit);
/** Tear down the unit */
void USIPO_deInit(Unit *unit);
// ------------------------------------------------------------------------
/**
* Write a buffer to the pins.
* Buffer contains data for the individual channels, sequentially (AAAAAA BBBBBB CCCCCC ...)
* The bytes are sent LSB first, from the last byte (e.g. 1,2,3 - 3 is sent first, LSB-first).
*
* The chunks order is from the lowest to the highest bit
*
* @param unit
* @param buffer - buffer of data to send
* @param buflen - number of bytes in the buffer
* @param terminal_data - data to set before sending the store pulse (final data lines state, will not appear in the SIPOs)
* @return success
*/
error_t UU_SIPO_Write(Unit *unit, const uint8_t *buffer, uint16_t buflen, uint16_t terminal_data);
/**
* Direct access to the output data pins (may be useful for debugging, or circuits that use them
* for something else when not loading a new value).
*
* @param unit
* @param data_packed - packed data to set on the output (right-aligned, highest to lowest pin)
* @return success
*/
error_t UU_SIPO_DirectData(Unit *unit, uint16_t data_packed);
/**
* Send a clear pulse.
*
* @param unit
* @return success
*/
error_t UU_SIPO_DirectClear(Unit *unit);
/**
* Send a shift pulse.
*
* @param unit
* @return success
*/
error_t UU_SIPO_DirectShift(Unit *unit);
/**
* Send a store pulse.
*
* @param unit
* @return success
*/
error_t UU_SIPO_DirectStore(Unit *unit);
#endif //GEX_F072_SIPO_INTERNAL_H
+122
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@@ -0,0 +1,122 @@
//
// Created by MightyPork on 2018/02/03.
//
#include "platform.h"
#include "unit_base.h"
#define SIPO_INTERNAL
#include "_sipo_internal.h"
/** Load from a binary buffer stored in Flash */
void USIPO_loadBinary(Unit *unit, PayloadParser *pp)
{
struct priv *priv = unit->data;
uint8_t version = pp_u8(pp);
(void)version;
priv->store_pname = pp_char(pp);
priv->store_pnum = pp_u8(pp);
priv->store_pol = pp_bool(pp);
priv->shift_pname = pp_char(pp);
priv->shift_pnum = pp_u8(pp);
priv->shift_pol = pp_bool(pp);
priv->clear_pname = pp_char(pp);
priv->clear_pnum = pp_u8(pp);
priv->clear_pol = pp_bool(pp);
priv->data_pname = pp_char(pp);
priv->data_pins = pp_u16(pp);
}
/** Write to a binary buffer for storing in Flash */
void USIPO_writeBinary(Unit *unit, PayloadBuilder *pb)
{
struct priv *priv = unit->data;
pb_u8(pb, 0); // version
pb_char(pb, priv->store_pname);
pb_u8(pb, priv->store_pnum);
pb_bool(pb, priv->store_pol);
pb_char(pb, priv->shift_pname);
pb_u8(pb, priv->shift_pnum);
pb_bool(pb, priv->shift_pol);
pb_char(pb, priv->clear_pname);
pb_u8(pb, priv->clear_pnum);
pb_bool(pb, priv->clear_pol);
pb_char(pb, priv->data_pname);
pb_u16(pb, priv->data_pins);
}
// ------------------------------------------------------------------------
/** Parse a key-value pair from the INI file */
error_t USIPO_loadIni(Unit *unit, const char *key, const char *value)
{
bool suc = true;
struct priv *priv = unit->data;
if (streq(key, "store-pin")) {
suc = parse_pin(value, &priv->store_pname, &priv->store_pnum);
}
else if (streq(key, "shift-pin")) {
suc = parse_pin(value, &priv->shift_pname, &priv->shift_pnum);
}
else if (streq(key, "clear-pin")) {
suc = parse_pin(value, &priv->clear_pname, &priv->clear_pnum);
}
else if (streq(key, "store-pol")) {
priv->store_pol = (bool) avr_atoi(value);
}
else if (streq(key, "shift-pol")) {
priv->shift_pol = (bool) avr_atoi(value);
}
else if (streq(key, "clear-pol")) {
priv->clear_pol = (bool) avr_atoi(value);
}
else if (streq(key, "data-port")) {
suc = parse_port_name(value, &priv->data_pname);
}
else if (streq(key, "data-pins")) {
priv->data_pins = (uint16_t) parse_pinmask(value, &suc);
}
else {
return E_BAD_KEY;
}
if (!suc) return E_BAD_VALUE;
return E_SUCCESS;
}
/** Generate INI file section for the unit */
void USIPO_writeIni(Unit *unit, IniWriter *iw)
{
struct priv *priv = unit->data;
iw_comment(iw, "Shift pin & its active edge (1-rising,0-falling)");
iw_entry(iw, "shift-pin", "%c%d", priv->shift_pname, priv->shift_pnum);
iw_entry(iw, "shift-pol", "%d", priv->shift_pol);
iw_comment(iw, "Store pin & its active edge");
iw_entry(iw, "store-pin", "%c%d", priv->store_pname, priv->store_pnum);
iw_entry(iw, "store-pol", "%d", priv->store_pol);
iw_comment(iw, "Clear pin & its active level");
iw_entry(iw, "clear-pin", "%c%d", priv->clear_pname, priv->clear_pnum);
iw_entry(iw, "clear-pol", "%d", priv->clear_pol);
iw_comment(iw, "Data port and pins");
iw_entry(iw, "data-port", "%c", priv->data_pname);
iw_entry(iw, "data-pins", "%s", pinmask2str_up(priv->data_pins, unit_tmp512));
}
+73
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@@ -0,0 +1,73 @@
//
// Created by MightyPork on 2017/11/25.
//
#include "unit_base.h"
#include "unit_sipo.h"
#define SIPO_INTERNAL
#include "_sipo_internal.h"
// ------------------------------------------------------------------------
enum SipoCmd_ {
CMD_WRITE = 0,
CMD_DIRECT_DATA = 1,
CMD_DIRECT_SHIFT = 2,
CMD_DIRECT_CLEAR = 3,
CMD_DIRECT_STORE = 4,
};
/** Handle a request message */
static error_t USIPO_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, PayloadParser *pp)
{
switch (command) {
case CMD_WRITE:
{
uint32_t len;
uint16_t terminal_packed = pp_u16(pp);
const uint8_t *tail = pp_tail(pp, &len);
TRY(UU_SIPO_Write(unit, (uint8_t *) tail, (uint16_t) len, terminal_packed));
}
return E_SUCCESS;
case CMD_DIRECT_DATA:
TRY(UU_SIPO_DirectData(unit, pp_u16(pp)));
return E_SUCCESS;
case CMD_DIRECT_CLEAR:
TRY(UU_SIPO_DirectClear(unit));
return E_SUCCESS;
case CMD_DIRECT_SHIFT:
TRY(UU_SIPO_DirectShift(unit));
return E_SUCCESS;
case CMD_DIRECT_STORE:
TRY(UU_SIPO_DirectStore(unit));
return E_SUCCESS;
default:
return E_UNKNOWN_COMMAND;
}
}
// ------------------------------------------------------------------------
/** Unit template */
const UnitDriver UNIT_SIPO = {
.name = "SIPO",
.description = "Shift register driver (595, 4094)",
// Settings
.preInit = USIPO_preInit,
.cfgLoadBinary = USIPO_loadBinary,
.cfgWriteBinary = USIPO_writeBinary,
.cfgLoadIni = USIPO_loadIni,
.cfgWriteIni = USIPO_writeIni,
// Init
.init = USIPO_init,
.deInit = USIPO_deInit,
// Function
.handleRequest = USIPO_handleRequest,
};
+16
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@@ -0,0 +1,16 @@
//
// Created by MightyPork on 2017/11/25.
//
// Digital input unit; single or multiple pin read access on one port (A-F)
//
#ifndef U_SIPO_H
#define U_SIPO_H
#include "unit.h"
extern const UnitDriver UNIT_SIPO;
// UU_ prototypes
#endif //U_SIPO_H
+2 -1
View File
@@ -119,9 +119,10 @@ void iw_entry(IniWriter *iw, const char *key, const char *format, ...)
iw_newline(iw); // one newline after entry
}
uint32_t iw_measure_total(void (*handler)(IniWriter *))
uint32_t iw_measure_total(void (*handler)(IniWriter *), uint32_t tag)
{
IniWriter iw = iw_init(NULL, 0xFFFFFFFF, 1);
iw.tag = tag;
iw_begin();
handler(&iw);
iw_end();
+3 -2
View File
@@ -18,6 +18,7 @@ typedef struct iniwriter_ {
char *ptr;
uint32_t skip;
uint32_t count;
uint32_t tag; // general purpose field (used to identify for which purpose is the file being read)
} IniWriter;
/**
@@ -43,7 +44,7 @@ void iw_end(void);
* @param count - number of bytes to write, truncate rest
* @return structure initializer
*/
#define iw_init(buffer, skip, count) (IniWriter){buffer, skip, count}
#define iw_init(xbuffer, xskip, xcount) (IniWriter){.ptr=(xbuffer), .skip=(xskip), .count=(xcount)}
/**
* Try to write a buffer to the file
@@ -131,6 +132,6 @@ void iw_entry(IniWriter *iw, const char *key, const char *format, ...)
* @param handler - function that normally writes to the writer
* @return byte count
*/
uint32_t iw_measure_total(void (*handler)(IniWriter *));
uint32_t iw_measure_total(void (*handler)(IniWriter *), uint32_t tag);
#endif //INIWRITER_H
+3 -3
View File
@@ -73,9 +73,9 @@ void vfs_user_build_filesystem(void)
// Setup the filesystem based on target parameters
vfs_init(daplink_drive_name, 0/*unused "disk size"*/);
vfs_create_file("UNITS INI", read_file_units_ini, NULL, iw_measure_total(settings_build_units_ini));
vfs_create_file("SYSTEM INI", read_file_system_ini, NULL, iw_measure_total(settings_build_system_ini));
vfs_create_file("PINOUT TXT", read_file_pinout_txt, NULL, iw_measure_total(settings_build_pinout_txt));
vfs_create_file("UNITS INI", read_file_units_ini, NULL, iw_measure_total(settings_build_units_ini, 0));
vfs_create_file("SYSTEM INI", read_file_system_ini, NULL, iw_measure_total(settings_build_system_ini, 0));
vfs_create_file("PINOUT TXT", read_file_pinout_txt, NULL, iw_measure_total(settings_build_pinout_txt, 0));
}