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basic work on uart

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This commit is contained in:
MightyPork
2018-01-13 19:49:12 +01:00
parent 8852f9f8b4
commit d49081b190
13 changed files with 275 additions and 140 deletions
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platform/debug_uart.c
+80 -33
View File
@@ -6,26 +6,94 @@
#include "framework/resources.h"
#include "debug_uart.h"
#include "plat_compat.h"
#include "pin_utils.h"
#if USE_DEBUG_UART
#define DEBUG_USART_BAUD 115200
#if GEX_PLAT_F072_DISCOVERY
#define DEBUG_USART USART1
#define DEBUG_USART_RSC R_USART1
#define DEBUG_USART_PORT 'A'
#define DEBUG_USART_PIN 9
#define DEBUG_USART_AF 1
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#elif GEX_PLAT_F103_BLUEPILL
#define DEBUG_USART USART2
#define DEBUG_USART_RSC R_USART2
#define DEBUG_USART_PORT 'A'
#define DEBUG_USART_PIN 2
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#elif GEX_PLAT_F303_DISCOVERY
#define DEBUG_USART USART3
#define DEBUG_USART_RSC R_USART3
#define DEBUG_USART_PORT 'D'
#define DEBUG_USART_PIN 8
#define DEBUG_USART_AF 7
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#elif GEX_PLAT_F407_DISCOVERY
#define DEBUG_USART USART2
#define DEBUG_USART_RSC R_USART2
#define DEBUG_USART_PORT 'A'
#define DEBUG_USART_PIN 2
#define DEBUG_USART_AF 7
#define DEBUG_USART_PCLK PLAT_APB1_HZ
#else
#error "BAD PLATFORM!"
#endif
/** Init the submodule. */
void DebugUart_Init(void)
{
bool suc = true;
// Debug UART
assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, R_USART2));
assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, R_PA2));
assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, DEBUG_USART_RSC));
assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, pin2resource(DEBUG_USART_PORT, DEBUG_USART_PIN, &suc)));
assert_param(suc);
}
/** Init the hardware peripheral - this is called early in the boot process */
void DebugUart_PreInit(void)
{
__HAL_RCC_USART2_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
// configure AF only if platform uses AF numbers
#if !PLAT_NO_AFNUM
configure_gpio_alternate(DEBUG_USART_PORT, DEBUG_USART_PIN, DEBUG_USART_AF);
#endif
LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_2, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetPinOutputType(GPIOA, LL_GPIO_PIN_2, LL_GPIO_OUTPUT_PUSHPULL);
LL_GPIO_SetPinSpeed(GPIOA, LL_GPIO_PIN_2, LL_GPIO_SPEED_FREQ_HIGH);
if (DEBUG_USART == USART1) {
__HAL_RCC_USART1_CLK_ENABLE();
}
else if (DEBUG_USART == USART2) {
__HAL_RCC_USART2_CLK_ENABLE();
}
else if (DEBUG_USART == USART3) {
__HAL_RCC_USART3_CLK_ENABLE();
}
#ifdef USART4
else if (DEBUG_USART == USART4) {
__HAL_RCC_USART4_CLK_ENABLE();
}
#endif
#ifdef USART5
else if (DEBUG_USART == USART5) {
__HAL_RCC_USART5_CLK_ENABLE();
}
#endif
// LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_2, LL_GPIO_MODE_ALTERNATE);
// LL_GPIO_SetPinOutputType(GPIOA, LL_GPIO_PIN_2, LL_GPIO_OUTPUT_PUSHPULL);
// LL_GPIO_SetPinSpeed(GPIOA, LL_GPIO_PIN_2, LL_GPIO_SPEED_FREQ_HIGH);
// commented out default values
// LL_USART_ConfigAsyncMode(USART2);
@@ -33,30 +101,9 @@ void DebugUart_PreInit(void)
// LL_USART_SetParity(USART2, LL_USART_PARITY_NONE);
// LL_USART_SetStopBitsLength(USART2, LL_USART_STOPBITS_1);
// LL_USART_SetHWFlowCtrl(USART2, LL_USART_HWCONTROL_NONE);
LL_USART_EnableDirectionTx(USART2);
#if GEX_PLAT_F072_DISCOVERY
LL_USART_SetBaudRate(USART2, SystemCoreClock, LL_USART_OVERSAMPLING_16, 115200); // This is not great, let's hope it's like this on all platforms...
LL_GPIO_SetAFPin_0_7(GPIOA, LL_GPIO_PIN_2, LL_GPIO_AF_1);
#elif GEX_PLAT_F103_BLUEPILL
LL_USART_SetBaudRate(USART2, SystemCoreClock/2, 115200); // This is not great, let's hope it's like this on all platforms...
#elif GEX_PLAT_F303_DISCOVERY
LL_USART_SetBaudRate(USART2,
LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE),
LL_USART_OVERSAMPLING_16,
115200);
LL_GPIO_SetAFPin_0_7(GPIOA, LL_GPIO_PIN_2, LL_GPIO_AF_7); // uart2 is AF7 here
#elif GEX_PLAT_F407_DISCOVERY
LL_USART_SetBaudRate(USART2,
SystemCoreClock/4, // if core is at 168 MHz, this is 48 MHz
LL_USART_OVERSAMPLING_16,
115200);
LL_GPIO_SetAFPin_0_7(GPIOA, LL_GPIO_PIN_2, LL_GPIO_AF_7); // uart2 is AF7 here (same like 303)
#else
#error "BAD PLATFORM!"
#endif
LL_USART_Enable(USART2);
LL_USART_EnableDirectionTx(DEBUG_USART);
LL_USART_SetBaudRate(DEBUG_USART, DEBUG_USART_PCLK, LL_USART_OVERSAMPLING_16, DEBUG_USART_BAUD);
LL_USART_Enable(DEBUG_USART);
}
/** Debug print, used by debug / newlib */
@@ -67,8 +114,8 @@ ssize_t _write_r(struct _reent *rptr, int fd, const void *buf, size_t len)
uint8_t *buff = buf;
for (uint32_t i = 0; i < len; i++) {
while (!LL_USART_IsActiveFlag_TC(USART2));
LL_USART_TransmitData8(USART2, *buff++);
while (!LL_USART_IsActiveFlag_TC(DEBUG_USART));
LL_USART_TransmitData8(DEBUG_USART, *buff++);
}
return len;
platform/pin_utils.c
+1 -1
View File
@@ -266,7 +266,7 @@ void deinit_unit_pins(Unit *unit)
{
for (uint32_t rsc = R_PA0; rsc <= R_PF15; rsc++) {
if (RSC_IS_HELD(unit->resources, rsc)) {
// dbg("Freeing pin %s", rsc_get_name((Resource)rsc));
rsc_dbg("Freeing pin %s", rsc_get_name((Resource)rsc));
GPIO_TypeDef *port = port_periphs[(rsc-R_PA0) / 16];
uint32_t ll_pin = ll_pins[(rsc-R_PA0)%16];
LL_GPIO_SetPinMode(port, ll_pin, LL_GPIO_MODE_ANALOG);
platform/pin_utils.h
+7
View File
@@ -126,4 +126,11 @@ error_t configure_gpio_alternate(char port_name, uint8_t pin_num, uint32_t ll_af
*/
error_t configure_sparse_pins(char port_name, uint16_t mask, GPIO_TypeDef **port_dest, uint32_t ll_mode, uint32_t ll_otype);
/** Helper struct for defining alternate mappings */
struct PinAF {
char port;
uint8_t pin;
uint8_t af;
};
#endif //GEX_PIN_UTILS_H
platform/plat_compat.h
+14 -2
View File
@@ -12,13 +12,13 @@
#if DISABLE_MSC
#define TSK_STACK_MAIN 100 // without MSC the stack usage is significantly lower
#else
#define TSK_STACK_MAIN 160
#define TSK_STACK_MAIN 170
#endif
#define TSK_STACK_MSG 220 // TF message handler task stack size (all unit commands run on this thread)
#define BULK_READ_BUF_LEN 256 // Buffer for TF bulk reads
#define UNIT_TMP_LEN 512 // Buffer for bulk read and varions internal unit operations
#define UNIT_TMP_LEN 512 // Buffer for bulk read and various internal unit operations
#define FLASH_SAVE_BUF_LEN 128 // Static buffer for saving to flash
@@ -57,16 +57,19 @@
// PLAT_USB_OTGFS - uses the USB OTG IP, needs different config code
// PLAT_LOCK_BTN - use a lock button instead of a lock jumper (push to toggle)
// PLAT_LOCK_1CLOSED - lock jumper is active (closed / button pressed) in logical 1
// PLAT_NO_AFNUM - legacy platform without numbered AF alternatives
#if defined(GEX_PLAT_F103_BLUEPILL)
// platform name for the version string
#define GEX_PLATFORM "STM32F103-Bluepill"
#define PLAT_AHB_MHZ 72
#define PLAT_APB1_MHZ 36
// feature flags
#define PLAT_FLASHBANKS 1
#define PLAT_NO_FLOATING_INPUTS 1
#define PLAT_NO_AFNUM 1
#include <stm32f1xx.h>
#include <stm32f1xx_hal.h>
@@ -114,6 +117,7 @@
// platform name for the version string
#define GEX_PLATFORM "STM32F072-Discovery"
#define PLAT_AHB_MHZ 48
#define PLAT_APB1_MHZ 48
#include <stm32f0xx.h>
#include <stm32f0xx_ll_adc.h>
@@ -161,6 +165,8 @@
// platform name for the version string
#define GEX_PLATFORM "STM32F303-Discovery"
#define PLAT_AHB_MHZ 72
#define PLAT_APB1_MHZ 36
#define PLAT_APB2_MHZ 72
#include <stm32f3xx.h>
#include <stm32f3xx_hal.h>
@@ -211,6 +217,8 @@
// platform name for the version string
#define GEX_PLATFORM "STM32F407-Discovery"
#define PLAT_AHB_MHZ 168
#define PLAT_APB1_MHZ 48
#define PLAT_APB2_MHZ 96
#define PLAT_USB_PHYCLOCK 1
#define PLAT_USB_OTGFS 1
@@ -263,4 +271,8 @@
#error "BAD PLATFORM! Please select GEX platform using a -DGEX_PLAT_* compile flag"
#endif
#define PLAT_AHB_HZ (PLAT_AHB_MHZ*1000000)
#define PLAT_APB1_HZ (PLAT_APB1_MHZ*1000000)
#define PLAT_APB2_HZ (PLAT_APB2_MHZ*1000000)
#endif //GEX_PLAT_COMPAT_H
platform/platform.c
+12 -11
View File
@@ -14,23 +14,23 @@
#include "units/neopixel/unit_neopixel.h"
#include "units/i2c/unit_i2c.h"
#include "units/test/unit_test.h"
#include "units/usart/unit_uart.h"
#include "units/usart/unit_usart.h"
#include "units/spi/unit_spi.h"
void plat_init_resources(void)
{
uint32_t rv = 0;
// switch everything ON (we should not write reserved bits, but nothing bad seems to happen)
RCC->APB1ENR = 0xFFFFFFFF;
RCC->APB2ENR = 0xFFFFFFFF;
RCC->AHBENR = 0xFFFFFFFF; // GPIOs are here
// __HAL_RCC_GPIOA_CLK_ENABLE();
// __HAL_RCC_GPIOB_CLK_ENABLE();
// __HAL_RCC_GPIOC_CLK_ENABLE();
// __HAL_RCC_GPIOD_CLK_ENABLE();
// __HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
#ifdef GPIOE
__HAL_RCC_GPIOE_CLK_ENABLE();
#endif
#ifdef GPIOF
__HAL_RCC_GPIOF_CLK_ENABLE();
#endif
// --- Common unit drivers ---
@@ -103,6 +103,7 @@ void plat_init_resources(void)
rsc_free_range(NULL, R_TIM6, R_TIM7);
rsc_free_range(NULL, R_TIM14, R_TIM17);
rsc_free_range(NULL, R_USART1, R_USART4);
rsc_free_range(NULL, R_DMA1_1, R_DMA1_7);
rsc_free_range(NULL, R_PA0, R_PA15);
rsc_free_range(NULL, R_PB0, R_PB15);