commit
bbbd216244
GPG Key ID:
2C5FD5035250423D
@ -0,0 +1,378 @@ |
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//
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// Created by MightyPork on 2018/01/14.
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//
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#include <stm32f072xb.h> |
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#include "platform.h" |
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#include "irq_dispatcher.h" |
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void irqd_init(void) |
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{ |
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// NVIC_EnableIRQ(WWDG_IRQn); /*!< Window WatchDog Interrupt */
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// NVIC_EnableIRQ(PVD_VDDIO2_IRQn); /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */
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// NVIC_EnableIRQ(RTC_IRQn); /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
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// NVIC_EnableIRQ(FLASH_IRQn); /*!< FLASH global Interrupt */
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// NVIC_EnableIRQ(RCC_CRS_IRQn); /*!< RCC & CRS global Interrupt */
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// NVIC_EnableIRQ(EXTI0_1_IRQn); /*!< EXTI Line 0 and 1 Interrupt */
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// NVIC_EnableIRQ(EXTI2_3_IRQn); /*!< EXTI Line 2 and 3 Interrupt */
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// NVIC_EnableIRQ(EXTI4_15_IRQn); /*!< EXTI Line 4 to 15 Interrupt */
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// NVIC_EnableIRQ(TSC_IRQn); /*!< Touch Sensing Controller Interrupts */
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NVIC_EnableIRQ(DMA1_Channel1_IRQn); /*!< DMA1 Channel 1 Interrupt */ |
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NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); /*!< DMA1 Channel 2 and Channel 3 Interrupt */ |
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NVIC_EnableIRQ(DMA1_Channel4_5_6_7_IRQn); /*!< DMA1 Channel 4 to Channel 7 Interrupt */ |
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HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 3, 0); |
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HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3, 0); |
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HAL_NVIC_SetPriority(DMA1_Channel4_5_6_7_IRQn, 3, 0); |
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// NVIC_EnableIRQ(ADC1_COMP_IRQn); /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
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// NVIC_EnableIRQ(TIM2_IRQn); /*!< TIM2 global Interrupt */
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// NVIC_EnableIRQ(TIM3_IRQn); /*!< TIM3 global Interrupt */
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// NVIC_EnableIRQ(TIM6_DAC_IRQn); /*!< TIM6 global and DAC channel underrun error Interrupt */
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// NVIC_EnableIRQ(TIM7_IRQn); /*!< TIM7 global Interrupt */
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// NVIC_EnableIRQ(TIM14_IRQn); /*!< TIM14 global Interrupt */
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// NVIC_EnableIRQ(TIM15_IRQn); /*!< TIM15 global Interrupt */
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// NVIC_EnableIRQ(TIM16_IRQn); /*!< TIM16 global Interrupt */
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// NVIC_EnableIRQ(TIM17_IRQn); /*!< TIM17 global Interrupt */
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// NVIC_EnableIRQ(I2C1_IRQn); /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
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// NVIC_EnableIRQ(I2C2_IRQn); /*!< I2C2 Event Interrupt */
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// NVIC_EnableIRQ(SPI1_IRQn); /*!< SPI1 global Interrupt */
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// NVIC_EnableIRQ(SPI2_IRQn); /*!< SPI2 global Interrupt */
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NVIC_EnableIRQ(USART1_IRQn); /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ |
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NVIC_EnableIRQ(USART2_IRQn); /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ |
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NVIC_EnableIRQ(USART3_4_IRQn); /*!< USART3 and USART4 global Interrupt */ |
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HAL_NVIC_SetPriority(USART1_IRQn, 3, 0); |
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HAL_NVIC_SetPriority(USART2_IRQn, 3, 0); |
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HAL_NVIC_SetPriority(USART3_4_IRQn, 3, 0); |
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// NVIC_EnableIRQ(CEC_CAN_IRQn); /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
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// NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ // - handled by hal msp init
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// NVIC_EnableIRQ(TIM1_CC_IRQn); /*!< TIM1 Capture Compare Interrupt */
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// NVIC_EnableIRQ(USB_IRQn); /*!< USB global Interrupt & EXTI Line18 Interrupt */ // - USB IRQ is handled by the USB library
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} |
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//void Default_Handler(void)
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//{
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// warn("Missing IRQHandler, ISPR[0]=0x%p", (void*)NVIC->ISPR[0]);
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//}
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struct cbslot { |
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IrqCallback callback; |
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void *arg; |
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}; |
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static struct callbacks_ { |
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struct cbslot usart1; |
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struct cbslot usart2; |
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struct cbslot usart3; |
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#ifdef USART4 |
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struct cbslot usart4; |
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#endif |
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#ifdef USART5 |
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struct cbslot usart5; |
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#endif |
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struct cbslot dma1_1; |
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struct cbslot dma1_2; |
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struct cbslot dma1_3; |
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struct cbslot dma1_4; |
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struct cbslot dma1_5; |
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struct cbslot dma1_6; |
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struct cbslot dma1_7; |
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struct cbslot dma1_8; |
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struct cbslot dma2_1; |
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struct cbslot dma2_2; |
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struct cbslot dma2_3; |
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struct cbslot dma2_4; |
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struct cbslot dma2_5; |
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struct cbslot dma2_6; |
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struct cbslot dma2_7; |
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struct cbslot dma2_8; |
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// XXX add more callbacks here when needed
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} callbacks = {0}; |
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static struct cbslot *get_slot_for_periph(void *periph) |
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{ |
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struct cbslot *slot = NULL; |
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// --- USART ---
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if (periph == USART1) slot = &callbacks.usart1; |
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else if (periph == USART2) slot = &callbacks.usart2; |
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else if (periph == USART3) slot = &callbacks.usart3; |
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#ifdef USART4 |
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else if (periph == USART4) slot = &callbacks.usart4; |
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#endif |
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#ifdef USART5 |
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else if (periph == USART5) slot = &callbacks.usart5; |
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#endif |
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// --- DMA1 ---
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else if (periph == DMA1_Channel1) slot = &callbacks.dma1_1; |
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else if (periph == DMA1_Channel2) slot = &callbacks.dma1_2; |
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else if (periph == DMA1_Channel3) slot = &callbacks.dma1_3; |
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else if (periph == DMA1_Channel4) slot = &callbacks.dma1_4; |
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else if (periph == DMA1_Channel5) slot = &callbacks.dma1_5; |
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else if (periph == DMA1_Channel6) slot = &callbacks.dma1_6; |
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else if (periph == DMA1_Channel7) slot = &callbacks.dma1_7; |
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#ifdef DMA1_Channel8 |
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else if (periph == DMA1_Channel7) slot = &callbacks.dma1_8; |
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#endif |
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// --- DMA2 ---
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#ifdef DMA2 |
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else if (periph == DMA2_Channel1) slot = &callbacks.dma2_1; |
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else if (periph == DMA2_Channel2) slot = &callbacks.dma2_2; |
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else if (periph == DMA2_Channel3) slot = &callbacks.dma2_3; |
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else if (periph == DMA2_Channel4) slot = &callbacks.dma2_4; |
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else if (periph == DMA2_Channel5) slot = &callbacks.dma2_5; |
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#ifdef DMA2_Channel6 |
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else if (periph == DMA2_Channel6) slot = &callbacks.dma2_6; |
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#endif |
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#ifdef DMA2_Channel7 |
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else if (periph == DMA2_Channel7) slot = &callbacks.dma2_7; |
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#endif |
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#ifdef DMA2_Channel8 |
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else if (periph == DMA2_Channel7) slot = &callbacks.dma2_8; |
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#endif |
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#endif |
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else { |
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trap("No IRQ cb slot for periph 0x%p", periph); |
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} |
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return slot; |
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} |
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void irqd_attach(void *periph, IrqCallback callback, void *arg) |
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{ |
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struct cbslot *slot = get_slot_for_periph(periph); |
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assert_param(slot->callback == NULL); |
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slot->callback = callback; |
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slot->arg = arg; |
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} |
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void irqd_detach(void *periph, IrqCallback callback) |
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{ |
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struct cbslot *slot = get_slot_for_periph(periph); |
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if (slot->callback == callback) { |
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slot->callback = NULL; |
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slot->arg = NULL; |
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} |
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} |
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#define CALL_IRQ_HANDLER(slot) do { if (slot.callback) slot.callback(slot.arg); } while (0) |
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void USART1_IRQHandler(void) |
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{ |
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CALL_IRQ_HANDLER(callbacks.usart1); |
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} |
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void USART2_IRQHandler(void) |
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{ |
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CALL_IRQ_HANDLER(callbacks.usart2); |
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} |
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#if 0 |
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static bool usart_check_irq(USART_TypeDef *USARTx) |
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{ |
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uint32_t isrflags = USARTx->ISR; |
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uint32_t cr1its = USARTx->CR1; |
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uint32_t cr2its = USARTx->CR2; |
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uint32_t cr3its = USARTx->CR3; |
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if ((cr1its & USART_CR1_RTOIE) && (isrflags & USART_ISR_RTOF)) return true; |
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if ((cr1its & USART_CR1_RXNEIE) && (isrflags & USART_ISR_RXNE)) return true; |
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if ((cr1its & USART_CR1_TCIE) && (isrflags & USART_ISR_TC)) return true; |
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if ((cr1its & USART_CR1_TXEIE) && (isrflags & USART_ISR_TXE)) return true; |
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if ((cr3its & USART_CR3_EIE) && (isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE))) return true; |
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if ((cr1its & USART_CR1_IDLEIE) && (isrflags & USART_ISR_IDLE)) return true; |
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if ((cr1its & USART_CR1_PEIE) && (isrflags & USART_ISR_PE)) return true; |
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if ((cr1its & USART_CR1_CMIE) && (isrflags & USART_ISR_CMF)) return true; |
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if ((cr1its & USART_CR1_EOBIE) && (isrflags & USART_ISR_EOBF)) return true; |
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if ((cr2its & USART_CR2_LBDIE) && (isrflags & USART_ISR_LBDF)) return true; |
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if ((cr3its & USART_CR3_CTSIE) && (isrflags & USART_ISR_CTS)) return true; |
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if ((cr3its & USART_CR3_WUFIE) && (isrflags & USART_ISR_WUF)) return true; |
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return false; |
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} |
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#endif |
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void USART3_4_IRQHandler(void) |
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{ |
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// we won't check the flags here, both can be pending and it's better to let the handler deal with it
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CALL_IRQ_HANDLER(callbacks.usart3); |
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CALL_IRQ_HANDLER(callbacks.usart4); |
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} |
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void DMA1_Channel1_IRQHandler(void) |
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{ |
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CALL_IRQ_HANDLER(callbacks.dma1_1); |
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} |
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void DMA1_Channel2_3_IRQHandler(void) |
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{ |
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if (LL_DMA_IsActiveFlag_GI2(DMA1)) CALL_IRQ_HANDLER(callbacks.dma1_2); |
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if (LL_DMA_IsActiveFlag_GI3(DMA1)) CALL_IRQ_HANDLER(callbacks.dma1_3); |
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} |
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void DMA1_Channel4_5_6_7_IRQHandler(void) |
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{ |
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if (LL_DMA_IsActiveFlag_GI4(DMA1)) CALL_IRQ_HANDLER(callbacks.dma1_4); |
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if (LL_DMA_IsActiveFlag_GI5(DMA1)) CALL_IRQ_HANDLER(callbacks.dma1_5); |
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if (LL_DMA_IsActiveFlag_GI6(DMA1)) CALL_IRQ_HANDLER(callbacks.dma1_6); |
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if (LL_DMA_IsActiveFlag_GI7(DMA1)) CALL_IRQ_HANDLER(callbacks.dma1_7); |
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} |
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#if 0 |
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void WWDG_IRQHandler(void) |
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{ |
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//
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} |
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void PVD_VDDIO2_IRQHandler(void) |
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{ |
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//
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} |
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void RTC_IRQHandler(void) |
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{ |
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//
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} |
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void FLASH_IRQHandler(void) |
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{ |
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//
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} |
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void RCC_CRS_IRQHandler(void) |
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{ |
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//
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} |
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void EXTI0_1_IRQHandler(void) |
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{ |
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//
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} |
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void EXTI2_3_IRQHandler(void) |
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{ |
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//
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} |
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void EXTI4_15_IRQHandler(void) |
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{ |
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//
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} |
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void TSC_IRQHandler(void) |
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{ |
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//
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} |
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void ADC1_COMP_IRQHandler(void) |
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{ |
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//
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} |
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void TIM1_BRK_UP_TRG_COM_IRQHandler(void) |
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{ |
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//
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} |
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void TIM1_CC_IRQHandler(void) |
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{ |
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//
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} |
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void TIM2_IRQHandler(void) |
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{ |
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//
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} |
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void TIM3_IRQHandler(void) |
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{ |
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//
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} |
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// not on F072
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void TIM4_IRQHandler(void) |
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{ |
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//
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} |
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// not on F072
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void TIM5_IRQHandler(void) |
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{ |
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//
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} |
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void TIM6_DAC_IRQHandler(void) |
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{ |
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//
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} |
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void TIM7_IRQHandler(void) |
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{ |
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//
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} |
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void TIM8_IRQHandler(void) |
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{ |
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//
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} |
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void TIM9_IRQHandler(void) |
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{ |
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//
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} |
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void TIM10_IRQHandler(void) |
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{ |
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//
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} |
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void TIM11_IRQHandler(void) |
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{ |
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//
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} |
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void TIM12_IRQHandler(void) |
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{ |
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//
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} |
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void TIM13_IRQHandler(void) |
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{ |
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//
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} |
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void TIM14_IRQHandler(void) |
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{ |
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//
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} |
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void TIM15_IRQHandler(void) |
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{ |
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//
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} |
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void TIM16_IRQHandler(void) |
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{ |
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//
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} |
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void TIM17_IRQHandler(void) |
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{ |
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//
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} |
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void CEC_CAN_IRQHandler(void) |
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{ |
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//
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} |
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// USB is handled by the USB driver
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//void USB_IRQHandler(void)
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//{
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// //
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//}
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#endif |
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@ -0,0 +1,39 @@ |
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//
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// Created by MightyPork on 2018/01/14.
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//
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#ifndef GEX_F072_IRQ_DISPATCHER_H |
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#define GEX_F072_IRQ_DISPATCHER_H |
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/**
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* Initialize the interrupt dispatcher |
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*/ |
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void irqd_init(void); |
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/** Typedef for a IRQ callback run by the dispatcher */ |
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typedef void (*IrqCallback)(void*); |
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/**
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* Attach a callback to a IRQ handler. |
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* Pass NULL to remove the handler. |
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* |
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* NOTE: The handler is responsible for clearing any interrupt status flags. |
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* NOTE: It is not guaranteed that the particular peripheral caused the interrupt when |
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* the function is called; some interrupt vectors are shared. Make sure to check the flags. |
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* |
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* @param periph - peripheral we're attaching to |
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* @param callback - callback to fire on IRQ |
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* @param data - data passed to the callback (user context) |
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*/ |
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void irqd_attach(void *periph, IrqCallback callback, void *data); |
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/**
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* Remove a callback |
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* |
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* @param periph - peripheral we're attaching to |
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* @param callback - callback to remove, if it doesn't match, do nothing |
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*/ |
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void irqd_detach(void *periph, IrqCallback callback); |
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#endif //GEX_F072_IRQ_DISPATCHER_H
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@ -0,0 +1,444 @@ |
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//
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// Created by MightyPork on 2018/01/14.
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//
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#include "platform.h" |
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#include "irq_dispatcher.h" |
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#include "unit_base.h" |
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#define UUSART_INTERNAL |
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#include "_internal.h" |
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static void UUSART_DMA_RxHandler(void *arg); |
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static void UUSART_DMA_TxHandler(void *arg); |
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#if UUSART_DEBUG |
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#define dbg_uusart(fmt, ...) dbg(fmt, ##__VA_ARGS__) |
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#else |
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#define dbg_uusart(fmt, ...) |
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#endif |
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error_t UUSART_ClaimDMAs(Unit *unit) |
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{ |
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error_t rv; |
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assert_param(unit); |
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struct priv *priv = unit->data; |
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assert_param(priv); |
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priv->dma = DMA1; |
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switch (priv->periph_num) { |
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/* USART1 */ |
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case 1: |
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// TX
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rv = rsc_claim(unit, R_DMA1_2); |
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if (rv == E_SUCCESS) { |
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LL_SYSCFG_SetRemapDMA_USART(LL_SYSCFG_USART1TX_RMP_DMA1CH2); |
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priv->dma_tx = DMA1_Channel2; |
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priv->dma_tx_chnum = 2; |
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} else { |
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// try the remap
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TRY(rsc_claim(unit, R_DMA1_4)); |
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LL_SYSCFG_SetRemapDMA_USART(LL_SYSCFG_USART1TX_RMP_DMA1CH4); |
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priv->dma_tx = DMA1_Channel4; |
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priv->dma_tx_chnum = 4; |
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} |
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// RX
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rv = rsc_claim(unit, R_DMA1_3); |
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if (rv == E_SUCCESS) { |
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LL_SYSCFG_SetRemapDMA_USART(LL_SYSCFG_USART1RX_RMP_DMA1CH3); |
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priv->dma_rx = DMA1_Channel3; |
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priv->dma_rx_chnum = 3; |
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} else { |
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// try the remap
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TRY(rsc_claim(unit, R_DMA1_5)); |
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LL_SYSCFG_SetRemapDMA_USART(LL_SYSCFG_USART1RX_RMP_DMA1CH5); |
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priv->dma_rx = DMA1_Channel5; |
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priv->dma_rx_chnum = 5; |
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} |
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break; |
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/* USART2 */ |
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case 2: |
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// RX,TX
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rv = rsc_claim_range(unit, R_DMA1_4, R_DMA1_5); |
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if (rv == E_SUCCESS) { |
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LL_SYSCFG_SetRemapDMA_USART(LL_SYSCFG_USART2_RMP_DMA1CH54); |
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priv->dma_tx = DMA1_Channel4; |
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priv->dma_rx = DMA1_Channel5; |
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priv->dma_tx_chnum = 4; |
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priv->dma_rx_chnum = 5; |
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} else { |
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// try the remap
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TRY(rsc_claim_range(unit, R_DMA1_6, R_DMA1_7)); |
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LL_SYSCFG_SetRemapDMA_USART(LL_SYSCFG_USART2_RMP_DMA1CH67); |
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priv->dma_tx = DMA1_Channel7; |
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priv->dma_rx = DMA1_Channel6; |
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priv->dma_tx_chnum = 7; |
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priv->dma_rx_chnum = 6; |
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} |
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break; |
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/* USART3 */ |
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case 3: |
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// RX,TX
|
||||
rv = rsc_claim_range(unit, R_DMA1_6, R_DMA1_7); |
||||
if (rv == E_SUCCESS) { |
||||
LL_SYSCFG_SetRemapDMA_USART(LL_SYSCFG_USART3_RMP_DMA1CH67); |
||||
priv->dma_tx = DMA1_Channel7; |
||||
priv->dma_rx = DMA1_Channel6; |
||||
priv->dma_tx_chnum = 7; |
||||
priv->dma_rx_chnum = 6; |
||||
} else { |
||||
// try the remap
|
||||
TRY(rsc_claim_range(unit, R_DMA1_2, R_DMA1_3)); |
||||
LL_SYSCFG_SetRemapDMA_USART(LL_SYSCFG_USART3_RMP_DMA1CH32); |
||||
priv->dma_tx = DMA1_Channel2; |
||||
priv->dma_rx = DMA1_Channel3; |
||||
priv->dma_tx_chnum = 2; |
||||
priv->dma_rx_chnum = 3; |
||||
} |
||||
break; |
||||
|
||||
/* USART4 */ |
||||
case 4: |
||||
// RX,TX
|
||||
TRY(rsc_claim_range(unit, R_DMA1_6, R_DMA1_7)); |
||||
priv->dma_tx = DMA1_Channel7; |
||||
priv->dma_rx = DMA1_Channel6; |
||||
priv->dma_tx_chnum = 7; |
||||
priv->dma_rx_chnum = 6; |
||||
break; |
||||
|
||||
default: |
||||
trap("Missing DMA mapping for USART%d", (int)priv->periph_num); |
||||
} |
||||
|
||||
dbg_uusart("USART %d - selected DMA ch Tx(%d), Rx(%d)", priv->periph_num, priv->dma_tx_chnum, priv->dma_rx_chnum); |
||||
|
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
error_t UUSART_SetupDMAs(Unit *unit) |
||||
{ |
||||
assert_param(unit); |
||||
struct priv *priv = unit->data; |
||||
assert_param(priv); |
||||
|
||||
priv->rx_buffer = malloc_ck(UUSART_RXBUF_LEN); |
||||
if (NULL == priv->rx_buffer) return E_OUT_OF_MEM; |
||||
|
||||
priv->tx_buffer = malloc_ck(UUSART_TXBUF_LEN); |
||||
if (NULL == priv->tx_buffer) return E_OUT_OF_MEM; |
||||
|
||||
// Those must be aligned to a word boundary for the DMAs to work.
|
||||
// Any well-behaved malloc impl should do this correctly.
|
||||
assert_param(((uint32_t)priv->rx_buffer & 3) == 0); |
||||
assert_param(((uint32_t)priv->tx_buffer & 3) == 0); |
||||
|
||||
priv->rx_buf_readpos = 0; |
||||
|
||||
LL_DMA_InitTypeDef init; |
||||
|
||||
// Transmit buffer
|
||||
{ |
||||
LL_DMA_StructInit(&init); |
||||
init.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH; |
||||
init.Mode = LL_DMA_MODE_NORMAL; |
||||
|
||||
init.PeriphOrM2MSrcAddress = (uint32_t) &priv->periph->TDR; |
||||
init.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; |
||||
init.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; |
||||
|
||||
init.MemoryOrM2MDstAddress = (uint32_t) priv->tx_buffer; |
||||
init.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; |
||||
init.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; |
||||
|
||||
assert_param(SUCCESS == LL_DMA_Init(priv->dma, priv->dma_tx_chnum, &init)); |
||||
|
||||
irqd_attach(priv->dma_tx, UUSART_DMA_TxHandler, unit); |
||||
// Interrupt on transfer complete
|
||||
LL_DMA_EnableIT_TC(priv->dma, priv->dma_tx_chnum); |
||||
} |
||||
|
||||
// Receive buffer
|
||||
{ |
||||
LL_DMA_StructInit(&init); |
||||
init.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; |
||||
|
||||
init.Mode = LL_DMA_MODE_CIRCULAR; |
||||
init.NbData = UUSART_RXBUF_LEN; |
||||
|
||||
init.PeriphOrM2MSrcAddress = (uint32_t) &priv->periph->RDR; |
||||
init.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; |
||||
init.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; |
||||
|
||||
init.MemoryOrM2MDstAddress = (uint32_t) priv->rx_buffer; |
||||
init.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; |
||||
init.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; |
||||
|
||||
assert_param(SUCCESS == LL_DMA_Init(priv->dma, priv->dma_rx_chnum, &init)); |
||||
|
||||
irqd_attach(priv->dma_rx, UUSART_DMA_RxHandler, unit); |
||||
// Interrupt on transfer 1/2 and complete
|
||||
// We will capture the first and second half and send it while the other half is being filled.
|
||||
LL_DMA_EnableIT_HT(priv->dma, priv->dma_rx_chnum); |
||||
LL_DMA_EnableIT_TC(priv->dma, priv->dma_rx_chnum); |
||||
} |
||||
|
||||
LL_DMA_EnableChannel(priv->dma, priv->dma_rx_chnum); |
||||
LL_DMA_EnableChannel(priv->dma, priv->dma_tx_chnum); |
||||
|
||||
// TODO also set up usart timeout interrupt that grabs whatever is in the DMA buffer and sends it
|
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
/**
|
||||
* Handler for the Rx DMA half or full interrupt |
||||
* @param arg - unit instance |
||||
*/ |
||||
static void UUSART_DMA_RxHandler(void *arg) |
||||
{ |
||||
Unit *unit = arg; |
||||
assert_param(unit); |
||||
struct priv *priv = unit->data; |
||||
assert_param(priv); |
||||
|
||||
uint32_t isrsnapshot = priv->dma->ISR; |
||||
|
||||
if (LL_DMA_IsActiveFlag_G(isrsnapshot, priv->dma_rx_chnum)) { |
||||
bool tc = LL_DMA_IsActiveFlag_TC(isrsnapshot, priv->dma_rx_chnum); |
||||
bool ht = LL_DMA_IsActiveFlag_HT(isrsnapshot, priv->dma_rx_chnum); |
||||
|
||||
// Here we have to either copy it somewhere else, or notify another thread (queue?)
|
||||
// that the data is ready for reading
|
||||
|
||||
if (ht) { |
||||
uint16_t end = (uint16_t) UUSART_RXBUF_LEN / 2; |
||||
UUSART_DMA_HandleRxFromIRQ(unit, end); |
||||
LL_DMA_ClearFlag_HT(priv->dma, priv->dma_rx_chnum); |
||||
} |
||||
|
||||
if (tc) { |
||||
uint16_t end = (uint16_t) UUSART_RXBUF_LEN; |
||||
UUSART_DMA_HandleRxFromIRQ(unit, end); |
||||
LL_DMA_ClearFlag_TC(priv->dma, priv->dma_rx_chnum); |
||||
} |
||||
|
||||
if (LL_DMA_IsActiveFlag_TE(isrsnapshot, priv->dma_rx_chnum)) { |
||||
// this shouldn't happen
|
||||
LL_DMA_ClearFlag_TE(priv->dma, priv->dma_rx_chnum); |
||||
} |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* Start sending a chunk of data. |
||||
* This must be called when the DMA is completed. |
||||
* |
||||
* @param priv |
||||
*/ |
||||
static void UUSART_DMA_TxStart(struct priv *priv) |
||||
{ |
||||
priv->tx_dma_busy = true; |
||||
assert_param(priv->dma_tx->CNDTR == 0); |
||||
|
||||
dbg_uusart("DMA_TxStart (nr %d, nw %d)", (int)priv->tx_buf_nr, (int)priv->tx_buf_nw); |
||||
|
||||
uint16_t nr = priv->tx_buf_nr; |
||||
uint16_t nw = priv->tx_buf_nw; |
||||
|
||||
if (nr == nw) { |
||||
dbg_uusart("remain=0,do nothing"); |
||||
return; |
||||
} // do nothing if we're done
|
||||
|
||||
uint8_t chunk = priv->tx_buffer[nr++]; |
||||
//nr += (uint16_t) (4 - (nr & 0b11));
|
||||
if (chunk == 0) { |
||||
// wrap-around
|
||||
chunk = priv->tx_buffer[0]; |
||||
nr = 1; |
||||
assert_param(nr < nw); |
||||
} |
||||
|
||||
// nr was advanced by the lpad preamble
|
||||
priv->tx_buf_nr = nr; |
||||
priv->tx_buf_chunk = chunk; // will be further moved by 'chunk' bytes when dma completes
|
||||
|
||||
dbg_uusart("# TX: chunk start %d, len %d", (int)nr, (int)chunk); |
||||
//#if UUSART_DEBUG
|
||||
// PUTS(">"); PUTSN((char *) (priv->tx_buffer + nr), chunk); PUTS("<");
|
||||
// PUTNL();
|
||||
//#endif
|
||||
|
||||
LL_DMA_DisableChannel(priv->dma, priv->dma_tx_chnum); |
||||
{ |
||||
LL_DMA_ClearFlags(priv->dma, priv->dma_tx_chnum); |
||||
LL_DMA_SetMemoryAddress(priv->dma, priv->dma_tx_chnum, (uint32_t) (priv->tx_buffer + nr)); |
||||
LL_DMA_SetDataLength(priv->dma, priv->dma_tx_chnum, chunk); |
||||
LL_USART_ClearFlag_TC(priv->periph); |
||||
} |
||||
LL_DMA_EnableChannel(priv->dma, priv->dma_tx_chnum); |
||||
} |
||||
|
||||
COMPILER_ASSERT(UUSART_TXBUF_LEN <= 256); // more would break the "len tag" algorithm
|
||||
|
||||
/**
|
||||
* Put data on the queue. Only a part may be sent due to a buffer size limit. |
||||
* |
||||
* @param priv |
||||
* @param buffer - buffer to send |
||||
* @param len - buffer size |
||||
* @return number of bytes that were really written (from the beginning) |
||||
*/ |
||||
uint16_t UUSART_DMA_TxQueue(struct priv *priv, const uint8_t *buffer, uint16_t len) |
||||
{ |
||||
const uint16_t nr = priv->tx_buf_nr; |
||||
uint16_t nw = priv->tx_buf_nw; |
||||
|
||||
// shortcut for checking a completely full buffer
|
||||
if (nw == nr-1 || (nr==0&&nw==UUSART_TXBUF_LEN-1)) { |
||||
dbg_uusart("Buffer full, cant queue"); |
||||
return 0; |
||||
} |
||||
|
||||
dbg_uusart("\r\nQueue.."); |
||||
|
||||
uint16_t used = 0; |
||||
if (nr == nw) { |
||||
used = 0; |
||||
} else if (nw > nr) { // simple linear
|
||||
used = (uint16_t) (nw - nr); |
||||
} else if (nw < nr) { // wrapped
|
||||
used = (uint16_t) ((UUSART_TXBUF_LEN - nr) + nw); |
||||
} |
||||
|
||||
dbg_uusart("Trying to send buffer of len %d", (int)len); |
||||
uint16_t avail = (const uint16_t) (UUSART_TXBUF_LEN - 1 - used); |
||||
dbg_uusart("nr %d, nw %d, used %d, avail %d", (int)nr, (int)nw, (int)used, (int)avail); |
||||
|
||||
// hack to avoid too large chunks (we use 1 byte to store chunk size)
|
||||
if (avail > 255) avail = 255; |
||||
|
||||
uint8_t written = 0; |
||||
|
||||
// this avoids attempting to write if we don't have space
|
||||
if (avail <= 5) { |
||||
dbg_uusart("No space (only %d)", (int) avail); |
||||
return written; |
||||
} |
||||
|
||||
int cnt = 0; |
||||
while (avail > 0 && written < len) { |
||||
assert_param(cnt < 2); // if more than two, we have a bug and it's repeating infinitely
|
||||
|
||||
cnt++; |
||||
// Padding with chunk information (1 byte: length) - for each chunk
|
||||
const uint8_t lpad = 1; |
||||
|
||||
// Chunk can go max to the end of the buffer
|
||||
uint8_t chunk = (uint8_t) MIN((len-written) + lpad, UUSART_TXBUF_LEN - nw); |
||||
if (chunk > avail) chunk = (uint8_t) avail; |
||||
|
||||
dbg_uusart("nw %d, raw available chunk %d", (int) nw, (int)chunk); |
||||
if (chunk < lpad + 1) { |
||||
// write 0 to indicate a wrap-around
|
||||
dbg_uusart("Wrap-around marker at offset %d", (int) nw); |
||||
priv->tx_buffer[nw] = 0; |
||||
nw = 0; |
||||
} |
||||
else { |
||||
// enough space for a preamble + some data
|
||||
dbg_uusart("Preamble of %d bytes at offset %d", (int) lpad, (int) nw); |
||||
priv->tx_buffer[nw] = (uint8_t) (chunk - lpad); |
||||
nw += lpad; |
||||
uint8_t datachunk = (uint8_t) (chunk - lpad); |
||||
dbg_uusart("Datachunk len %d at offset %d", (int) datachunk, (int) nw); |
||||
//#if UUSART_DEBUG
|
||||
// PUTS("mcpy src >"); PUTSN((char *) (buffer), datachunk); PUTS("<\r\n");
|
||||
//#endif
|
||||
memcpy((uint8_t *) (priv->tx_buffer + nw), buffer, datachunk); |
||||
//#if UUSART_DEBUG
|
||||
// PUTS("mcpy dst >"); PUTSN((char *) (priv->tx_buffer + nw), datachunk); PUTS("<\r\n");
|
||||
//#endif
|
||||
buffer += datachunk; |
||||
nw += datachunk; |
||||
written += datachunk; |
||||
if (nw == UUSART_TXBUF_LEN) nw = 0; |
||||
} |
||||
avail -= chunk; |
||||
dbg_uusart(". end of loop, avail is %d", (int)avail); |
||||
} |
||||
|
||||
{ |
||||
dbg_uusart("Write done -> nr %d, nw %d", (int) nr, (int) nw); |
||||
|
||||
// FIXME a potential race condition can happen here (but it's unlikely)
|
||||
|
||||
priv->tx_buf_nw = nw; |
||||
|
||||
if (!priv->tx_dma_busy) { |
||||
dbg_uusart("Write done, requesting DMA."); |
||||
UUSART_DMA_TxStart(priv); |
||||
} |
||||
else { |
||||
dbg_uusart("DMA in progress, not requesting"); |
||||
} |
||||
} |
||||
|
||||
return written; |
||||
} |
||||
|
||||
/**
|
||||
* Handler for the Tx DMA - completion interrupt |
||||
* @param arg - unit instance |
||||
*/ |
||||
static void UUSART_DMA_TxHandler(void *arg) |
||||
{ |
||||
Unit *unit = arg; |
||||
assert_param(unit); |
||||
struct priv *priv = unit->data; |
||||
assert_param(priv); |
||||
|
||||
uint32_t isrsnapshot = priv->dma->ISR; |
||||
if (LL_DMA_IsActiveFlag_TC(isrsnapshot, priv->dma_tx_chnum)) { |
||||
// chunk Tx is finished
|
||||
dbg_uusart("~ DMA tx done, nr %d, nw %d, chunk %d", (int)priv->tx_buf_nr, (int)priv->tx_buf_nw, (int)priv->tx_buf_chunk); |
||||
|
||||
priv->tx_buf_nr += priv->tx_buf_chunk; |
||||
if (UUSART_TXBUF_LEN == priv->tx_buf_nr) priv->tx_buf_nr = 0; |
||||
priv->tx_buf_chunk = 0; |
||||
|
||||
LL_DMA_ClearFlag_TC(priv->dma, priv->dma_tx_chnum); |
||||
|
||||
// Wait for TC
|
||||
while (!LL_USART_IsActiveFlag_TC(priv->periph)); // TODO timeout
|
||||
|
||||
// start the next chunk
|
||||
if (priv->tx_buf_nr != priv->tx_buf_nw) { |
||||
dbg_uusart(" Asking for more, if any"); |
||||
UUSART_DMA_TxStart(priv); |
||||
} else { |
||||
priv->tx_dma_busy = false; |
||||
} |
||||
} |
||||
} |
||||
|
||||
|
||||
void UUSART_DeInitDMAs(Unit *unit) |
||||
{ |
||||
assert_param(unit); |
||||
struct priv *priv = unit->data; |
||||
assert_param(priv); |
||||
|
||||
irqd_detach(priv->dma_tx, UUSART_DMA_RxHandler); |
||||
irqd_detach(priv->dma_rx, UUSART_DMA_TxHandler); |
||||
|
||||
LL_DMA_DeInit(priv->dma, priv->dma_rx_chnum); |
||||
LL_DMA_DeInit(priv->dma, priv->dma_tx_chnum); |
||||
|
||||
free_ck(priv->rx_buffer); |
||||
free_ck(priv->tx_buffer); |
||||
} |
||||
@ -0,0 +1,345 @@ |
||||
//
|
||||
// Created by MightyPork on 2018/01/14.
|
||||
//
|
||||
#include <platform/irq_dispatcher.h> |
||||
#include "platform.h" |
||||
#include "unit_base.h" |
||||
|
||||
#define UUSART_INTERNAL |
||||
#include "_internal.h" |
||||
|
||||
extern error_t UUSART_ClaimDMAs(Unit *unit); |
||||
extern error_t UUSART_SetupDMAs(Unit *unit); |
||||
extern void UUSART_DeInitDMAs(Unit *unit); |
||||
|
||||
/** Allocate data structure and set defaults */ |
||||
error_t UUSART_preInit(Unit *unit) |
||||
{ |
||||
struct priv *priv = unit->data = calloc_ck(1, sizeof(struct priv)); |
||||
if (priv == NULL) return E_OUT_OF_MEM; |
||||
|
||||
// some defaults
|
||||
priv->periph_num = 1; |
||||
priv->remap = 0; |
||||
|
||||
priv->baudrate = 115200; |
||||
priv->parity = 0; //!< 0-none, 1-odd, 2-even
|
||||
priv->stopbits = 1; //!< 0-half, 1-one, 2-1.5, 3-two
|
||||
priv->direction = 3; // RXTX
|
||||
|
||||
priv->hw_flow_control = false; |
||||
priv->clock_output = false; |
||||
priv->cpol = 0; |
||||
priv->cpha = 0; |
||||
priv->lsb_first = true; // LSB first is default for UART
|
||||
priv->width = 8; |
||||
|
||||
priv->data_inv = false; |
||||
priv->rx_inv = false; |
||||
priv->tx_inv = false; |
||||
|
||||
priv->de_output = false; |
||||
priv->de_polarity = 1; // active high
|
||||
// this should equal to a half-byte length when oversampling by 16 is used (default)
|
||||
priv->de_assert_time = 8; |
||||
priv->de_clear_time = 8; |
||||
|
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
/** Claim the peripheral and assign priv->periph */ |
||||
static inline error_t UUSART_claimPeriph(Unit *unit) |
||||
{ |
||||
struct priv *priv = unit->data; |
||||
|
||||
if (!(priv->periph_num >= 1 && priv->periph_num <= 5)) { |
||||
dbg("!! Bad USART periph"); |
||||
return E_BAD_CONFIG; |
||||
} |
||||
|
||||
// assign and claim the peripheral
|
||||
if (priv->periph_num == 1) { |
||||
TRY(rsc_claim(unit, R_USART1)); |
||||
priv->periph = USART1; |
||||
} |
||||
else if (priv->periph_num == 2) { |
||||
TRY(rsc_claim(unit, R_USART2)); |
||||
priv->periph = USART2; |
||||
} |
||||
else if (priv->periph_num == 3) { |
||||
TRY(rsc_claim(unit, R_USART3)); |
||||
priv->periph = USART3; |
||||
} |
||||
#if defined(USART4) |
||||
else if (priv->periph_num == 4) { |
||||
TRY(rsc_claim(unit, R_USART4)); |
||||
priv->periph = USART4; |
||||
} |
||||
#endif |
||||
#if defined(USART5) |
||||
else if (priv->periph_num == 5) { |
||||
TRY(rsc_claim(unit, R_USART5)); |
||||
priv->periph = USART5; |
||||
} |
||||
#endif |
||||
else return E_BAD_CONFIG; |
||||
|
||||
TRY(UUSART_ClaimDMAs(unit)); |
||||
|
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
/** Claim and configure GPIOs used */ |
||||
static inline error_t UUSART_configPins(Unit *unit) |
||||
{ |
||||
struct priv *priv = unit->data; |
||||
// This is written for F072, other platforms will need adjustments
|
||||
|
||||
// Configure UART pins (AF)
|
||||
|
||||
#define want_ck_pin(priv) ((priv)->clock_output) |
||||
#define want_tx_pin(priv) (bool)((priv)->direction & 2) |
||||
#define want_rx_pin(priv) (bool)((priv)->direction & 1) |
||||
#define want_cts_pin(priv) ((priv)->hw_flow_control==2 || (priv)->hw_flow_control==3) |
||||
#define want_rts_pin(priv) ((priv)->de_output || (priv)->hw_flow_control==1 || (priv)->hw_flow_control==3) |
||||
|
||||
/* List of required pins based on the user config */ |
||||
bool pins_wanted[5] = { |
||||
want_ck_pin(priv), |
||||
want_tx_pin(priv), |
||||
want_rx_pin(priv), |
||||
want_cts_pin(priv), |
||||
want_rts_pin(priv) |
||||
}; |
||||
|
||||
#if GEX_PLAT_F072_DISCOVERY |
||||
|
||||
const struct PinAF *mappings = NULL; |
||||
|
||||
// TODO adjust this, possibly remove / split to individual pin config for ..
|
||||
// the final board
|
||||
|
||||
const struct PinAF mapping_1_0[5] = { |
||||
{'A', 8, LL_GPIO_AF_1}, // CK
|
||||
{'A', 9, LL_GPIO_AF_1}, // TX
|
||||
{'A', 10, LL_GPIO_AF_1}, // RX
|
||||
{'A', 11, LL_GPIO_AF_1}, // CTS - collides with USB
|
||||
{'A', 12, LL_GPIO_AF_1}, // RTS - collides with USB
|
||||
}; |
||||
|
||||
const struct PinAF mapping_1_1[5] = { |
||||
{'A', 8, LL_GPIO_AF_1}, // CK*
|
||||
{'B', 6, LL_GPIO_AF_1}, // TX
|
||||
{'B', 7, LL_GPIO_AF_1}, // RX
|
||||
{'A', 11, LL_GPIO_AF_1}, // CTS* - collides with USB
|
||||
{'A', 12, LL_GPIO_AF_1}, // RTS* - collides with USB
|
||||
}; |
||||
|
||||
const struct PinAF mapping_2_0[5] = { |
||||
{'A', 4, LL_GPIO_AF_1}, // CK
|
||||
{'A', 2, LL_GPIO_AF_1}, // TX
|
||||
{'A', 3, LL_GPIO_AF_1}, // RX
|
||||
{'A', 0, LL_GPIO_AF_1}, // CTS
|
||||
{'A', 1, LL_GPIO_AF_1}, // RTS
|
||||
}; |
||||
|
||||
const struct PinAF mapping_2_1[5] = { |
||||
{'A', 4, LL_GPIO_AF_1}, // CK*
|
||||
{'A', 14, LL_GPIO_AF_1}, // TX
|
||||
{'A', 15, LL_GPIO_AF_1}, // RX
|
||||
{'A', 0, LL_GPIO_AF_1}, // CTS*
|
||||
{'A', 1, LL_GPIO_AF_1}, // RTS*
|
||||
}; |
||||
|
||||
const struct PinAF mapping_3_0[5] = { |
||||
{'B', 12, LL_GPIO_AF_4}, // CK
|
||||
{'B', 10, LL_GPIO_AF_4}, // TX
|
||||
{'B', 11, LL_GPIO_AF_4}, // RX
|
||||
{'B', 13, LL_GPIO_AF_4}, // CTS
|
||||
{'B', 14, LL_GPIO_AF_4}, // RTS
|
||||
}; |
||||
|
||||
const struct PinAF mapping_4_0[5] = { |
||||
{'C', 12, LL_GPIO_AF_0}, // CK
|
||||
{'A', 0, LL_GPIO_AF_4}, // TX
|
||||
{'A', 1, LL_GPIO_AF_4}, // RX
|
||||
{'B', 7, LL_GPIO_AF_4}, // CTS
|
||||
{'A', 15, LL_GPIO_AF_4}, // RTS
|
||||
}; |
||||
|
||||
const struct PinAF mapping_4_1[5] = { |
||||
{'C', 12, LL_GPIO_AF_0}, // CK*
|
||||
{'C', 10, LL_GPIO_AF_0}, // TX
|
||||
{'C', 11, LL_GPIO_AF_0}, // RX
|
||||
{'B', 7, LL_GPIO_AF_4}, // CTS*
|
||||
{'A', 15, LL_GPIO_AF_4}, // RTS*
|
||||
}; |
||||
|
||||
if (priv->periph_num == 1) { |
||||
// USART1
|
||||
if (priv->remap == 0) mappings = &mapping_1_0[0]; |
||||
else if (priv->remap == 1) mappings = &mapping_1_1[0]; |
||||
else return E_BAD_CONFIG; |
||||
} |
||||
else if (priv->periph_num == 2) { |
||||
// USART2
|
||||
if (priv->remap == 0) mappings = &mapping_2_0[0]; |
||||
else if (priv->remap == 1) mappings = &mapping_2_1[0]; |
||||
else return E_BAD_CONFIG; |
||||
} |
||||
else if (priv->periph_num == 3) { |
||||
// USART3
|
||||
if (priv->remap == 0) mappings = &mapping_3_0[0]; |
||||
else return E_BAD_CONFIG; |
||||
} |
||||
else if (priv->periph_num == 4) { |
||||
// USART3
|
||||
if (priv->remap == 0) mappings = &mapping_4_0[0]; |
||||
else if (priv->remap == 1) mappings = &mapping_4_1[0]; |
||||
else return E_BAD_CONFIG; |
||||
} |
||||
else return E_BAD_CONFIG; |
||||
|
||||
// Apply mappings based on the 'wanted' table
|
||||
for (int i = 0; i < 5; i++) { |
||||
if (pins_wanted[i]) { |
||||
if (mappings[i].port == 0) return E_BAD_CONFIG; |
||||
TRY(rsc_claim_pin(unit, mappings[i].port, mappings[i].pin)); |
||||
hw_configure_gpio_af(mappings[i].port, mappings[i].pin, mappings[i].af); |
||||
} |
||||
} |
||||
|
||||
#elif GEX_PLAT_F103_BLUEPILL |
||||
#error "NO IMPL" |
||||
#elif GEX_PLAT_F303_DISCOVERY |
||||
#error "NO IMPL" |
||||
#elif GEX_PLAT_F407_DISCOVERY |
||||
#error "NO IMPL" |
||||
#else |
||||
#error "BAD PLATFORM!" |
||||
#endif |
||||
|
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
/** Finalize unit set-up */ |
||||
error_t UUSART_init(Unit *unit) |
||||
{ |
||||
struct priv *priv = unit->data; |
||||
|
||||
TRY(UUSART_claimPeriph(unit)); |
||||
TRY(UUSART_configPins(unit)); |
||||
|
||||
// --- Configure the peripheral ---
|
||||
|
||||
// Enable clock for the peripheral used
|
||||
hw_periph_clock_enable(priv->periph); |
||||
|
||||
LL_USART_Disable(priv->periph); |
||||
{ |
||||
LL_USART_DeInit(priv->periph); |
||||
LL_USART_SetBaudRate(priv->periph, PLAT_APB1_HZ, LL_USART_OVERSAMPLING_16, priv->baudrate); |
||||
|
||||
LL_USART_SetParity(priv->periph, |
||||
priv->parity == 0 ? LL_USART_PARITY_NONE : |
||||
priv->parity == 1 ? LL_USART_PARITY_ODD |
||||
: LL_USART_PARITY_EVEN); |
||||
|
||||
LL_USART_SetStopBitsLength(priv->periph, |
||||
priv->stopbits == 0 ? LL_USART_STOPBITS_0_5 : |
||||
priv->stopbits == 1 ? LL_USART_STOPBITS_1 : |
||||
priv->stopbits == 2 ? LL_USART_STOPBITS_1_5 |
||||
: LL_USART_STOPBITS_2); |
||||
|
||||
LL_USART_SetTransferDirection(priv->periph, |
||||
priv->direction == 1 ? LL_USART_DIRECTION_RX : |
||||
priv->direction == 2 ? LL_USART_DIRECTION_TX |
||||
: LL_USART_DIRECTION_TX_RX); |
||||
|
||||
LL_USART_SetHWFlowCtrl(priv->periph, |
||||
priv->hw_flow_control == 0 ? LL_USART_HWCONTROL_NONE : |
||||
priv->hw_flow_control == 1 ? LL_USART_HWCONTROL_RTS : |
||||
priv->hw_flow_control == 2 ? LL_USART_HWCONTROL_CTS |
||||
: LL_USART_HWCONTROL_RTS_CTS); |
||||
|
||||
LL_USART_ConfigClock(priv->periph, |
||||
priv->cpha ? LL_USART_PHASE_2EDGE : LL_USART_PHASE_1EDGE, |
||||
priv->cpol ? LL_USART_POLARITY_HIGH : LL_USART_POLARITY_LOW, |
||||
true); // clock on last bit - TODO configurable?
|
||||
|
||||
if (priv->clock_output) |
||||
LL_USART_EnableSCLKOutput(priv->periph); |
||||
else |
||||
LL_USART_DisableSCLKOutput(priv->periph); |
||||
|
||||
LL_USART_SetTransferBitOrder(priv->periph, |
||||
priv->lsb_first ? LL_USART_BITORDER_LSBFIRST |
||||
: LL_USART_BITORDER_MSBFIRST); |
||||
|
||||
LL_USART_SetDataWidth(priv->periph, |
||||
priv->width == 7 ? LL_USART_DATAWIDTH_7B : |
||||
priv->width == 8 ? LL_USART_DATAWIDTH_8B |
||||
: LL_USART_DATAWIDTH_9B); |
||||
|
||||
LL_USART_SetBinaryDataLogic(priv->periph, |
||||
priv->data_inv ? LL_USART_BINARY_LOGIC_NEGATIVE |
||||
: LL_USART_BINARY_LOGIC_POSITIVE); |
||||
|
||||
LL_USART_SetRXPinLevel(priv->periph, priv->rx_inv ? LL_USART_RXPIN_LEVEL_INVERTED |
||||
: LL_USART_RXPIN_LEVEL_STANDARD); |
||||
|
||||
LL_USART_SetTXPinLevel(priv->periph, priv->tx_inv ? LL_USART_TXPIN_LEVEL_INVERTED |
||||
: LL_USART_TXPIN_LEVEL_STANDARD); |
||||
|
||||
if (priv->de_output) |
||||
LL_USART_EnableDEMode(priv->periph); |
||||
else |
||||
LL_USART_DisableDEMode(priv->periph); |
||||
|
||||
LL_USART_SetDESignalPolarity(priv->periph, |
||||
priv->de_polarity ? LL_USART_DE_POLARITY_HIGH |
||||
: LL_USART_DE_POLARITY_LOW); |
||||
|
||||
LL_USART_SetDEAssertionTime(priv->periph, priv->de_assert_time); |
||||
LL_USART_SetDEDeassertionTime(priv->periph, priv->de_clear_time); |
||||
|
||||
// Prepare for DMA
|
||||
LL_USART_ClearFlag_TC(priv->periph); |
||||
LL_USART_EnableDMAReq_RX(priv->periph); |
||||
LL_USART_EnableDMAReq_TX(priv->periph); |
||||
} |
||||
LL_USART_Enable(priv->periph); |
||||
|
||||
// modifies some usart registers that can't be modified when enabled
|
||||
TRY(UUSART_SetupDMAs(unit)); |
||||
|
||||
// timeout based on the baudrate
|
||||
unit->tick_interval = (uint16_t) ((50 * 1000) / priv->baudrate); // receive timeout (ms)
|
||||
if (unit->tick_interval < 5) unit->tick_interval = 5; |
||||
|
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
/** Tear down the unit */ |
||||
void UUSART_deInit(Unit *unit) |
||||
{ |
||||
struct priv *priv = unit->data; |
||||
|
||||
// de-init the pins & peripheral only if inited correctly
|
||||
if (unit->status == E_SUCCESS) { |
||||
assert_param(priv->periph); |
||||
LL_USART_DeInit(priv->periph); |
||||
|
||||
// Disable clock
|
||||
hw_periph_clock_disable(priv->periph); |
||||
|
||||
UUSART_DeInitDMAs(unit); |
||||
} |
||||
|
||||
// Release all resources
|
||||
rsc_teardown(unit); |
||||
|
||||
// Free memory
|
||||
free_ck(unit->data); |
||||
unit->data = NULL; |
||||
} |
||||
@ -0,0 +1,110 @@ |
||||
//
|
||||
// Created by MightyPork on 2018/01/14.
|
||||
//
|
||||
|
||||
#ifndef GEX_F072_UUSART_INTERNAL_H |
||||
#define GEX_F072_UUSART_INTERNAL_H |
||||
|
||||
#ifndef UUSART_INTERNAL |
||||
#error "Bad include" |
||||
#endif |
||||
|
||||
#include "platform.h" |
||||
|
||||
#define UUSART_RXBUF_LEN 64 |
||||
#define UUSART_TXBUF_LEN 128 |
||||
|
||||
/** Private data structure */ |
||||
struct priv { |
||||
uint8_t periph_num; //!< 1-6
|
||||
uint8_t remap; //!< UART remap option
|
||||
|
||||
uint32_t baudrate; //!< baud rate
|
||||
uint8_t parity; //!< 0-none, 1-odd, 2-even
|
||||
uint8_t stopbits; //!< 0-half, 1-one, 2-one-and-half, 3-two (halves - 1)
|
||||
uint8_t direction; //!< 1-RX, 2-TX, 3-RXTX
|
||||
|
||||
uint8_t hw_flow_control; //!< HW flow control 0-none, 1-RTC, 2-CTS, 3-full
|
||||
bool clock_output; //!< Output serial clock
|
||||
bool cpol; //!< clock CPOL setting
|
||||
bool cpha; //!< clock CPHA setting
|
||||
bool lsb_first; //!< bit order
|
||||
uint8_t width; //!< word width - 7, 8, 9 (this includes parity)
|
||||
|
||||
bool data_inv; //!< Invert data bytes
|
||||
bool rx_inv; //!< Invert the RX pin levels
|
||||
bool tx_inv; //!< Invert the TX pin levels
|
||||
|
||||
bool de_output; //!< Generate the Driver Enable signal for RS485
|
||||
bool de_polarity; //!< DE active level
|
||||
uint8_t de_assert_time; //!< Time to assert the DE signal before transmit
|
||||
uint8_t de_clear_time; //!< Time to clear the DE signal after transmit
|
||||
|
||||
USART_TypeDef *periph; |
||||
|
||||
DMA_TypeDef *dma; |
||||
DMA_Channel_TypeDef *dma_rx; |
||||
DMA_Channel_TypeDef *dma_tx; |
||||
uint8_t dma_rx_chnum; |
||||
uint8_t dma_tx_chnum; |
||||
|
||||
// DMA stuff
|
||||
volatile uint8_t *rx_buffer; |
||||
volatile uint16_t rx_buf_readpos; |
||||
|
||||
volatile uint8_t *tx_buffer; |
||||
volatile uint16_t tx_buf_nr; |
||||
volatile uint16_t tx_buf_nw; |
||||
volatile uint16_t tx_buf_chunk; |
||||
volatile bool tx_dma_busy; |
||||
|
||||
volatile uint16_t rx_last_dmapos; |
||||
}; |
||||
|
||||
/** Allocate data structure and set defaults */ |
||||
error_t UUSART_preInit(Unit *unit); |
||||
// ------------------------------------------------------------------------
|
||||
/** Load from a binary buffer stored in Flash */ |
||||
void UUSART_loadBinary(Unit *unit, PayloadParser *pp); |
||||
/** Write to a binary buffer for storing in Flash */ |
||||
void UUSART_writeBinary(Unit *unit, PayloadBuilder *pb); |
||||
// ------------------------------------------------------------------------
|
||||
/** Parse a key-value pair from the INI file */ |
||||
error_t UUSART_loadIni(Unit *unit, const char *key, const char *value); |
||||
/** Generate INI file section for the unit */ |
||||
void UUSART_writeIni(Unit *unit, IniWriter *iw); |
||||
// ------------------------------------------------------------------------
|
||||
/** Tear down the unit */ |
||||
void UUSART_deInit(Unit *unit); |
||||
/** Finalize unit set-up */ |
||||
error_t UUSART_init(Unit *unit); |
||||
|
||||
/**
|
||||
* Handle received data (we're inside the IRQ) |
||||
* |
||||
* @param unit - handled unit |
||||
* @param endpos - end position in the buffer |
||||
*/ |
||||
void UUSART_DMA_HandleRxFromIRQ(Unit *unit, uint16_t endpos); |
||||
|
||||
/**
|
||||
* Put data on the queue. Only a part may be sent due to a buffer size limit. |
||||
* |
||||
* @param priv |
||||
* @param buffer - buffer to send |
||||
* @param len - buffer size |
||||
* @return number of bytes that were really written (from the beginning) |
||||
*/ |
||||
uint16_t UUSART_DMA_TxQueue(struct priv *priv, const uint8_t *buffer, uint16_t len); |
||||
|
||||
/**
|
||||
* Handle rx timeout, grab what is received and send it immediately. |
||||
* |
||||
* @param unit |
||||
*/ |
||||
void UUSART_DMA_HandleRxTimeout(Unit *unit); |
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
|
||||
#endif //GEX_F072_UUSART_INTERNAL_H
|
||||
@ -0,0 +1,74 @@ |
||||
//
|
||||
// Created by MightyPork on 2018/01/14.
|
||||
//
|
||||
|
||||
#include "platform.h" |
||||
#include "unit_base.h" |
||||
|
||||
#define UUSART_INTERNAL |
||||
#include "_internal.h" |
||||
|
||||
/** Load from a binary buffer stored in Flash */ |
||||
void UUSART_loadBinary(Unit *unit, PayloadParser *pp) |
||||
{ |
||||
struct priv *priv = unit->data; |
||||
|
||||
uint8_t version = pp_u8(pp); |
||||
(void)version; |
||||
|
||||
priv->periph_num = pp_u8(pp); |
||||
priv->remap = pp_u8(pp); |
||||
|
||||
priv->baudrate = pp_u32(pp); |
||||
priv->parity = pp_u8(pp); |
||||
priv->stopbits = pp_u8(pp); |
||||
priv->direction = pp_u8(pp); |
||||
|
||||
priv->hw_flow_control = pp_u8(pp); |
||||
priv->clock_output = pp_bool(pp); |
||||
priv->cpol = pp_bool(pp); |
||||
priv->cpha = pp_bool(pp); |
||||
priv->lsb_first = pp_bool(pp); |
||||
priv->width = pp_u8(pp); |
||||
|
||||
priv->data_inv = pp_bool(pp); |
||||
priv->rx_inv = pp_bool(pp); |
||||
priv->tx_inv = pp_bool(pp); |
||||
|
||||
priv->de_output = pp_bool(pp); |
||||
priv->de_polarity = pp_bool(pp); |
||||
priv->de_assert_time = pp_u8(pp); |
||||
priv->de_clear_time = pp_u8(pp); |
||||
} |
||||
|
||||
/** Write to a binary buffer for storing in Flash */ |
||||
void UUSART_writeBinary(Unit *unit, PayloadBuilder *pb) |
||||
{ |
||||
struct priv *priv = unit->data; |
||||
|
||||
pb_u8(pb, 0); // version
|
||||
|
||||
pb_u8(pb, priv->periph_num); |
||||
pb_u8(pb, priv->remap); |
||||
|
||||
pb_u32(pb, priv->baudrate); |
||||
pb_u8(pb, priv->parity); |
||||
pb_u8(pb, priv->stopbits); |
||||
pb_u8(pb, priv->direction); |
||||
|
||||
pb_u8(pb, priv->hw_flow_control); |
||||
pb_bool(pb, priv->clock_output); |
||||
pb_bool(pb, priv->cpol); |
||||
pb_bool(pb, priv->cpha); |
||||
pb_bool(pb, priv->lsb_first); |
||||
pb_u8(pb, priv->width); |
||||
|
||||
pb_bool(pb, priv->data_inv); |
||||
pb_bool(pb, priv->rx_inv); |
||||
pb_bool(pb, priv->tx_inv); |
||||
|
||||
pb_bool(pb, priv->de_output); |
||||
pb_bool(pb, priv->de_polarity); |
||||
pb_u8(pb, priv->de_assert_time); |
||||
pb_u8(pb, priv->de_clear_time); |
||||
} |
||||
@ -0,0 +1,168 @@ |
||||
//
|
||||
// Created by MightyPork on 2018/01/14.
|
||||
//
|
||||
|
||||
#include "platform.h" |
||||
#include "unit_base.h" |
||||
#include "avrlibc.h" |
||||
|
||||
#define UUSART_INTERNAL |
||||
#include "_internal.h" |
||||
|
||||
/** Parse a key-value pair from the INI file */ |
||||
error_t UUSART_loadIni(Unit *unit, const char *key, const char *value) |
||||
{ |
||||
bool suc = true; |
||||
struct priv *priv = unit->data; |
||||
|
||||
if (streq(key, "device")) { |
||||
priv->periph_num = (uint8_t) avr_atoi(value); |
||||
} |
||||
else if (streq(key, "remap")) { |
||||
priv->remap = (uint8_t) avr_atoi(value); |
||||
} |
||||
else if (streq(key, "baud-rate")) { |
||||
priv->baudrate = (uint32_t ) avr_atoi(value); |
||||
} |
||||
else if (streq(key, "parity")) { |
||||
priv->parity = (uint8_t) str_parse_3(value, |
||||
"NONE", 0, |
||||
"ODD", 1, |
||||
"EVEN", 2, &suc); |
||||
} |
||||
else if (streq(key, "stop-bits")) { |
||||
priv->stopbits = (uint8_t) str_parse_4(value, |
||||
"0.5", 0, |
||||
"1", 1, |
||||
"1.5", 2, |
||||
"2", 3, &suc); |
||||
} |
||||
else if (streq(key, "direction")) { |
||||
priv->direction = (uint8_t) str_parse_3(value, |
||||
"RX", 1, |
||||
"TX", 2, |
||||
"RXTX", 3, &suc); |
||||
} |
||||
else if (streq(key, "hw-flow-control")) { |
||||
priv->hw_flow_control = (uint8_t) str_parse_4(value, |
||||
"NONE", 0, |
||||
"RTS", 1, |
||||
"CTS", 2, |
||||
"FULL", 3, &suc); |
||||
} |
||||
else if (streq(key, "word-width")) { |
||||
priv->width = (uint8_t ) avr_atoi(value); |
||||
} |
||||
else if (streq(key, "first-bit")) { |
||||
priv->lsb_first = (bool)str_parse_2(value, "MSB", 0, "LSB", 1, &suc); |
||||
} |
||||
else if (streq(key, "clock-output")) { |
||||
priv->clock_output = str_parse_yn(value, &suc); |
||||
} |
||||
else if (streq(key, "cpol")) { |
||||
priv->cpol = (bool) avr_atoi(value); |
||||
} |
||||
else if (streq(key, "cpha")) { |
||||
priv->cpha = (bool) avr_atoi(value); |
||||
} |
||||
else if (streq(key, "de-output")) { |
||||
priv->de_output = str_parse_yn(value, &suc); |
||||
} |
||||
else if (streq(key, "de-polarity")) { |
||||
priv->de_polarity = (bool) avr_atoi(value); |
||||
} |
||||
else if (streq(key, "de-assert-time")) { |
||||
priv->de_assert_time = (uint8_t) avr_atoi(value); |
||||
} |
||||
else if (streq(key, "de-clear-time")) { |
||||
priv->de_clear_time = (uint8_t) avr_atoi(value); |
||||
} |
||||
else { |
||||
return E_BAD_KEY; |
||||
} |
||||
|
||||
if (!suc) return E_BAD_VALUE; |
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
/** Generate INI file section for the unit */ |
||||
void UUSART_writeIni(Unit *unit, IniWriter *iw) |
||||
{ |
||||
struct priv *priv = unit->data; |
||||
|
||||
iw_comment(iw, "Peripheral number (UARTx 1-4)"); |
||||
iw_entry(iw, "device", "%d", (int)priv->periph_num); |
||||
|
||||
iw_comment(iw, "Pin mappings (TX,RX,CK,CTS,RTS/DE)"); |
||||
#if GEX_PLAT_F072_DISCOVERY |
||||
iw_comment(iw, " USART1: (0) A9,A10,A8,A11,A12 (1) B6,B7,A8,A11,A12"); |
||||
iw_comment(iw, " USART2: (0) A2,A3,A4,A0,A1 (1) A14,A15,A4,A0,A1"); |
||||
iw_comment(iw, " USART3: (0) B10,B11,B12,B13,B14"); |
||||
iw_comment(iw, " USART4: (0) A0,A1,C12,B7,A15 (1) C10,C11,C12,B7,A15"); |
||||
#elif GEX_PLAT_F103_BLUEPILL |
||||
#error "NO IMPL" |
||||
#elif GEX_PLAT_F303_DISCOVERY |
||||
#error "NO IMPL" |
||||
#elif GEX_PLAT_F407_DISCOVERY |
||||
#error "NO IMPL" |
||||
#else |
||||
#error "BAD PLATFORM!" |
||||
#endif |
||||
iw_entry(iw, "remap", "%d", (int)priv->remap); |
||||
|
||||
iw_cmt_newline(iw); |
||||
iw_comment(iw, "Baud rate in bps (eg. 9600, 115200)"); // TODO examples/range
|
||||
iw_entry(iw, "baud-rate", "%d", (int)priv->baudrate); |
||||
|
||||
iw_comment(iw, "Parity type (NONE, ODD, EVEN)"); |
||||
iw_entry(iw, "parity", "%s", str_3(priv->parity, |
||||
0, "NONE", |
||||
1, "ODD", |
||||
2, "EVEN")); |
||||
|
||||
iw_comment(iw, "Number of stop bits (0.5, 1, 1.5, 2)"); |
||||
iw_entry(iw, "stop-bits", "%s", str_4(priv->stopbits, |
||||
0, "0.5", |
||||
1, "1", |
||||
2, "1.5", |
||||
3, "2")); |
||||
|
||||
iw_comment(iw, "Bit order (LSB or MSB first)"); |
||||
iw_entry(iw, "first-bit", str_2((uint32_t)priv->lsb_first, |
||||
0, "MSB", |
||||
1, "LSB")); |
||||
|
||||
iw_comment(iw, "Word width (7,8,9) - including parity bit if used"); |
||||
iw_entry(iw, "word-width", "%d", (int)priv->width); |
||||
|
||||
iw_comment(iw, "Enabled lines (RX,TX,RXTX)"); |
||||
iw_entry(iw, "direction", str_3(priv->direction, |
||||
1, "RX", |
||||
2, "TX", |
||||
3, "RXTX")); |
||||
|
||||
iw_comment(iw, "Hardware flow control (NONE, RTS, CTS, FULL)"); |
||||
iw_entry(iw, "hw-flow-control", "%s", str_4(priv->hw_flow_control, |
||||
0, "NONE", |
||||
1, "RTS", |
||||
2, "CTS", |
||||
3, "FULL")); |
||||
|
||||
iw_cmt_newline(iw); |
||||
iw_comment(iw, "Generate serial clock (Y,N)"); |
||||
iw_entry(iw, "clock-output", str_yn(priv->clock_output)); |
||||
iw_comment(iw, "Output clock polarity: 0,1 (clock idle level)"); |
||||
iw_entry(iw, "cpol", "%d", (int)priv->cpol); |
||||
iw_comment(iw, "Output clock phase: 0,1 (active edge, 0-first, 1-second)"); |
||||
iw_entry(iw, "cpha", "%d", (int)priv->cpha); |
||||
|
||||
iw_cmt_newline(iw); |
||||
iw_comment(iw, "Generate RS485 Driver Enable signal (Y,N) - uses RTS pin"); |
||||
iw_entry(iw, "de-output", str_yn(priv->de_output)); |
||||
iw_comment(iw, "DE active level: 0,1"); |
||||
iw_entry(iw, "de-polarity", "%d", (int)(priv->de_polarity)); |
||||
iw_comment(iw, "DE assert time (0-31)"); |
||||
iw_entry(iw, "de-assert-time", "%d", (int)(priv->de_assert_time)); |
||||
iw_comment(iw, "DE clear time (0-31)"); |
||||
iw_entry(iw, "de-clear-time", "%d", (int)(priv->de_clear_time)); |
||||
} |
||||
@ -0,0 +1,178 @@ |
||||
//
|
||||
// Created by MightyPork on 2018/01/02.
|
||||
//
|
||||
|
||||
#include <stm32f072xb.h> |
||||
#include "platform.h" |
||||
#include "comm/messages.h" |
||||
#include "unit_base.h" |
||||
#include "unit_usart.h" |
||||
#include "tasks/task_msg.h" |
||||
|
||||
#define UUSART_INTERNAL |
||||
#include "_internal.h" |
||||
|
||||
static void UUSART_SendReceivedDataToMaster(Job *job) |
||||
{ |
||||
Unit *unit = job->data1; |
||||
struct priv *priv = unit->data; |
||||
|
||||
uint32_t readpos = job->d32; |
||||
uint32_t count = job->len; |
||||
|
||||
// Debug: print to debug port
|
||||
// PUTS("Job rx >");
|
||||
// PUTSN((char *) priv->rx_buffer + readpos, (uint16_t) count);
|
||||
// PUTS("<\r\n");
|
||||
|
||||
// Debug: Write out
|
||||
// UU_USART_Write(unit, (const uint8_t *) (priv->rx_buffer + readpos), count);
|
||||
|
||||
// TODO modify TF to allow writing in multiple chunks to avoid this useless buffer copying
|
||||
PayloadBuilder pb = pb_start(unit_tmp512, UNIT_TMP_LEN, NULL); |
||||
pb_u8(&pb, unit->callsign); |
||||
pb_u8(&pb, 0x00); // report type "Data received"
|
||||
pb_buf(&pb, (uint8_t *) (priv->rx_buffer + readpos), count); |
||||
assert_param(pb.ok); |
||||
com_send_pb(MSG_UNIT_REPORT, &pb); |
||||
} |
||||
|
||||
/**
|
||||
* Handle received data (we're inside the IRQ) |
||||
* |
||||
* @param unit - handled unit |
||||
* @param endpos - end position in the buffer |
||||
*/ |
||||
void UUSART_DMA_HandleRxFromIRQ(Unit *unit, uint16_t endpos) |
||||
{ |
||||
assert_param(unit); |
||||
struct priv *priv = unit->data; |
||||
assert_param(priv); |
||||
|
||||
uint16_t readpos = priv->rx_buf_readpos; |
||||
assert_param(endpos > readpos); |
||||
|
||||
uint16_t count = (endpos - readpos); |
||||
|
||||
// We defer it to the job queue
|
||||
// FIXME this can starve the shared queue if full duplex is used, we need a second higher priority queue for those report jobs
|
||||
Job j = { |
||||
.data1 = unit, |
||||
.d32 = priv->rx_buf_readpos, |
||||
.len = count, |
||||
.cb = UUSART_SendReceivedDataToMaster |
||||
}; |
||||
scheduleJob(&j); |
||||
|
||||
// Move the read cursor, wrap around if needed
|
||||
if (endpos == UUSART_RXBUF_LEN) endpos = 0; |
||||
priv->rx_buf_readpos = endpos; |
||||
} |
||||
|
||||
void UUSART_Tick(Unit *unit) |
||||
{ |
||||
assert_param(unit); |
||||
struct priv *priv = unit->data; |
||||
assert_param(priv); |
||||
|
||||
if (priv->rx_last_dmapos == priv->dma_rx->CNDTR) { |
||||
uint16_t endpos = (uint16_t) (UUSART_RXBUF_LEN - priv->rx_last_dmapos); |
||||
if (endpos != priv->rx_buf_readpos) { |
||||
dbg("DMA timeout"); |
||||
UUSART_DMA_HandleRxFromIRQ(unit, endpos); |
||||
} |
||||
} else { |
||||
priv->rx_last_dmapos = (uint16_t) priv->dma_rx->CNDTR; |
||||
} |
||||
} |
||||
|
||||
|
||||
error_t UU_USART_Write(Unit *unit, const uint8_t *buffer, uint32_t len) |
||||
{ |
||||
CHECK_TYPE(unit, &UNIT_USART); |
||||
struct priv *priv = unit->data; |
||||
|
||||
uint32_t t_start = HAL_GetTick(); |
||||
while (len > 0) { |
||||
// this should be long enough even for the slowest bitrates and 512 bytes
|
||||
if (HAL_GetTick() - t_start > 5000) { |
||||
return E_HW_TIMEOUT; |
||||
} |
||||
|
||||
uint16_t chunk = UUSART_DMA_TxQueue(priv, buffer, (uint16_t) len); |
||||
|
||||
buffer += chunk; |
||||
len -= chunk; |
||||
|
||||
// We give up control if there's another thread waiting and this isn't the last cycle
|
||||
if (len > 0) { |
||||
osThreadYield(); |
||||
} |
||||
} |
||||
|
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
error_t UU_USART_WriteSync(Unit *unit, const uint8_t *buffer, uint32_t len) |
||||
{ |
||||
CHECK_TYPE(unit, &UNIT_USART); |
||||
struct priv *priv = unit->data; |
||||
|
||||
TRY(UU_USART_Write(unit, buffer, len)); |
||||
|
||||
// Now wait for the last DMA to complete
|
||||
uint32_t t_start = HAL_GetTick(); |
||||
while (priv->tx_dma_busy) { |
||||
if (HAL_GetTick() - t_start > 1000) { |
||||
return E_HW_TIMEOUT; |
||||
} |
||||
} |
||||
|
||||
return E_SUCCESS; |
||||
} |
||||
|
||||
enum PinCmd_ { |
||||
CMD_WRITE = 0, |
||||
CMD_WRITE_SYNC = 1, |
||||
}; |
||||
|
||||
/** Handle a request message */ |
||||
static error_t UUSART_handleRequest(Unit *unit, TF_ID frame_id, uint8_t command, PayloadParser *pp) |
||||
{ |
||||
uint32_t len; |
||||
const uint8_t *pld; |
||||
switch (command) { |
||||
case CMD_WRITE: |
||||
pld = pp_tail(pp, &len); |
||||
TRY(UU_USART_Write(unit, pld, len)); |
||||
return E_SUCCESS; |
||||
|
||||
case CMD_WRITE_SYNC: |
||||
pld = pp_tail(pp, &len); |
||||
TRY(UU_USART_WriteSync(unit, pld, len)); |
||||
return E_SUCCESS; |
||||
|
||||
default: |
||||
return E_UNKNOWN_COMMAND; |
||||
} |
||||
} |
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
/** Unit template */ |
||||
const UnitDriver UNIT_USART = { |
||||
.name = "USART", |
||||
.description = "Serial port", |
||||
// Settings
|
||||
.preInit = UUSART_preInit, |
||||
.cfgLoadBinary = UUSART_loadBinary, |
||||
.cfgWriteBinary = UUSART_writeBinary, |
||||
.cfgLoadIni = UUSART_loadIni, |
||||
.cfgWriteIni = UUSART_writeIni, |
||||
// Init
|
||||
.init = UUSART_init, |
||||
.deInit = UUSART_deInit, |
||||
// Function
|
||||
.updateTick = UUSART_Tick, |
||||
.handleRequest = UUSART_handleRequest, |
||||
}; |
||||
@ -0,0 +1,34 @@ |
||||
//
|
||||
// Created by MightyPork on 2018/01/02.
|
||||
//
|
||||
|
||||
#ifndef GEX_F072_UNIT_USART_H |
||||
#define GEX_F072_UNIT_USART_H |
||||
|
||||
#include "unit.h" |
||||
|
||||
extern const UnitDriver UNIT_USART; |
||||
|
||||
/**
|
||||
* Write bytes. This function is asynchronous and does not wait for completion. |
||||
* It blocks until there's space in the Tx buffer for the data. |
||||
* |
||||
* @param unit |
||||
* @param buffer - bytes to send |
||||
* @param len - number of bytes to send |
||||
* @return success |
||||
*/ |
||||
error_t UU_USART_Write(Unit *unit, const uint8_t *buffer, uint32_t len); |
||||
|
||||
/**
|
||||
* Write bytes. Same like UU_USART_Write(), except it waits for the transmission |
||||
* to complete after sending the last data. |
||||
* |
||||
* @param unit |
||||
* @param buffer - bytes to send |
||||
* @param len - number of bytes to send |
||||
* @return success |
||||
*/ |
||||
error_t UU_USART_WriteSync(Unit *unit, const uint8_t *buffer, uint32_t len); |
||||
|
||||
#endif //GEX_F072_UNIT_USART_H
|
||||
Loading…
Reference in new issue