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/* |
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* File : uart.c |
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* Copyright (C) 2013 - 2016, Espressif Systems |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of version 3 of the GNU General Public License as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License along |
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* with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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#include <esp8266.h> |
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#include <uart_register.h> |
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#include "uart_asyncdrv.h-" |
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|
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// UartDev is defined and initialized in rom code. |
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extern UartDevice UartDev; |
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|
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struct UartBuffer { |
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uint32 UartBuffSize; |
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uint8 *pUartBuff; |
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uint8 *pInPos; |
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uint8 *pOutPos; |
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STATUS BuffState; |
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uint16 Space; //remanent space of the buffer |
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uint8 TcpControl; |
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struct UartBuffer *nextBuff; |
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}; |
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|
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struct UartRxBuff { |
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uint32 UartRxBuffSize; |
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uint8 *pUartRxBuff; |
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uint8 *pWritePos; |
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uint8 *pReadPos; |
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STATUS RxBuffState; |
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uint32 Space; //remanent space of the buffer |
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}; |
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|
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LOCAL struct UartBuffer* pTxBuffer = NULL; |
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LOCAL struct UartBuffer* pRxBuffer = NULL; |
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|
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// Forward declare |
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#if UART_BUFF_EN |
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LOCAL void Uart_Buf_Cpy(struct UartBuffer* pCur, char* pdata , uint16 data_len); |
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void uart_buf_free(struct UartBuffer* pBuff); |
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void tx_buff_enq(char* pdata, uint16 data_len ); |
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LOCAL void tx_fifo_insert(struct UartBuffer* pTxBuff, uint8 data_len, uint8 uart_no); |
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void tx_start_uart_buffer(uint8 uart_no); |
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uint16 rx_buff_deq(char* pdata, uint16 data_len ); |
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void Uart_rx_buff_enq(); |
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#endif |
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|
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//void ICACHE_FLASH_ATTR uart_test_rx(); |
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STATUS uart_tx_one_char(uint8 uart, uint8 TxChar); |
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STATUS uart_tx_one_char_no_wait(uint8 uart, uint8 TxChar); |
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void uart1_sendStr_no_wait(const char *str); |
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struct UartBuffer* UART_AsyncBufferInit(u32 size); |
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|
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void uart_rx_intr_enable(uint8 uart_no); |
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void uart_rx_intr_disable(uint8 uart_no); |
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void uart0_tx_buffer(uint8 *buf, uint16 len); |
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|
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void uart0_sendStr(const char *str); |
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|
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|
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/*uart demo with a system task, to output what uart receives*/ |
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/*this is a example to process uart data from task,please change the priority to fit your application task if exists*/ |
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/*it might conflict with your task, if so,please arrange the priority of different task, or combine it to a different event in the same task. */ |
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#define uart_recvTaskPrio 0 |
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#define uart_recvTaskQueueLen 10 |
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os_event_t uart_recvTaskQueue[uart_recvTaskQueueLen]; |
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|
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#define DBG |
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#define DBG1 uart1_sendStr_no_wait |
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#define DBG2 os_printf |
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|
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|
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LOCAL void uart0_rx_intr_handler(void *para); |
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|
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/****************************************************************************** |
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* FunctionName : uart_config |
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* Description : Internal used function |
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* UART0 used for data TX/RX, RX buffer size is 0x100, interrupt enabled |
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* UART1 just used for debug output |
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* Parameters : uart_no, use UART0 or UART1 defined ahead |
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* Returns : NONE |
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*******************************************************************************/ |
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LOCAL void ICACHE_FLASH_ATTR |
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uart_config(uint8 uart_no) |
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{ |
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if (uart_no == UART1){ |
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK); |
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}else{ |
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/* rcv_buff size if 0x100 */ |
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ETS_UART_INTR_ATTACH(uart0_rx_intr_handler, &(UartDev.rcv_buff)); |
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U); |
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD); |
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#if UART_HW_RTS |
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS); //HW FLOW CONTROL RTS PIN |
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#endif |
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#if UART_HW_CTS |
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_U0CTS); //HW FLOW CONTROL CTS PIN |
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#endif |
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} |
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uart_div_modify(uart_no, UART_CLK_FREQ / (UartDev.baut_rate));//SET BAUDRATE |
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|
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WRITE_PERI_REG(UART_CONF0(uart_no), ((UartDev.exist_parity & UART_PARITY_EN_M) << UART_PARITY_EN_S) //SET BIT AND PARITY MODE |
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| ((UartDev.parity & UART_PARITY_M) <<UART_PARITY_S ) |
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| ((UartDev.stop_bits & UART_STOP_BIT_NUM) << UART_STOP_BIT_NUM_S) |
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| ((UartDev.data_bits & UART_BIT_NUM) << UART_BIT_NUM_S)); |
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|
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//clear rx and tx fifo,not ready |
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SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); //RESET FIFO |
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CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); |
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|
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if (uart_no == UART0){ |
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//set rx fifo trigger |
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WRITE_PERI_REG(UART_CONF1(uart_no), |
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((100 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) | |
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#if UART_HW_RTS |
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((110 & UART_RX_FLOW_THRHD) << UART_RX_FLOW_THRHD_S) | |
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UART_RX_FLOW_EN | //enbale rx flow control |
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#endif |
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(0x02 & UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S | |
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UART_RX_TOUT_EN| |
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((0x10 & UART_TXFIFO_EMPTY_THRHD)<<UART_TXFIFO_EMPTY_THRHD_S));//wjl |
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#if UART_HW_CTS |
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SET_PERI_REG_MASK( UART_CONF0(uart_no),UART_TX_FLOW_EN); //add this sentense to add a tx flow control via MTCK( CTS ) |
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#endif |
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_TOUT_INT_ENA |UART_FRM_ERR_INT_ENA); |
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}else{ |
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WRITE_PERI_REG(UART_CONF1(uart_no),((UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S));//TrigLvl default val == 1 |
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} |
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//clear all interrupt |
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WRITE_PERI_REG(UART_INT_CLR(uart_no), 0xffff); |
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//enable rx_interrupt |
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_OVF_INT_ENA); |
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} |
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|
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/****************************************************************************** |
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* FunctionName : uart1_tx_one_char |
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* Description : Internal used function |
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* Use uart1 interface to transfer one char |
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* Parameters : uint8 TxChar - character to tx |
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* Returns : OK |
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*******************************************************************************/ |
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STATUS uart_tx_one_char(uint8 uart, uint8 TxChar) |
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{ |
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while (true){ |
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uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT<<UART_TXFIFO_CNT_S); |
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if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) < 126) { |
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break; |
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} |
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} |
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WRITE_PERI_REG(UART_FIFO(uart) , TxChar); |
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return OK; |
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} |
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/****************************************************************************** |
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* FunctionName : uart1_write_char |
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* Description : Internal used function |
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* Do some special deal while tx char is '\r' or '\n' |
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* Parameters : char c - character to tx |
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* Returns : NONE |
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*******************************************************************************/ |
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LOCAL void ICACHE_FLASH_ATTR |
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uart1_write_char(char c) |
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{ |
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if (c == '\n'){ |
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uart_tx_one_char(UART1, '\r'); |
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uart_tx_one_char(UART1, '\n'); |
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}else if (c == '\r'){ |
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}else{ |
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uart_tx_one_char(UART1, c); |
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} |
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} |
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//os_printf output to fifo or to the tx buffer |
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LOCAL void ICACHE_FLASH_ATTR |
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uart0_write_char_no_wait(char c) |
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{ |
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#if UART_BUFF_EN //send to uart0 fifo but do not wait |
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uint8 chr; |
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// if (c == '\n'){ |
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// chr = '\r'; |
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// tx_buff_enq(&chr, 1); |
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// chr = '\n'; |
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// tx_buff_enq(&chr, 1); |
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// }else if (c == '\r'){ |
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// |
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// }else{ |
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tx_buff_enq(&c,1); |
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// } |
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#else //send to uart tx buffer |
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if (c == '\n'){ |
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uart_tx_one_char_no_wait(UART0, '\r'); |
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uart_tx_one_char_no_wait(UART0, '\n'); |
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}else if (c == '\r'){ |
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} |
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else{ |
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uart_tx_one_char_no_wait(UART0, c); |
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} |
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#endif |
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} |
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|
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/****************************************************************************** |
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* FunctionName : uart0_tx_buffer |
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* Description : use uart0 to transfer buffer |
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* Parameters : uint8 *buf - point to send buffer |
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* uint16 len - buffer len |
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* Returns : |
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*******************************************************************************/ |
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void ICACHE_FLASH_ATTR |
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uart0_tx_buffer(uint8 *buf, uint16 len) |
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{ |
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uint16 i; |
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for (i = 0; i < len; i++) |
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{ |
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uart_tx_one_char(UART0, buf[i]); |
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} |
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} |
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|
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/****************************************************************************** |
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* FunctionName : uart0_sendStr |
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* Description : use uart0 to transfer buffer |
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* Parameters : uint8 *buf - point to send buffer |
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* uint16 len - buffer len |
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* Returns : |
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*******************************************************************************/ |
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void ICACHE_FLASH_ATTR |
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uart0_sendStr(const char *str) |
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{ |
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while(*str){ |
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uart_tx_one_char(UART0, *str++); |
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} |
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} |
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void at_port_print(const char *str) __attribute__((alias("uart0_sendStr"))); |
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/****************************************************************************** |
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* FunctionName : uart0_rx_intr_handler |
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* Description : Internal used function |
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* UART0 interrupt handler, add self handle code inside |
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* Parameters : void *para - point to ETS_UART_INTR_ATTACH's arg |
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* Returns : NONE |
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*******************************************************************************/ |
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LOCAL void |
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uart0_rx_intr_handler(void *para) |
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{ |
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/* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents |
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* uart1 and uart0 respectively |
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*/ |
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uint8 RcvChar; |
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uint8 uart_no = UART0;//UartDev.buff_uart_no; |
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uint8 fifo_len = 0; |
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uint8 buf_idx = 0; |
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uint8 temp,cnt; |
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//RcvMsgBuff *pRxBuff = (RcvMsgBuff *)para; |
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/*ATTENTION:*/ |
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/*IN NON-OS VERSION SDK, DO NOT USE "ICACHE_FLASH_ATTR" FUNCTIONS IN THE WHOLE HANDLER PROCESS*/ |
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/*ALL THE FUNCTIONS CALLED IN INTERRUPT HANDLER MUST BE DECLARED IN RAM */ |
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/*IF NOT , POST AN EVENT AND PROCESS IN SYSTEM TASK */ |
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if(UART_FRM_ERR_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_FRM_ERR_INT_ST)){ |
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DBG1("FRM_ERR\r\n"); |
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WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_FRM_ERR_INT_CLR); |
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}else if(UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)){ |
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// Full interrupt - FIFO threshold reached |
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DBG("f"); |
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uart_rx_intr_disable(UART0); |
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WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR); |
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system_os_post(uart_recvTaskPrio, 0, 0); // tell the handler |
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}else if(UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_TOUT_INT_ST)){ |
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// Timeout interrupt - Line idle for a while |
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DBG("t"); |
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uart_rx_intr_disable(UART0); |
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WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_TOUT_INT_CLR); |
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system_os_post(uart_recvTaskPrio, 0, 0); // tell the handler |
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}else if(UART_TXFIFO_EMPTY_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_TXFIFO_EMPTY_INT_ST)){ |
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DBG("e"); |
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// TX fifo is empty, can send more. |
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/* to output uart data from uart buffer directly in empty interrupt handler*/ |
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/*instead of processing in system event, in order not to wait for current task/function to quit */ |
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/*ATTENTION:*/ |
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/*IN NON-OS VERSION SDK, DO NOT USE "ICACHE_FLASH_ATTR" FUNCTIONS IN THE WHOLE HANDLER PROCESS*/ |
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/*ALL THE FUNCTIONS CALLED IN INTERRUPT HANDLER MUST BE DECLARED IN RAM */ |
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CLEAR_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA); |
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#if UART_BUFF_EN |
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tx_start_uart_buffer(UART0); |
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#endif |
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//system_os_post(uart_recvTaskPrio, 1, 0); |
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WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_TXFIFO_EMPTY_INT_CLR); |
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}else if(UART_RXFIFO_OVF_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_OVF_INT_ST)){ |
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WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_RXFIFO_OVF_INT_CLR); |
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DBG1("RX OVF!!\r\n"); |
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} |
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} |
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/****************************************************************************** |
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* FunctionName : uart_init |
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* Description : user interface for init uart |
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* Parameters : UartBautRate uart0_br - uart0 bautrate |
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* UartBautRate uart1_br - uart1 bautrate |
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* Returns : NONE |
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*******************************************************************************/ |
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#if UART_SELFTEST&UART_BUFF_EN |
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os_timer_t buff_timer_t; |
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void ICACHE_FLASH_ATTR |
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uart_test_rx() |
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{ |
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uint8 uart_buf[128]={0}; |
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uint16 len = 0; |
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len = rx_buff_deq(uart_buf, 128 ); |
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tx_buff_enq(uart_buf,len); |
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} |
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#endif |
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LOCAL void ICACHE_FLASH_ATTR /////// |
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uart_recvTask(os_event_t *events) |
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{ |
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if(events->sig == 0){ |
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#if UART_BUFF_EN |
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Uart_rx_buff_enq(); |
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#else |
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uint8 fifo_len = (READ_PERI_REG(UART_STATUS(UART0))>>UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT; |
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uint8 d_tmp = 0; |
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uint8 idx=0; |
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for(idx=0;idx<fifo_len;idx++) { |
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d_tmp = READ_PERI_REG(UART_FIFO(UART0)) & 0xFF; |
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uart_tx_one_char(UART0, d_tmp); |
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} |
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WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR|UART_RXFIFO_TOUT_INT_CLR); |
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uart_rx_intr_enable(UART0); |
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#endif |
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}else if(events->sig == 1){ |
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#if UART_BUFF_EN |
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//already move uart buffer output to uart empty interrupt |
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//tx_start_uart_buffer(UART0); |
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#else |
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#endif |
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} |
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} |
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void ICACHE_FLASH_ATTR |
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uart_init(UartBautRate uart0_br, UartBautRate uart1_br) |
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{ |
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/*this is a example to process uart data from task,please change the priority to fit your application task if exists*/ |
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system_os_task(uart_recvTask, uart_recvTaskPrio, uart_recvTaskQueue, uart_recvTaskQueueLen); //demo with a task to process the uart data |
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UartDev.baut_rate = uart0_br; |
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uart_config(UART0); |
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UartDev.baut_rate = uart1_br; |
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uart_config(UART1); |
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ETS_UART_INTR_ENABLE(); |
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#if UART_BUFF_EN |
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pTxBuffer = UART_AsyncBufferInit(UART_TX_BUFFER_SIZE); |
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pRxBuffer = UART_AsyncBufferInit(UART_RX_BUFFER_SIZE); |
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#endif |
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/*option 1: use default print, output from uart0 , will wait some time if fifo is full */ |
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//do nothing... |
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/*option 2: output from uart1,uart1 output will not wait , just for output debug info */ |
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/*os_printf output uart data via uart1(GPIO2)*/ |
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os_install_putc1((void *)uart1_write_char); //use this one to output debug information via uart1 // |
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/*option 3: output from uart0 will skip current byte if fifo is full now... */ |
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/*see uart0_write_char_no_wait:you can output via a buffer or output directly */ |
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/*os_printf output uart data via uart0 or uart buffer*/ |
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//os_install_putc1((void *)uart0_write_char_no_wait); //use this to print via uart0 |
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#if UART_SELFTEST&UART_BUFF_EN |
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os_timer_disarm(&buff_timer_t); |
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os_timer_setfn(&buff_timer_t, uart_test_rx , NULL); //a demo to process the data in uart rx buffer |
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os_timer_arm(&buff_timer_t,10,1); |
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#endif |
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} |
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//void ICACHE_FLASH_ATTR |
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//uart_reattach() |
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//{ |
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// uart_init(BIT_RATE_115200, BIT_RATE_115200); |
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//} |
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/****************************************************************************** |
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* FunctionName : uart_tx_one_char_no_wait |
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* Description : uart tx a single char without waiting for fifo |
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* Parameters : uint8 uart - uart port |
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* uint8 TxChar - char to tx |
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* Returns : STATUS |
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*******************************************************************************/ |
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STATUS uart_tx_one_char_no_wait(uint8 uart, uint8 TxChar) |
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{ |
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uint8 fifo_cnt = (( READ_PERI_REG(UART_STATUS(uart))>>UART_TXFIFO_CNT_S)& UART_TXFIFO_CNT); |
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if (fifo_cnt < 126) { |
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WRITE_PERI_REG(UART_FIFO(uart) , TxChar); |
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} |
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return OK; |
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} |
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//STATUS uart0_tx_one_char_no_wait(uint8 TxChar) |
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//{ |
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// uint8 fifo_cnt = (( READ_PERI_REG(UART_STATUS(UART0))>>UART_TXFIFO_CNT_S)& UART_TXFIFO_CNT); |
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// if (fifo_cnt < 126) { |
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// WRITE_PERI_REG(UART_FIFO(UART0) , TxChar); |
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// } |
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// return OK; |
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//} |
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/****************************************************************************** |
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* FunctionName : uart1_sendStr_no_wait |
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* Description : uart tx a string without waiting for every char, used for print debug info which can be lost |
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* Parameters : const char *str - string to be sent |
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* Returns : NONE |
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*******************************************************************************/ |
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void uart1_sendStr_no_wait(const char *str) |
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{ |
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while(*str){ |
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uart_tx_one_char_no_wait(UART1, *str++); |
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} |
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} |
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#if UART_BUFF_EN |
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/****************************************************************************** |
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* FunctionName : Uart_Buf_Init |
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* Description : tx buffer enqueue: fill a first linked buffer |
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* Parameters : char *pdata - data point to be enqueue |
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* Returns : NONE |
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*******************************************************************************/ |
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struct UartBuffer* ICACHE_FLASH_ATTR |
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UART_AsyncBufferInit(uint32 buf_size) |
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{ |
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uint32 heap_size = system_get_free_heap_size(); |
||||
if(heap_size <=buf_size){ |
||||
DBG1("no buf for uart\n\r"); |
||||
return NULL; |
||||
}else{ |
||||
DBG("test heap size: %d\n\r",heap_size); |
||||
struct UartBuffer* pBuff = (struct UartBuffer* )os_malloc(sizeof(struct UartBuffer)); |
||||
pBuff->UartBuffSize = buf_size; |
||||
pBuff->pUartBuff = (uint8*)os_malloc(pBuff->UartBuffSize); |
||||
pBuff->pInPos = pBuff->pUartBuff; |
||||
pBuff->pOutPos = pBuff->pUartBuff; |
||||
pBuff->Space = (uint16) pBuff->UartBuffSize; |
||||
pBuff->BuffState = OK; |
||||
pBuff->nextBuff = NULL; |
||||
pBuff->TcpControl = RUN; |
||||
return pBuff; |
||||
} |
||||
} |
||||
|
||||
|
||||
//copy uart buffer |
||||
LOCAL void Uart_Buf_Cpy(struct UartBuffer* pCur, char* pdata , uint16 data_len) |
||||
{ |
||||
if(data_len == 0) return; |
||||
|
||||
uint16 tail_len = (uint16) (pCur->pUartBuff + pCur->UartBuffSize - pCur->pInPos); |
||||
if(tail_len >= data_len){ //do not need to loop back the queue |
||||
os_memcpy(pCur->pInPos , pdata , data_len ); |
||||
pCur->pInPos += ( data_len ); |
||||
pCur->pInPos = (pCur->pUartBuff + (pCur->pInPos - pCur->pUartBuff) % pCur->UartBuffSize ); |
||||
pCur->Space -=data_len; |
||||
}else{ |
||||
os_memcpy(pCur->pInPos, pdata, tail_len); |
||||
pCur->pInPos += ( tail_len ); |
||||
pCur->pInPos = (pCur->pUartBuff + (pCur->pInPos - pCur->pUartBuff) % pCur->UartBuffSize ); |
||||
pCur->Space -=tail_len; |
||||
os_memcpy(pCur->pInPos, pdata+tail_len , data_len-tail_len); |
||||
pCur->pInPos += ( data_len-tail_len ); |
||||
pCur->pInPos = (pCur->pUartBuff + (pCur->pInPos - pCur->pUartBuff) % pCur->UartBuffSize ); |
||||
pCur->Space -=( data_len-tail_len); |
||||
} |
||||
|
||||
} |
||||
|
||||
/****************************************************************************** |
||||
* FunctionName : uart_buf_free |
||||
* Description : deinit of the tx buffer |
||||
* Parameters : struct UartBuffer* pTxBuff - tx buffer struct pointer |
||||
* Returns : NONE |
||||
*******************************************************************************/ |
||||
void ICACHE_FLASH_ATTR |
||||
uart_buf_free(struct UartBuffer* pBuff) |
||||
{ |
||||
os_free(pBuff->pUartBuff); |
||||
os_free(pBuff); |
||||
} |
||||
|
||||
|
||||
//rx buffer dequeue |
||||
uint16 ICACHE_FLASH_ATTR |
||||
rx_buff_deq(char* pdata, uint16 data_len) |
||||
{ |
||||
uint16 buf_len = (pRxBuffer->UartBuffSize- pRxBuffer->Space); |
||||
uint16 tail_len = pRxBuffer->pUartBuff + pRxBuffer->UartBuffSize - pRxBuffer->pOutPos ; |
||||
uint16 len_tmp = 0; |
||||
len_tmp = ((data_len > buf_len)?buf_len:data_len); |
||||
if(pRxBuffer->pOutPos <= pRxBuffer->pInPos){ |
||||
os_memcpy(pdata, pRxBuffer->pOutPos,len_tmp); |
||||
pRxBuffer->pOutPos+= len_tmp; |
||||
pRxBuffer->Space += len_tmp; |
||||
}else{ |
||||
if(len_tmp>tail_len){ |
||||
os_memcpy(pdata, pRxBuffer->pOutPos, tail_len); |
||||
pRxBuffer->pOutPos += tail_len; |
||||
pRxBuffer->pOutPos = (pRxBuffer->pUartBuff + (pRxBuffer->pOutPos- pRxBuffer->pUartBuff) % pRxBuffer->UartBuffSize ); |
||||
pRxBuffer->Space += tail_len; |
||||
|
||||
os_memcpy(pdata+tail_len , pRxBuffer->pOutPos, len_tmp-tail_len); |
||||
pRxBuffer->pOutPos+= ( len_tmp-tail_len ); |
||||
pRxBuffer->pOutPos= (pRxBuffer->pUartBuff + (pRxBuffer->pOutPos- pRxBuffer->pUartBuff) % pRxBuffer->UartBuffSize ); |
||||
pRxBuffer->Space +=( len_tmp-tail_len); |
||||
}else{ |
||||
//os_printf("case 3 in rx deq\n\r"); |
||||
os_memcpy(pdata, pRxBuffer->pOutPos, len_tmp); |
||||
pRxBuffer->pOutPos += len_tmp; |
||||
pRxBuffer->pOutPos = (pRxBuffer->pUartBuff + (pRxBuffer->pOutPos- pRxBuffer->pUartBuff) % pRxBuffer->UartBuffSize ); |
||||
pRxBuffer->Space += len_tmp; |
||||
} |
||||
} |
||||
if(pRxBuffer->Space >= UART_FIFO_LEN){ |
||||
uart_rx_intr_enable(UART0); |
||||
} |
||||
return len_tmp; |
||||
} |
||||
|
||||
|
||||
//move data from uart fifo to rx buffer |
||||
void Uart_rx_buff_enq() |
||||
{ |
||||
uint8 fifo_len,buf_idx; |
||||
uint8 fifo_data; |
||||
#if 1 |
||||
fifo_len = (READ_PERI_REG(UART_STATUS(UART0))>>UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT; |
||||
if(fifo_len >= pRxBuffer->Space){ |
||||
os_printf("buf full!!!\n\r"); |
||||
}else{ |
||||
buf_idx=0; |
||||
while(buf_idx < fifo_len){ |
||||
buf_idx++; |
||||
fifo_data = READ_PERI_REG(UART_FIFO(UART0)) & 0xFF; |
||||
*(pRxBuffer->pInPos++) = fifo_data; |
||||
if(pRxBuffer->pInPos == (pRxBuffer->pUartBuff + pRxBuffer->UartBuffSize)){ |
||||
pRxBuffer->pInPos = pRxBuffer->pUartBuff; |
||||
} |
||||
} |
||||
pRxBuffer->Space -= fifo_len ; |
||||
if(pRxBuffer->Space >= UART_FIFO_LEN){ |
||||
//os_printf("after rx enq buf enough\n\r"); |
||||
uart_rx_intr_enable(UART0); |
||||
} |
||||
} |
||||
#endif |
||||
} |
||||
|
||||
|
||||
//fill the uart tx buffer |
||||
void ICACHE_FLASH_ATTR |
||||
tx_buff_enq(char* pdata, uint16 data_len ) |
||||
{ |
||||
if(pTxBuffer == NULL){ |
||||
DBG1("\n\rnull, create buffer struct\n\r"); |
||||
pTxBuffer = UART_AsyncBufferInit(UART_TX_BUFFER_SIZE); |
||||
if(pTxBuffer!= NULL){ |
||||
Uart_Buf_Cpy(pTxBuffer , pdata, data_len ); |
||||
}else{ |
||||
DBG1("uart tx MALLOC no buf \n\r"); |
||||
} |
||||
}else{ |
||||
if(data_len <= pTxBuffer->Space){ |
||||
Uart_Buf_Cpy(pTxBuffer , pdata, data_len); |
||||
}else{ |
||||
DBG1("UART TX BUF FULL!!!!\n\r"); |
||||
} |
||||
} |
||||
#if 0 |
||||
if(pTxBuffer->Space <= URAT_TX_LOWER_SIZE){ |
||||
set_tcp_block(); |
||||
} |
||||
#endif |
||||
SET_PERI_REG_MASK(UART_CONF1(UART0), (UART_TX_EMPTY_THRESH_VAL & UART_TXFIFO_EMPTY_THRHD)<<UART_TXFIFO_EMPTY_THRHD_S); |
||||
SET_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA); |
||||
} |
||||
|
||||
|
||||
|
||||
//-------------------------------- |
||||
LOCAL void tx_fifo_insert(struct UartBuffer* pTxBuff, uint8 data_len, uint8 uart_no) |
||||
{ |
||||
uint8 i; |
||||
for(i = 0; i<data_len;i++){ |
||||
WRITE_PERI_REG(UART_FIFO(uart_no) , *(pTxBuff->pOutPos++)); |
||||
if(pTxBuff->pOutPos == (pTxBuff->pUartBuff + pTxBuff->UartBuffSize)){ |
||||
pTxBuff->pOutPos = pTxBuff->pUartBuff; |
||||
} |
||||
} |
||||
pTxBuff->pOutPos = (pTxBuff->pUartBuff + (pTxBuff->pOutPos - pTxBuff->pUartBuff) % pTxBuff->UartBuffSize ); |
||||
pTxBuff->Space += data_len; |
||||
} |
||||
|
||||
|
||||
/****************************************************************************** |
||||
* FunctionName : tx_start_uart_buffer |
||||
* Description : get data from the tx buffer and fill the uart tx fifo, co-work with the uart fifo empty interrupt |
||||
* Parameters : uint8 uart_no - uart port num |
||||
* Returns : NONE |
||||
*******************************************************************************/ |
||||
void tx_start_uart_buffer(uint8 uart_no) |
||||
{ |
||||
uint8 tx_fifo_len = (READ_PERI_REG(UART_STATUS(uart_no))>>UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT; |
||||
uint8 fifo_remain = UART_FIFO_LEN - tx_fifo_len ; |
||||
uint8 len_tmp; |
||||
uint16 tail_ptx_len,head_ptx_len,data_len; |
||||
//struct UartBuffer* pTxBuff = *get_buff_prt(); |
||||
|
||||
if(pTxBuffer){ |
||||
data_len = (pTxBuffer->UartBuffSize - pTxBuffer->Space); |
||||
if(data_len > fifo_remain){ |
||||
len_tmp = fifo_remain; |
||||
tx_fifo_enq(pTxBuffer, len_tmp, uart_no); |
||||
SET_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA); |
||||
}else{ |
||||
len_tmp = data_len; |
||||
tx_fifo_enq(pTxBuffer, len_tmp, uart_no); |
||||
} |
||||
}else{ |
||||
DBG1("pTxBuff null \n\r"); |
||||
} |
||||
} |
||||
|
||||
#endif |
||||
|
||||
|
||||
void uart_rx_intr_disable(uint8 uart_no) |
||||
{ |
||||
#if 1 |
||||
CLEAR_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_TOUT_INT_ENA); |
||||
#else |
||||
ETS_UART_INTR_DISABLE(); |
||||
#endif |
||||
} |
||||
|
||||
void uart_rx_intr_enable(uint8 uart_no) |
||||
{ |
||||
#if 1 |
||||
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA|UART_RXFIFO_TOUT_INT_ENA); |
||||
#else |
||||
ETS_UART_INTR_ENABLE(); |
||||
#endif |
||||
} |
||||
|
||||
|
||||
//======================================================== |
||||
LOCAL void |
||||
uart0_write_char(char c) |
||||
{ |
||||
if (c == '\n') { |
||||
uart_tx_one_char(UART0, '\r'); |
||||
uart_tx_one_char(UART0, '\n'); |
||||
} else if (c == '\r') { |
||||
} else { |
||||
uart_tx_one_char(UART0, c); |
||||
} |
||||
} |
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_SetWordLength(uint8 uart_no, UartBitsNum4Char len) |
||||
{ |
||||
SET_PERI_REG_BITS(UART_CONF0(uart_no),UART_BIT_NUM,len,UART_BIT_NUM_S); |
||||
} |
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_SetStopBits(uint8 uart_no, UartStopBitsNum bit_num) |
||||
{ |
||||
SET_PERI_REG_BITS(UART_CONF0(uart_no),UART_STOP_BIT_NUM,bit_num,UART_STOP_BIT_NUM_S); |
||||
} |
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_SetLineInverse(uint8 uart_no, UART_LineLevelInverse inverse_mask) |
||||
{ |
||||
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_LINE_INV_MASK); |
||||
SET_PERI_REG_MASK(UART_CONF0(uart_no), inverse_mask); |
||||
} |
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_SetParity(uint8 uart_no, UartParityMode Parity_mode) |
||||
{ |
||||
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_PARITY |UART_PARITY_EN); |
||||
if(Parity_mode==NONE_BITS){ |
||||
}else{ |
||||
SET_PERI_REG_MASK(UART_CONF0(uart_no), Parity_mode|UART_PARITY_EN); |
||||
} |
||||
} |
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_SetBaudrate(uint8 uart_no,uint32 baud_rate) |
||||
{ |
||||
uart_div_modify(uart_no, UART_CLK_FREQ /baud_rate); |
||||
} |
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_SetFlowCtrl(uint8 uart_no,UART_HwFlowCtrl flow_ctrl,uint8 rx_thresh) |
||||
{ |
||||
if(flow_ctrl&USART_HardwareFlowControl_RTS){ |
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS); |
||||
SET_PERI_REG_BITS(UART_CONF1(uart_no),UART_RX_FLOW_THRHD,rx_thresh,UART_RX_FLOW_THRHD_S); |
||||
SET_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN); |
||||
}else{ |
||||
CLEAR_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN); |
||||
} |
||||
if(flow_ctrl&USART_HardwareFlowControl_CTS){ |
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_UART0_CTS); |
||||
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN); |
||||
}else{ |
||||
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN); |
||||
} |
||||
} |
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_WaitTxFifoEmpty(uint8 uart_no , uint32 time_out_us) //do not use if tx flow control enabled |
||||
{ |
||||
uint32 t_s = system_get_time(); |
||||
while (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S)){ |
||||
|
||||
if(( system_get_time() - t_s )> time_out_us){ |
||||
break; |
||||
} |
||||
WRITE_PERI_REG(0X60000914, 0X73);//WTD |
||||
|
||||
} |
||||
} |
||||
|
||||
|
||||
bool ICACHE_FLASH_ATTR |
||||
UART_CheckOutputFinished(uint8 uart_no, uint32 time_out_us) |
||||
{ |
||||
uint32 t_start = system_get_time(); |
||||
uint8 tx_fifo_len; |
||||
uint32 tx_buff_len; |
||||
while(1){ |
||||
tx_fifo_len =( (READ_PERI_REG(UART_STATUS(uart_no))>>UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT); |
||||
if(pTxBuffer){ |
||||
tx_buff_len = ((pTxBuffer->UartBuffSize)-(pTxBuffer->Space)); |
||||
}else{ |
||||
tx_buff_len = 0; |
||||
} |
||||
|
||||
if( tx_fifo_len==0 && tx_buff_len==0){ |
||||
return TRUE; |
||||
} |
||||
if( system_get_time() - t_start > time_out_us){ |
||||
return FALSE; |
||||
} |
||||
WRITE_PERI_REG(0X60000914, 0X73);//WTD |
||||
} |
||||
} |
||||
|
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_ResetFifo(uint8 uart_no) |
||||
{ |
||||
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); |
||||
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); |
||||
} |
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_ClearIntrStatus(uint8 uart_no,uint32 clr_mask) |
||||
{ |
||||
WRITE_PERI_REG(UART_INT_CLR(uart_no), clr_mask); |
||||
} |
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_SetIntrEna(uint8 uart_no,uint32 ena_mask) |
||||
{ |
||||
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), ena_mask); |
||||
} |
||||
|
||||
|
||||
void ICACHE_FLASH_ATTR |
||||
UART_SetPrintPort(uint8 uart_no) |
||||
{ |
||||
if(uart_no==1){ |
||||
os_install_putc1(uart1_write_char); |
||||
}else{ |
||||
/*option 1: do not wait if uart fifo is full,drop current character*/ |
||||
os_install_putc1(uart0_write_char_no_wait); |
||||
/*option 2: wait for a while if uart fifo is full*/ |
||||
os_install_putc1(uart0_write_char); |
||||
} |
||||
} |
||||
|
||||
|
||||
//======================================================== |
||||
|
||||
// |
||||
///*test code*/ |
||||
//void ICACHE_FLASH_ATTR |
||||
//uart_init_2(UartBautRate uart0_br, UartBautRate uart1_br) |
||||
//{ |
||||
// // rom use 74880 baut_rate, here reinitialize |
||||
// UartDev.baut_rate = uart0_br; |
||||
// UartDev.exist_parity = STICK_PARITY_EN; |
||||
// UartDev.parity = EVEN_BITS; |
||||
// UartDev.stop_bits = ONE_STOP_BIT; |
||||
// UartDev.data_bits = EIGHT_BITS; |
||||
// |
||||
// uart_config(UART0); |
||||
// UartDev.baut_rate = uart1_br; |
||||
// uart_config(UART1); |
||||
// ETS_UART_INTR_ENABLE(); |
||||
// |
||||
// // install uart1 putc callback |
||||
// os_install_putc1((void *)uart1_write_char);//print output at UART1 |
||||
//} |
||||
// |
||||
// |
||||
@ -1,178 +0,0 @@ |
||||
/* |
||||
* File : uart.h |
||||
* Copyright (C) 2013 - 2016, Espressif Systems |
||||
* |
||||
* This program is free software: you can redistribute it and/or modify |
||||
* it under the terms of version 3 of the GNU General Public License as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License along |
||||
* with this program. If not, see <http://www.gnu.org/licenses/>. |
||||
*/ |
||||
#ifndef UART_APP_H |
||||
#define UART_APP_H |
||||
|
||||
#include <esp8266.h> |
||||
|
||||
#define UART_TX_BUFFER_SIZE 512 //Ring buffer length of tx buffer |
||||
#define UART_RX_BUFFER_SIZE 512 //Ring buffer length of rx buffer |
||||
|
||||
#define UART_BUFF_EN 1 //use uart buffer , FOR UART0 |
||||
#define UART_SELFTEST 0 //set 1:enable the loop test demo for uart buffer, FOR UART0 |
||||
|
||||
#define UART_HW_RTS 0 //set 1: enable uart hw flow control RTS, PIN MTDO, FOR UART0 |
||||
#define UART_HW_CTS 0 //set1: enable uart hw flow contrl CTS , PIN MTCK, FOR UART0 |
||||
|
||||
#define UART0 0 |
||||
#define UART1 1 |
||||
|
||||
typedef enum { |
||||
FIVE_BITS = 0x0, |
||||
SIX_BITS = 0x1, |
||||
SEVEN_BITS = 0x2, |
||||
EIGHT_BITS = 0x3 |
||||
} UartBitsNum4Char; |
||||
|
||||
typedef enum { |
||||
ONE_STOP_BIT = 0x1, |
||||
ONE_HALF_STOP_BIT = 0x2, |
||||
TWO_STOP_BIT = 0x3 |
||||
} UartStopBitsNum; |
||||
|
||||
typedef enum { |
||||
NONE_BITS = 0x2, |
||||
ODD_BITS = 1, |
||||
EVEN_BITS = 0 |
||||
} UartParityMode; |
||||
|
||||
typedef enum { |
||||
STICK_PARITY_DIS = 0, |
||||
STICK_PARITY_EN = 1 |
||||
} UartExistParity; |
||||
|
||||
typedef enum { |
||||
UART_None_Inverse = 0x0, |
||||
UART_Rxd_Inverse = UART_RXD_INV, |
||||
UART_CTS_Inverse = UART_CTS_INV, |
||||
UART_Txd_Inverse = UART_TXD_INV, |
||||
UART_RTS_Inverse = UART_RTS_INV, |
||||
} UART_LineLevelInverse; |
||||
|
||||
|
||||
typedef enum { |
||||
BIT_RATE_300 = 300, |
||||
BIT_RATE_600 = 600, |
||||
BIT_RATE_1200 = 1200, |
||||
BIT_RATE_2400 = 2400, |
||||
BIT_RATE_4800 = 4800, |
||||
BIT_RATE_9600 = 9600, |
||||
BIT_RATE_19200 = 19200, |
||||
BIT_RATE_38400 = 38400, |
||||
BIT_RATE_57600 = 57600, |
||||
BIT_RATE_74880 = 74880, |
||||
BIT_RATE_115200 = 115200, |
||||
BIT_RATE_230400 = 230400, |
||||
BIT_RATE_460800 = 460800, |
||||
BIT_RATE_921600 = 921600, |
||||
BIT_RATE_1843200 = 1843200, |
||||
BIT_RATE_3686400 = 3686400, |
||||
} UartBautRate; |
||||
|
||||
typedef enum { |
||||
NONE_CTRL, |
||||
HARDWARE_CTRL, |
||||
XON_XOFF_CTRL |
||||
} UartFlowCtrl; |
||||
|
||||
typedef enum { |
||||
USART_HardwareFlowControl_None = 0x0, |
||||
USART_HardwareFlowControl_RTS = 0x1, |
||||
USART_HardwareFlowControl_CTS = 0x2, |
||||
USART_HardwareFlowControl_CTS_RTS = 0x3 |
||||
} UART_HwFlowCtrl; |
||||
|
||||
typedef enum { |
||||
EMPTY, |
||||
UNDER_WRITE, |
||||
WRITE_OVER |
||||
} RcvMsgBuffState; |
||||
|
||||
typedef struct { |
||||
uint32 RcvBuffSize; |
||||
uint8 *pRcvMsgBuff; |
||||
uint8 *pWritePos; |
||||
uint8 *pReadPos; |
||||
uint8 TrigLvl; //JLU: may need to pad |
||||
RcvMsgBuffState BuffState; |
||||
} RcvMsgBuff; |
||||
|
||||
typedef struct { |
||||
uint32 TrxBuffSize; |
||||
uint8 *pTrxBuff; |
||||
} TrxMsgBuff; |
||||
|
||||
typedef enum { |
||||
BAUD_RATE_DET, |
||||
WAIT_SYNC_FRM, |
||||
SRCH_MSG_HEAD, |
||||
RCV_MSG_BODY, |
||||
RCV_ESC_CHAR, |
||||
} RcvMsgState; |
||||
|
||||
typedef struct { |
||||
UartBautRate baut_rate; |
||||
UartBitsNum4Char data_bits; |
||||
UartExistParity exist_parity; |
||||
UartParityMode parity; |
||||
UartStopBitsNum stop_bits; |
||||
UartFlowCtrl flow_ctrl; |
||||
RcvMsgBuff rcv_buff; |
||||
TrxMsgBuff trx_buff; |
||||
RcvMsgState rcv_state; |
||||
int received; |
||||
int buff_uart_no; //indicate which uart use tx/rx buffer |
||||
} UartDevice; |
||||
|
||||
void uart_init(UartBautRate uart0_br, UartBautRate uart1_br); |
||||
|
||||
/////////////////////////////////////// |
||||
#define UART_FIFO_LEN 128 //define the tx fifo length |
||||
#define UART_TX_EMPTY_THRESH_VAL 0x10 |
||||
|
||||
|
||||
typedef enum { |
||||
RUN = 0, |
||||
BLOCK = 1, |
||||
} TCPState; |
||||
|
||||
|
||||
//============================================== |
||||
#define FUNC_UART0_CTS 4 |
||||
#define FUNC_U0CTS 4 |
||||
#define FUNC_U1TXD_BK 2 |
||||
#define UART_LINE_INV_MASK (0x3f<<19) |
||||
void UART_SetWordLength(uint8 uart_no, UartBitsNum4Char len); |
||||
void UART_SetStopBits(uint8 uart_no, UartStopBitsNum bit_num); |
||||
void UART_SetLineInverse(uint8 uart_no, UART_LineLevelInverse inverse_mask); |
||||
void UART_SetParity(uint8 uart_no, UartParityMode Parity_mode); |
||||
void UART_SetBaudrate(uint8 uart_no, uint32 baud_rate); |
||||
void UART_SetFlowCtrl(uint8 uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh); |
||||
void UART_WaitTxFifoEmpty(uint8 uart_no, uint32 time_out_us); //do not use if tx flow control enabled |
||||
void UART_ResetFifo(uint8 uart_no); |
||||
void UART_ClearIntrStatus(uint8 uart_no, uint32 clr_mask); |
||||
void UART_SetIntrEna(uint8 uart_no, uint32 ena_mask); |
||||
void UART_SetPrintPort(uint8 uart_no); |
||||
bool UART_CheckOutputFinished(uint8 uart_no, uint32 time_out_us); |
||||
//============================================== |
||||
|
||||
// Buffer functions |
||||
uint16 rx_buff_deq(char* pdata, uint16 data_len); |
||||
void tx_buff_enq(char* pdata, uint16 data_len); |
||||
|
||||
#endif |
||||
|
||||
Loading…
Reference in new issue