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/* USER CODE BEGIN Header */ |
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/**
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****************************************************************************** |
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* @file stm32f1xx_hal_conf.h |
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* @brief HAL configuration file. |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2017 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file |
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* in the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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* |
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****************************************************************************** |
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*/ |
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/* USER CODE END Header */ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __STM32F1xx_HAL_CONF_H |
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#define __STM32F1xx_HAL_CONF_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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/* Exported types ------------------------------------------------------------*/ |
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/* Exported constants --------------------------------------------------------*/ |
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/* ########################## Module Selection ############################## */ |
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/**
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* @brief This is the list of modules to be used in the HAL driver |
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*/ |
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#define HAL_MODULE_ENABLED |
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/*#define HAL_ADC_MODULE_ENABLED */ |
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/*#define HAL_CRYP_MODULE_ENABLED */ |
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/*#define HAL_CAN_MODULE_ENABLED */ |
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/*#define HAL_CAN_LEGACY_MODULE_ENABLED */ |
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/*#define HAL_CEC_MODULE_ENABLED */ |
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/*#define HAL_CORTEX_MODULE_ENABLED */ |
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/*#define HAL_CRC_MODULE_ENABLED */ |
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/*#define HAL_DAC_MODULE_ENABLED */ |
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/*#define HAL_DMA_MODULE_ENABLED */ |
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/*#define HAL_ETH_MODULE_ENABLED */ |
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/*#define HAL_FLASH_MODULE_ENABLED */ |
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/*#define HAL_GPIO_MODULE_ENABLED */ |
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/*#define HAL_I2C_MODULE_ENABLED */ |
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/*#define HAL_I2S_MODULE_ENABLED */ |
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/*#define HAL_IRDA_MODULE_ENABLED */ |
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/*#define HAL_IWDG_MODULE_ENABLED */ |
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/*#define HAL_NOR_MODULE_ENABLED */ |
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/*#define HAL_NAND_MODULE_ENABLED */ |
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/*#define HAL_PCCARD_MODULE_ENABLED */ |
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/*#define HAL_PCD_MODULE_ENABLED */ |
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/*#define HAL_HCD_MODULE_ENABLED */ |
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/*#define HAL_PWR_MODULE_ENABLED */ |
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/*#define HAL_RCC_MODULE_ENABLED */ |
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/*#define HAL_RTC_MODULE_ENABLED */ |
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/*#define HAL_SD_MODULE_ENABLED */ |
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/*#define HAL_MMC_MODULE_ENABLED */ |
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/*#define HAL_SDRAM_MODULE_ENABLED */ |
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/*#define HAL_SMARTCARD_MODULE_ENABLED */ |
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/*#define HAL_SPI_MODULE_ENABLED */ |
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/*#define HAL_SRAM_MODULE_ENABLED */ |
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#define HAL_TIM_MODULE_ENABLED |
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/*#define HAL_UART_MODULE_ENABLED */ |
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/*#define HAL_USART_MODULE_ENABLED */ |
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/*#define HAL_WWDG_MODULE_ENABLED */ |
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#define HAL_CORTEX_MODULE_ENABLED |
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#define HAL_DMA_MODULE_ENABLED |
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#define HAL_FLASH_MODULE_ENABLED |
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#define HAL_EXTI_MODULE_ENABLED |
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#define HAL_GPIO_MODULE_ENABLED |
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#define HAL_PWR_MODULE_ENABLED |
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#define HAL_RCC_MODULE_ENABLED |
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/* ########################## Oscillator Values adaptation ####################*/ |
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/**
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* @brief Adjust the value of External High Speed oscillator (HSE) used in your application. |
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* This value is used by the RCC HAL module to compute the system frequency |
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* (when HSE is used as system clock source, directly or through the PLL). |
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*/ |
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#if !defined (HSE_VALUE) |
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#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ |
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#endif /* HSE_VALUE */ |
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#if !defined (HSE_STARTUP_TIMEOUT) |
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#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ |
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#endif /* HSE_STARTUP_TIMEOUT */ |
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/**
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* @brief Internal High Speed oscillator (HSI) value. |
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* This value is used by the RCC HAL module to compute the system frequency |
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* (when HSI is used as system clock source, directly or through the PLL). |
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*/ |
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#if !defined (HSI_VALUE) |
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#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/ |
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#endif /* HSI_VALUE */ |
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/**
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* @brief Internal Low Speed oscillator (LSI) value. |
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*/ |
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#if !defined (LSI_VALUE) |
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#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ |
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#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz |
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The real value may vary depending on the variations |
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in voltage and temperature. */ |
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/**
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* @brief External Low Speed oscillator (LSE) value. |
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* This value is used by the UART, RTC HAL module to compute the system frequency |
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*/ |
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#if !defined (LSE_VALUE) |
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#define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ |
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#endif /* LSE_VALUE */ |
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#if !defined (LSE_STARTUP_TIMEOUT) |
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#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ |
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#endif /* LSE_STARTUP_TIMEOUT */ |
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/* Tip: To avoid modifying this file each time you need to use different HSE,
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=== you can define the HSE value in your toolchain compiler preprocessor. */ |
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/* ########################### System Configuration ######################### */ |
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/**
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* @brief This is the HAL system configuration section |
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*/ |
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#define VDD_VALUE 3300U /*!< Value of VDD in mv */ |
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#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */ |
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#define USE_RTOS 0U |
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#define PREFETCH_ENABLE 1U |
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#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ |
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#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ |
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#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ |
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#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ |
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#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ |
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#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ |
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#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ |
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#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ |
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#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ |
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#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ |
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#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ |
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#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ |
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#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ |
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#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ |
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#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ |
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#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ |
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#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ |
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#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ |
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#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ |
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#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ |
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#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ |
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#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ |
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#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ |
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/* ########################## Assert Selection ############################## */ |
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/**
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* @brief Uncomment the line below to expanse the "assert_param" macro in the |
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* HAL drivers code |
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*/ |
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#define USE_FULL_ASSERT 1U |
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/* ################## Ethernet peripheral configuration ##################### */ |
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/* Section 1 : Ethernet peripheral configuration */ |
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/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ |
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#define MAC_ADDR0 2U |
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#define MAC_ADDR1 0U |
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#define MAC_ADDR2 0U |
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#define MAC_ADDR3 0U |
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#define MAC_ADDR4 0U |
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#define MAC_ADDR5 0U |
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/* Definition of the Ethernet driver buffers size and count */ |
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ |
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ |
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#define ETH_RXBUFNB 8U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ |
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#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ |
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/* Section 2: PHY configuration section */ |
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/* DP83848_PHY_ADDRESS Address*/ |
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#define DP83848_PHY_ADDRESS 0x01U |
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/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ |
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#define PHY_RESET_DELAY 0x000000FFU |
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/* PHY Configuration delay */ |
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#define PHY_CONFIG_DELAY 0x00000FFFU |
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#define PHY_READ_TO 0x0000FFFFU |
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#define PHY_WRITE_TO 0x0000FFFFU |
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/* Section 3: Common PHY Registers */ |
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#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ |
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#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ |
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#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ |
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#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ |
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#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ |
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#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ |
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#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ |
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#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ |
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#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ |
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#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ |
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#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ |
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#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ |
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#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ |
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#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ |
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#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ |
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/* Section 4: Extended PHY Registers */ |
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#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ |
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#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ |
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#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ |
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/* ################## SPI peripheral configuration ########################## */ |
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/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
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* Activated: CRC code is present inside driver |
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* Deactivated: CRC code cleaned from driver |
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*/ |
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#define USE_SPI_CRC 0U |
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/* Includes ------------------------------------------------------------------*/ |
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/**
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* @brief Include module's header file |
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*/ |
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#ifdef HAL_RCC_MODULE_ENABLED |
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#include "stm32f1xx_hal_rcc.h" |
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#endif /* HAL_RCC_MODULE_ENABLED */ |
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#ifdef HAL_GPIO_MODULE_ENABLED |
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#include "stm32f1xx_hal_gpio.h" |
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#endif /* HAL_GPIO_MODULE_ENABLED */ |
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#ifdef HAL_EXTI_MODULE_ENABLED |
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#include "stm32f1xx_hal_exti.h" |
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#endif /* HAL_EXTI_MODULE_ENABLED */ |
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#ifdef HAL_DMA_MODULE_ENABLED |
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#include "stm32f1xx_hal_dma.h" |
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#endif /* HAL_DMA_MODULE_ENABLED */ |
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#ifdef HAL_ETH_MODULE_ENABLED |
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#include "stm32f1xx_hal_eth.h" |
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#endif /* HAL_ETH_MODULE_ENABLED */ |
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#ifdef HAL_CAN_MODULE_ENABLED |
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#include "stm32f1xx_hal_can.h" |
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#endif /* HAL_CAN_MODULE_ENABLED */ |
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#ifdef HAL_CAN_LEGACY_MODULE_ENABLED |
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#include "Legacy/stm32f1xx_hal_can_legacy.h" |
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#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ |
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#ifdef HAL_CEC_MODULE_ENABLED |
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#include "stm32f1xx_hal_cec.h" |
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#endif /* HAL_CEC_MODULE_ENABLED */ |
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#ifdef HAL_CORTEX_MODULE_ENABLED |
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#include "stm32f1xx_hal_cortex.h" |
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#endif /* HAL_CORTEX_MODULE_ENABLED */ |
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#ifdef HAL_ADC_MODULE_ENABLED |
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#include "stm32f1xx_hal_adc.h" |
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#endif /* HAL_ADC_MODULE_ENABLED */ |
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#ifdef HAL_CRC_MODULE_ENABLED |
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#include "stm32f1xx_hal_crc.h" |
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#endif /* HAL_CRC_MODULE_ENABLED */ |
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#ifdef HAL_DAC_MODULE_ENABLED |
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#include "stm32f1xx_hal_dac.h" |
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#endif /* HAL_DAC_MODULE_ENABLED */ |
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#ifdef HAL_FLASH_MODULE_ENABLED |
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#include "stm32f1xx_hal_flash.h" |
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#endif /* HAL_FLASH_MODULE_ENABLED */ |
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#ifdef HAL_SRAM_MODULE_ENABLED |
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#include "stm32f1xx_hal_sram.h" |
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#endif /* HAL_SRAM_MODULE_ENABLED */ |
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#ifdef HAL_NOR_MODULE_ENABLED |
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#include "stm32f1xx_hal_nor.h" |
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#endif /* HAL_NOR_MODULE_ENABLED */ |
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#ifdef HAL_I2C_MODULE_ENABLED |
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#include "stm32f1xx_hal_i2c.h" |
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#endif /* HAL_I2C_MODULE_ENABLED */ |
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#ifdef HAL_I2S_MODULE_ENABLED |
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#include "stm32f1xx_hal_i2s.h" |
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#endif /* HAL_I2S_MODULE_ENABLED */ |
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#ifdef HAL_IWDG_MODULE_ENABLED |
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#include "stm32f1xx_hal_iwdg.h" |
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#endif /* HAL_IWDG_MODULE_ENABLED */ |
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#ifdef HAL_PWR_MODULE_ENABLED |
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#include "stm32f1xx_hal_pwr.h" |
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#endif /* HAL_PWR_MODULE_ENABLED */ |
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#ifdef HAL_RTC_MODULE_ENABLED |
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#include "stm32f1xx_hal_rtc.h" |
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#endif /* HAL_RTC_MODULE_ENABLED */ |
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#ifdef HAL_PCCARD_MODULE_ENABLED |
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#include "stm32f1xx_hal_pccard.h" |
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#endif /* HAL_PCCARD_MODULE_ENABLED */ |
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#ifdef HAL_SD_MODULE_ENABLED |
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#include "stm32f1xx_hal_sd.h" |
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#endif /* HAL_SD_MODULE_ENABLED */ |
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#ifdef HAL_NAND_MODULE_ENABLED |
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#include "stm32f1xx_hal_nand.h" |
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#endif /* HAL_NAND_MODULE_ENABLED */ |
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#ifdef HAL_SPI_MODULE_ENABLED |
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#include "stm32f1xx_hal_spi.h" |
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#endif /* HAL_SPI_MODULE_ENABLED */ |
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#ifdef HAL_TIM_MODULE_ENABLED |
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#include "stm32f1xx_hal_tim.h" |
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#endif /* HAL_TIM_MODULE_ENABLED */ |
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#ifdef HAL_UART_MODULE_ENABLED |
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#include "stm32f1xx_hal_uart.h" |
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#endif /* HAL_UART_MODULE_ENABLED */ |
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#ifdef HAL_USART_MODULE_ENABLED |
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#include "stm32f1xx_hal_usart.h" |
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#endif /* HAL_USART_MODULE_ENABLED */ |
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#ifdef HAL_IRDA_MODULE_ENABLED |
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#include "stm32f1xx_hal_irda.h" |
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#endif /* HAL_IRDA_MODULE_ENABLED */ |
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#ifdef HAL_SMARTCARD_MODULE_ENABLED |
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#include "stm32f1xx_hal_smartcard.h" |
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#endif /* HAL_SMARTCARD_MODULE_ENABLED */ |
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#ifdef HAL_WWDG_MODULE_ENABLED |
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#include "stm32f1xx_hal_wwdg.h" |
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#endif /* HAL_WWDG_MODULE_ENABLED */ |
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#ifdef HAL_PCD_MODULE_ENABLED |
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#include "stm32f1xx_hal_pcd.h" |
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#endif /* HAL_PCD_MODULE_ENABLED */ |
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||||||
|
|
||||||
#ifdef HAL_HCD_MODULE_ENABLED |
|
||||||
#include "stm32f1xx_hal_hcd.h" |
|
||||||
#endif /* HAL_HCD_MODULE_ENABLED */ |
|
||||||
|
|
||||||
#ifdef HAL_MMC_MODULE_ENABLED |
|
||||||
#include "stm32f1xx_hal_mmc.h" |
|
||||||
#endif /* HAL_MMC_MODULE_ENABLED */ |
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
#ifdef USE_FULL_ASSERT |
|
||||||
/**
|
|
||||||
* @brief The assert_param macro is used for function's parameters check. |
|
||||||
* @param expr If expr is false, it calls assert_failed function |
|
||||||
* which reports the name of the source file and the source |
|
||||||
* line number of the call that failed. |
|
||||||
* If expr is true, it returns no value. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) |
|
||||||
/* Exported functions ------------------------------------------------------- */ |
|
||||||
void assert_failed(uint8_t* file, uint32_t line); |
|
||||||
#else |
|
||||||
#define assert_param(expr) ((void)0U) |
|
||||||
#endif /* USE_FULL_ASSERT */ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* __STM32F1xx_HAL_CONF_H */ |
|
||||||
|
|
||||||
@ -1,87 +0,0 @@ |
|||||||
/* USER CODE BEGIN Header */ |
|
||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_msp.c |
|
||||||
* @brief This file provides code for the MSP Initialization |
|
||||||
* and de-Initialization codes. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* Copyright (c) 2023 STMicroelectronics. |
|
||||||
* All rights reserved. |
|
||||||
* |
|
||||||
* This software is licensed under terms that can be found in the LICENSE file |
|
||||||
* in the root directory of this software component. |
|
||||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
/* USER CODE END Header */ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "main.h" |
|
||||||
/* USER CODE BEGIN Includes */ |
|
||||||
|
|
||||||
/* USER CODE END Includes */ |
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/ |
|
||||||
/* USER CODE BEGIN TD */ |
|
||||||
|
|
||||||
/* USER CODE END TD */ |
|
||||||
|
|
||||||
/* Private define ------------------------------------------------------------*/ |
|
||||||
/* USER CODE BEGIN Define */ |
|
||||||
|
|
||||||
/* USER CODE END Define */ |
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/ |
|
||||||
/* USER CODE BEGIN Macro */ |
|
||||||
|
|
||||||
/* USER CODE END Macro */ |
|
||||||
|
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/* USER CODE BEGIN PV */ |
|
||||||
|
|
||||||
/* USER CODE END PV */ |
|
||||||
|
|
||||||
/* Private function prototypes -----------------------------------------------*/ |
|
||||||
/* USER CODE BEGIN PFP */ |
|
||||||
|
|
||||||
/* USER CODE END PFP */ |
|
||||||
|
|
||||||
/* External functions --------------------------------------------------------*/ |
|
||||||
/* USER CODE BEGIN ExternalFunctions */ |
|
||||||
|
|
||||||
/* USER CODE END ExternalFunctions */ |
|
||||||
|
|
||||||
/* USER CODE BEGIN 0 */ |
|
||||||
|
|
||||||
/* USER CODE END 0 */ |
|
||||||
/**
|
|
||||||
* Initializes the Global MSP. |
|
||||||
*/ |
|
||||||
void HAL_MspInit(void) |
|
||||||
{ |
|
||||||
/* USER CODE BEGIN MspInit 0 */ |
|
||||||
|
|
||||||
/* USER CODE END MspInit 0 */ |
|
||||||
|
|
||||||
__HAL_RCC_AFIO_CLK_ENABLE(); |
|
||||||
__HAL_RCC_PWR_CLK_ENABLE(); |
|
||||||
|
|
||||||
/* System interrupt init*/ |
|
||||||
/* PendSV_IRQn interrupt configuration */ |
|
||||||
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); |
|
||||||
|
|
||||||
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
|
|
||||||
*/ |
|
||||||
__HAL_AFIO_REMAP_SWJ_NOJTAG(); |
|
||||||
|
|
||||||
/* USER CODE BEGIN MspInit 1 */ |
|
||||||
|
|
||||||
/* USER CODE END MspInit 1 */ |
|
||||||
} |
|
||||||
|
|
||||||
/* USER CODE BEGIN 1 */ |
|
||||||
|
|
||||||
/* USER CODE END 1 */ |
|
||||||
@ -1,111 +0,0 @@ |
|||||||
/* USER CODE BEGIN Header */ |
|
||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_timebase_TIM.c |
|
||||||
* @brief HAL time base based on the hardware TIM. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* Copyright (c) 2023 STMicroelectronics. |
|
||||||
* All rights reserved. |
|
||||||
* |
|
||||||
* This software is licensed under terms that can be found in the LICENSE file |
|
||||||
* in the root directory of this software component. |
|
||||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
/* USER CODE END Header */ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal.h" |
|
||||||
#include "stm32f1xx_hal_tim.h" |
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/ |
|
||||||
/* Private define ------------------------------------------------------------*/ |
|
||||||
/* Private macro -------------------------------------------------------------*/ |
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
TIM_HandleTypeDef htim1; |
|
||||||
/* Private function prototypes -----------------------------------------------*/ |
|
||||||
/* Private functions ---------------------------------------------------------*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function configures the TIM1 as a time base source. |
|
||||||
* The time source is configured to have 1ms time base with a dedicated |
|
||||||
* Tick interrupt priority. |
|
||||||
* @note This function is called automatically at the beginning of program after |
|
||||||
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). |
|
||||||
* @param TickPriority: Tick interrupt priority. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) |
|
||||||
{ |
|
||||||
RCC_ClkInitTypeDef clkconfig; |
|
||||||
uint32_t uwTimclock = 0; |
|
||||||
uint32_t uwPrescalerValue = 0; |
|
||||||
uint32_t pFLatency; |
|
||||||
/*Configure the TIM1 IRQ priority */ |
|
||||||
HAL_NVIC_SetPriority(TIM1_UP_IRQn, TickPriority ,0); |
|
||||||
|
|
||||||
/* Enable the TIM1 global Interrupt */ |
|
||||||
HAL_NVIC_EnableIRQ(TIM1_UP_IRQn); |
|
||||||
|
|
||||||
/* Enable TIM1 clock */ |
|
||||||
__HAL_RCC_TIM1_CLK_ENABLE(); |
|
||||||
|
|
||||||
/* Get clock configuration */ |
|
||||||
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); |
|
||||||
|
|
||||||
/* Compute TIM1 clock */ |
|
||||||
uwTimclock = HAL_RCC_GetPCLK2Freq(); |
|
||||||
/* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */ |
|
||||||
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); |
|
||||||
|
|
||||||
/* Initialize TIM1 */ |
|
||||||
htim1.Instance = TIM1; |
|
||||||
|
|
||||||
/* Initialize TIMx peripheral as follow:
|
|
||||||
+ Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base. |
|
||||||
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. |
|
||||||
+ ClockDivision = 0 |
|
||||||
+ Counter direction = Up |
|
||||||
*/ |
|
||||||
htim1.Init.Period = (1000000U / 1000U) - 1U; |
|
||||||
htim1.Init.Prescaler = uwPrescalerValue; |
|
||||||
htim1.Init.ClockDivision = 0; |
|
||||||
htim1.Init.CounterMode = TIM_COUNTERMODE_UP; |
|
||||||
|
|
||||||
if(HAL_TIM_Base_Init(&htim1) == HAL_OK) |
|
||||||
{ |
|
||||||
/* Start the TIM time Base generation in interrupt mode */ |
|
||||||
return HAL_TIM_Base_Start_IT(&htim1); |
|
||||||
} |
|
||||||
|
|
||||||
/* Return function status */ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Suspend Tick increment. |
|
||||||
* @note Disable the tick increment by disabling TIM1 update interrupt. |
|
||||||
* @param None |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_SuspendTick(void) |
|
||||||
{ |
|
||||||
/* Disable TIM1 update Interrupt */ |
|
||||||
__HAL_TIM_DISABLE_IT(&htim1, TIM_IT_UPDATE); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Resume Tick increment. |
|
||||||
* @note Enable the tick increment by Enabling TIM1 update interrupt. |
|
||||||
* @param None |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_ResumeTick(void) |
|
||||||
{ |
|
||||||
/* Enable TIM1 Update interrupt */ |
|
||||||
__HAL_TIM_ENABLE_IT(&htim1, TIM_IT_UPDATE); |
|
||||||
} |
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,358 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief This file contains all the functions prototypes for the HAL |
|
||||||
* module driver. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef __STM32F1xx_HAL_H |
|
||||||
#define __STM32F1xx_HAL_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_conf.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup HAL
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
typedef enum |
|
||||||
{ |
|
||||||
HAL_TICK_FREQ_10HZ = 100U, |
|
||||||
HAL_TICK_FREQ_100HZ = 10U, |
|
||||||
HAL_TICK_FREQ_1KHZ = 1U, |
|
||||||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ |
|
||||||
} HAL_TickFreqTypeDef; |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* Exported types ------------------------------------------------------------*/ |
|
||||||
extern __IO uint32_t uwTick; |
|
||||||
extern uint32_t uwTickPrio; |
|
||||||
extern HAL_TickFreqTypeDef uwTickFreq; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
|
|
||||||
* @brief Freeze/Unfreeze Peripherals in Debug mode |
|
||||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
|
||||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
|
||||||
* STM32F101xF/G and STM32F103xF/G |
|
||||||
* STM32F10xx4 and STM32F10xx6 |
|
||||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
|
||||||
* debug mode (not accessible by the user software in normal mode). |
|
||||||
* Refer to errata sheet of these devices for more details. |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Peripherals on APB1 */ |
|
||||||
/**
|
|
||||||
* @brief TIM2 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief TIM3 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM4_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM4 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM5_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM5 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM6_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM6 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM7_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM7 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM12_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM12 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM13_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM13 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM14_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM14 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief WWDG Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief IWDG Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief I2C1 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
|
||||||
/**
|
|
||||||
* @brief I2C2 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_CAN1_STOP) |
|
||||||
/**
|
|
||||||
* @brief CAN1 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_CAN2_STOP) |
|
||||||
/**
|
|
||||||
* @brief CAN2 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Peripherals on APB2 */ |
|
||||||
#if defined (DBGMCU_CR_DBG_TIM1_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM1 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM8_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM8 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM9_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM9 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM10_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM10 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM11_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM11 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM15_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM15 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM16_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM16 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (DBGMCU_CR_DBG_TIM17_STOP) |
|
||||||
/**
|
|
||||||
* @brief TIM17 Peripherals Debug mode |
|
||||||
*/ |
|
||||||
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) |
|
||||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) |
|
||||||
#endif |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ |
|
||||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
|
||||||
((FREQ) == HAL_TICK_FREQ_1KHZ)) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
/** @addtogroup HAL_Exported_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/** @addtogroup HAL_Exported_Functions_Group1
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Initialization and de-initialization functions ******************************/ |
|
||||||
HAL_StatusTypeDef HAL_Init(void); |
|
||||||
HAL_StatusTypeDef HAL_DeInit(void); |
|
||||||
void HAL_MspInit(void); |
|
||||||
void HAL_MspDeInit(void); |
|
||||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup HAL_Exported_Functions_Group2
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Peripheral Control functions ************************************************/ |
|
||||||
void HAL_IncTick(void); |
|
||||||
void HAL_Delay(uint32_t Delay); |
|
||||||
uint32_t HAL_GetTick(void); |
|
||||||
uint32_t HAL_GetTickPrio(void); |
|
||||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); |
|
||||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void); |
|
||||||
void HAL_SuspendTick(void); |
|
||||||
void HAL_ResumeTick(void); |
|
||||||
uint32_t HAL_GetHalVersion(void); |
|
||||||
uint32_t HAL_GetREVID(void); |
|
||||||
uint32_t HAL_GetDEVID(void); |
|
||||||
uint32_t HAL_GetUIDw0(void); |
|
||||||
uint32_t HAL_GetUIDw1(void); |
|
||||||
uint32_t HAL_GetUIDw2(void); |
|
||||||
void HAL_DBGMCU_EnableDBGSleepMode(void); |
|
||||||
void HAL_DBGMCU_DisableDBGSleepMode(void); |
|
||||||
void HAL_DBGMCU_EnableDBGStopMode(void); |
|
||||||
void HAL_DBGMCU_DisableDBGStopMode(void); |
|
||||||
void HAL_DBGMCU_EnableDBGStandbyMode(void); |
|
||||||
void HAL_DBGMCU_DisableDBGStandbyMode(void); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* Private types -------------------------------------------------------------*/ |
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/** @defgroup HAL_Private_Variables HAL Private Variables
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* Private constants ---------------------------------------------------------*/ |
|
||||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* Private macros ------------------------------------------------------------*/ |
|
||||||
/* Private functions ---------------------------------------------------------*/ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* __STM32F1xx_HAL_H */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,410 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_cortex.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Header file of CORTEX HAL module. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef __STM32F1xx_HAL_CORTEX_H |
|
||||||
#define __STM32F1xx_HAL_CORTEX_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_def.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup CORTEX
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
/* Exported types ------------------------------------------------------------*/ |
|
||||||
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U) |
|
||||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
|
||||||
* @brief MPU Region initialization structure
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
uint8_t Enable; /*!< Specifies the status of the region.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
|
||||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
|
||||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
|
||||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
|
||||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
|
||||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
|
||||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
|
||||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
|
||||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
|
||||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
|
||||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
|
||||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
|
||||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
|
||||||
}MPU_Region_InitTypeDef; |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
#endif /* __MPU_PRESENT */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority |
|
||||||
4 bits for subpriority */ |
|
||||||
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority |
|
||||||
3 bits for subpriority */ |
|
||||||
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority |
|
||||||
2 bits for subpriority */ |
|
||||||
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority |
|
||||||
1 bits for subpriority */ |
|
||||||
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority |
|
||||||
0 bits for subpriority */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U |
|
||||||
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1) |
|
||||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U |
|
||||||
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk |
|
||||||
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk |
|
||||||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define MPU_REGION_ENABLE ((uint8_t)0x01) |
|
||||||
#define MPU_REGION_DISABLE ((uint8_t)0x00) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) |
|
||||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) |
|
||||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) |
|
||||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) |
|
||||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00) |
|
||||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01) |
|
||||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04) |
|
||||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05) |
|
||||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06) |
|
||||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07) |
|
||||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08) |
|
||||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) |
|
||||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) |
|
||||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) |
|
||||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) |
|
||||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) |
|
||||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) |
|
||||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) |
|
||||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) |
|
||||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) |
|
||||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) |
|
||||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) |
|
||||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) |
|
||||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) |
|
||||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) |
|
||||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) |
|
||||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) |
|
||||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) |
|
||||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) |
|
||||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) |
|
||||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) |
|
||||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) |
|
||||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) |
|
||||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) |
|
||||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01) |
|
||||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) |
|
||||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) |
|
||||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05) |
|
||||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00) |
|
||||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01) |
|
||||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02) |
|
||||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03) |
|
||||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04) |
|
||||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05) |
|
||||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06) |
|
||||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
#endif /* __MPU_PRESENT */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/* Exported Macros -----------------------------------------------------------*/ |
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
/** @addtogroup CORTEX_Exported_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup CORTEX_Exported_Functions_Group1
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Initialization and de-initialization functions *****************************/ |
|
||||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); |
|
||||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
|
||||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
|
||||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
|
||||||
void HAL_NVIC_SystemReset(void); |
|
||||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup CORTEX_Exported_Functions_Group2
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Peripheral Control functions ***********************************************/ |
|
||||||
uint32_t HAL_NVIC_GetPriorityGrouping(void); |
|
||||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); |
|
||||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
|
||||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
|
||||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
|
||||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); |
|
||||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
|
||||||
void HAL_SYSTICK_IRQHandler(void); |
|
||||||
void HAL_SYSTICK_Callback(void); |
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U) |
|
||||||
void HAL_MPU_Enable(uint32_t MPU_Control); |
|
||||||
void HAL_MPU_Disable(void); |
|
||||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
|
||||||
#endif /* __MPU_PRESENT */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/ |
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/* Private constants ---------------------------------------------------------*/ |
|
||||||
/* Private macros ------------------------------------------------------------*/ |
|
||||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ |
|
||||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
|
||||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
|
||||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
|
||||||
((GROUP) == NVIC_PRIORITYGROUP_4)) |
|
||||||
|
|
||||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
|
||||||
|
|
||||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
|
||||||
|
|
||||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) |
|
||||||
|
|
||||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ |
|
||||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U) |
|
||||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
|
||||||
((STATE) == MPU_REGION_DISABLE)) |
|
||||||
|
|
||||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
|
||||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
|
||||||
|
|
||||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
|
||||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
|
||||||
|
|
||||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
|
||||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
|
||||||
|
|
||||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
|
||||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
|
||||||
|
|
||||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ |
|
||||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
|
||||||
((TYPE) == MPU_TEX_LEVEL2)) |
|
||||||
|
|
||||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
|
||||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
|
||||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
|
||||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
|
||||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
|
||||||
((TYPE) == MPU_REGION_PRIV_RO_URO)) |
|
||||||
|
|
||||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
|
||||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
|
||||||
((NUMBER) == MPU_REGION_NUMBER7)) |
|
||||||
|
|
||||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ |
|
||||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
|
||||||
((SIZE) == MPU_REGION_SIZE_4GB)) |
|
||||||
|
|
||||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) |
|
||||||
#endif /* __MPU_PRESENT */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* __STM32F1xx_HAL_CORTEX_H */ |
|
||||||
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,210 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_def.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief This file contains HAL common defines, enumeration, macros and |
|
||||||
* structures definitions. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef __STM32F1xx_HAL_DEF |
|
||||||
#define __STM32F1xx_HAL_DEF |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx.h" |
|
||||||
#include "Legacy/stm32_hal_legacy.h" |
|
||||||
#include <stddef.h> |
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL Status structures definition |
|
||||||
*/ |
|
||||||
typedef enum |
|
||||||
{ |
|
||||||
HAL_OK = 0x00U, |
|
||||||
HAL_ERROR = 0x01U, |
|
||||||
HAL_BUSY = 0x02U, |
|
||||||
HAL_TIMEOUT = 0x03U |
|
||||||
} HAL_StatusTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL Lock structures definition |
|
||||||
*/ |
|
||||||
typedef enum |
|
||||||
{ |
|
||||||
HAL_UNLOCKED = 0x00U, |
|
||||||
HAL_LOCKED = 0x01U |
|
||||||
} HAL_LockTypeDef; |
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
#define HAL_MAX_DELAY 0xFFFFFFFFU |
|
||||||
|
|
||||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) |
|
||||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) |
|
||||||
|
|
||||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ |
|
||||||
do{ \
|
|
||||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
|
||||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
|
||||||
} while(0U) |
|
||||||
|
|
||||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ |
|
||||||
|
|
||||||
/** @brief Reset the Handle's State field.
|
|
||||||
* @param __HANDLE__ specifies the Peripheral Handle. |
|
||||||
* @note This macro can be used for the following purpose: |
|
||||||
* - When the Handle is declared as local variable; before passing it as parameter |
|
||||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro |
|
||||||
* to set to 0 the Handle's "State" field. |
|
||||||
* Otherwise, "State" field may have any random value and the first time the function |
|
||||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed |
|
||||||
* (i.e. HAL_PPP_MspInit() will not be executed). |
|
||||||
* - When there is a need to reconfigure the low level hardware: instead of calling |
|
||||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). |
|
||||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function |
|
||||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) |
|
||||||
|
|
||||||
#if (USE_RTOS == 1U) |
|
||||||
/* Reserved for future use */ |
|
||||||
#error "USE_RTOS should be 0 in the current HAL release" |
|
||||||
#else |
|
||||||
#define __HAL_LOCK(__HANDLE__) \ |
|
||||||
do{ \
|
|
||||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
|
||||||
{ \
|
|
||||||
return HAL_BUSY; \
|
|
||||||
} \
|
|
||||||
else \
|
|
||||||
{ \
|
|
||||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
|
||||||
} \
|
|
||||||
}while (0U) |
|
||||||
|
|
||||||
#define __HAL_UNLOCK(__HANDLE__) \ |
|
||||||
do{ \
|
|
||||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
|
||||||
}while (0U) |
|
||||||
#endif /* USE_RTOS */ |
|
||||||
|
|
||||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ |
|
||||||
#ifndef __weak |
|
||||||
#define __weak __attribute__((weak)) |
|
||||||
#endif |
|
||||||
#ifndef __packed |
|
||||||
#define __packed __attribute__((packed)) |
|
||||||
#endif |
|
||||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ |
|
||||||
#ifndef __weak |
|
||||||
#define __weak __attribute__((weak)) |
|
||||||
#endif /* __weak */ |
|
||||||
#ifndef __packed |
|
||||||
#define __packed __attribute__((__packed__)) |
|
||||||
#endif /* __packed */ |
|
||||||
#endif /* __GNUC__ */ |
|
||||||
|
|
||||||
|
|
||||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ |
|
||||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ |
|
||||||
#ifndef __ALIGN_BEGIN |
|
||||||
#define __ALIGN_BEGIN |
|
||||||
#endif |
|
||||||
#ifndef __ALIGN_END |
|
||||||
#define __ALIGN_END __attribute__ ((aligned (4))) |
|
||||||
#endif |
|
||||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ |
|
||||||
#ifndef __ALIGN_END |
|
||||||
#define __ALIGN_END __attribute__ ((aligned (4))) |
|
||||||
#endif /* __ALIGN_END */ |
|
||||||
#ifndef __ALIGN_BEGIN |
|
||||||
#define __ALIGN_BEGIN |
|
||||||
#endif /* __ALIGN_BEGIN */ |
|
||||||
#else |
|
||||||
#ifndef __ALIGN_END |
|
||||||
#define __ALIGN_END |
|
||||||
#endif /* __ALIGN_END */ |
|
||||||
#ifndef __ALIGN_BEGIN |
|
||||||
#if defined (__CC_ARM) /* ARM Compiler V5*/ |
|
||||||
#define __ALIGN_BEGIN __align(4) |
|
||||||
#elif defined (__ICCARM__) /* IAR Compiler */ |
|
||||||
#define __ALIGN_BEGIN |
|
||||||
#endif /* __CC_ARM */ |
|
||||||
#endif /* __ALIGN_BEGIN */ |
|
||||||
#endif /* __GNUC__ */ |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief __RAM_FUNC definition |
|
||||||
*/ |
|
||||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) |
|
||||||
/* ARM Compiler V4/V5 and V6
|
|
||||||
-------------------------- |
|
||||||
RAM functions are defined using the toolchain options. |
|
||||||
Functions that are executed in RAM should reside in a separate source module. |
|
||||||
Using the 'Options for File' dialog you can simply change the 'Code / Const' |
|
||||||
area of a module to a memory space in physical RAM. |
|
||||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target' |
|
||||||
dialog. |
|
||||||
*/ |
|
||||||
#define __RAM_FUNC |
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ ) |
|
||||||
/* ICCARM Compiler
|
|
||||||
--------------- |
|
||||||
RAM functions are defined using a specific toolchain keyword "__ramfunc". |
|
||||||
*/ |
|
||||||
#define __RAM_FUNC __ramfunc |
|
||||||
|
|
||||||
#elif defined ( __GNUC__ ) |
|
||||||
/* GNU Compiler
|
|
||||||
------------ |
|
||||||
RAM functions are defined using a specific toolchain attribute |
|
||||||
"__attribute__((section(".RamFunc")))". |
|
||||||
*/ |
|
||||||
#define __RAM_FUNC __attribute__((section(".RamFunc"))) |
|
||||||
|
|
||||||
#endif |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief __NOINLINE definition |
|
||||||
*/ |
|
||||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) |
|
||||||
/* ARM V4/V5 and V6 & GNU Compiler
|
|
||||||
------------------------------- |
|
||||||
*/ |
|
||||||
#define __NOINLINE __attribute__ ( (noinline) ) |
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ ) |
|
||||||
/* ICCARM Compiler
|
|
||||||
--------------- |
|
||||||
*/ |
|
||||||
#define __NOINLINE _Pragma("optimize = no_inline") |
|
||||||
|
|
||||||
#endif |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* ___STM32F1xx_HAL_DEF */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,457 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_dma.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Header file of DMA HAL module. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef __STM32F1xx_HAL_DMA_H |
|
||||||
#define __STM32F1xx_HAL_DMA_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_def.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup DMA
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DMA Configuration Structure definition |
|
||||||
*/ |
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
|
||||||
from memory to memory or from peripheral to memory. |
|
||||||
This parameter can be a value of @ref DMA_Data_transfer_direction */ |
|
||||||
|
|
||||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
|
||||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
|
||||||
|
|
||||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
|
||||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
|
||||||
|
|
||||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
|
||||||
This parameter can be a value of @ref DMA_Peripheral_data_size */ |
|
||||||
|
|
||||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
|
||||||
This parameter can be a value of @ref DMA_Memory_data_size */ |
|
||||||
|
|
||||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
|
||||||
This parameter can be a value of @ref DMA_mode |
|
||||||
@note The circular buffer mode cannot be used if the memory-to-memory |
|
||||||
data transfer is configured on the selected Channel */ |
|
||||||
|
|
||||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
|
||||||
This parameter can be a value of @ref DMA_Priority_level */ |
|
||||||
} DMA_InitTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL DMA State structures definition |
|
||||||
*/ |
|
||||||
typedef enum |
|
||||||
{ |
|
||||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ |
|
||||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ |
|
||||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ |
|
||||||
HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ |
|
||||||
}HAL_DMA_StateTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL DMA Error Code structure definition |
|
||||||
*/ |
|
||||||
typedef enum |
|
||||||
{ |
|
||||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
|
||||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ |
|
||||||
}HAL_DMA_LevelCompleteTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL DMA Callback ID structure definition |
|
||||||
*/ |
|
||||||
typedef enum |
|
||||||
{ |
|
||||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ |
|
||||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ |
|
||||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
|
||||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
|
||||||
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
|
||||||
|
|
||||||
}HAL_DMA_CallbackIDTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DMA handle Structure definition |
|
||||||
*/ |
|
||||||
typedef struct __DMA_HandleTypeDef |
|
||||||
{ |
|
||||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
|
||||||
|
|
||||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
|
||||||
|
|
||||||
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
|
||||||
|
|
||||||
void *Parent; /*!< Parent object state */
|
|
||||||
|
|
||||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
|
||||||
|
|
||||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
|
||||||
|
|
||||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
|
||||||
|
|
||||||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< DMA Error code */ |
|
||||||
|
|
||||||
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ |
|
||||||
|
|
||||||
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
|
||||||
|
|
||||||
} DMA_HandleTypeDef;
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Error_Code DMA Error Code
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ |
|
||||||
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ |
|
||||||
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ |
|
||||||
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ |
|
||||||
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ |
|
||||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
|
||||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
|
||||||
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
|
||||||
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ |
|
||||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
|
||||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ |
|
||||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
|
||||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_mode DMA mode
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define DMA_NORMAL 0x00000000U /*!< Normal mode */ |
|
||||||
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Priority_level DMA Priority level
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ |
|
||||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
|
||||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
|
||||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
|
||||||
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
|
||||||
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define DMA_FLAG_GL1 0x00000001U |
|
||||||
#define DMA_FLAG_TC1 0x00000002U |
|
||||||
#define DMA_FLAG_HT1 0x00000004U |
|
||||||
#define DMA_FLAG_TE1 0x00000008U |
|
||||||
#define DMA_FLAG_GL2 0x00000010U |
|
||||||
#define DMA_FLAG_TC2 0x00000020U |
|
||||||
#define DMA_FLAG_HT2 0x00000040U |
|
||||||
#define DMA_FLAG_TE2 0x00000080U |
|
||||||
#define DMA_FLAG_GL3 0x00000100U |
|
||||||
#define DMA_FLAG_TC3 0x00000200U |
|
||||||
#define DMA_FLAG_HT3 0x00000400U |
|
||||||
#define DMA_FLAG_TE3 0x00000800U |
|
||||||
#define DMA_FLAG_GL4 0x00001000U |
|
||||||
#define DMA_FLAG_TC4 0x00002000U |
|
||||||
#define DMA_FLAG_HT4 0x00004000U |
|
||||||
#define DMA_FLAG_TE4 0x00008000U |
|
||||||
#define DMA_FLAG_GL5 0x00010000U |
|
||||||
#define DMA_FLAG_TC5 0x00020000U |
|
||||||
#define DMA_FLAG_HT5 0x00040000U |
|
||||||
#define DMA_FLAG_TE5 0x00080000U |
|
||||||
#define DMA_FLAG_GL6 0x00100000U |
|
||||||
#define DMA_FLAG_TC6 0x00200000U |
|
||||||
#define DMA_FLAG_HT6 0x00400000U |
|
||||||
#define DMA_FLAG_TE6 0x00800000U |
|
||||||
#define DMA_FLAG_GL7 0x01000000U |
|
||||||
#define DMA_FLAG_TC7 0x02000000U |
|
||||||
#define DMA_FLAG_HT7 0x04000000U |
|
||||||
#define DMA_FLAG_TE7 0x08000000U |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/ |
|
||||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @brief Reset DMA handle state.
|
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the specified DMA Channel. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the specified DMA Channel. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
|
||||||
|
|
||||||
|
|
||||||
/* Interrupt & Flag management */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables the specified DMA Channel interrupts. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
|
||||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
|
||||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the specified DMA Channel interrupts. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
|
||||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
|
||||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified DMA Channel interrupt is enabled or not. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @param __INTERRUPT__: specifies the DMA interrupt source to check. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
|
||||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
|
||||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
|
||||||
* @retval The state of DMA_IT (SET or RESET). |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the number of remaining data units in the current DMA Channel transfer. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval The number of remaining data units in the current DMA Channel transfer. |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Include DMA HAL Extension module */ |
|
||||||
#include "stm32f1xx_hal_dma_ex.h" |
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
/** @addtogroup DMA_Exported_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup DMA_Exported_Functions_Group1
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Initialization and de-initialization functions *****************************/ |
|
||||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
|
||||||
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup DMA_Exported_Functions_Group2
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* IO operation functions *****************************************************/ |
|
||||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
|
||||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
|
||||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
|
||||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
|
||||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
|
||||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
|
||||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); |
|
||||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup DMA_Exported_Functions_Group3
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Peripheral State and Error functions ***************************************/ |
|
||||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
|
||||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/ |
|
||||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
|
||||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
|
||||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
|
||||||
|
|
||||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) |
|
||||||
|
|
||||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
|
||||||
((STATE) == DMA_PINC_DISABLE)) |
|
||||||
|
|
||||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
|
||||||
((STATE) == DMA_MINC_DISABLE)) |
|
||||||
|
|
||||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
|
||||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
|
||||||
((SIZE) == DMA_PDATAALIGN_WORD)) |
|
||||||
|
|
||||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
|
||||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
|
||||||
((SIZE) == DMA_MDATAALIGN_WORD )) |
|
||||||
|
|
||||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
|
||||||
((MODE) == DMA_CIRCULAR)) |
|
||||||
|
|
||||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
|
||||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
|
||||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
|
||||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* __STM32F1xx_HAL_DMA_H */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,277 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_dma_ex.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Header file of DMA HAL extension module. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef __STM32F1xx_HAL_DMA_EX_H |
|
||||||
#define __STM32F1xx_HAL_DMA_EX_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_def.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMAEx DMAEx
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Interrupt & Flag management */ |
|
||||||
#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ |
|
||||||
defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) |
|
||||||
/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the current DMA Channel transfer complete flag. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval The specified transfer complete flag index. |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
|
||||||
DMA_FLAG_TC5) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the current DMA Channel half transfer complete flag. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval The specified half transfer complete flag index. |
|
||||||
*/
|
|
||||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
|
||||||
DMA_FLAG_HT5) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the current DMA Channel transfer error flag. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval The specified transfer error flag index. |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
|
||||||
DMA_FLAG_TE5) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the current DMA Channel Global interrupt flag. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval The specified transfer error flag index. |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
|
|
||||||
DMA_FLAG_GL5) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the DMA Channel pending flags. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @param __FLAG__: Get the specified flag. |
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg DMA_FLAG_TCx: Transfer complete flag |
|
||||||
* @arg DMA_FLAG_HTx: Half transfer complete flag |
|
||||||
* @arg DMA_FLAG_TEx: Transfer error flag |
|
||||||
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
|
|
||||||
* @retval The state of FLAG (SET or RESET). |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
|
||||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
|
|
||||||
(DMA1->ISR & (__FLAG__))) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the DMA Channel pending flags. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @param __FLAG__: specifies the flag to clear. |
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg DMA_FLAG_TCx: Transfer complete flag |
|
||||||
* @arg DMA_FLAG_HTx: Half transfer complete flag |
|
||||||
* @arg DMA_FLAG_TEx: Transfer error flag |
|
||||||
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
|
||||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
|
|
||||||
(DMA1->IFCR = (__FLAG__))) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#else |
|
||||||
/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the current DMA Channel transfer complete flag. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval The specified transfer complete flag index. |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
|
||||||
DMA_FLAG_TC7) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the current DMA Channel half transfer complete flag. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval The specified half transfer complete flag index. |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
|
||||||
DMA_FLAG_HT7) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the current DMA Channel transfer error flag. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval The specified transfer error flag index. |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
|
||||||
DMA_FLAG_TE7) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the current DMA Channel Global interrupt flag. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @retval The specified transfer error flag index. |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
|
||||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
|
|
||||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
|
|
||||||
DMA_FLAG_GL7) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the DMA Channel pending flags. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @param __FLAG__: Get the specified flag. |
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg DMA_FLAG_TCx: Transfer complete flag |
|
||||||
* @arg DMA_FLAG_HTx: Half transfer complete flag |
|
||||||
* @arg DMA_FLAG_TEx: Transfer error flag |
|
||||||
* @arg DMA_FLAG_GLx: Global interrupt flag |
|
||||||
* Where x can be 1_7 to select the DMA Channel flag.
|
|
||||||
* @retval The state of FLAG (SET or RESET). |
|
||||||
*/ |
|
||||||
|
|
||||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the DMA Channel pending flags. |
|
||||||
* @param __HANDLE__: DMA handle |
|
||||||
* @param __FLAG__: specifies the flag to clear. |
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg DMA_FLAG_TCx: Transfer complete flag |
|
||||||
* @arg DMA_FLAG_HTx: Half transfer complete flag |
|
||||||
* @arg DMA_FLAG_TEx: Transfer error flag |
|
||||||
* @arg DMA_FLAG_GLx: Global interrupt flag |
|
||||||
* Where x can be 1_7 to select the DMA Channel flag.
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */ |
|
||||||
/* STM32F103xG || STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
#endif /* __STM32F1xx_HAL_DMA_H */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,320 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_exti.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Header file of EXTI HAL module. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef STM32F1xx_HAL_EXTI_H |
|
||||||
#define STM32F1xx_HAL_EXTI_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_def.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup EXTI EXTI
|
|
||||||
* @brief EXTI HAL module driver |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL EXTI common Callback ID enumeration definition |
|
||||||
*/ |
|
||||||
typedef enum |
|
||||||
{ |
|
||||||
HAL_EXTI_COMMON_CB_ID = 0x00U |
|
||||||
} EXTI_CallbackIDTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Handle structure definition |
|
||||||
*/ |
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
uint32_t Line; /*!< Exti line number */ |
|
||||||
void (* PendingCallback)(void); /*!< Exti pending callback */ |
|
||||||
} EXTI_HandleTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Configuration structure definition |
|
||||||
*/ |
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
|
||||||
can be a value of @ref EXTI_Line */ |
|
||||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
|
||||||
This parameter can be a combination of @ref EXTI_Mode */ |
|
||||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
|
||||||
can be a value of @ref EXTI_Trigger */ |
|
||||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
|
||||||
This parameter is only possible for line 0 to 15. It |
|
||||||
can be a value of @ref EXTI_GPIOSel */ |
|
||||||
} EXTI_ConfigTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup EXTI_Line EXTI Line
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ |
|
||||||
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ |
|
||||||
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ |
|
||||||
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ |
|
||||||
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ |
|
||||||
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ |
|
||||||
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ |
|
||||||
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ |
|
||||||
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ |
|
||||||
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ |
|
||||||
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ |
|
||||||
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ |
|
||||||
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ |
|
||||||
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ |
|
||||||
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ |
|
||||||
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ |
|
||||||
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ |
|
||||||
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ |
|
||||||
#if defined(EXTI_IMR_IM18) |
|
||||||
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */ |
|
||||||
#endif /* EXTI_IMR_IM18 */ |
|
||||||
#if defined(EXTI_IMR_IM19) |
|
||||||
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ |
|
||||||
#endif /* EXTI_IMR_IM19 */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup EXTI_Mode EXTI Mode
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define EXTI_MODE_NONE 0x00000000u |
|
||||||
#define EXTI_MODE_INTERRUPT 0x00000001u |
|
||||||
#define EXTI_MODE_EVENT 0x00000002u |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define EXTI_TRIGGER_NONE 0x00000000u |
|
||||||
#define EXTI_TRIGGER_RISING 0x00000001u |
|
||||||
#define EXTI_TRIGGER_FALLING 0x00000002u |
|
||||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
|
||||||
* @brief |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define EXTI_GPIOA 0x00000000u |
|
||||||
#define EXTI_GPIOB 0x00000001u |
|
||||||
#define EXTI_GPIOC 0x00000002u |
|
||||||
#define EXTI_GPIOD 0x00000003u |
|
||||||
#if defined (GPIOE) |
|
||||||
#define EXTI_GPIOE 0x00000004u |
|
||||||
#endif /* GPIOE */ |
|
||||||
#if defined (GPIOF) |
|
||||||
#define EXTI_GPIOF 0x00000005u |
|
||||||
#endif /* GPIOF */ |
|
||||||
#if defined (GPIOG) |
|
||||||
#define EXTI_GPIOG 0x00000006u |
|
||||||
#endif /* GPIOG */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private constants --------------------------------------------------------*/ |
|
||||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/**
|
|
||||||
* @brief EXTI Line property definition |
|
||||||
*/ |
|
||||||
#define EXTI_PROPERTY_SHIFT 24u |
|
||||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) |
|
||||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) |
|
||||||
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI bit usage |
|
||||||
*/ |
|
||||||
#define EXTI_PIN_MASK 0x0000001Fu |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Mask for interrupt & event mode |
|
||||||
*/ |
|
||||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Mask for trigger possibilities |
|
||||||
*/ |
|
||||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI Line number |
|
||||||
*/ |
|
||||||
#if defined(EXTI_IMR_IM19) |
|
||||||
#define EXTI_LINE_NB 20UL |
|
||||||
#elif defined(EXTI_IMR_IM18) |
|
||||||
#define EXTI_LINE_NB 19UL |
|
||||||
#else /* EXTI_IMR_IM17 */ |
|
||||||
#define EXTI_LINE_NB 18UL |
|
||||||
#endif /* EXTI_IMR_IM19 */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/ |
|
||||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ |
|
||||||
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
|
||||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
|
||||||
(((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) |
|
||||||
|
|
||||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ |
|
||||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) |
|
||||||
|
|
||||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) |
|
||||||
|
|
||||||
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) |
|
||||||
|
|
||||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) |
|
||||||
|
|
||||||
#if defined (GPIOG) |
|
||||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
|
||||||
((__PORT__) == EXTI_GPIOB) || \
|
|
||||||
((__PORT__) == EXTI_GPIOC) || \
|
|
||||||
((__PORT__) == EXTI_GPIOD) || \
|
|
||||||
((__PORT__) == EXTI_GPIOE) || \
|
|
||||||
((__PORT__) == EXTI_GPIOF) || \
|
|
||||||
((__PORT__) == EXTI_GPIOG)) |
|
||||||
#elif defined (GPIOF) |
|
||||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
|
||||||
((__PORT__) == EXTI_GPIOB) || \
|
|
||||||
((__PORT__) == EXTI_GPIOC) || \
|
|
||||||
((__PORT__) == EXTI_GPIOD) || \
|
|
||||||
((__PORT__) == EXTI_GPIOE) || \
|
|
||||||
((__PORT__) == EXTI_GPIOF)) |
|
||||||
#elif defined (GPIOE) |
|
||||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
|
||||||
((__PORT__) == EXTI_GPIOB) || \
|
|
||||||
((__PORT__) == EXTI_GPIOC) || \
|
|
||||||
((__PORT__) == EXTI_GPIOD) || \
|
|
||||||
((__PORT__) == EXTI_GPIOE)) |
|
||||||
#else |
|
||||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
|
||||||
((__PORT__) == EXTI_GPIOB) || \
|
|
||||||
((__PORT__) == EXTI_GPIOC) || \
|
|
||||||
((__PORT__) == EXTI_GPIOD)) |
|
||||||
#endif /* GPIOG */ |
|
||||||
|
|
||||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
|
||||||
* @brief EXTI Exported Functions |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
|
||||||
* @brief Configuration functions |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Configuration functions ****************************************************/ |
|
||||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); |
|
||||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); |
|
||||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); |
|
||||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); |
|
||||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
|
||||||
* @brief IO operation functions |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* IO operation functions *****************************************************/ |
|
||||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); |
|
||||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); |
|
||||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); |
|
||||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* STM32F1xx_HAL_EXTI_H */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,328 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_flash.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Header file of Flash HAL module. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef __STM32F1xx_HAL_FLASH_H |
|
||||||
#define __STM32F1xx_HAL_FLASH_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_def.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASH
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASH_Private_Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASH_Private_Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ |
|
||||||
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
|
|
||||||
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
|
|
||||||
|
|
||||||
#if defined(FLASH_ACR_LATENCY) |
|
||||||
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ |
|
||||||
((__LATENCY__) == FLASH_LATENCY_1) || \
|
|
||||||
((__LATENCY__) == FLASH_LATENCY_2)) |
|
||||||
|
|
||||||
#else |
|
||||||
#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) |
|
||||||
#endif /* FLASH_ACR_LATENCY */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief FLASH Procedure structure definition |
|
||||||
*/ |
|
||||||
typedef enum
|
|
||||||
{ |
|
||||||
FLASH_PROC_NONE = 0U,
|
|
||||||
FLASH_PROC_PAGEERASE = 1U, |
|
||||||
FLASH_PROC_MASSERASE = 2U, |
|
||||||
FLASH_PROC_PROGRAMHALFWORD = 3U, |
|
||||||
FLASH_PROC_PROGRAMWORD = 4U, |
|
||||||
FLASH_PROC_PROGRAMDOUBLEWORD = 5U |
|
||||||
} FLASH_ProcedureTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief FLASH handle Structure definition
|
|
||||||
*/ |
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ |
|
||||||
|
|
||||||
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ |
|
||||||
|
|
||||||
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ |
|
||||||
|
|
||||||
__IO uint64_t Data; /*!< Internal variable to save data to be programmed */ |
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< FLASH locking object */ |
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< FLASH error code
|
|
||||||
This parameter can be a value of @ref FLASH_Error_Codes */ |
|
||||||
} FLASH_ProcessTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASH_Error_Codes FLASH Error Codes
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ |
|
||||||
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ |
|
||||||
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ |
|
||||||
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!<Program a half-word (16-bit) at a specified address.*/ |
|
||||||
#define FLASH_TYPEPROGRAM_WORD 0x02U /*!<Program a word (32-bit) at a specified address.*/ |
|
||||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#if defined(FLASH_ACR_LATENCY) |
|
||||||
/** @defgroup FLASH_Latency FLASH Latency
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
|
||||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ |
|
||||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#else |
|
||||||
/** @defgroup FLASH_Latency FLASH Latency
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* FLASH_ACR_LATENCY */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
|
||||||
* @brief macros to control FLASH features
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
|
|
||||||
* @brief macros to handle FLASH half cycle |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the FLASH half cycle access. |
|
||||||
* @note half cycle access can only be used with a low-frequency clock of less than |
|
||||||
8 MHz that can be obtained with the use of HSI or HSE but not of PLL. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the FLASH half cycle access. |
|
||||||
* @note half cycle access can only be used with a low-frequency clock of less than |
|
||||||
8 MHz that can be obtained with the use of HSI or HSE but not of PLL. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#if defined(FLASH_ACR_LATENCY) |
|
||||||
/** @defgroup FLASH_EM_Latency FLASH Latency
|
|
||||||
* @brief macros to handle FLASH Latency |
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set the FLASH Latency. |
|
||||||
* @param __LATENCY__ FLASH Latency
|
|
||||||
* The value of this parameter depend on device used within the same series |
|
||||||
* @retval None |
|
||||||
*/
|
|
||||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the FLASH Latency. |
|
||||||
* @retval FLASH Latency
|
|
||||||
* The value of this parameter depend on device used within the same series |
|
||||||
*/
|
|
||||||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* FLASH_ACR_LATENCY */ |
|
||||||
/** @defgroup FLASH_Prefetch FLASH Prefetch
|
|
||||||
* @brief macros to handle FLASH Prefetch buffer |
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
/**
|
|
||||||
* @brief Enable the FLASH prefetch buffer. |
|
||||||
* @retval None |
|
||||||
*/
|
|
||||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the FLASH prefetch buffer. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include FLASH HAL Extended module */ |
|
||||||
#include "stm32f1xx_hal_flash_ex.h" |
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
/** @addtogroup FLASH_Exported_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* IO operation functions *****************************************************/ |
|
||||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); |
|
||||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); |
|
||||||
|
|
||||||
/* FLASH IRQ handler function */ |
|
||||||
void HAL_FLASH_IRQHandler(void); |
|
||||||
/* Callbacks in non blocking modes */
|
|
||||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); |
|
||||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Peripheral Control functions ***********************************************/ |
|
||||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void); |
|
||||||
HAL_StatusTypeDef HAL_FLASH_Lock(void); |
|
||||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); |
|
||||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); |
|
||||||
void HAL_FLASH_OB_Launch(void); |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Peripheral State and Error functions ***************************************/ |
|
||||||
uint32_t HAL_FLASH_GetError(void); |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private function -------------------------------------------------*/ |
|
||||||
/** @addtogroup FLASH_Private_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* __STM32F1xx_HAL_FLASH_H */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
|
|
||||||
@ -1,786 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_flash_ex.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Header file of Flash HAL Extended module. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef __STM32F1xx_HAL_FLASH_EX_H |
|
||||||
#define __STM32F1xx_HAL_FLASH_EX_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_def.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASHEx
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup FLASHEx_Private_Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U |
|
||||||
#define OBR_REG_INDEX 1U |
|
||||||
#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup FLASHEx_Private_Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) |
|
||||||
|
|
||||||
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) |
|
||||||
|
|
||||||
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) |
|
||||||
|
|
||||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) |
|
||||||
|
|
||||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) |
|
||||||
|
|
||||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) |
|
||||||
|
|
||||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) |
|
||||||
|
|
||||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
/* Low Density */ |
|
||||||
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) |
|
||||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \ |
|
||||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU)) |
|
||||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
|
||||||
|
|
||||||
/* Medium Density */ |
|
||||||
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) |
|
||||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ |
|
||||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
|
|
||||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
|
|
||||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU)))) |
|
||||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ |
|
||||||
|
|
||||||
/* High Density */ |
|
||||||
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) |
|
||||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \ |
|
||||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
|
|
||||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU))) |
|
||||||
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ |
|
||||||
|
|
||||||
/* XL Density */ |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \ |
|
||||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU)) |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
/* Connectivity Line */ |
|
||||||
#if (defined(STM32F105xC) || defined(STM32F107xC)) |
|
||||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \ |
|
||||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
|
|
||||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU))) |
|
||||||
#endif /* STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ |
|
||||||
((BANK) == FLASH_BANK_2) || \
|
|
||||||
((BANK) == FLASH_BANK_BOTH)) |
|
||||||
#else |
|
||||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
/* Low Density */ |
|
||||||
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) |
|
||||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ |
|
||||||
((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU))) |
|
||||||
|
|
||||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
|
||||||
|
|
||||||
/* Medium Density */ |
|
||||||
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) |
|
||||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ |
|
||||||
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
|
|
||||||
((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
|
|
||||||
((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) |
|
||||||
|
|
||||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ |
|
||||||
|
|
||||||
/* High Density */ |
|
||||||
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) |
|
||||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \ |
|
||||||
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
|
|
||||||
((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) |
|
||||||
|
|
||||||
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ |
|
||||||
|
|
||||||
/* XL Density */ |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \ |
|
||||||
((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU))) |
|
||||||
|
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
/* Connectivity Line */ |
|
||||||
#if (defined(STM32F105xC) || defined(STM32F107xC)) |
|
||||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ |
|
||||||
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
|
|
||||||
((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) |
|
||||||
|
|
||||||
#endif /* STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief FLASH Erase structure definition |
|
||||||
*/ |
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
|
|
||||||
This parameter can be a value of @ref FLASHEx_Type_Erase */ |
|
||||||
|
|
||||||
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
|
|
||||||
This parameter must be a value of @ref FLASHEx_Banks */
|
|
||||||
|
|
||||||
uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
|
|
||||||
This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
|
|
||||||
(x = 1 or 2 depending on devices)*/ |
|
||||||
|
|
||||||
uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
|
|
||||||
This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ |
|
||||||
|
|
||||||
} FLASH_EraseInitTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief FLASH Options bytes program structure definition |
|
||||||
*/ |
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
|
|
||||||
This parameter can be a value of @ref FLASHEx_OB_Type */ |
|
||||||
|
|
||||||
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
|
|
||||||
This parameter can be a value of @ref FLASHEx_OB_WRP_State */ |
|
||||||
|
|
||||||
uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
|
|
||||||
This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ |
|
||||||
|
|
||||||
uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
|
|
||||||
This parameter must be a value of @ref FLASHEx_Banks */
|
|
||||||
|
|
||||||
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
|
|
||||||
This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
|
|
||||||
IWDG / STOP / STDBY / BOOT1 |
|
||||||
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
|
|
||||||
@ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ |
|
||||||
#else |
|
||||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
|
|
||||||
IWDG / STOP / STDBY |
|
||||||
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
|
|
||||||
@ref FLASHEx_OB_nRST_STDBY */ |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
|
|
||||||
This parameter can be a value of @ref FLASHEx_OB_Data_Address */ |
|
||||||
|
|
||||||
uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
|
|
||||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
|
||||||
} FLASH_OBProgramInitTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASHEx_Constants FLASH Constants
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASHEx_Page_Size Page Size
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) |
|
||||||
#define FLASH_PAGE_SIZE 0x400U |
|
||||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
|
||||||
/* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
|
||||||
|
|
||||||
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) |
|
||||||
#define FLASH_PAGE_SIZE 0x800U |
|
||||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
|
||||||
/* STM32F101xG || STM32F103xG */
|
|
||||||
/* STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASHEx_Type_Erase Type Erase
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
#define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/ |
|
||||||
#define FLASH_TYPEERASE_MASSERASE 0x02U /*!<Flash mass erase activation*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASHEx_Banks Banks
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
#define FLASH_BANK_1 1U /*!< Bank 1 */ |
|
||||||
#define FLASH_BANK_2 2U /*!< Bank 2 */ |
|
||||||
#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ |
|
||||||
|
|
||||||
#else |
|
||||||
#define FLASH_BANK_1 1U /*!< Bank 1 */ |
|
||||||
#endif |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASHEx_OB_Type Option Bytes Type
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define OPTIONBYTE_WRP 0x01U /*!<WRP option byte configuration*/ |
|
||||||
#define OPTIONBYTE_RDP 0x02U /*!<RDP option byte configuration*/ |
|
||||||
#define OPTIONBYTE_USER 0x04U /*!<USER option byte configuration*/ |
|
||||||
#define OPTIONBYTE_DATA 0x08U /*!<DATA option byte configuration*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
#define OB_WRPSTATE_DISABLE 0x00U /*!<Disable the write protection of the desired pages*/ |
|
||||||
#define OB_WRPSTATE_ENABLE 0x01U /*!<Enable the write protection of the desired pagess*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* STM32 Low and Medium density devices */ |
|
||||||
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \ |
|
||||||
|| defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
|
|
||||||
|| defined(STM32F103xB) |
|
||||||
#define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */ |
|
||||||
#define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */ |
|
||||||
#define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */ |
|
||||||
#define OB_WRP_PAGES12TO15 0x00000008U /*!< Write protection of page 12 to 15 */ |
|
||||||
#define OB_WRP_PAGES16TO19 0x00000010U /*!< Write protection of page 16 to 19 */ |
|
||||||
#define OB_WRP_PAGES20TO23 0x00000020U /*!< Write protection of page 20 to 23 */ |
|
||||||
#define OB_WRP_PAGES24TO27 0x00000040U /*!< Write protection of page 24 to 27 */ |
|
||||||
#define OB_WRP_PAGES28TO31 0x00000080U /*!< Write protection of page 28 to 31 */ |
|
||||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
|
||||||
/* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
|
||||||
|
|
||||||
/* STM32 Medium-density devices */ |
|
||||||
#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) |
|
||||||
#define OB_WRP_PAGES32TO35 0x00000100U /*!< Write protection of page 32 to 35 */ |
|
||||||
#define OB_WRP_PAGES36TO39 0x00000200U /*!< Write protection of page 36 to 39 */ |
|
||||||
#define OB_WRP_PAGES40TO43 0x00000400U /*!< Write protection of page 40 to 43 */ |
|
||||||
#define OB_WRP_PAGES44TO47 0x00000800U /*!< Write protection of page 44 to 47 */ |
|
||||||
#define OB_WRP_PAGES48TO51 0x00001000U /*!< Write protection of page 48 to 51 */ |
|
||||||
#define OB_WRP_PAGES52TO55 0x00002000U /*!< Write protection of page 52 to 55 */ |
|
||||||
#define OB_WRP_PAGES56TO59 0x00004000U /*!< Write protection of page 56 to 59 */ |
|
||||||
#define OB_WRP_PAGES60TO63 0x00008000U /*!< Write protection of page 60 to 63 */ |
|
||||||
#define OB_WRP_PAGES64TO67 0x00010000U /*!< Write protection of page 64 to 67 */ |
|
||||||
#define OB_WRP_PAGES68TO71 0x00020000U /*!< Write protection of page 68 to 71 */ |
|
||||||
#define OB_WRP_PAGES72TO75 0x00040000U /*!< Write protection of page 72 to 75 */ |
|
||||||
#define OB_WRP_PAGES76TO79 0x00080000U /*!< Write protection of page 76 to 79 */ |
|
||||||
#define OB_WRP_PAGES80TO83 0x00100000U /*!< Write protection of page 80 to 83 */ |
|
||||||
#define OB_WRP_PAGES84TO87 0x00200000U /*!< Write protection of page 84 to 87 */ |
|
||||||
#define OB_WRP_PAGES88TO91 0x00400000U /*!< Write protection of page 88 to 91 */ |
|
||||||
#define OB_WRP_PAGES92TO95 0x00800000U /*!< Write protection of page 92 to 95 */ |
|
||||||
#define OB_WRP_PAGES96TO99 0x01000000U /*!< Write protection of page 96 to 99 */ |
|
||||||
#define OB_WRP_PAGES100TO103 0x02000000U /*!< Write protection of page 100 to 103 */ |
|
||||||
#define OB_WRP_PAGES104TO107 0x04000000U /*!< Write protection of page 104 to 107 */ |
|
||||||
#define OB_WRP_PAGES108TO111 0x08000000U /*!< Write protection of page 108 to 111 */ |
|
||||||
#define OB_WRP_PAGES112TO115 0x10000000U /*!< Write protection of page 112 to 115 */ |
|
||||||
#define OB_WRP_PAGES116TO119 0x20000000U /*!< Write protection of page 115 to 119 */ |
|
||||||
#define OB_WRP_PAGES120TO123 0x40000000U /*!< Write protection of page 120 to 123 */ |
|
||||||
#define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */ |
|
||||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
|
||||||
|
|
||||||
|
|
||||||
/* STM32 High-density, XL-density and Connectivity line devices */ |
|
||||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \ |
|
||||||
|| defined(STM32F101xG) || defined(STM32F103xG) \
|
|
||||||
|| defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
#define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */ |
|
||||||
#define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */ |
|
||||||
#define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */ |
|
||||||
#define OB_WRP_PAGES6TO7 0x00000008U /*!< Write protection of page 6 TO 7 */ |
|
||||||
#define OB_WRP_PAGES8TO9 0x00000010U /*!< Write protection of page 8 TO 9 */ |
|
||||||
#define OB_WRP_PAGES10TO11 0x00000020U /*!< Write protection of page 10 TO 11 */ |
|
||||||
#define OB_WRP_PAGES12TO13 0x00000040U /*!< Write protection of page 12 TO 13 */ |
|
||||||
#define OB_WRP_PAGES14TO15 0x00000080U /*!< Write protection of page 14 TO 15 */ |
|
||||||
#define OB_WRP_PAGES16TO17 0x00000100U /*!< Write protection of page 16 TO 17 */ |
|
||||||
#define OB_WRP_PAGES18TO19 0x00000200U /*!< Write protection of page 18 TO 19 */ |
|
||||||
#define OB_WRP_PAGES20TO21 0x00000400U /*!< Write protection of page 20 TO 21 */ |
|
||||||
#define OB_WRP_PAGES22TO23 0x00000800U /*!< Write protection of page 22 TO 23 */ |
|
||||||
#define OB_WRP_PAGES24TO25 0x00001000U /*!< Write protection of page 24 TO 25 */ |
|
||||||
#define OB_WRP_PAGES26TO27 0x00002000U /*!< Write protection of page 26 TO 27 */ |
|
||||||
#define OB_WRP_PAGES28TO29 0x00004000U /*!< Write protection of page 28 TO 29 */ |
|
||||||
#define OB_WRP_PAGES30TO31 0x00008000U /*!< Write protection of page 30 TO 31 */ |
|
||||||
#define OB_WRP_PAGES32TO33 0x00010000U /*!< Write protection of page 32 TO 33 */ |
|
||||||
#define OB_WRP_PAGES34TO35 0x00020000U /*!< Write protection of page 34 TO 35 */ |
|
||||||
#define OB_WRP_PAGES36TO37 0x00040000U /*!< Write protection of page 36 TO 37 */ |
|
||||||
#define OB_WRP_PAGES38TO39 0x00080000U /*!< Write protection of page 38 TO 39 */ |
|
||||||
#define OB_WRP_PAGES40TO41 0x00100000U /*!< Write protection of page 40 TO 41 */ |
|
||||||
#define OB_WRP_PAGES42TO43 0x00200000U /*!< Write protection of page 42 TO 43 */ |
|
||||||
#define OB_WRP_PAGES44TO45 0x00400000U /*!< Write protection of page 44 TO 45 */ |
|
||||||
#define OB_WRP_PAGES46TO47 0x00800000U /*!< Write protection of page 46 TO 47 */ |
|
||||||
#define OB_WRP_PAGES48TO49 0x01000000U /*!< Write protection of page 48 TO 49 */ |
|
||||||
#define OB_WRP_PAGES50TO51 0x02000000U /*!< Write protection of page 50 TO 51 */ |
|
||||||
#define OB_WRP_PAGES52TO53 0x04000000U /*!< Write protection of page 52 TO 53 */ |
|
||||||
#define OB_WRP_PAGES54TO55 0x08000000U /*!< Write protection of page 54 TO 55 */ |
|
||||||
#define OB_WRP_PAGES56TO57 0x10000000U /*!< Write protection of page 56 TO 57 */ |
|
||||||
#define OB_WRP_PAGES58TO59 0x20000000U /*!< Write protection of page 58 TO 59 */ |
|
||||||
#define OB_WRP_PAGES60TO61 0x40000000U /*!< Write protection of page 60 TO 61 */ |
|
||||||
#define OB_WRP_PAGES62TO127 0x80000000U /*!< Write protection of page 62 TO 127 */ |
|
||||||
#define OB_WRP_PAGES62TO255 0x80000000U /*!< Write protection of page 62 TO 255 */ |
|
||||||
#define OB_WRP_PAGES62TO511 0x80000000U /*!< Write protection of page 62 TO 511 */ |
|
||||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
|
||||||
/* STM32F101xG || STM32F103xG */
|
|
||||||
/* STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
#define OB_WRP_ALLPAGES 0xFFFFFFFFU /*!< Write protection of all Pages */ |
|
||||||
|
|
||||||
/* Low Density */ |
|
||||||
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) |
|
||||||
#define OB_WRP_PAGES0TO31MASK 0x000000FFU |
|
||||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
|
||||||
|
|
||||||
/* Medium Density */ |
|
||||||
#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) |
|
||||||
#define OB_WRP_PAGES0TO31MASK 0x000000FFU |
|
||||||
#define OB_WRP_PAGES32TO63MASK 0x0000FF00U |
|
||||||
#define OB_WRP_PAGES64TO95MASK 0x00FF0000U |
|
||||||
#define OB_WRP_PAGES96TO127MASK 0xFF000000U |
|
||||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ |
|
||||||
|
|
||||||
/* High Density */ |
|
||||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) |
|
||||||
#define OB_WRP_PAGES0TO15MASK 0x000000FFU |
|
||||||
#define OB_WRP_PAGES16TO31MASK 0x0000FF00U |
|
||||||
#define OB_WRP_PAGES32TO47MASK 0x00FF0000U |
|
||||||
#define OB_WRP_PAGES48TO255MASK 0xFF000000U |
|
||||||
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ |
|
||||||
|
|
||||||
/* XL Density */ |
|
||||||
#if defined(STM32F101xG) || defined(STM32F103xG) |
|
||||||
#define OB_WRP_PAGES0TO15MASK 0x000000FFU |
|
||||||
#define OB_WRP_PAGES16TO31MASK 0x0000FF00U |
|
||||||
#define OB_WRP_PAGES32TO47MASK 0x00FF0000U |
|
||||||
#define OB_WRP_PAGES48TO511MASK 0xFF000000U |
|
||||||
#endif /* STM32F101xG || STM32F103xG */ |
|
||||||
|
|
||||||
/* Connectivity line devices */ |
|
||||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
#define OB_WRP_PAGES0TO15MASK 0x000000FFU |
|
||||||
#define OB_WRP_PAGES16TO31MASK 0x0000FF00U |
|
||||||
#define OB_WRP_PAGES32TO47MASK 0x00FF0000U |
|
||||||
#define OB_WRP_PAGES48TO127MASK 0xFF000000U |
|
||||||
#endif /* STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xA5) |
|
||||||
#define OB_RDP_LEVEL_1 ((uint8_t)0x00) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ |
|
||||||
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
#define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ |
|
||||||
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
#define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ |
|
||||||
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */ |
|
||||||
#define OB_BOOT1_SET ((uint16_t)0x0008) /*!< BOOT1 Set */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define OB_DATA_ADDRESS_DATA0 0x1FFFF804U |
|
||||||
#define OB_DATA_ADDRESS_DATA1 0x1FFFF806U |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASHEx_Constants
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASH_Flag_definition Flag definition
|
|
||||||
* @brief Flag definition |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
#define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */ |
|
||||||
#define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */ |
|
||||||
#define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */ |
|
||||||
#define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */ |
|
||||||
|
|
||||||
#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */ |
|
||||||
#define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */ |
|
||||||
#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */ |
|
||||||
#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */ |
|
||||||
|
|
||||||
#define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U) /*!< FLASH Bank2 Busy flag */ |
|
||||||
#define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U) /*!< FLASH Bank2 Programming error flag */ |
|
||||||
#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag */ |
|
||||||
#define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U) /*!< FLASH Bank2 End of Operation flag */ |
|
||||||
|
|
||||||
#else |
|
||||||
|
|
||||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ |
|
||||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ |
|
||||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */ |
|
||||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ |
|
||||||
|
|
||||||
#endif |
|
||||||
#define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASH_Interrupt_definition Interrupt definition
|
|
||||||
* @brief FLASH Interrupt definition |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
#define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */ |
|
||||||
#define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */ |
|
||||||
|
|
||||||
#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */ |
|
||||||
#define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */ |
|
||||||
|
|
||||||
#define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */ |
|
||||||
#define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2 */ |
|
||||||
|
|
||||||
#else |
|
||||||
|
|
||||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ |
|
||||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */ |
|
||||||
|
|
||||||
#endif |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASH_Interrupt Interrupt
|
|
||||||
* @brief macros to handle FLASH interrupts |
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
/**
|
|
||||||
* @brief Enable the specified FLASH interrupt. |
|
||||||
* @param __INTERRUPT__ FLASH interrupt
|
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 |
|
||||||
* @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 |
|
||||||
* @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 |
|
||||||
* @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 |
|
||||||
* @retval none |
|
||||||
*/
|
|
||||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \ |
|
||||||
/* Enable Bank1 IT */ \
|
|
||||||
SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
|
|
||||||
/* Enable Bank2 IT */ \
|
|
||||||
SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
|
|
||||||
} while(0U) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the specified FLASH interrupt. |
|
||||||
* @param __INTERRUPT__ FLASH interrupt
|
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 |
|
||||||
* @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 |
|
||||||
* @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 |
|
||||||
* @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 |
|
||||||
* @retval none |
|
||||||
*/
|
|
||||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ |
|
||||||
/* Disable Bank1 IT */ \
|
|
||||||
CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
|
|
||||||
/* Disable Bank2 IT */ \
|
|
||||||
CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
|
|
||||||
} while(0U) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the specified FLASH flag status.
|
|
||||||
* @param __FLAG__ specifies the FLASH flag to check. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 |
|
||||||
* @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 |
|
||||||
* @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 |
|
||||||
* @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 |
|
||||||
* @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 |
|
||||||
* @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 |
|
||||||
* @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 |
|
||||||
* @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 |
|
||||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
|
||||||
* @retval The new state of __FLAG__ (SET or RESET). |
|
||||||
*/ |
|
||||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ |
|
||||||
(FLASH->OBR & FLASH_OBR_OPTERR) : \
|
|
||||||
((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
|
|
||||||
(FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
|
|
||||||
(FLASH->SR2 & ((__FLAG__) >> 16U)))) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the specified FLASH flag. |
|
||||||
* @param __FLAG__ specifies the FLASH flags to clear. |
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 |
|
||||||
* @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 |
|
||||||
* @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 |
|
||||||
* @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 |
|
||||||
* @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 |
|
||||||
* @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 |
|
||||||
* @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 |
|
||||||
* @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 |
|
||||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
|
||||||
* @retval none |
|
||||||
*/ |
|
||||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ |
|
||||||
/* Clear FLASH_FLAG_OPTVERR flag */ \
|
|
||||||
if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
|
|
||||||
{ \
|
|
||||||
CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
|
|
||||||
} \
|
|
||||||
else { \
|
|
||||||
/* Clear Flag in Bank1 */ \
|
|
||||||
if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
|
|
||||||
{ \
|
|
||||||
FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
|
|
||||||
} \
|
|
||||||
/* Clear Flag in Bank2 */ \
|
|
||||||
if (((__FLAG__) >> 16U) != RESET) \
|
|
||||||
{ \
|
|
||||||
FLASH->SR2 = ((__FLAG__) >> 16U); \
|
|
||||||
} \
|
|
||||||
} \
|
|
||||||
} while(0U) |
|
||||||
#else |
|
||||||
/**
|
|
||||||
* @brief Enable the specified FLASH interrupt. |
|
||||||
* @param __INTERRUPT__ FLASH interrupt
|
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt |
|
||||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
|
||||||
* @retval none |
|
||||||
*/
|
|
||||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the specified FLASH interrupt. |
|
||||||
* @param __INTERRUPT__ FLASH interrupt
|
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt |
|
||||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
|
||||||
* @retval none |
|
||||||
*/
|
|
||||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the specified FLASH flag status.
|
|
||||||
* @param __FLAG__ specifies the FLASH flag to check. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
|
||||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
|
||||||
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag |
|
||||||
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag |
|
||||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
|
||||||
* @retval The new state of __FLAG__ (SET or RESET). |
|
||||||
*/ |
|
||||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ |
|
||||||
(FLASH->OBR & FLASH_OBR_OPTERR) : \
|
|
||||||
(FLASH->SR & (__FLAG__))) |
|
||||||
/**
|
|
||||||
* @brief Clear the specified FLASH flag. |
|
||||||
* @param __FLAG__ specifies the FLASH flags to clear. |
|
||||||
* This parameter can be any combination of the following values: |
|
||||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
|
||||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
|
||||||
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
|
|
||||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
|
||||||
* @retval none |
|
||||||
*/ |
|
||||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ |
|
||||||
/* Clear FLASH_FLAG_OPTVERR flag */ \
|
|
||||||
if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
|
|
||||||
{ \
|
|
||||||
CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
|
|
||||||
} \
|
|
||||||
else { \
|
|
||||||
/* Clear Flag in Bank1 */ \
|
|
||||||
FLASH->SR = (__FLAG__); \
|
|
||||||
} \
|
|
||||||
} while(0U) |
|
||||||
|
|
||||||
#endif |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
/** @addtogroup FLASHEx_Exported_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* IO operation functions *****************************************************/ |
|
||||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); |
|
||||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASHEx_Exported_Functions_Group2
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Peripheral Control functions ***********************************************/ |
|
||||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void); |
|
||||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); |
|
||||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); |
|
||||||
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* __STM32F1xx_HAL_FLASH_EX_H */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,308 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_gpio.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Header file of GPIO HAL module. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef STM32F1xx_HAL_GPIO_H |
|
||||||
#define STM32F1xx_HAL_GPIO_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_def.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup GPIO
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/ |
|
||||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief GPIO Init structure definition |
|
||||||
*/ |
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
|
||||||
This parameter can be any value of @ref GPIO_pins_define */ |
|
||||||
|
|
||||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
|
||||||
This parameter can be a value of @ref GPIO_mode_define */ |
|
||||||
|
|
||||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
|
||||||
This parameter can be a value of @ref GPIO_pull_define */ |
|
||||||
|
|
||||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
|
||||||
This parameter can be a value of @ref GPIO_speed_define */ |
|
||||||
} GPIO_InitTypeDef; |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief GPIO Bit SET and Bit RESET enumeration |
|
||||||
*/ |
|
||||||
typedef enum |
|
||||||
{ |
|
||||||
GPIO_PIN_RESET = 0u, |
|
||||||
GPIO_PIN_SET |
|
||||||
} GPIO_PinState; |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIO_pins_define GPIO pins define
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ |
|
||||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ |
|
||||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ |
|
||||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ |
|
||||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ |
|
||||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ |
|
||||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ |
|
||||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ |
|
||||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ |
|
||||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ |
|
||||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ |
|
||||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ |
|
||||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ |
|
||||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ |
|
||||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ |
|
||||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ |
|
||||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ |
|
||||||
|
|
||||||
#define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIO_mode_define GPIO mode define
|
|
||||||
* @brief GPIO Configuration Mode |
|
||||||
* Elements values convention: 0xX0yz00YZ |
|
||||||
* - X : GPIO mode or EXTI Mode |
|
||||||
* - y : External IT or Event trigger detection |
|
||||||
* - z : IO configuration on External IT or Event |
|
||||||
* - Y : Output type (Push Pull or Open Drain) |
|
||||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog) |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */ |
|
||||||
#define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */ |
|
||||||
#define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */ |
|
||||||
#define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */ |
|
||||||
#define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */ |
|
||||||
#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ |
|
||||||
|
|
||||||
#define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */ |
|
||||||
|
|
||||||
#define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */ |
|
||||||
#define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */ |
|
||||||
#define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
|
||||||
|
|
||||||
#define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */ |
|
||||||
#define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */ |
|
||||||
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIO_speed_define GPIO speed define
|
|
||||||
* @brief GPIO Output Maximum frequency |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ |
|
||||||
#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ |
|
||||||
#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIO_pull_define GPIO pull define
|
|
||||||
* @brief GPIO Pull-Up or Pull-Down Activation |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ |
|
||||||
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ |
|
||||||
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified EXTI line flag is set or not. |
|
||||||
* @param __EXTI_LINE__: specifies the EXTI line flag to check. |
|
||||||
* This parameter can be GPIO_PIN_x where x can be(0..15) |
|
||||||
* @retval The new state of __EXTI_LINE__ (SET or RESET). |
|
||||||
*/ |
|
||||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the EXTI's line pending flags. |
|
||||||
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear. |
|
||||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Checks whether the specified EXTI line is asserted or not. |
|
||||||
* @param __EXTI_LINE__: specifies the EXTI line to check. |
|
||||||
* This parameter can be GPIO_PIN_x where x can be(0..15) |
|
||||||
* @retval The new state of __EXTI_LINE__ (SET or RESET). |
|
||||||
*/ |
|
||||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the EXTI's line pending bits. |
|
||||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear. |
|
||||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Generates a Software interrupt on selected EXTI line. |
|
||||||
* @param __EXTI_LINE__: specifies the EXTI line to check. |
|
||||||
* This parameter can be GPIO_PIN_x where x can be(0..15) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Include GPIO HAL Extension module */ |
|
||||||
#include "stm32f1xx_hal_gpio_ex.h" |
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
/** @addtogroup GPIO_Exported_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Initialization and de-initialization functions *****************************/ |
|
||||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); |
|
||||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* IO operation functions *****************************************************/ |
|
||||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); |
|
||||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); |
|
||||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); |
|
||||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); |
|
||||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); |
|
||||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* Private types -------------------------------------------------------------*/ |
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/* Private constants ---------------------------------------------------------*/ |
|
||||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/ |
|
||||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) |
|
||||||
#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u)) |
|
||||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ |
|
||||||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
|
||||||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
|
||||||
((MODE) == GPIO_MODE_AF_PP) ||\
|
|
||||||
((MODE) == GPIO_MODE_AF_OD) ||\
|
|
||||||
((MODE) == GPIO_MODE_IT_RISING) ||\
|
|
||||||
((MODE) == GPIO_MODE_IT_FALLING) ||\
|
|
||||||
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
|
|
||||||
((MODE) == GPIO_MODE_EVT_RISING) ||\
|
|
||||||
((MODE) == GPIO_MODE_EVT_FALLING) ||\
|
|
||||||
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
|
||||||
((MODE) == GPIO_MODE_ANALOG)) |
|
||||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ |
|
||||||
((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) |
|
||||||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ |
|
||||||
((PULL) == GPIO_PULLDOWN)) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/ |
|
||||||
/** @defgroup GPIO_Private_Functions GPIO Private Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* STM32F1xx_HAL_GPIO_H */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,894 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_gpio_ex.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Header file of GPIO HAL Extension module. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef STM32F1xx_HAL_GPIO_EX_H |
|
||||||
#define STM32F1xx_HAL_GPIO_EX_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_def.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIOEx GPIOEx
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Exported types ------------------------------------------------------------*/ |
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
|
|
||||||
* @brief This section propose definition to use the Cortex EVENTOUT signal. |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ |
|
||||||
#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ |
|
||||||
|
|
||||||
#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ |
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
|
|
||||||
((__PIN__) == AFIO_EVENTOUT_PIN_15)) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ |
|
||||||
#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ |
|
||||||
#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ |
|
||||||
#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ |
|
||||||
#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ |
|
||||||
|
|
||||||
#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ |
|
||||||
((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
|
|
||||||
((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
|
|
||||||
((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
|
|
||||||
((__PORT__) == AFIO_EVENTOUT_PORT_E)) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
|
|
||||||
* @brief This section propose definition to remap the alternate function to some other port/pins. |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
|
||||||
* @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
|
||||||
* @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of I2C1 alternate function SCL and SDA. |
|
||||||
* @note ENABLE: Remap (SCL/PB8, SDA/PB9) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of I2C1 alternate function SCL and SDA. |
|
||||||
* @note DISABLE: No remap (SCL/PB6, SDA/PB7) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of USART1 alternate function TX and RX. |
|
||||||
* @note ENABLE: Remap (TX/PB6, RX/PB7) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of USART1 alternate function TX and RX. |
|
||||||
* @note DISABLE: No remap (TX/PA9, RX/PA10) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
|
||||||
* @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
|
||||||
* @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
|
||||||
* @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
|
||||||
* @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
|
||||||
* @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
|
||||||
* @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
|
||||||
* @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
|
||||||
* @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
|
||||||
* @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
|
||||||
* @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
|
||||||
* @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
|
||||||
* @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
|
||||||
* @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) |
|
||||||
* @note TIM3_ETR on PE0 is not re-mapped. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
|
||||||
* @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) |
|
||||||
* @note TIM3_ETR on PE0 is not re-mapped. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM3 alternate function channels 1 to 4 |
|
||||||
* @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) |
|
||||||
* @note TIM3_ETR on PE0 is not re-mapped. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM4 alternate function channels 1 to 4. |
|
||||||
* @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) |
|
||||||
* @note TIM4_ETR on PE0 is not re-mapped. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM4 alternate function channels 1 to 4. |
|
||||||
* @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) |
|
||||||
* @note TIM4_ETR on PE0 is not re-mapped. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP) |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR_CAN_REMAP_REMAP1) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
|
||||||
* @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
|
||||||
* @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
|
||||||
* @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP) |
|
||||||
|
|
||||||
#endif |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used |
|
||||||
* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
|
||||||
* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
|
||||||
* on 100-pin and 144-pin packages, no need for remapping). |
|
||||||
* @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used |
|
||||||
* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
|
||||||
* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
|
||||||
* on 100-pin and 144-pin packages, no need for remapping). |
|
||||||
* @note DISABLE: No remapping of PD0 and PD1 |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP) |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR_TIM5CH4_IREMAP) |
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM5CH4. |
|
||||||
* @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. |
|
||||||
* @note This function is available only in high density value line devices. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM5CH4. |
|
||||||
* @note DISABLE: TIM5_CH4 is connected to PA3 |
|
||||||
* @note This function is available only in high density value line devices. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR_ETH_REMAP) |
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of Ethernet MAC connections with the PHY. |
|
||||||
* @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of Ethernet MAC connections with the PHY. |
|
||||||
* @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR_CAN2_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
|
||||||
* @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
|
||||||
* @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR_MII_RMII_SEL) |
|
||||||
/**
|
|
||||||
* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
|
||||||
* @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
|
||||||
* @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL) |
|
||||||
#endif |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
|
||||||
* @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
|
||||||
* @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
|
||||||
* @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
|
||||||
* @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
|
||||||
* @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
|
||||||
* @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
|
||||||
* @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
|
||||||
* @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the Serial wire JTAG configuration |
|
||||||
* @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the Serial wire JTAG configuration |
|
||||||
* @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the Serial wire JTAG configuration |
|
||||||
* @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
|
|
||||||
#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the Serial wire JTAG configuration |
|
||||||
* @note DISABLE: JTAG-DP Disabled and SW-DP Disabled |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE) |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR_SPI3_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
|
||||||
* @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
|
||||||
* @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR_TIM2ITR1_IREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Control of TIM2_ITR1 internal mapping. |
|
||||||
* @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Control of TIM2_ITR1 internal mapping. |
|
||||||
* @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR_PTP_PPS_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
|
||||||
* @note ENABLE: PTP_PPS is output on PB5 pin. |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
|
||||||
* @note DISABLE: PTP_PPS not output on PB5 pin. |
|
||||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM9_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. |
|
||||||
* @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. |
|
||||||
* @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM10_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM10_CH1. |
|
||||||
* @note ENABLE: Remap (TIM10_CH1 on PF6). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM10_CH1. |
|
||||||
* @note DISABLE: No remap (TIM10_CH1 on PB8). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM11_REMAP) |
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM11_CH1. |
|
||||||
* @note ENABLE: Remap (TIM11_CH1 on PF7). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM11_CH1. |
|
||||||
* @note DISABLE: No remap (TIM11_CH1 on PB9). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM13_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM13_CH1. |
|
||||||
* @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM13_CH1. |
|
||||||
* @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM14_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM14_CH1. |
|
||||||
* @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM14_CH1. |
|
||||||
* @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_FSMC_NADV_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Controls the use of the optional FSMC_NADV signal. |
|
||||||
* @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Controls the use of the optional FSMC_NADV signal. |
|
||||||
* @note CONNECTED: The NADV signal is connected to the output (default). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM15_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. |
|
||||||
* @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. |
|
||||||
* @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM16_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM16_CH1. |
|
||||||
* @note ENABLE: Remap (TIM16_CH1 on PA6). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM16_CH1. |
|
||||||
* @note DISABLE: No remap (TIM16_CH1 on PB8). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM17_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM17_CH1. |
|
||||||
* @note ENABLE: Remap (TIM17_CH1 on PA7). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM17_CH1. |
|
||||||
* @note DISABLE: No remap (TIM17_CH1 on PB9). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_CEC_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of CEC. |
|
||||||
* @note ENABLE: Remap (CEC on PB10). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of CEC. |
|
||||||
* @note DISABLE: No remap (CEC on PB8). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM1_DMA_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
|
||||||
* @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
|
||||||
* @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
|
||||||
* @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
|
||||||
* @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_TIM12_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. |
|
||||||
* @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). |
|
||||||
* @note This bit is available only in high density value line devices. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. |
|
||||||
* @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). |
|
||||||
* @note This bit is available only in high density value line devices. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(AFIO_MAPR2_MISC_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Miscellaneous features remapping. |
|
||||||
* This bit is set and cleared by software. It controls miscellaneous features. |
|
||||||
* The DMA2 channel 5 interrupt position in the vector table. |
|
||||||
* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
|
||||||
* @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is |
|
||||||
* selected as DAC Trigger 3, TIM15 triggers TIM1/3. |
|
||||||
* @note This bit is available only in high density value line devices. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Miscellaneous features remapping. |
|
||||||
* This bit is set and cleared by software. It controls miscellaneous features. |
|
||||||
* The DMA2 channel 5 interrupt position in the vector table. |
|
||||||
* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
|
||||||
* @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO |
|
||||||
* event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. |
|
||||||
* @note This bit is available only in high density value line devices. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
|
||||||
#endif |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) |
|
||||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
|
||||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
|
||||||
((__GPIOx__) == (GPIOC))? 2uL :3uL) |
|
||||||
#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
|
||||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
|
||||||
((__GPIOx__) == (GPIOC))? 2uL :\
|
|
||||||
((__GPIOx__) == (GPIOD))? 3uL :4uL) |
|
||||||
#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
|
||||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
|
||||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
|
||||||
((__GPIOx__) == (GPIOC))? 2uL :\
|
|
||||||
((__GPIOx__) == (GPIOD))? 3uL :\
|
|
||||||
((__GPIOx__) == (GPIOE))? 4uL :\
|
|
||||||
((__GPIOx__) == (GPIOF))? 5uL :6uL) |
|
||||||
#endif |
|
||||||
|
|
||||||
#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ |
|
||||||
tmpreg |= AFIO_MAPR_SWJ_CFG; \
|
|
||||||
tmpreg |= REMAP_PIN; \
|
|
||||||
AFIO->MAPR = tmpreg; \
|
|
||||||
}while(0u) |
|
||||||
|
|
||||||
#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ |
|
||||||
tmpreg |= AFIO_MAPR_SWJ_CFG; \
|
|
||||||
tmpreg &= ~REMAP_PIN; \
|
|
||||||
AFIO->MAPR = tmpreg; \
|
|
||||||
}while(0u) |
|
||||||
|
|
||||||
#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \ |
|
||||||
tmpreg &= ~REMAP_PIN_MASK; \
|
|
||||||
tmpreg |= AFIO_MAPR_SWJ_CFG; \
|
|
||||||
tmpreg |= REMAP_PIN; \
|
|
||||||
AFIO->MAPR = tmpreg; \
|
|
||||||
}while(0u) |
|
||||||
|
|
||||||
#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \ |
|
||||||
tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
|
|
||||||
tmpreg |= DBGAFR_SWJCFG; \
|
|
||||||
AFIO->MAPR = tmpreg; \
|
|
||||||
}while(0u) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @addtogroup GPIOEx_Exported_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup GPIOEx_Exported_Functions_Group1
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); |
|
||||||
void HAL_GPIOEx_EnableEventout(void); |
|
||||||
void HAL_GPIOEx_DisableEventout(void); |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
#endif /* STM32F1xx_HAL_GPIO_EX_H */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,388 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_pwr.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Header file of PWR HAL module. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef __STM32F1xx_HAL_PWR_H |
|
||||||
#define __STM32F1xx_HAL_PWR_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_def.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup PWR
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PWR PVD configuration structure definition |
|
||||||
*/ |
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
|
||||||
This parameter can be a value of @ref PWR_PVD_detection_level */ |
|
||||||
|
|
||||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
|
||||||
This parameter can be a value of @ref PWR_PVD_Mode */ |
|
||||||
}PWR_PVDTypeDef; |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/* Internal constants --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @addtogroup PWR_Private_Constants
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 |
|
||||||
#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 |
|
||||||
#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 |
|
||||||
#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 |
|
||||||
#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 |
|
||||||
#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 |
|
||||||
#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 |
|
||||||
#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_PVD_Mode PWR PVD Mode
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ |
|
||||||
#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ |
|
||||||
#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ |
|
||||||
#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
|
||||||
#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ |
|
||||||
#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ |
|
||||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define PWR_MAINREGULATOR_ON 0x00000000U |
|
||||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) |
|
||||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) |
|
||||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_Flag PWR Flag
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define PWR_FLAG_WU PWR_CSR_WUF |
|
||||||
#define PWR_FLAG_SB PWR_CSR_SBF |
|
||||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
/** @defgroup PWR_Exported_Macros PWR Exported Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @brief Check PWR flag is set or not.
|
|
||||||
* @param __FLAG__: specifies the flag to check. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
|
||||||
* was received from the WKUP pin or from the RTC alarm |
|
||||||
* An additional wakeup event is detected if the WKUP pin is enabled |
|
||||||
* (by setting the EWUP bit) when the WKUP pin level is already high. |
|
||||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
|
||||||
* resumed from StandBy mode. |
|
||||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
|
||||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode |
|
||||||
* For this reason, this bit is equal to 0 after Standby or reset |
|
||||||
* until the PVDE bit is set. |
|
||||||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
|
||||||
|
|
||||||
/** @brief Clear the PWR's pending flags.
|
|
||||||
* @param __FLAG__: specifies the flag to clear. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg PWR_FLAG_WU: Wake Up flag |
|
||||||
* @arg PWR_FLAG_SB: StandBy flag |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable interrupt on PVD Exti Line 16. |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable interrupt on PVD Exti Line 16.
|
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable event on PVD Exti Line 16. |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable event on PVD Exti Line 16. |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PVD EXTI line configuration: set falling edge trigger.
|
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVD Extended Interrupt Falling Trigger. |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PVD EXTI line configuration: set rising edge trigger. |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVD Extended Interrupt Rising Trigger. |
|
||||||
* This parameter can be: |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PVD EXTI line configuration: set rising & falling edge trigger. |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
|
||||||
* This parameter can be: |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); |
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
|
||||||
* @retval EXTI PVD Line Status. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear the PVD EXTI flag. |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Generate a Software interrupt on selected EXTI line. |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/ |
|
||||||
/** @defgroup PWR_Private_Macros PWR Private Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
|
||||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
|
||||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
|
||||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
|
||||||
|
|
||||||
|
|
||||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
|
||||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
|
||||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
|
||||||
((MODE) == PWR_PVD_MODE_NORMAL))
|
|
||||||
|
|
||||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) |
|
||||||
|
|
||||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
|
||||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
|
||||||
|
|
||||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
|
||||||
|
|
||||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Initialization and de-initialization functions *******************************/ |
|
||||||
void HAL_PWR_DeInit(void); |
|
||||||
void HAL_PWR_EnableBkUpAccess(void); |
|
||||||
void HAL_PWR_DisableBkUpAccess(void); |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Peripheral Control functions ************************************************/ |
|
||||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
|
||||||
/* #define HAL_PWR_ConfigPVD 12*/ |
|
||||||
void HAL_PWR_EnablePVD(void); |
|
||||||
void HAL_PWR_DisablePVD(void); |
|
||||||
|
|
||||||
/* WakeUp pins configuration functions ****************************************/ |
|
||||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
|
||||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
|
||||||
|
|
||||||
/* Low Power modes configuration functions ************************************/ |
|
||||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
|
||||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
|
||||||
void HAL_PWR_EnterSTANDBYMode(void); |
|
||||||
|
|
||||||
void HAL_PWR_EnableSleepOnExit(void); |
|
||||||
void HAL_PWR_DisableSleepOnExit(void); |
|
||||||
void HAL_PWR_EnableSEVOnPend(void); |
|
||||||
void HAL_PWR_DisableSEVOnPend(void); |
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
void HAL_PWR_PVD_IRQHandler(void); |
|
||||||
void HAL_PWR_PVDCallback(void); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#endif /* __STM32F1xx_HAL_PWR_H */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,262 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_tim_ex.h |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Header file of TIM HAL Extended module. |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|
||||||
#ifndef STM32F1xx_HAL_TIM_EX_H |
|
||||||
#define STM32F1xx_HAL_TIM_EX_H |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
extern "C" { |
|
||||||
#endif |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal_def.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup TIMEx
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/ |
|
||||||
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief TIM Hall sensor Configuration Structure definition |
|
||||||
*/ |
|
||||||
|
|
||||||
typedef struct |
|
||||||
{ |
|
||||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
|
||||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
|
||||||
|
|
||||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
|
||||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
|
||||||
|
|
||||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
|
||||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
|
||||||
|
|
||||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
|
||||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
|
||||||
} TIM_HallSensor_InitTypeDef; |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* End of exported types -----------------------------------------------------*/ |
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/ |
|
||||||
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* End of exported constants -------------------------------------------------*/ |
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/ |
|
||||||
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* End of exported macro -----------------------------------------------------*/ |
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/ |
|
||||||
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* End of private macro ------------------------------------------------------*/ |
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
|
||||||
* @brief Timer Hall Sensor functions |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Timer Hall Sensor functions **********************************************/ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); |
|
||||||
|
|
||||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); |
|
||||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); |
|
||||||
|
|
||||||
/* Blocking mode: Polling */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); |
|
||||||
/* Non-Blocking mode: Interrupt */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); |
|
||||||
/* Non-Blocking mode: DMA */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
|
||||||
* @brief Timer Complementary Output Compare functions |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Timer Complementary Output Compare functions *****************************/ |
|
||||||
/* Blocking mode: Polling */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
||||||
|
|
||||||
/* Non-Blocking mode: Interrupt */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
||||||
|
|
||||||
/* Non-Blocking mode: DMA */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
|
||||||
* @brief Timer Complementary PWM functions |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Timer Complementary PWM functions ****************************************/ |
|
||||||
/* Blocking mode: Polling */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
||||||
|
|
||||||
/* Non-Blocking mode: Interrupt */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
||||||
/* Non-Blocking mode: DMA */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
|
||||||
* @brief Timer Complementary One Pulse functions |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Timer Complementary One Pulse functions **********************************/ |
|
||||||
/* Blocking mode: Polling */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
|
||||||
|
|
||||||
/* Non-Blocking mode: Interrupt */ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
|
||||||
* @brief Peripheral Control functions |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Extended Control functions ************************************************/ |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, |
|
||||||
uint32_t CommutationSource); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, |
|
||||||
uint32_t CommutationSource); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, |
|
||||||
uint32_t CommutationSource); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, |
|
||||||
TIM_MasterConfigTypeDef *sMasterConfig); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, |
|
||||||
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); |
|
||||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
|
||||||
* @brief Extended Callbacks functions |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Extended Callback **********************************************************/ |
|
||||||
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); |
|
||||||
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); |
|
||||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
|
||||||
* @brief Extended Peripheral State functions |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Extended Peripheral State functions ***************************************/ |
|
||||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); |
|
||||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* End of exported functions -------------------------------------------------*/ |
|
||||||
|
|
||||||
/* Private functions----------------------------------------------------------*/ |
|
||||||
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); |
|
||||||
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* End of private functions --------------------------------------------------*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef __cplusplus |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#endif /* STM32F1xx_HAL_TIM_EX_H */ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,606 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal.c |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief HAL module driver. |
|
||||||
* This is the common part of the HAL initialization |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
============================================================================== |
|
||||||
##### How to use this driver ##### |
|
||||||
============================================================================== |
|
||||||
[..] |
|
||||||
The common HAL driver contains a set of generic and common APIs that can be |
|
||||||
used by the PPP peripheral drivers and the user to start using the HAL. |
|
||||||
[..] |
|
||||||
The HAL contains two APIs' categories: |
|
||||||
(+) Common HAL APIs |
|
||||||
(+) Services HAL APIs |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup HAL HAL
|
|
||||||
* @brief HAL module driver. |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef HAL_MODULE_ENABLED |
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/ |
|
||||||
/* Private define ------------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/**
|
|
||||||
* @brief STM32F1xx HAL Driver version number V1.1.8 |
|
||||||
*/ |
|
||||||
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ |
|
||||||
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ |
|
||||||
#define __STM32F1xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */ |
|
||||||
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ |
|
||||||
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\ |
|
||||||
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
|
|
||||||
|(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
|
|
||||||
|(__STM32F1xx_HAL_VERSION_RC)) |
|
||||||
|
|
||||||
#define IDCODE_DEVID_MASK 0x00000FFFU |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/ |
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup HAL_Private_Variables HAL Private Variables
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
__IO uint32_t uwTick; |
|
||||||
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ |
|
||||||
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* Private function prototypes -----------------------------------------------*/ |
|
||||||
/* Exported functions ---------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
|
|
||||||
* @brief Initialization and de-initialization functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### Initialization and de-initialization functions ##### |
|
||||||
=============================================================================== |
|
||||||
[..] This section provides functions allowing to: |
|
||||||
(+) Initializes the Flash interface, the NVIC allocation and initial clock |
|
||||||
configuration. It initializes the systick also when timeout is needed |
|
||||||
and the backup domain when enabled. |
|
||||||
(+) de-Initializes common part of the HAL. |
|
||||||
(+) Configure The time base source to have 1ms time base with a dedicated |
|
||||||
Tick interrupt priority. |
|
||||||
(++) SysTick timer is used by default as source of time base, but user |
|
||||||
can eventually implement his proper time base source (a general purpose |
|
||||||
timer for example or other time source), keeping in mind that Time base |
|
||||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and |
|
||||||
handled in milliseconds basis. |
|
||||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically |
|
||||||
at the beginning of the program after reset by HAL_Init() or at any time |
|
||||||
when clock is configured, by HAL_RCC_ClockConfig(). |
|
||||||
(++) Source of time base is configured to generate interrupts at regular |
|
||||||
time intervals. Care must be taken if HAL_Delay() is called from a |
|
||||||
peripheral ISR process, the Tick interrupt line must have higher priority |
|
||||||
(numerically lower) than the peripheral interrupt. Otherwise the caller |
|
||||||
ISR process will be blocked. |
|
||||||
(++) functions affecting time base configurations are declared as __weak |
|
||||||
to make override possible in case of other implementations in user file. |
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function is used to initialize the HAL Library; it must be the first |
|
||||||
* instruction to be executed in the main program (before to call any other |
|
||||||
* HAL function), it performs the following: |
|
||||||
* Configure the Flash prefetch. |
|
||||||
* Configures the SysTick to generate an interrupt each 1 millisecond, |
|
||||||
* which is clocked by the HSI (at this stage, the clock is not yet |
|
||||||
* configured and thus the system is running from the internal HSI at 16 MHz). |
|
||||||
* Set NVIC Group Priority to 4. |
|
||||||
* Calls the HAL_MspInit() callback function defined in user file |
|
||||||
* "stm32f1xx_hal_msp.c" to do the global low level hardware initialization |
|
||||||
* |
|
||||||
* @note SysTick is used as time base for the HAL_Delay() function, the application |
|
||||||
* need to ensure that the SysTick time base is always set to 1 millisecond |
|
||||||
* to have correct HAL operation. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_Init(void) |
|
||||||
{ |
|
||||||
/* Configure Flash prefetch */ |
|
||||||
#if (PREFETCH_ENABLE != 0) |
|
||||||
#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \ |
|
||||||
defined(STM32F102x6) || defined(STM32F102xB) || \
|
|
||||||
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
|
|
||||||
defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
|
|
||||||
/* Prefetch buffer is not available on value line devices */ |
|
||||||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE(); |
|
||||||
#endif |
|
||||||
#endif /* PREFETCH_ENABLE */ |
|
||||||
|
|
||||||
/* Set Interrupt Group Priority */ |
|
||||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); |
|
||||||
|
|
||||||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ |
|
||||||
HAL_InitTick(TICK_INT_PRIORITY); |
|
||||||
|
|
||||||
/* Init the low level hardware */ |
|
||||||
HAL_MspInit(); |
|
||||||
|
|
||||||
/* Return function status */ |
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function de-Initializes common part of the HAL and stops the systick. |
|
||||||
* of time base. |
|
||||||
* @note This function is optional. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_DeInit(void) |
|
||||||
{ |
|
||||||
/* Reset of all peripherals */ |
|
||||||
__HAL_RCC_APB1_FORCE_RESET(); |
|
||||||
__HAL_RCC_APB1_RELEASE_RESET(); |
|
||||||
|
|
||||||
__HAL_RCC_APB2_FORCE_RESET(); |
|
||||||
__HAL_RCC_APB2_RELEASE_RESET(); |
|
||||||
|
|
||||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
__HAL_RCC_AHB_FORCE_RESET(); |
|
||||||
__HAL_RCC_AHB_RELEASE_RESET(); |
|
||||||
#endif |
|
||||||
|
|
||||||
/* De-Init the low level hardware */ |
|
||||||
HAL_MspDeInit(); |
|
||||||
|
|
||||||
/* Return function status */ |
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initialize the MSP. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
__weak void HAL_MspInit(void) |
|
||||||
{ |
|
||||||
/* NOTE : This function should not be modified, when the callback is needed,
|
|
||||||
the HAL_MspInit could be implemented in the user file |
|
||||||
*/ |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DeInitializes the MSP. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
__weak void HAL_MspDeInit(void) |
|
||||||
{ |
|
||||||
/* NOTE : This function should not be modified, when the callback is needed,
|
|
||||||
the HAL_MspDeInit could be implemented in the user file |
|
||||||
*/ |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function configures the source of the time base. |
|
||||||
* The time source is configured to have 1ms time base with a dedicated |
|
||||||
* Tick interrupt priority. |
|
||||||
* @note This function is called automatically at the beginning of program after |
|
||||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). |
|
||||||
* @note In the default implementation, SysTick timer is the source of time base. |
|
||||||
* It is used to generate interrupts at regular time intervals. |
|
||||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process, |
|
||||||
* The SysTick interrupt must have higher priority (numerically lower) |
|
||||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked. |
|
||||||
* The function is declared as __weak to be overwritten in case of other |
|
||||||
* implementation in user file. |
|
||||||
* @param TickPriority Tick interrupt priority. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) |
|
||||||
{ |
|
||||||
/* Configure the SysTick to have interrupt in 1ms time basis*/ |
|
||||||
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Configure the SysTick IRQ priority */ |
|
||||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS)) |
|
||||||
{ |
|
||||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); |
|
||||||
uwTickPrio = TickPriority; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Return function status */ |
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
|
||||||
* @brief HAL Control functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### HAL Control functions ##### |
|
||||||
=============================================================================== |
|
||||||
[..] This section provides functions allowing to: |
|
||||||
(+) Provide a tick value in millisecond |
|
||||||
(+) Provide a blocking delay in millisecond |
|
||||||
(+) Suspend the time base source interrupt |
|
||||||
(+) Resume the time base source interrupt |
|
||||||
(+) Get the HAL API driver version |
|
||||||
(+) Get the device identifier |
|
||||||
(+) Get the device revision identifier |
|
||||||
(+) Enable/Disable Debug module during SLEEP mode |
|
||||||
(+) Enable/Disable Debug module during STOP mode |
|
||||||
(+) Enable/Disable Debug module during STANDBY mode |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function is called to increment a global variable "uwTick" |
|
||||||
* used as application time base. |
|
||||||
* @note In the default implementation, this variable is incremented each 1ms |
|
||||||
* in SysTick ISR. |
|
||||||
* @note This function is declared as __weak to be overwritten in case of other |
|
||||||
* implementations in user file. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
__weak void HAL_IncTick(void) |
|
||||||
{ |
|
||||||
uwTick += uwTickFreq; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Provides a tick value in millisecond. |
|
||||||
* @note This function is declared as __weak to be overwritten in case of other |
|
||||||
* implementations in user file. |
|
||||||
* @retval tick value |
|
||||||
*/ |
|
||||||
__weak uint32_t HAL_GetTick(void) |
|
||||||
{ |
|
||||||
return uwTick; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function returns a tick priority. |
|
||||||
* @retval tick priority |
|
||||||
*/ |
|
||||||
uint32_t HAL_GetTickPrio(void) |
|
||||||
{ |
|
||||||
return uwTickPrio; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set new tick Freq. |
|
||||||
* @retval status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) |
|
||||||
{ |
|
||||||
HAL_StatusTypeDef status = HAL_OK; |
|
||||||
HAL_TickFreqTypeDef prevTickFreq; |
|
||||||
|
|
||||||
assert_param(IS_TICKFREQ(Freq)); |
|
||||||
|
|
||||||
if (uwTickFreq != Freq) |
|
||||||
{ |
|
||||||
/* Back up uwTickFreq frequency */ |
|
||||||
prevTickFreq = uwTickFreq; |
|
||||||
|
|
||||||
/* Update uwTickFreq global variable used by HAL_InitTick() */ |
|
||||||
uwTickFreq = Freq; |
|
||||||
|
|
||||||
/* Apply the new tick Freq */ |
|
||||||
status = HAL_InitTick(uwTickPrio); |
|
||||||
|
|
||||||
if (status != HAL_OK) |
|
||||||
{ |
|
||||||
/* Restore previous tick frequency */ |
|
||||||
uwTickFreq = prevTickFreq; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
return status; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return tick frequency. |
|
||||||
* @retval tick period in Hz |
|
||||||
*/ |
|
||||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void) |
|
||||||
{ |
|
||||||
return uwTickFreq; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function provides minimum delay (in milliseconds) based |
|
||||||
* on variable incremented. |
|
||||||
* @note In the default implementation , SysTick timer is the source of time base. |
|
||||||
* It is used to generate interrupts at regular time intervals where uwTick |
|
||||||
* is incremented. |
|
||||||
* @note This function is declared as __weak to be overwritten in case of other |
|
||||||
* implementations in user file. |
|
||||||
* @param Delay specifies the delay time length, in milliseconds. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
__weak void HAL_Delay(uint32_t Delay) |
|
||||||
{ |
|
||||||
uint32_t tickstart = HAL_GetTick(); |
|
||||||
uint32_t wait = Delay; |
|
||||||
|
|
||||||
/* Add a freq to guarantee minimum wait */ |
|
||||||
if (wait < HAL_MAX_DELAY) |
|
||||||
{ |
|
||||||
wait += (uint32_t)(uwTickFreq); |
|
||||||
} |
|
||||||
|
|
||||||
while ((HAL_GetTick() - tickstart) < wait) |
|
||||||
{ |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Suspend Tick increment. |
|
||||||
* @note In the default implementation , SysTick timer is the source of time base. It is |
|
||||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick() |
|
||||||
* is called, the SysTick interrupt will be disabled and so Tick increment |
|
||||||
* is suspended. |
|
||||||
* @note This function is declared as __weak to be overwritten in case of other |
|
||||||
* implementations in user file. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
__weak void HAL_SuspendTick(void) |
|
||||||
{ |
|
||||||
/* Disable SysTick Interrupt */ |
|
||||||
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Resume Tick increment. |
|
||||||
* @note In the default implementation , SysTick timer is the source of time base. It is |
|
||||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick() |
|
||||||
* is called, the SysTick interrupt will be enabled and so Tick increment |
|
||||||
* is resumed. |
|
||||||
* @note This function is declared as __weak to be overwritten in case of other |
|
||||||
* implementations in user file. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
__weak void HAL_ResumeTick(void) |
|
||||||
{ |
|
||||||
/* Enable SysTick Interrupt */ |
|
||||||
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the HAL revision |
|
||||||
* @retval version 0xXYZR (8bits for each decimal, R for RC) |
|
||||||
*/ |
|
||||||
uint32_t HAL_GetHalVersion(void) |
|
||||||
{ |
|
||||||
return __STM32F1xx_HAL_VERSION; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the device revision identifier. |
|
||||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
|
||||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
|
||||||
* STM32F101xF/G and STM32F103xF/G |
|
||||||
* STM32F10xx4 and STM32F10xx6 |
|
||||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
|
||||||
* debug mode (not accessible by the user software in normal mode). |
|
||||||
* Refer to errata sheet of these devices for more details. |
|
||||||
* @retval Device revision identifier |
|
||||||
*/ |
|
||||||
uint32_t HAL_GetREVID(void) |
|
||||||
{ |
|
||||||
return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the device identifier. |
|
||||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
|
||||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
|
||||||
* STM32F101xF/G and STM32F103xF/G |
|
||||||
* STM32F10xx4 and STM32F10xx6 |
|
||||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
|
||||||
* debug mode (not accessible by the user software in normal mode). |
|
||||||
* Refer to errata sheet of these devices for more details. |
|
||||||
* @retval Device identifier |
|
||||||
*/ |
|
||||||
uint32_t HAL_GetDEVID(void) |
|
||||||
{ |
|
||||||
return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns first word of the unique device identifier (UID based on 96 bits) |
|
||||||
* @retval Device identifier |
|
||||||
*/ |
|
||||||
uint32_t HAL_GetUIDw0(void) |
|
||||||
{ |
|
||||||
return(READ_REG(*((uint32_t *)UID_BASE))); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns second word of the unique device identifier (UID based on 96 bits) |
|
||||||
* @retval Device identifier |
|
||||||
*/ |
|
||||||
uint32_t HAL_GetUIDw1(void) |
|
||||||
{ |
|
||||||
return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns third word of the unique device identifier (UID based on 96 bits) |
|
||||||
* @retval Device identifier |
|
||||||
*/ |
|
||||||
uint32_t HAL_GetUIDw2(void) |
|
||||||
{ |
|
||||||
return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the Debug Module during SLEEP mode |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_DBGMCU_EnableDBGSleepMode(void) |
|
||||||
{ |
|
||||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the Debug Module during SLEEP mode |
|
||||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
|
||||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
|
||||||
* STM32F101xF/G and STM32F103xF/G |
|
||||||
* STM32F10xx4 and STM32F10xx6 |
|
||||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
|
||||||
* debug mode (not accessible by the user software in normal mode). |
|
||||||
* Refer to errata sheet of these devices for more details. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_DBGMCU_DisableDBGSleepMode(void) |
|
||||||
{ |
|
||||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the Debug Module during STOP mode |
|
||||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
|
||||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
|
||||||
* STM32F101xF/G and STM32F103xF/G |
|
||||||
* STM32F10xx4 and STM32F10xx6 |
|
||||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
|
||||||
* debug mode (not accessible by the user software in normal mode). |
|
||||||
* Refer to errata sheet of these devices for more details. |
|
||||||
* Note: On all STM32F1 devices: |
|
||||||
* If the system tick timer interrupt is enabled during the Stop mode |
|
||||||
* debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup |
|
||||||
* the system from Stop mode. |
|
||||||
* Workaround: To debug the Stop mode, disable the system tick timer |
|
||||||
* interrupt. |
|
||||||
* Refer to errata sheet of these devices for more details. |
|
||||||
* Note: On all STM32F1 devices: |
|
||||||
* If the system tick timer interrupt is enabled during the Stop mode |
|
||||||
* debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup |
|
||||||
* the system from Stop mode. |
|
||||||
* Workaround: To debug the Stop mode, disable the system tick timer |
|
||||||
* interrupt. |
|
||||||
* Refer to errata sheet of these devices for more details. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_DBGMCU_EnableDBGStopMode(void) |
|
||||||
{ |
|
||||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the Debug Module during STOP mode |
|
||||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
|
||||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
|
||||||
* STM32F101xF/G and STM32F103xF/G |
|
||||||
* STM32F10xx4 and STM32F10xx6 |
|
||||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
|
||||||
* debug mode (not accessible by the user software in normal mode). |
|
||||||
* Refer to errata sheet of these devices for more details. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_DBGMCU_DisableDBGStopMode(void) |
|
||||||
{ |
|
||||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the Debug Module during STANDBY mode |
|
||||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
|
||||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
|
||||||
* STM32F101xF/G and STM32F103xF/G |
|
||||||
* STM32F10xx4 and STM32F10xx6 |
|
||||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
|
||||||
* debug mode (not accessible by the user software in normal mode). |
|
||||||
* Refer to errata sheet of these devices for more details. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_DBGMCU_EnableDBGStandbyMode(void) |
|
||||||
{ |
|
||||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable the Debug Module during STANDBY mode |
|
||||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
|
||||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
|
||||||
* STM32F101xF/G and STM32F103xF/G |
|
||||||
* STM32F10xx4 and STM32F10xx6 |
|
||||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
|
||||||
* debug mode (not accessible by the user software in normal mode). |
|
||||||
* Refer to errata sheet of these devices for more details. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_DBGMCU_DisableDBGStandbyMode(void) |
|
||||||
{ |
|
||||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* HAL_MODULE_ENABLED */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,505 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_cortex.c |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief CORTEX HAL module driver. |
|
||||||
* This file provides firmware functions to manage the following
|
|
||||||
* functionalities of the CORTEX: |
|
||||||
* + Initialization and de-initialization functions |
|
||||||
* + Peripheral Control functions
|
|
||||||
* |
|
||||||
@verbatim
|
|
||||||
============================================================================== |
|
||||||
##### How to use this driver ##### |
|
||||||
============================================================================== |
|
||||||
|
|
||||||
[..]
|
|
||||||
*** How to configure Interrupts using CORTEX HAL driver *** |
|
||||||
=========================================================== |
|
||||||
[..]
|
|
||||||
This section provides functions allowing to configure the NVIC interrupts (IRQ). |
|
||||||
The Cortex-M3 exceptions are managed by CMSIS functions. |
|
||||||
|
|
||||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() |
|
||||||
function according to the following table. |
|
||||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
|
|
||||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). |
|
||||||
(#) please refer to programming manual for details in how to configure priority.
|
|
||||||
|
|
||||||
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
|
|
||||||
The pending IRQ priority will be managed only by the sub priority. |
|
||||||
|
|
||||||
-@- IRQ priority order (sorted by highest to lowest priority): |
|
||||||
(+@) Lowest preemption priority |
|
||||||
(+@) Lowest sub priority |
|
||||||
(+@) Lowest hardware priority (IRQ number) |
|
||||||
|
|
||||||
[..]
|
|
||||||
*** How to configure Systick using CORTEX HAL driver *** |
|
||||||
======================================================== |
|
||||||
[..] |
|
||||||
Setup SysTick Timer for time base. |
|
||||||
|
|
||||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which |
|
||||||
is a CMSIS function that: |
|
||||||
(++) Configures the SysTick Reload register with value passed as function parameter. |
|
||||||
(++) Configures the SysTick IRQ priority to the lowest value 0x0F. |
|
||||||
(++) Resets the SysTick Counter register. |
|
||||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). |
|
||||||
(++) Enables the SysTick Interrupt. |
|
||||||
(++) Starts the SysTick Counter. |
|
||||||
|
|
||||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro |
|
||||||
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the |
|
||||||
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined |
|
||||||
inside the stm32f1xx_hal_cortex.h file. |
|
||||||
|
|
||||||
(+) You can change the SysTick IRQ priority by calling the |
|
||||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
|
||||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. |
|
||||||
|
|
||||||
(+) To adjust the SysTick time base, use the following formula: |
|
||||||
|
|
||||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) |
|
||||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function |
|
||||||
(++) Reload Value should not exceed 0xFFFFFF |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX CORTEX
|
|
||||||
* @brief CORTEX HAL module driver |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef HAL_CORTEX_MODULE_ENABLED |
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/ |
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/* Private constants ---------------------------------------------------------*/ |
|
||||||
/* Private macros ------------------------------------------------------------*/ |
|
||||||
/* Private functions ---------------------------------------------------------*/ |
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @brief Initialization and Configuration functions
|
|
||||||
* |
|
||||||
@verbatim
|
|
||||||
============================================================================== |
|
||||||
##### Initialization and de-initialization functions ##### |
|
||||||
============================================================================== |
|
||||||
[..] |
|
||||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts |
|
||||||
Systick functionalities
|
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Sets the priority grouping field (preemption priority and subpriority) |
|
||||||
* using the required unlock sequence. |
|
||||||
* @param PriorityGroup: The priority grouping bits length.
|
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority |
|
||||||
* 4 bits for subpriority |
|
||||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority |
|
||||||
* 3 bits for subpriority |
|
||||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority |
|
||||||
* 2 bits for subpriority |
|
||||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority |
|
||||||
* 1 bits for subpriority |
|
||||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority |
|
||||||
* 0 bits for subpriority |
|
||||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
||||||
* The pending IRQ priority will be managed only by the subpriority.
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); |
|
||||||
|
|
||||||
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ |
|
||||||
NVIC_SetPriorityGrouping(PriorityGroup); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Sets the priority of an interrupt. |
|
||||||
* @param IRQn: External interrupt number. |
|
||||||
* This parameter can be an enumerator of IRQn_Type enumeration |
|
||||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h)) |
|
||||||
* @param PreemptPriority: The preemption priority for the IRQn channel. |
|
||||||
* This parameter can be a value between 0 and 15 |
|
||||||
* A lower priority value indicates a higher priority
|
|
||||||
* @param SubPriority: the subpriority level for the IRQ channel. |
|
||||||
* This parameter can be a value between 0 and 15 |
|
||||||
* A lower priority value indicates a higher priority.
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) |
|
||||||
{
|
|
||||||
uint32_t prioritygroup = 0x00U; |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); |
|
||||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); |
|
||||||
|
|
||||||
prioritygroup = NVIC_GetPriorityGrouping(); |
|
||||||
|
|
||||||
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller. |
|
||||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() |
|
||||||
* function should be called before.
|
|
||||||
* @param IRQn External interrupt number. |
|
||||||
* This parameter can be an enumerator of IRQn_Type enumeration |
|
||||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
|
||||||
|
|
||||||
/* Enable interrupt */ |
|
||||||
NVIC_EnableIRQ(IRQn); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller. |
|
||||||
* @param IRQn External interrupt number. |
|
||||||
* This parameter can be an enumerator of IRQn_Type enumeration |
|
||||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
|
||||||
|
|
||||||
/* Disable interrupt */ |
|
||||||
NVIC_DisableIRQ(IRQn); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initiates a system reset request to reset the MCU. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_NVIC_SystemReset(void) |
|
||||||
{ |
|
||||||
/* System Reset */ |
|
||||||
NVIC_SystemReset(); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
|
||||||
* Counter is in free running mode to generate periodic interrupts. |
|
||||||
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. |
|
||||||
* @retval status: - 0 Function succeeded. |
|
||||||
* - 1 Function failed. |
|
||||||
*/ |
|
||||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) |
|
||||||
{ |
|
||||||
return SysTick_Config(TicksNumb); |
|
||||||
} |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
|
||||||
* @brief Cortex control functions
|
|
||||||
* |
|
||||||
@verbatim
|
|
||||||
============================================================================== |
|
||||||
##### Peripheral Control functions ##### |
|
||||||
============================================================================== |
|
||||||
[..] |
|
||||||
This subsection provides a set of functions allowing to control the CORTEX |
|
||||||
(NVIC, SYSTICK, MPU) functionalities.
|
|
||||||
|
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U) |
|
||||||
/**
|
|
||||||
* @brief Disables the MPU |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_MPU_Disable(void) |
|
||||||
{ |
|
||||||
/* Make sure outstanding transfers are done */ |
|
||||||
__DMB(); |
|
||||||
|
|
||||||
/* Disable fault exceptions */ |
|
||||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
|
||||||
|
|
||||||
/* Disable the MPU and clear the control register*/ |
|
||||||
MPU->CTRL = 0U; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable the MPU. |
|
||||||
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
|
|
||||||
* NMI, FAULTMASK and privileged access to the default memory
|
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg MPU_HFNMI_PRIVDEF_NONE |
|
||||||
* @arg MPU_HARDFAULT_NMI |
|
||||||
* @arg MPU_PRIVILEGED_DEFAULT |
|
||||||
* @arg MPU_HFNMI_PRIVDEF |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_MPU_Enable(uint32_t MPU_Control) |
|
||||||
{ |
|
||||||
/* Enable the MPU */ |
|
||||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
|
||||||
|
|
||||||
/* Enable fault exceptions */ |
|
||||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
|
||||||
|
|
||||||
/* Ensure MPU setting take effects */ |
|
||||||
__DSB(); |
|
||||||
__ISB(); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes and configures the Region and the memory to be protected. |
|
||||||
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains |
|
||||||
* the initialization and configuration information. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); |
|
||||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); |
|
||||||
|
|
||||||
/* Set the Region number */ |
|
||||||
MPU->RNR = MPU_Init->Number; |
|
||||||
|
|
||||||
if ((MPU_Init->Enable) != RESET) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); |
|
||||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); |
|
||||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); |
|
||||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); |
|
||||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); |
|
||||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); |
|
||||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); |
|
||||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); |
|
||||||
|
|
||||||
MPU->RBAR = MPU_Init->BaseAddress; |
|
||||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | |
|
||||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | |
|
||||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | |
|
||||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | |
|
||||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | |
|
||||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | |
|
||||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | |
|
||||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | |
|
||||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
MPU->RBAR = 0x00U; |
|
||||||
MPU->RASR = 0x00U; |
|
||||||
} |
|
||||||
} |
|
||||||
#endif /* __MPU_PRESENT */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Gets the priority grouping field from the NVIC Interrupt Controller. |
|
||||||
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) |
|
||||||
*/ |
|
||||||
uint32_t HAL_NVIC_GetPriorityGrouping(void) |
|
||||||
{ |
|
||||||
/* Get the PRIGROUP[10:8] field value */ |
|
||||||
return NVIC_GetPriorityGrouping(); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Gets the priority of an interrupt. |
|
||||||
* @param IRQn: External interrupt number. |
|
||||||
* This parameter can be an enumerator of IRQn_Type enumeration |
|
||||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) |
|
||||||
* @param PriorityGroup: the priority grouping bits length. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority |
|
||||||
* 4 bits for subpriority |
|
||||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority |
|
||||||
* 3 bits for subpriority |
|
||||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority |
|
||||||
* 2 bits for subpriority |
|
||||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority |
|
||||||
* 1 bits for subpriority |
|
||||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority |
|
||||||
* 0 bits for subpriority |
|
||||||
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). |
|
||||||
* @param pSubPriority: Pointer on the Subpriority value (starting from 0). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); |
|
||||||
/* Get priority for Cortex-M system or device specific interrupts */ |
|
||||||
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Sets Pending bit of an external interrupt. |
|
||||||
* @param IRQn External interrupt number |
|
||||||
* This parameter can be an enumerator of IRQn_Type enumeration |
|
||||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
|
||||||
|
|
||||||
/* Set interrupt pending */ |
|
||||||
NVIC_SetPendingIRQ(IRQn); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
|
||||||
* and returns the pending bit for the specified interrupt). |
|
||||||
* @param IRQn External interrupt number. |
|
||||||
* This parameter can be an enumerator of IRQn_Type enumeration |
|
||||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
|
||||||
* @retval status: - 0 Interrupt status is not pending. |
|
||||||
* - 1 Interrupt status is pending. |
|
||||||
*/ |
|
||||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
|
||||||
|
|
||||||
/* Return 1 if pending else 0 */ |
|
||||||
return NVIC_GetPendingIRQ(IRQn); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clears the pending bit of an external interrupt. |
|
||||||
* @param IRQn External interrupt number. |
|
||||||
* This parameter can be an enumerator of IRQn_Type enumeration |
|
||||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
|
||||||
|
|
||||||
/* Clear pending interrupt */ |
|
||||||
NVIC_ClearPendingIRQ(IRQn); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). |
|
||||||
* @param IRQn External interrupt number |
|
||||||
* This parameter can be an enumerator of IRQn_Type enumeration |
|
||||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
|
||||||
* @retval status: - 0 Interrupt status is not pending. |
|
||||||
* - 1 Interrupt status is pending. |
|
||||||
*/ |
|
||||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
|
||||||
|
|
||||||
/* Return 1 if active else 0 */ |
|
||||||
return NVIC_GetActive(IRQn); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures the SysTick clock source. |
|
||||||
* @param CLKSource: specifies the SysTick clock source. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. |
|
||||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); |
|
||||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK) |
|
||||||
{ |
|
||||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function handles SYSTICK interrupt request. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_SYSTICK_IRQHandler(void) |
|
||||||
{ |
|
||||||
HAL_SYSTICK_Callback(); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SYSTICK callback. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
__weak void HAL_SYSTICK_Callback(void) |
|
||||||
{ |
|
||||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
||||||
the HAL_SYSTICK_Callback could be implemented in the user file |
|
||||||
*/ |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* HAL_CORTEX_MODULE_ENABLED */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,899 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_dma.c |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief DMA HAL module driver. |
|
||||||
* This file provides firmware functions to manage the following |
|
||||||
* functionalities of the Direct Memory Access (DMA) peripheral: |
|
||||||
* + Initialization and de-initialization functions |
|
||||||
* + IO operation functions |
|
||||||
* + Peripheral State and errors functions |
|
||||||
@verbatim |
|
||||||
============================================================================== |
|
||||||
##### How to use this driver ##### |
|
||||||
============================================================================== |
|
||||||
[..] |
|
||||||
(#) Enable and configure the peripheral to be connected to the DMA Channel |
|
||||||
(except for internal SRAM / FLASH memories: no initialization is
|
|
||||||
necessary). Please refer to the Reference manual for connection between peripherals |
|
||||||
and DMA requests. |
|
||||||
|
|
||||||
(#) For a given Channel, program the required configuration through the following parameters: |
|
||||||
Channel request, Transfer Direction, Source and Destination data formats, |
|
||||||
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode |
|
||||||
using HAL_DMA_Init() function. |
|
||||||
|
|
||||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
|
||||||
detection. |
|
||||||
|
|
||||||
(#) Use HAL_DMA_Abort() function to abort the current transfer |
|
||||||
|
|
||||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed. |
|
||||||
*** Polling mode IO operation *** |
|
||||||
================================= |
|
||||||
[..] |
|
||||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source |
|
||||||
address and destination address and the Length of data to be transferred |
|
||||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this |
|
||||||
case a fixed Timeout can be configured by User depending from his application. |
|
||||||
|
|
||||||
*** Interrupt mode IO operation *** |
|
||||||
=================================== |
|
||||||
[..] |
|
||||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() |
|
||||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() |
|
||||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of |
|
||||||
Source address and destination address and the Length of data to be transferred. |
|
||||||
In this case the DMA interrupt is configured |
|
||||||
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine |
|
||||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can |
|
||||||
add his own function by customization of function pointer XferCpltCallback and |
|
||||||
XferErrorCallback (i.e. a member of DMA handle structure). |
|
||||||
|
|
||||||
*** DMA HAL driver macros list *** |
|
||||||
=============================================
|
|
||||||
[..] |
|
||||||
Below the list of most used macros in DMA HAL driver. |
|
||||||
|
|
||||||
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. |
|
||||||
(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. |
|
||||||
(+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. |
|
||||||
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. |
|
||||||
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. |
|
||||||
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. |
|
||||||
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
|
|
||||||
|
|
||||||
[..]
|
|
||||||
(@) You can refer to the DMA HAL driver header file for more useful macros
|
|
||||||
|
|
||||||
@endverbatim |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA DMA
|
|
||||||
* @brief DMA HAL module driver |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef HAL_DMA_MODULE_ENABLED |
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/ |
|
||||||
/* Private define ------------------------------------------------------------*/ |
|
||||||
/* Private macro -------------------------------------------------------------*/ |
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/* Private function prototypes -----------------------------------------------*/ |
|
||||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported functions ---------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @brief Initialization and de-initialization functions
|
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### Initialization and de-initialization functions ##### |
|
||||||
=============================================================================== |
|
||||||
[..] |
|
||||||
This section provides functions allowing to initialize the DMA Channel source |
|
||||||
and destination addresses, incrementation and data sizes, transfer direction,
|
|
||||||
circular/normal mode selection, memory-to-memory mode selection and Channel priority value. |
|
||||||
[..] |
|
||||||
The HAL_DMA_Init() function follows the DMA configuration procedures as described in |
|
||||||
reference manual.
|
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initialize the DMA according to the specified |
|
||||||
* parameters in the DMA_InitTypeDef and initialize the associated handle. |
|
||||||
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) |
|
||||||
{ |
|
||||||
uint32_t tmp = 0U; |
|
||||||
|
|
||||||
/* Check the DMA handle allocation */ |
|
||||||
if(hdma == NULL) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
|
||||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); |
|
||||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); |
|
||||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); |
|
||||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
|
||||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
|
||||||
assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
|
||||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
|
||||||
|
|
||||||
#if defined (DMA2) |
|
||||||
/* calculation of the channel index */ |
|
||||||
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
|
||||||
{ |
|
||||||
/* DMA1 */ |
|
||||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
|
||||||
hdma->DmaBaseAddress = DMA1; |
|
||||||
} |
|
||||||
else
|
|
||||||
{ |
|
||||||
/* DMA2 */ |
|
||||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; |
|
||||||
hdma->DmaBaseAddress = DMA2; |
|
||||||
} |
|
||||||
#else |
|
||||||
/* DMA1 */ |
|
||||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
|
||||||
hdma->DmaBaseAddress = DMA1; |
|
||||||
#endif /* DMA2 */ |
|
||||||
|
|
||||||
/* Change DMA peripheral state */ |
|
||||||
hdma->State = HAL_DMA_STATE_BUSY; |
|
||||||
|
|
||||||
/* Get the CR register value */ |
|
||||||
tmp = hdma->Instance->CCR; |
|
||||||
|
|
||||||
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ |
|
||||||
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
|
||||||
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
|
|
||||||
DMA_CCR_DIR)); |
|
||||||
|
|
||||||
/* Prepare the DMA Channel configuration */ |
|
||||||
tmp |= hdma->Init.Direction | |
|
||||||
hdma->Init.PeriphInc | hdma->Init.MemInc | |
|
||||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | |
|
||||||
hdma->Init.Mode | hdma->Init.Priority; |
|
||||||
|
|
||||||
/* Write to DMA Channel CR register */ |
|
||||||
hdma->Instance->CCR = tmp; |
|
||||||
|
|
||||||
/* Initialise the error code */ |
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
|
||||||
|
|
||||||
/* Initialize the DMA state*/ |
|
||||||
hdma->State = HAL_DMA_STATE_READY; |
|
||||||
/* Allocate lock resource and initialize it */ |
|
||||||
hdma->Lock = HAL_UNLOCKED; |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief DeInitialize the DMA peripheral. |
|
||||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) |
|
||||||
{ |
|
||||||
/* Check the DMA handle allocation */ |
|
||||||
if(hdma == NULL) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
|
||||||
|
|
||||||
/* Disable the selected DMA Channelx */ |
|
||||||
__HAL_DMA_DISABLE(hdma); |
|
||||||
|
|
||||||
/* Reset DMA Channel control register */ |
|
||||||
hdma->Instance->CCR = 0U; |
|
||||||
|
|
||||||
/* Reset DMA Channel Number of Data to Transfer register */ |
|
||||||
hdma->Instance->CNDTR = 0U; |
|
||||||
|
|
||||||
/* Reset DMA Channel peripheral address register */ |
|
||||||
hdma->Instance->CPAR = 0U; |
|
||||||
|
|
||||||
/* Reset DMA Channel memory address register */ |
|
||||||
hdma->Instance->CMAR = 0U; |
|
||||||
|
|
||||||
#if defined (DMA2) |
|
||||||
/* calculation of the channel index */ |
|
||||||
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
|
||||||
{ |
|
||||||
/* DMA1 */ |
|
||||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
|
||||||
hdma->DmaBaseAddress = DMA1; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* DMA2 */ |
|
||||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; |
|
||||||
hdma->DmaBaseAddress = DMA2; |
|
||||||
} |
|
||||||
#else |
|
||||||
/* DMA1 */ |
|
||||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
|
||||||
hdma->DmaBaseAddress = DMA1; |
|
||||||
#endif /* DMA2 */ |
|
||||||
|
|
||||||
/* Clear all flags */ |
|
||||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); |
|
||||||
|
|
||||||
/* Clean all callbacks */ |
|
||||||
hdma->XferCpltCallback = NULL; |
|
||||||
hdma->XferHalfCpltCallback = NULL; |
|
||||||
hdma->XferErrorCallback = NULL; |
|
||||||
hdma->XferAbortCallback = NULL; |
|
||||||
|
|
||||||
/* Reset the error code */ |
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
|
||||||
|
|
||||||
/* Reset the DMA state */ |
|
||||||
hdma->State = HAL_DMA_STATE_RESET; |
|
||||||
|
|
||||||
/* Release Lock */ |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
|
|
||||||
* @brief Input and Output operation functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### IO operation functions ##### |
|
||||||
=============================================================================== |
|
||||||
[..] This section provides functions allowing to: |
|
||||||
(+) Configure the source, destination address and data length and Start DMA transfer |
|
||||||
(+) Configure the source, destination address and data length and |
|
||||||
Start DMA transfer with interrupt |
|
||||||
(+) Abort DMA transfer |
|
||||||
(+) Poll for transfer complete |
|
||||||
(+) Handle DMA interrupt request |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Start the DMA Transfer. |
|
||||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @param SrcAddress: The source memory Buffer address |
|
||||||
* @param DstAddress: The destination memory Buffer address |
|
||||||
* @param DataLength: The length of data to be transferred from source to destination |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
|
||||||
{ |
|
||||||
HAL_StatusTypeDef status = HAL_OK; |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
|
||||||
|
|
||||||
/* Process locked */ |
|
||||||
__HAL_LOCK(hdma); |
|
||||||
|
|
||||||
if(HAL_DMA_STATE_READY == hdma->State) |
|
||||||
{ |
|
||||||
/* Change DMA peripheral state */ |
|
||||||
hdma->State = HAL_DMA_STATE_BUSY; |
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
|
||||||
|
|
||||||
/* Disable the peripheral */ |
|
||||||
__HAL_DMA_DISABLE(hdma); |
|
||||||
|
|
||||||
/* Configure the source, destination address and the data length & clear flags*/ |
|
||||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
|
||||||
|
|
||||||
/* Enable the Peripheral */ |
|
||||||
__HAL_DMA_ENABLE(hdma); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(hdma);
|
|
||||||
status = HAL_BUSY; |
|
||||||
}
|
|
||||||
return status; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Start the DMA Transfer with interrupt enabled. |
|
||||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @param SrcAddress: The source memory Buffer address |
|
||||||
* @param DstAddress: The destination memory Buffer address |
|
||||||
* @param DataLength: The length of data to be transferred from source to destination |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
|
||||||
{ |
|
||||||
HAL_StatusTypeDef status = HAL_OK; |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
|
||||||
|
|
||||||
/* Process locked */ |
|
||||||
__HAL_LOCK(hdma); |
|
||||||
|
|
||||||
if(HAL_DMA_STATE_READY == hdma->State) |
|
||||||
{ |
|
||||||
/* Change DMA peripheral state */ |
|
||||||
hdma->State = HAL_DMA_STATE_BUSY; |
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
|
||||||
|
|
||||||
/* Disable the peripheral */ |
|
||||||
__HAL_DMA_DISABLE(hdma); |
|
||||||
|
|
||||||
/* Configure the source, destination address and the data length & clear flags*/ |
|
||||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
|
||||||
|
|
||||||
/* Enable the transfer complete interrupt */ |
|
||||||
/* Enable the transfer Error interrupt */ |
|
||||||
if(NULL != hdma->XferHalfCpltCallback) |
|
||||||
{ |
|
||||||
/* Enable the Half transfer complete interrupt as well */ |
|
||||||
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
|
||||||
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); |
|
||||||
} |
|
||||||
/* Enable the Peripheral */ |
|
||||||
__HAL_DMA_ENABLE(hdma); |
|
||||||
} |
|
||||||
else |
|
||||||
{
|
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(hdma);
|
|
||||||
|
|
||||||
/* Remain BUSY */ |
|
||||||
status = HAL_BUSY; |
|
||||||
}
|
|
||||||
return status; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Abort the DMA Transfer. |
|
||||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
|
||||||
{ |
|
||||||
HAL_StatusTypeDef status = HAL_OK; |
|
||||||
|
|
||||||
if(hdma->State != HAL_DMA_STATE_BUSY) |
|
||||||
{ |
|
||||||
/* no transfer ongoing */ |
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
|
||||||
|
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
|
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
else |
|
||||||
|
|
||||||
{ |
|
||||||
/* Disable DMA IT */ |
|
||||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
|
||||||
|
|
||||||
/* Disable the channel */ |
|
||||||
__HAL_DMA_DISABLE(hdma); |
|
||||||
|
|
||||||
/* Clear all flags */ |
|
||||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
|
||||||
} |
|
||||||
/* Change the DMA state */ |
|
||||||
hdma->State = HAL_DMA_STATE_READY; |
|
||||||
|
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(hdma);
|
|
||||||
|
|
||||||
return status;
|
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Aborts the DMA Transfer in Interrupt mode. |
|
||||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) |
|
||||||
{
|
|
||||||
HAL_StatusTypeDef status = HAL_OK; |
|
||||||
|
|
||||||
if(HAL_DMA_STATE_BUSY != hdma->State) |
|
||||||
{ |
|
||||||
/* no transfer ongoing */ |
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
|
||||||
|
|
||||||
status = HAL_ERROR; |
|
||||||
} |
|
||||||
else |
|
||||||
{
|
|
||||||
/* Disable DMA IT */ |
|
||||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
|
||||||
|
|
||||||
/* Disable the channel */ |
|
||||||
__HAL_DMA_DISABLE(hdma); |
|
||||||
|
|
||||||
/* Clear all flags */ |
|
||||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); |
|
||||||
|
|
||||||
/* Change the DMA state */ |
|
||||||
hdma->State = HAL_DMA_STATE_READY; |
|
||||||
|
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
|
|
||||||
/* Call User Abort callback */ |
|
||||||
if(hdma->XferAbortCallback != NULL) |
|
||||||
{ |
|
||||||
hdma->XferAbortCallback(hdma); |
|
||||||
}
|
|
||||||
} |
|
||||||
return status; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Polling for transfer complete. |
|
||||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @param CompleteLevel: Specifies the DMA level complete. |
|
||||||
* @param Timeout: Timeout duration. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) |
|
||||||
{ |
|
||||||
uint32_t temp; |
|
||||||
uint32_t tickstart = 0U; |
|
||||||
|
|
||||||
if(HAL_DMA_STATE_BUSY != hdma->State) |
|
||||||
{ |
|
||||||
/* no transfer ongoing */ |
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Polling mode not supported in circular mode */ |
|
||||||
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) |
|
||||||
{ |
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Get the level transfer complete flag */ |
|
||||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
|
||||||
{ |
|
||||||
/* Transfer Complete flag */ |
|
||||||
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Half Transfer Complete flag */ |
|
||||||
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); |
|
||||||
} |
|
||||||
|
|
||||||
/* Get tick */ |
|
||||||
tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) |
|
||||||
{ |
|
||||||
if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) |
|
||||||
{ |
|
||||||
/* When a DMA transfer error occurs */ |
|
||||||
/* A hardware clear of its EN bits is performed */ |
|
||||||
/* Clear all flags */ |
|
||||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
|
||||||
|
|
||||||
/* Update error code */ |
|
||||||
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); |
|
||||||
|
|
||||||
/* Change the DMA state */ |
|
||||||
hdma->State= HAL_DMA_STATE_READY; |
|
||||||
|
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
|
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
/* Check for the Timeout */ |
|
||||||
if(Timeout != HAL_MAX_DELAY) |
|
||||||
{ |
|
||||||
if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) |
|
||||||
{ |
|
||||||
/* Update error code */ |
|
||||||
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); |
|
||||||
|
|
||||||
/* Change the DMA state */ |
|
||||||
hdma->State = HAL_DMA_STATE_READY; |
|
||||||
|
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
|
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
|
||||||
{ |
|
||||||
/* Clear the transfer complete flag */ |
|
||||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
|
||||||
|
|
||||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
|
||||||
all transfers are complete) */ |
|
||||||
hdma->State = HAL_DMA_STATE_READY; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Clear the half transfer complete flag */ |
|
||||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
|
||||||
} |
|
||||||
|
|
||||||
/* Process unlocked */ |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Handles DMA interrupt request. |
|
||||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel.
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) |
|
||||||
{ |
|
||||||
uint32_t flag_it = hdma->DmaBaseAddress->ISR; |
|
||||||
uint32_t source_it = hdma->Instance->CCR; |
|
||||||
|
|
||||||
/* Half Transfer Complete Interrupt management ******************************/ |
|
||||||
if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) |
|
||||||
{ |
|
||||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ |
|
||||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
|
||||||
{ |
|
||||||
/* Disable the half transfer interrupt */ |
|
||||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
|
||||||
} |
|
||||||
/* Clear the half transfer complete flag */ |
|
||||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
|
||||||
|
|
||||||
/* DMA peripheral state is not updated in Half Transfer */ |
|
||||||
/* but in Transfer Complete case */ |
|
||||||
|
|
||||||
if(hdma->XferHalfCpltCallback != NULL) |
|
||||||
{ |
|
||||||
/* Half transfer callback */ |
|
||||||
hdma->XferHalfCpltCallback(hdma); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* Transfer Complete Interrupt management ***********************************/ |
|
||||||
else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) |
|
||||||
{ |
|
||||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
|
||||||
{ |
|
||||||
/* Disable the transfer complete and error interrupt */ |
|
||||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
|
|
||||||
|
|
||||||
/* Change the DMA state */ |
|
||||||
hdma->State = HAL_DMA_STATE_READY; |
|
||||||
} |
|
||||||
/* Clear the transfer complete flag */ |
|
||||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
|
||||||
|
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
|
|
||||||
if(hdma->XferCpltCallback != NULL) |
|
||||||
{ |
|
||||||
/* Transfer complete callback */ |
|
||||||
hdma->XferCpltCallback(hdma); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* Transfer Error Interrupt management **************************************/ |
|
||||||
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) |
|
||||||
{ |
|
||||||
/* When a DMA transfer error occurs */ |
|
||||||
/* A hardware clear of its EN bits is performed */ |
|
||||||
/* Disable ALL DMA IT */ |
|
||||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
|
||||||
|
|
||||||
/* Clear all flags */ |
|
||||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
|
||||||
|
|
||||||
/* Update error code */ |
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_TE; |
|
||||||
|
|
||||||
/* Change the DMA state */ |
|
||||||
hdma->State = HAL_DMA_STATE_READY; |
|
||||||
|
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
|
|
||||||
if (hdma->XferErrorCallback != NULL) |
|
||||||
{ |
|
||||||
/* Transfer error callback */ |
|
||||||
hdma->XferErrorCallback(hdma); |
|
||||||
} |
|
||||||
} |
|
||||||
return; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Register callbacks |
|
||||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @param CallbackID: User Callback identifer |
|
||||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
|
||||||
* @param pCallback: pointer to private callbacsk function which has pointer to
|
|
||||||
* a DMA_HandleTypeDef structure as parameter. |
|
||||||
* @retval HAL status |
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) |
|
||||||
{ |
|
||||||
HAL_StatusTypeDef status = HAL_OK; |
|
||||||
|
|
||||||
/* Process locked */ |
|
||||||
__HAL_LOCK(hdma); |
|
||||||
|
|
||||||
if(HAL_DMA_STATE_READY == hdma->State) |
|
||||||
{ |
|
||||||
switch (CallbackID) |
|
||||||
{ |
|
||||||
case HAL_DMA_XFER_CPLT_CB_ID: |
|
||||||
hdma->XferCpltCallback = pCallback; |
|
||||||
break; |
|
||||||
|
|
||||||
case HAL_DMA_XFER_HALFCPLT_CB_ID: |
|
||||||
hdma->XferHalfCpltCallback = pCallback; |
|
||||||
break;
|
|
||||||
|
|
||||||
case HAL_DMA_XFER_ERROR_CB_ID: |
|
||||||
hdma->XferErrorCallback = pCallback; |
|
||||||
break;
|
|
||||||
|
|
||||||
case HAL_DMA_XFER_ABORT_CB_ID: |
|
||||||
hdma->XferAbortCallback = pCallback; |
|
||||||
break;
|
|
||||||
|
|
||||||
default: |
|
||||||
status = HAL_ERROR; |
|
||||||
break;
|
|
||||||
} |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
status = HAL_ERROR; |
|
||||||
}
|
|
||||||
|
|
||||||
/* Release Lock */ |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
|
|
||||||
return status; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief UnRegister callbacks |
|
||||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @param CallbackID: User Callback identifer |
|
||||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
|
||||||
* @retval HAL status |
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) |
|
||||||
{ |
|
||||||
HAL_StatusTypeDef status = HAL_OK; |
|
||||||
|
|
||||||
/* Process locked */ |
|
||||||
__HAL_LOCK(hdma); |
|
||||||
|
|
||||||
if(HAL_DMA_STATE_READY == hdma->State) |
|
||||||
{ |
|
||||||
switch (CallbackID) |
|
||||||
{ |
|
||||||
case HAL_DMA_XFER_CPLT_CB_ID: |
|
||||||
hdma->XferCpltCallback = NULL; |
|
||||||
break; |
|
||||||
|
|
||||||
case HAL_DMA_XFER_HALFCPLT_CB_ID: |
|
||||||
hdma->XferHalfCpltCallback = NULL; |
|
||||||
break;
|
|
||||||
|
|
||||||
case HAL_DMA_XFER_ERROR_CB_ID: |
|
||||||
hdma->XferErrorCallback = NULL; |
|
||||||
break;
|
|
||||||
|
|
||||||
case HAL_DMA_XFER_ABORT_CB_ID: |
|
||||||
hdma->XferAbortCallback = NULL; |
|
||||||
break;
|
|
||||||
|
|
||||||
case HAL_DMA_XFER_ALL_CB_ID: |
|
||||||
hdma->XferCpltCallback = NULL; |
|
||||||
hdma->XferHalfCpltCallback = NULL; |
|
||||||
hdma->XferErrorCallback = NULL; |
|
||||||
hdma->XferAbortCallback = NULL; |
|
||||||
break;
|
|
||||||
|
|
||||||
default: |
|
||||||
status = HAL_ERROR; |
|
||||||
break; |
|
||||||
} |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
status = HAL_ERROR; |
|
||||||
}
|
|
||||||
|
|
||||||
/* Release Lock */ |
|
||||||
__HAL_UNLOCK(hdma); |
|
||||||
|
|
||||||
return status; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
|
|
||||||
* @brief Peripheral State and Errors functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### Peripheral State and Errors functions ##### |
|
||||||
===============================================================================
|
|
||||||
[..] |
|
||||||
This subsection provides functions allowing to |
|
||||||
(+) Check the DMA state |
|
||||||
(+) Get error code |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the DMA hande state. |
|
||||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @retval HAL state |
|
||||||
*/ |
|
||||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) |
|
||||||
{ |
|
||||||
/* Return DMA handle state */ |
|
||||||
return hdma->State; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Return the DMA error code. |
|
||||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @retval DMA Error Code |
|
||||||
*/ |
|
||||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) |
|
||||||
{ |
|
||||||
return hdma->ErrorCode; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup DMA_Private_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Sets the DMA Transfer parameter. |
|
||||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
|
||||||
* the configuration information for the specified DMA Channel. |
|
||||||
* @param SrcAddress: The source memory Buffer address |
|
||||||
* @param DstAddress: The destination memory Buffer address |
|
||||||
* @param DataLength: The length of data to be transferred from source to destination |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
|
||||||
{ |
|
||||||
/* Clear all flags */ |
|
||||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
|
||||||
|
|
||||||
/* Configure DMA Channel data length */ |
|
||||||
hdma->Instance->CNDTR = DataLength; |
|
||||||
|
|
||||||
/* Memory to Peripheral */ |
|
||||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) |
|
||||||
{ |
|
||||||
/* Configure DMA Channel destination address */ |
|
||||||
hdma->Instance->CPAR = DstAddress; |
|
||||||
|
|
||||||
/* Configure DMA Channel source address */ |
|
||||||
hdma->Instance->CMAR = SrcAddress; |
|
||||||
} |
|
||||||
/* Peripheral to Memory */ |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Configure DMA Channel source address */ |
|
||||||
hdma->Instance->CPAR = SrcAddress; |
|
||||||
|
|
||||||
/* Configure DMA Channel destination address */ |
|
||||||
hdma->Instance->CMAR = DstAddress; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* HAL_DMA_MODULE_ENABLED */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,555 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_exti.c |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief EXTI HAL module driver. |
|
||||||
* This file provides firmware functions to manage the following |
|
||||||
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral: |
|
||||||
* + Initialization and de-initialization functions |
|
||||||
* + IO operation functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
============================================================================== |
|
||||||
##### EXTI Peripheral features ##### |
|
||||||
============================================================================== |
|
||||||
[..] |
|
||||||
(+) Each Exti line can be configured within this driver. |
|
||||||
|
|
||||||
(+) Exti line can be configured in 3 different modes |
|
||||||
(++) Interrupt |
|
||||||
(++) Event |
|
||||||
(++) Both of them |
|
||||||
|
|
||||||
(+) Configurable Exti lines can be configured with 3 different triggers |
|
||||||
(++) Rising |
|
||||||
(++) Falling |
|
||||||
(++) Both of them |
|
||||||
|
|
||||||
(+) When set in interrupt mode, configurable Exti lines have two different |
|
||||||
interrupts pending registers which allow to distinguish which transition |
|
||||||
occurs: |
|
||||||
(++) Rising edge pending interrupt |
|
||||||
(++) Falling |
|
||||||
|
|
||||||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can |
|
||||||
be selected through multiplexer. |
|
||||||
|
|
||||||
##### How to use this driver ##### |
|
||||||
============================================================================== |
|
||||||
[..] |
|
||||||
|
|
||||||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). |
|
||||||
(++) Choose the interrupt line number by setting "Line" member from |
|
||||||
EXTI_ConfigTypeDef structure. |
|
||||||
(++) Configure the interrupt and/or event mode using "Mode" member from |
|
||||||
EXTI_ConfigTypeDef structure. |
|
||||||
(++) For configurable lines, configure rising and/or falling trigger |
|
||||||
"Trigger" member from EXTI_ConfigTypeDef structure. |
|
||||||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" |
|
||||||
member from GPIO_InitTypeDef structure. |
|
||||||
|
|
||||||
(#) Get current Exti configuration of a dedicated line using |
|
||||||
HAL_EXTI_GetConfigLine(). |
|
||||||
(++) Provide exiting handle as parameter. |
|
||||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. |
|
||||||
|
|
||||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). |
|
||||||
(++) Provide exiting handle as parameter. |
|
||||||
|
|
||||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). |
|
||||||
(++) Provide exiting handle as first parameter. |
|
||||||
(++) Provide which callback will be registered using one value from |
|
||||||
EXTI_CallbackIDTypeDef. |
|
||||||
(++) Provide callback function pointer. |
|
||||||
|
|
||||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending(). |
|
||||||
|
|
||||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending(). |
|
||||||
|
|
||||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI(). |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup EXTI
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/** MISRA C:2012 deviation rule has been granted for following rule:
|
|
||||||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out |
|
||||||
* of bounds [0,3] in following API : |
|
||||||
* HAL_EXTI_SetConfigLine |
|
||||||
* HAL_EXTI_GetConfigLine |
|
||||||
* HAL_EXTI_ClearConfigLine |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef HAL_EXTI_MODULE_ENABLED |
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/ |
|
||||||
/* Private defines -----------------------------------------------------------*/ |
|
||||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/ |
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/* Private function prototypes -----------------------------------------------*/ |
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @addtogroup EXTI_Exported_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup EXTI_Exported_Functions_Group1
|
|
||||||
* @brief Configuration functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### Configuration functions ##### |
|
||||||
=============================================================================== |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set configuration of a dedicated Exti line. |
|
||||||
* @param hexti Exti handle. |
|
||||||
* @param pExtiConfig Pointer on EXTI configuration to be set. |
|
||||||
* @retval HAL Status. |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) |
|
||||||
{ |
|
||||||
uint32_t regval; |
|
||||||
uint32_t linepos; |
|
||||||
uint32_t maskline; |
|
||||||
|
|
||||||
/* Check null pointer */ |
|
||||||
if ((hexti == NULL) || (pExtiConfig == NULL)) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Check parameters */ |
|
||||||
assert_param(IS_EXTI_LINE(pExtiConfig->Line)); |
|
||||||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); |
|
||||||
|
|
||||||
/* Assign line number to handle */ |
|
||||||
hexti->Line = pExtiConfig->Line; |
|
||||||
|
|
||||||
/* Compute line mask */ |
|
||||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK); |
|
||||||
maskline = (1uL << linepos); |
|
||||||
|
|
||||||
/* Configure triggers for configurable lines */ |
|
||||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) |
|
||||||
{ |
|
||||||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); |
|
||||||
|
|
||||||
/* Configure rising trigger */ |
|
||||||
/* Mask or set line */ |
|
||||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) |
|
||||||
{ |
|
||||||
EXTI->RTSR |= maskline; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
EXTI->RTSR &= ~maskline; |
|
||||||
} |
|
||||||
|
|
||||||
/* Configure falling trigger */ |
|
||||||
/* Mask or set line */ |
|
||||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) |
|
||||||
{ |
|
||||||
EXTI->FTSR |= maskline; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
EXTI->FTSR &= ~maskline; |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
/* Configure gpio port selection in case of gpio exti line */ |
|
||||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) |
|
||||||
{ |
|
||||||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); |
|
||||||
assert_param(IS_EXTI_GPIO_PIN(linepos)); |
|
||||||
|
|
||||||
regval = AFIO->EXTICR[linepos >> 2u]; |
|
||||||
regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); |
|
||||||
regval |= (pExtiConfig->GPIOSel << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); |
|
||||||
AFIO->EXTICR[linepos >> 2u] = regval; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* Configure interrupt mode : read current mode */ |
|
||||||
/* Mask or set line */ |
|
||||||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) |
|
||||||
{ |
|
||||||
EXTI->IMR |= maskline; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
EXTI->IMR &= ~maskline; |
|
||||||
} |
|
||||||
|
|
||||||
/* Configure event mode : read current mode */ |
|
||||||
/* Mask or set line */ |
|
||||||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) |
|
||||||
{ |
|
||||||
EXTI->EMR |= maskline; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
EXTI->EMR &= ~maskline; |
|
||||||
} |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get configuration of a dedicated Exti line. |
|
||||||
* @param hexti Exti handle. |
|
||||||
* @param pExtiConfig Pointer on structure to store Exti configuration. |
|
||||||
* @retval HAL Status. |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) |
|
||||||
{ |
|
||||||
uint32_t regval; |
|
||||||
uint32_t linepos; |
|
||||||
uint32_t maskline; |
|
||||||
|
|
||||||
/* Check null pointer */ |
|
||||||
if ((hexti == NULL) || (pExtiConfig == NULL)) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Check the parameter */ |
|
||||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
|
||||||
|
|
||||||
/* Store handle line number to configuration structure */ |
|
||||||
pExtiConfig->Line = hexti->Line; |
|
||||||
|
|
||||||
/* Compute line mask */ |
|
||||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK); |
|
||||||
maskline = (1uL << linepos); |
|
||||||
|
|
||||||
/* 1] Get core mode : interrupt */ |
|
||||||
|
|
||||||
/* Check if selected line is enable */ |
|
||||||
if ((EXTI->IMR & maskline) != 0x00u) |
|
||||||
{ |
|
||||||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
pExtiConfig->Mode = EXTI_MODE_NONE; |
|
||||||
} |
|
||||||
|
|
||||||
/* Get event mode */ |
|
||||||
/* Check if selected line is enable */ |
|
||||||
if ((EXTI->EMR & maskline) != 0x00u) |
|
||||||
{ |
|
||||||
pExtiConfig->Mode |= EXTI_MODE_EVENT; |
|
||||||
} |
|
||||||
|
|
||||||
/* Get default Trigger and GPIOSel configuration */ |
|
||||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE; |
|
||||||
pExtiConfig->GPIOSel = 0x00u; |
|
||||||
|
|
||||||
/* 2] Get trigger for configurable lines : rising */ |
|
||||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) |
|
||||||
{ |
|
||||||
/* Check if configuration of selected line is enable */ |
|
||||||
if ((EXTI->RTSR & maskline) != 0x00u) |
|
||||||
{ |
|
||||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING; |
|
||||||
} |
|
||||||
|
|
||||||
/* Get falling configuration */ |
|
||||||
/* Check if configuration of selected line is enable */ |
|
||||||
if ((EXTI->FTSR & maskline) != 0x00u) |
|
||||||
{ |
|
||||||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; |
|
||||||
} |
|
||||||
|
|
||||||
/* Get Gpio port selection for gpio lines */ |
|
||||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) |
|
||||||
{ |
|
||||||
assert_param(IS_EXTI_GPIO_PIN(linepos)); |
|
||||||
|
|
||||||
regval = AFIO->EXTICR[linepos >> 2u]; |
|
||||||
pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear whole configuration of a dedicated Exti line. |
|
||||||
* @param hexti Exti handle. |
|
||||||
* @retval HAL Status. |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) |
|
||||||
{ |
|
||||||
uint32_t regval; |
|
||||||
uint32_t linepos; |
|
||||||
uint32_t maskline; |
|
||||||
|
|
||||||
/* Check null pointer */ |
|
||||||
if (hexti == NULL) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Check the parameter */ |
|
||||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
|
||||||
|
|
||||||
/* compute line mask */ |
|
||||||
linepos = (hexti->Line & EXTI_PIN_MASK); |
|
||||||
maskline = (1uL << linepos); |
|
||||||
|
|
||||||
/* 1] Clear interrupt mode */ |
|
||||||
EXTI->IMR = (EXTI->IMR & ~maskline); |
|
||||||
|
|
||||||
/* 2] Clear event mode */ |
|
||||||
EXTI->EMR = (EXTI->EMR & ~maskline); |
|
||||||
|
|
||||||
/* 3] Clear triggers in case of configurable lines */ |
|
||||||
if ((hexti->Line & EXTI_CONFIG) != 0x00u) |
|
||||||
{ |
|
||||||
EXTI->RTSR = (EXTI->RTSR & ~maskline); |
|
||||||
EXTI->FTSR = (EXTI->FTSR & ~maskline); |
|
||||||
|
|
||||||
/* Get Gpio port selection for gpio lines */ |
|
||||||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) |
|
||||||
{ |
|
||||||
assert_param(IS_EXTI_GPIO_PIN(linepos)); |
|
||||||
|
|
||||||
regval = AFIO->EXTICR[linepos >> 2u]; |
|
||||||
regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); |
|
||||||
AFIO->EXTICR[linepos >> 2u] = regval; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Register callback for a dedicated Exti line. |
|
||||||
* @param hexti Exti handle. |
|
||||||
* @param CallbackID User callback identifier. |
|
||||||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. |
|
||||||
* @param pPendingCbfn function pointer to be stored as callback. |
|
||||||
* @retval HAL Status. |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) |
|
||||||
{ |
|
||||||
HAL_StatusTypeDef status = HAL_OK; |
|
||||||
|
|
||||||
switch (CallbackID) |
|
||||||
{ |
|
||||||
case HAL_EXTI_COMMON_CB_ID: |
|
||||||
hexti->PendingCallback = pPendingCbfn; |
|
||||||
break; |
|
||||||
|
|
||||||
default: |
|
||||||
status = HAL_ERROR; |
|
||||||
break; |
|
||||||
} |
|
||||||
|
|
||||||
return status; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Store line number as handle private field. |
|
||||||
* @param hexti Exti handle. |
|
||||||
* @param ExtiLine Exti line number. |
|
||||||
* This parameter can be from 0 to @ref EXTI_LINE_NB. |
|
||||||
* @retval HAL Status. |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_EXTI_LINE(ExtiLine)); |
|
||||||
|
|
||||||
/* Check null pointer */ |
|
||||||
if (hexti == NULL) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Store line number as handle private field */ |
|
||||||
hexti->Line = ExtiLine; |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup EXTI_Exported_Functions_Group2
|
|
||||||
* @brief EXTI IO functions. |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### IO operation functions ##### |
|
||||||
=============================================================================== |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Handle EXTI interrupt request. |
|
||||||
* @param hexti Exti handle. |
|
||||||
* @retval none. |
|
||||||
*/ |
|
||||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) |
|
||||||
{ |
|
||||||
uint32_t regval; |
|
||||||
uint32_t maskline; |
|
||||||
|
|
||||||
/* Compute line mask */ |
|
||||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); |
|
||||||
|
|
||||||
/* Get pending bit */ |
|
||||||
regval = (EXTI->PR & maskline); |
|
||||||
if (regval != 0x00u) |
|
||||||
{ |
|
||||||
/* Clear pending bit */ |
|
||||||
EXTI->PR = maskline; |
|
||||||
|
|
||||||
/* Call callback */ |
|
||||||
if (hexti->PendingCallback != NULL) |
|
||||||
{ |
|
||||||
hexti->PendingCallback(); |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get interrupt pending bit of a dedicated line. |
|
||||||
* @param hexti Exti handle. |
|
||||||
* @param Edge Specify which pending edge as to be checked. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING |
|
||||||
* This parameter is kept for compatibility with other series. |
|
||||||
* @retval 1 if interrupt is pending else 0. |
|
||||||
*/ |
|
||||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) |
|
||||||
{ |
|
||||||
uint32_t regval; |
|
||||||
uint32_t maskline; |
|
||||||
uint32_t linepos; |
|
||||||
|
|
||||||
/* Check parameters */ |
|
||||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
|
||||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); |
|
||||||
assert_param(IS_EXTI_PENDING_EDGE(Edge)); |
|
||||||
|
|
||||||
/* Prevent unused argument compilation warning */ |
|
||||||
UNUSED(Edge); |
|
||||||
|
|
||||||
/* Compute line mask */ |
|
||||||
linepos = (hexti->Line & EXTI_PIN_MASK); |
|
||||||
maskline = (1uL << linepos); |
|
||||||
|
|
||||||
/* return 1 if bit is set else 0 */ |
|
||||||
regval = ((EXTI->PR & maskline) >> linepos); |
|
||||||
return regval; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Clear interrupt pending bit of a dedicated line. |
|
||||||
* @param hexti Exti handle. |
|
||||||
* @param Edge Specify which pending edge as to be clear. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING |
|
||||||
* This parameter is kept for compatibility with other series. |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) |
|
||||||
{ |
|
||||||
uint32_t maskline; |
|
||||||
|
|
||||||
/* Check parameters */ |
|
||||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
|
||||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); |
|
||||||
assert_param(IS_EXTI_PENDING_EDGE(Edge)); |
|
||||||
|
|
||||||
/* Prevent unused argument compilation warning */ |
|
||||||
UNUSED(Edge); |
|
||||||
|
|
||||||
/* Compute line mask */ |
|
||||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); |
|
||||||
|
|
||||||
/* Clear Pending bit */ |
|
||||||
EXTI->PR = maskline; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Generate a software interrupt for a dedicated line. |
|
||||||
* @param hexti Exti handle. |
|
||||||
* @retval None. |
|
||||||
*/ |
|
||||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) |
|
||||||
{ |
|
||||||
uint32_t maskline; |
|
||||||
|
|
||||||
/* Check parameters */ |
|
||||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
|
||||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); |
|
||||||
|
|
||||||
/* Compute line mask */ |
|
||||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); |
|
||||||
|
|
||||||
/* Generate Software interrupt */ |
|
||||||
EXTI->SWIER = maskline; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* HAL_EXTI_MODULE_ENABLED */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,967 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_flash.c |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief FLASH HAL module driver. |
|
||||||
* This file provides firmware functions to manage the following
|
|
||||||
* functionalities of the internal FLASH memory: |
|
||||||
* + Program operations functions |
|
||||||
* + Memory Control functions
|
|
||||||
* + Peripheral State functions |
|
||||||
*
|
|
||||||
@verbatim |
|
||||||
============================================================================== |
|
||||||
##### FLASH peripheral features ##### |
|
||||||
============================================================================== |
|
||||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
|
||||||
to the Flash memory. It implements the erase and program Flash memory operations
|
|
||||||
and the read and write protection mechanisms. |
|
||||||
|
|
||||||
[..] The Flash memory interface accelerates code execution with a system of instruction |
|
||||||
prefetch.
|
|
||||||
|
|
||||||
[..] The FLASH main features are: |
|
||||||
(+) Flash memory read operations |
|
||||||
(+) Flash memory program/erase operations |
|
||||||
(+) Read / write protections |
|
||||||
(+) Prefetch on I-Code |
|
||||||
(+) Option Bytes programming |
|
||||||
|
|
||||||
|
|
||||||
##### How to use this driver ##### |
|
||||||
============================================================================== |
|
||||||
[..]
|
|
||||||
This driver provides functions and macros to configure and program the FLASH
|
|
||||||
memory of all STM32F1xx devices. |
|
||||||
|
|
||||||
(#) FLASH Memory I/O Programming functions: this group includes all needed |
|
||||||
functions to erase and program the main memory: |
|
||||||
(++) Lock and Unlock the FLASH interface |
|
||||||
(++) Erase function: Erase page, erase all pages |
|
||||||
(++) Program functions: half word, word and doubleword |
|
||||||
(#) FLASH Option Bytes Programming functions: this group includes all needed |
|
||||||
functions to manage the Option Bytes: |
|
||||||
(++) Lock and Unlock the Option Bytes |
|
||||||
(++) Set/Reset the write protection |
|
||||||
(++) Set the Read protection Level |
|
||||||
(++) Program the user Option Bytes |
|
||||||
(++) Launch the Option Bytes loader |
|
||||||
(++) Erase Option Bytes |
|
||||||
(++) Program the data Option Bytes |
|
||||||
(++) Get the Write protection. |
|
||||||
(++) Get the user option bytes. |
|
||||||
|
|
||||||
(#) Interrupts and flags management functions : this group
|
|
||||||
includes all needed functions to: |
|
||||||
(++) Handle FLASH interrupts |
|
||||||
(++) Wait for last FLASH operation according to its status |
|
||||||
(++) Get error flag status |
|
||||||
|
|
||||||
[..] In addition to these function, this driver includes a set of macros allowing |
|
||||||
to handle the following operations: |
|
||||||
|
|
||||||
(+) Set/Get the latency |
|
||||||
(+) Enable/Disable the prefetch buffer |
|
||||||
(+) Enable/Disable the half cycle access |
|
||||||
(+) Enable/Disable the FLASH interrupts |
|
||||||
(+) Monitor the FLASH flags status |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef HAL_FLASH_MODULE_ENABLED |
|
||||||
|
|
||||||
/** @defgroup FLASH FLASH
|
|
||||||
* @brief FLASH HAL module driver |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/ |
|
||||||
/* Private define ------------------------------------------------------------*/ |
|
||||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private macro ---------------------------- ---------------------------------*/ |
|
||||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/* Variables used for Erase pages under interruption*/ |
|
||||||
FLASH_ProcessTypeDef pFlash; |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private function prototypes -----------------------------------------------*/ |
|
||||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); |
|
||||||
static void FLASH_SetErrorCode(void); |
|
||||||
extern void FLASH_PageErase(uint32_t PageAddress); |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Exported functions ---------------------------------------------------------*/ |
|
||||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
|
||||||
* @brief Programming operation functions
|
|
||||||
* |
|
||||||
@verbatim
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Program halfword, word or double word at a specified address |
|
||||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface |
|
||||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface |
|
||||||
* |
|
||||||
* @note If an erase and a program operations are requested simultaneously,
|
|
||||||
* the erase operation is performed before the program one. |
|
||||||
*
|
|
||||||
* @note FLASH should be previously erased before new programmation (only exception to this
|
|
||||||
* is when 0x0000 is programmed) |
|
||||||
* |
|
||||||
* @param TypeProgram: Indicate the way to program at a specified address. |
|
||||||
* This parameter can be a value of @ref FLASH_Type_Program |
|
||||||
* @param Address: Specifies the address to be programmed. |
|
||||||
* @param Data: Specifies the data to be programmed |
|
||||||
*
|
|
||||||
* @retval HAL_StatusTypeDef HAL Status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) |
|
||||||
{ |
|
||||||
HAL_StatusTypeDef status = HAL_ERROR; |
|
||||||
uint8_t index = 0; |
|
||||||
uint8_t nbiterations = 0; |
|
||||||
|
|
||||||
/* Process Locked */ |
|
||||||
__HAL_LOCK(&pFlash); |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); |
|
||||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
if(Address <= FLASH_BANK1_END) |
|
||||||
{ |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
/* Wait for last operation to be completed */ |
|
||||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Wait for last operation to be completed */ |
|
||||||
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); |
|
||||||
} |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
if(status == HAL_OK) |
|
||||||
{ |
|
||||||
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) |
|
||||||
{ |
|
||||||
/* Program halfword (16-bit) at a specified address. */ |
|
||||||
nbiterations = 1U; |
|
||||||
} |
|
||||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) |
|
||||||
{ |
|
||||||
/* Program word (32-bit = 2*16-bit) at a specified address. */ |
|
||||||
nbiterations = 2U; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Program double word (64-bit = 4*16-bit) at a specified address. */ |
|
||||||
nbiterations = 4U; |
|
||||||
} |
|
||||||
|
|
||||||
for (index = 0U; index < nbiterations; index++) |
|
||||||
{ |
|
||||||
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
if(Address <= FLASH_BANK1_END) |
|
||||||
{ |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
/* Wait for last operation to be completed */ |
|
||||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
|
||||||
|
|
||||||
/* If the program operation is completed, disable the PG Bit */ |
|
||||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG); |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Wait for last operation to be completed */ |
|
||||||
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); |
|
||||||
|
|
||||||
/* If the program operation is completed, disable the PG Bit */ |
|
||||||
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); |
|
||||||
} |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
/* In case of error, stop programation procedure */ |
|
||||||
if (status != HAL_OK) |
|
||||||
{ |
|
||||||
break; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(&pFlash); |
|
||||||
|
|
||||||
return status; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Program halfword, word or double word at a specified address with interrupt enabled. |
|
||||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface |
|
||||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface |
|
||||||
* |
|
||||||
* @note If an erase and a program operations are requested simultaneously,
|
|
||||||
* the erase operation is performed before the program one. |
|
||||||
* |
|
||||||
* @param TypeProgram: Indicate the way to program at a specified address. |
|
||||||
* This parameter can be a value of @ref FLASH_Type_Program |
|
||||||
* @param Address: Specifies the address to be programmed. |
|
||||||
* @param Data: Specifies the data to be programmed |
|
||||||
*
|
|
||||||
* @retval HAL_StatusTypeDef HAL Status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) |
|
||||||
{ |
|
||||||
HAL_StatusTypeDef status = HAL_OK; |
|
||||||
|
|
||||||
/* Process Locked */ |
|
||||||
__HAL_LOCK(&pFlash); |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); |
|
||||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
/* If procedure already ongoing, reject the next one */ |
|
||||||
if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
if(Address <= FLASH_BANK1_END) |
|
||||||
{ |
|
||||||
/* Enable End of FLASH Operation and Error source interrupts */ |
|
||||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1); |
|
||||||
|
|
||||||
}else |
|
||||||
{ |
|
||||||
/* Enable End of FLASH Operation and Error source interrupts */ |
|
||||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); |
|
||||||
} |
|
||||||
#else |
|
||||||
/* Enable End of FLASH Operation and Error source interrupts */ |
|
||||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
pFlash.Address = Address; |
|
||||||
pFlash.Data = Data; |
|
||||||
|
|
||||||
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) |
|
||||||
{ |
|
||||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; |
|
||||||
/* Program halfword (16-bit) at a specified address. */ |
|
||||||
pFlash.DataRemaining = 1U; |
|
||||||
} |
|
||||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) |
|
||||||
{ |
|
||||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; |
|
||||||
/* Program word (32-bit : 2*16-bit) at a specified address. */ |
|
||||||
pFlash.DataRemaining = 2U; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; |
|
||||||
/* Program double word (64-bit : 4*16-bit) at a specified address. */ |
|
||||||
pFlash.DataRemaining = 4U; |
|
||||||
} |
|
||||||
|
|
||||||
/* Program halfword (16-bit) at a specified address. */ |
|
||||||
FLASH_Program_HalfWord(Address, (uint16_t)Data); |
|
||||||
|
|
||||||
return status; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function handles FLASH interrupt request. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_FLASH_IRQHandler(void) |
|
||||||
{ |
|
||||||
uint32_t addresstmp = 0U; |
|
||||||
|
|
||||||
/* Check FLASH operation error flags */ |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \
|
|
||||||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))) |
|
||||||
#else |
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
{ |
|
||||||
/* Return the faulty address */ |
|
||||||
addresstmp = pFlash.Address; |
|
||||||
/* Reset address */ |
|
||||||
pFlash.Address = 0xFFFFFFFFU; |
|
||||||
|
|
||||||
/* Save the Error code */ |
|
||||||
FLASH_SetErrorCode(); |
|
||||||
|
|
||||||
/* FLASH error interrupt user callback */ |
|
||||||
HAL_FLASH_OperationErrorCallback(addresstmp); |
|
||||||
|
|
||||||
/* Stop the procedure ongoing */ |
|
||||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
|
||||||
} |
|
||||||
|
|
||||||
/* Check FLASH End of Operation flag */ |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) |
|
||||||
{ |
|
||||||
/* Clear FLASH End of Operation pending bit */ |
|
||||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1); |
|
||||||
#else |
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) |
|
||||||
{ |
|
||||||
/* Clear FLASH End of Operation pending bit */ |
|
||||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
/* Process can continue only if no error detected */ |
|
||||||
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) |
|
||||||
{ |
|
||||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) |
|
||||||
{ |
|
||||||
/* Nb of pages to erased can be decreased */ |
|
||||||
pFlash.DataRemaining--; |
|
||||||
|
|
||||||
/* Check if there are still pages to erase */ |
|
||||||
if(pFlash.DataRemaining != 0U) |
|
||||||
{ |
|
||||||
addresstmp = pFlash.Address; |
|
||||||
/*Indicate user which sector has been erased */ |
|
||||||
HAL_FLASH_EndOfOperationCallback(addresstmp); |
|
||||||
|
|
||||||
/*Increment sector number*/ |
|
||||||
addresstmp = pFlash.Address + FLASH_PAGE_SIZE; |
|
||||||
pFlash.Address = addresstmp; |
|
||||||
|
|
||||||
/* If the erase operation is completed, disable the PER Bit */ |
|
||||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PER); |
|
||||||
|
|
||||||
FLASH_PageErase(addresstmp); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* No more pages to Erase, user callback can be called. */ |
|
||||||
/* Reset Sector and stop Erase pages procedure */ |
|
||||||
pFlash.Address = addresstmp = 0xFFFFFFFFU; |
|
||||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
|
||||||
/* FLASH EOP interrupt user callback */ |
|
||||||
HAL_FLASH_EndOfOperationCallback(addresstmp); |
|
||||||
} |
|
||||||
} |
|
||||||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) |
|
||||||
{ |
|
||||||
/* Operation is completed, disable the MER Bit */ |
|
||||||
CLEAR_BIT(FLASH->CR, FLASH_CR_MER); |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
/* Stop Mass Erase procedure if no pending mass erase on other bank */ |
|
||||||
if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) |
|
||||||
{ |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
/* MassErase ended. Return the selected bank */ |
|
||||||
/* FLASH EOP interrupt user callback */ |
|
||||||
HAL_FLASH_EndOfOperationCallback(0U); |
|
||||||
|
|
||||||
/* Stop Mass Erase procedure*/ |
|
||||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
|
||||||
} |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
} |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Nb of 16-bit data to program can be decreased */ |
|
||||||
pFlash.DataRemaining--; |
|
||||||
|
|
||||||
/* Check if there are still 16-bit data to program */ |
|
||||||
if(pFlash.DataRemaining != 0U) |
|
||||||
{ |
|
||||||
/* Increment address to 16-bit */ |
|
||||||
pFlash.Address += 2U; |
|
||||||
addresstmp = pFlash.Address; |
|
||||||
|
|
||||||
/* Shift to have next 16-bit data */ |
|
||||||
pFlash.Data = (pFlash.Data >> 16U); |
|
||||||
|
|
||||||
/* Operation is completed, disable the PG Bit */ |
|
||||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG); |
|
||||||
|
|
||||||
/*Program halfword (16-bit) at a specified address.*/ |
|
||||||
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Program ended. Return the selected address */ |
|
||||||
/* FLASH EOP interrupt user callback */ |
|
||||||
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) |
|
||||||
{ |
|
||||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address); |
|
||||||
} |
|
||||||
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) |
|
||||||
{ |
|
||||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); |
|
||||||
} |
|
||||||
else
|
|
||||||
{ |
|
||||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); |
|
||||||
} |
|
||||||
|
|
||||||
/* Reset Address and stop Program procedure */ |
|
||||||
pFlash.Address = 0xFFFFFFFFU; |
|
||||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
/* Check FLASH End of Operation flag */ |
|
||||||
if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2)) |
|
||||||
{ |
|
||||||
/* Clear FLASH End of Operation pending bit */ |
|
||||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); |
|
||||||
|
|
||||||
/* Process can continue only if no error detected */ |
|
||||||
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) |
|
||||||
{ |
|
||||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) |
|
||||||
{ |
|
||||||
/* Nb of pages to erased can be decreased */ |
|
||||||
pFlash.DataRemaining--; |
|
||||||
|
|
||||||
/* Check if there are still pages to erase*/ |
|
||||||
if(pFlash.DataRemaining != 0U) |
|
||||||
{ |
|
||||||
/* Indicate user which page address has been erased*/ |
|
||||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address); |
|
||||||
|
|
||||||
/* Increment page address to next page */ |
|
||||||
pFlash.Address += FLASH_PAGE_SIZE; |
|
||||||
addresstmp = pFlash.Address; |
|
||||||
|
|
||||||
/* Operation is completed, disable the PER Bit */ |
|
||||||
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); |
|
||||||
|
|
||||||
FLASH_PageErase(addresstmp); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/*No more pages to Erase*/ |
|
||||||
|
|
||||||
/*Reset Address and stop Erase pages procedure*/ |
|
||||||
pFlash.Address = 0xFFFFFFFFU; |
|
||||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
|
||||||
|
|
||||||
/* FLASH EOP interrupt user callback */ |
|
||||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address); |
|
||||||
} |
|
||||||
} |
|
||||||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) |
|
||||||
{ |
|
||||||
/* Operation is completed, disable the MER Bit */ |
|
||||||
CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); |
|
||||||
|
|
||||||
if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) |
|
||||||
{ |
|
||||||
/* MassErase ended. Return the selected bank*/ |
|
||||||
/* FLASH EOP interrupt user callback */ |
|
||||||
HAL_FLASH_EndOfOperationCallback(0U); |
|
||||||
|
|
||||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
|
||||||
} |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Nb of 16-bit data to program can be decreased */ |
|
||||||
pFlash.DataRemaining--; |
|
||||||
|
|
||||||
/* Check if there are still 16-bit data to program */ |
|
||||||
if(pFlash.DataRemaining != 0U) |
|
||||||
{ |
|
||||||
/* Increment address to 16-bit */ |
|
||||||
pFlash.Address += 2U; |
|
||||||
addresstmp = pFlash.Address; |
|
||||||
|
|
||||||
/* Shift to have next 16-bit data */ |
|
||||||
pFlash.Data = (pFlash.Data >> 16U); |
|
||||||
|
|
||||||
/* Operation is completed, disable the PG Bit */ |
|
||||||
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); |
|
||||||
|
|
||||||
/*Program halfword (16-bit) at a specified address.*/ |
|
||||||
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/*Program ended. Return the selected address*/ |
|
||||||
/* FLASH EOP interrupt user callback */ |
|
||||||
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) |
|
||||||
{ |
|
||||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address); |
|
||||||
} |
|
||||||
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) |
|
||||||
{ |
|
||||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U); |
|
||||||
} |
|
||||||
else
|
|
||||||
{ |
|
||||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U); |
|
||||||
} |
|
||||||
|
|
||||||
/* Reset Address and stop Program procedure*/ |
|
||||||
pFlash.Address = 0xFFFFFFFFU; |
|
||||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) |
|
||||||
{ |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
/* Operation is completed, disable the PG, PER and MER Bits for both bank */ |
|
||||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); |
|
||||||
CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER));
|
|
||||||
|
|
||||||
/* Disable End of FLASH Operation and Error source interrupts for both banks */ |
|
||||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); |
|
||||||
#else |
|
||||||
/* Operation is completed, disable the PG, PER and MER Bits */ |
|
||||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); |
|
||||||
|
|
||||||
/* Disable End of FLASH Operation and Error source interrupts */ |
|
||||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
/* Process Unlocked */ |
|
||||||
__HAL_UNLOCK(&pFlash); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief FLASH end of operation interrupt callback |
|
||||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure |
|
||||||
* - Mass Erase: No return value expected |
|
||||||
* - Pages Erase: Address of the page which has been erased
|
|
||||||
* (if 0xFFFFFFFF, it means that all the selected pages have been erased) |
|
||||||
* - Program: Address which was selected for data program |
|
||||||
* @retval none |
|
||||||
*/ |
|
||||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) |
|
||||||
{ |
|
||||||
/* Prevent unused argument(s) compilation warning */ |
|
||||||
UNUSED(ReturnValue); |
|
||||||
|
|
||||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
||||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file |
|
||||||
*/
|
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief FLASH operation error interrupt callback |
|
||||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure |
|
||||||
* - Mass Erase: No return value expected |
|
||||||
* - Pages Erase: Address of the page which returned an error |
|
||||||
* - Program: Address which was selected for data program |
|
||||||
* @retval none |
|
||||||
*/ |
|
||||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) |
|
||||||
{ |
|
||||||
/* Prevent unused argument(s) compilation warning */ |
|
||||||
UNUSED(ReturnValue); |
|
||||||
|
|
||||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
||||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file |
|
||||||
*/
|
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
|
||||||
* @brief management functions
|
|
||||||
* |
|
||||||
@verbatim
|
|
||||||
=============================================================================== |
|
||||||
##### Peripheral Control functions ##### |
|
||||||
===============================================================================
|
|
||||||
[..] |
|
||||||
This subsection provides a set of functions allowing to control the FLASH
|
|
||||||
memory operations. |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Unlock the FLASH control register access |
|
||||||
* @retval HAL Status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void) |
|
||||||
{ |
|
||||||
HAL_StatusTypeDef status = HAL_OK; |
|
||||||
|
|
||||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) |
|
||||||
{ |
|
||||||
/* Authorize the FLASH Registers access */ |
|
||||||
WRITE_REG(FLASH->KEYR, FLASH_KEY1); |
|
||||||
WRITE_REG(FLASH->KEYR, FLASH_KEY2); |
|
||||||
|
|
||||||
/* Verify Flash is unlocked */ |
|
||||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) |
|
||||||
{ |
|
||||||
status = HAL_ERROR; |
|
||||||
} |
|
||||||
} |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) |
|
||||||
{ |
|
||||||
/* Authorize the FLASH BANK2 Registers access */ |
|
||||||
WRITE_REG(FLASH->KEYR2, FLASH_KEY1); |
|
||||||
WRITE_REG(FLASH->KEYR2, FLASH_KEY2); |
|
||||||
|
|
||||||
/* Verify Flash BANK2 is unlocked */ |
|
||||||
if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) |
|
||||||
{ |
|
||||||
status = HAL_ERROR; |
|
||||||
} |
|
||||||
} |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
return status; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Locks the FLASH control register access |
|
||||||
* @retval HAL Status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_FLASH_Lock(void) |
|
||||||
{ |
|
||||||
/* Set the LOCK Bit to lock the FLASH Registers access */ |
|
||||||
SET_BIT(FLASH->CR, FLASH_CR_LOCK); |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
/* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ |
|
||||||
SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); |
|
||||||
|
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
return HAL_OK;
|
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Unlock the FLASH Option Control Registers access. |
|
||||||
* @retval HAL Status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) |
|
||||||
{ |
|
||||||
if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) |
|
||||||
{ |
|
||||||
/* Authorizes the Option Byte register programming */ |
|
||||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); |
|
||||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
}
|
|
||||||
|
|
||||||
return HAL_OK;
|
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Lock the FLASH Option Control Registers access. |
|
||||||
* @retval HAL Status
|
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) |
|
||||||
{ |
|
||||||
/* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ |
|
||||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); |
|
||||||
|
|
||||||
return HAL_OK;
|
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Launch the option byte loading. |
|
||||||
* @note This function will reset automatically the MCU. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_FLASH_OB_Launch(void) |
|
||||||
{ |
|
||||||
/* Initiates a system reset request to launch the option byte loading */ |
|
||||||
HAL_NVIC_SystemReset(); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
|
|
||||||
* @brief Peripheral errors functions
|
|
||||||
* |
|
||||||
@verbatim
|
|
||||||
=============================================================================== |
|
||||||
##### Peripheral Errors functions ##### |
|
||||||
===============================================================================
|
|
||||||
[..] |
|
||||||
This subsection permit to get in run-time errors of the FLASH peripheral. |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the specific FLASH error flag. |
|
||||||
* @retval FLASH_ErrorCode The returned value can be: |
|
||||||
* @ref FLASH_Error_Codes |
|
||||||
*/ |
|
||||||
uint32_t HAL_FLASH_GetError(void) |
|
||||||
{ |
|
||||||
return pFlash.ErrorCode; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @addtogroup FLASH_Private_Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Program a half-word (16-bit) at a specified address. |
|
||||||
* @param Address specify the address to be programmed. |
|
||||||
* @param Data specify the data to be programmed. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) |
|
||||||
{ |
|
||||||
/* Clean the error context */ |
|
||||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
if(Address <= FLASH_BANK1_END) |
|
||||||
{ |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
/* Proceed to program the new data */ |
|
||||||
SET_BIT(FLASH->CR, FLASH_CR_PG); |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Proceed to program the new data */ |
|
||||||
SET_BIT(FLASH->CR2, FLASH_CR2_PG); |
|
||||||
} |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
/* Write data in the address */ |
|
||||||
*(__IO uint16_t*)Address = Data; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Wait for a FLASH operation to complete. |
|
||||||
* @param Timeout maximum flash operation timeout |
|
||||||
* @retval HAL Status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) |
|
||||||
{ |
|
||||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
|
||||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error |
|
||||||
flag will be set */ |
|
||||||
|
|
||||||
uint32_t tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
|
||||||
{
|
|
||||||
if (Timeout != HAL_MAX_DELAY) |
|
||||||
{ |
|
||||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* Check FLASH End of Operation flag */ |
|
||||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) |
|
||||||
{ |
|
||||||
/* Clear FLASH End of Operation pending bit */ |
|
||||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); |
|
||||||
} |
|
||||||
|
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
|
||||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
|
||||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) |
|
||||||
{ |
|
||||||
/*Save the error code*/ |
|
||||||
FLASH_SetErrorCode(); |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* There is no error flag set */ |
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
/**
|
|
||||||
* @brief Wait for a FLASH BANK2 operation to complete. |
|
||||||
* @param Timeout maximum flash operation timeout |
|
||||||
* @retval HAL_StatusTypeDef HAL Status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) |
|
||||||
{
|
|
||||||
/* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
|
|
||||||
Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error |
|
||||||
flag will be set */ |
|
||||||
|
|
||||||
uint32_t tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2))
|
|
||||||
{
|
|
||||||
if (Timeout != HAL_MAX_DELAY) |
|
||||||
{ |
|
||||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* Check FLASH End of Operation flag */ |
|
||||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) |
|
||||||
{ |
|
||||||
/* Clear FLASH End of Operation pending bit */ |
|
||||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); |
|
||||||
} |
|
||||||
|
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) |
|
||||||
{ |
|
||||||
/*Save the error code*/ |
|
||||||
FLASH_SetErrorCode(); |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* If there is an error flag set */ |
|
||||||
return HAL_OK; |
|
||||||
|
|
||||||
} |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set the specific FLASH error flag. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
static void FLASH_SetErrorCode(void) |
|
||||||
{ |
|
||||||
uint32_t flags = 0U; |
|
||||||
|
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) |
|
||||||
#else |
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
{ |
|
||||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; |
|
||||||
#else |
|
||||||
flags |= FLASH_FLAG_WRPERR; |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
} |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) |
|
||||||
#else |
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
{ |
|
||||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; |
|
||||||
#if defined(FLASH_BANK2_END) |
|
||||||
flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; |
|
||||||
#else |
|
||||||
flags |= FLASH_FLAG_PGERR; |
|
||||||
#endif /* FLASH_BANK2_END */ |
|
||||||
} |
|
||||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) |
|
||||||
{ |
|
||||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; |
|
||||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); |
|
||||||
} |
|
||||||
|
|
||||||
/* Clear FLASH error pending bits */ |
|
||||||
__HAL_FLASH_CLEAR_FLAG(flags); |
|
||||||
}
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* HAL_FLASH_MODULE_ENABLED */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,587 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_gpio.c |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief GPIO HAL module driver. |
|
||||||
* This file provides firmware functions to manage the following |
|
||||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral: |
|
||||||
* + Initialization and de-initialization functions |
|
||||||
* + IO operation functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
============================================================================== |
|
||||||
##### GPIO Peripheral features ##### |
|
||||||
============================================================================== |
|
||||||
[..] |
|
||||||
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each |
|
||||||
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software |
|
||||||
in several modes: |
|
||||||
(+) Input mode |
|
||||||
(+) Analog mode |
|
||||||
(+) Output mode |
|
||||||
(+) Alternate function mode |
|
||||||
(+) External interrupt/event lines |
|
||||||
|
|
||||||
[..] |
|
||||||
During and just after reset, the alternate functions and external interrupt |
|
||||||
lines are not active and the I/O ports are configured in input floating mode. |
|
||||||
|
|
||||||
[..] |
|
||||||
All GPIO pins have weak internal pull-up and pull-down resistors, which can be |
|
||||||
activated or not. |
|
||||||
|
|
||||||
[..] |
|
||||||
In Output or Alternate mode, each IO can be configured on open-drain or push-pull |
|
||||||
type and the IO speed can be selected depending on the VDD value. |
|
||||||
|
|
||||||
[..] |
|
||||||
All ports have external interrupt/event capability. To use external interrupt |
|
||||||
lines, the port must be configured in input mode. All available GPIO pins are |
|
||||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. |
|
||||||
|
|
||||||
[..] |
|
||||||
The external interrupt/event controller consists of up to 20 edge detectors in connectivity |
|
||||||
line devices, or 19 edge detectors in other devices for generating event/interrupt requests. |
|
||||||
Each input line can be independently configured to select the type (event or interrupt) and |
|
||||||
the corresponding trigger event (rising or falling or both). Each line can also masked |
|
||||||
independently. A pending register maintains the status line of the interrupt requests |
|
||||||
|
|
||||||
##### How to use this driver ##### |
|
||||||
============================================================================== |
|
||||||
[..] |
|
||||||
(#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). |
|
||||||
|
|
||||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init(). |
|
||||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure |
|
||||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef |
|
||||||
structure. |
|
||||||
(++) In case of Output or alternate function mode selection: the speed is |
|
||||||
configured through "Speed" member from GPIO_InitTypeDef structure |
|
||||||
(++) Analog mode is required when a pin is to be used as ADC channel |
|
||||||
or DAC output. |
|
||||||
(++) In case of external interrupt/event selection the "Mode" member from |
|
||||||
GPIO_InitTypeDef structure select the type (interrupt or event) and |
|
||||||
the corresponding trigger event (rising or falling or both). |
|
||||||
|
|
||||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority |
|
||||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using |
|
||||||
HAL_NVIC_EnableIRQ(). |
|
||||||
|
|
||||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). |
|
||||||
|
|
||||||
(#) To set/reset the level of a pin configured in output mode use |
|
||||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). |
|
||||||
|
|
||||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). |
|
||||||
|
|
||||||
(#) During and just after reset, the alternate functions are not |
|
||||||
active and the GPIO pins are configured in input floating mode (except JTAG |
|
||||||
pins). |
|
||||||
|
|
||||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose |
|
||||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has |
|
||||||
priority over the GPIO function. |
|
||||||
|
|
||||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as |
|
||||||
general purpose PD0 and PD1, respectively, when the HSE oscillator is off. |
|
||||||
The HSE has priority over the GPIO function. |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIO GPIO
|
|
||||||
* @brief GPIO HAL module driver |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef HAL_GPIO_MODULE_ENABLED |
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/ |
|
||||||
/* Private define ------------------------------------------------------------*/ |
|
||||||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
#define GPIO_MODE 0x00000003u |
|
||||||
#define EXTI_MODE 0x10000000u |
|
||||||
#define GPIO_MODE_IT 0x00010000u |
|
||||||
#define GPIO_MODE_EVT 0x00020000u |
|
||||||
#define RISING_EDGE 0x00100000u |
|
||||||
#define FALLING_EDGE 0x00200000u |
|
||||||
#define GPIO_OUTPUT_TYPE 0x00000010u |
|
||||||
|
|
||||||
#define GPIO_NUMBER 16u |
|
||||||
|
|
||||||
/* Definitions for bit manipulation of CRL and CRH register */ |
|
||||||
#define GPIO_CR_MODE_INPUT 0x00000000u /*!< 00: Input mode (reset state) */ |
|
||||||
#define GPIO_CR_CNF_ANALOG 0x00000000u /*!< 00: Analog mode */ |
|
||||||
#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004u /*!< 01: Floating input (reset state) */ |
|
||||||
#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008u /*!< 10: Input with pull-up / pull-down */ |
|
||||||
#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000u /*!< 00: General purpose output push-pull */ |
|
||||||
#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004u /*!< 01: General purpose output Open-drain */ |
|
||||||
#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008u /*!< 10: Alternate function output Push-pull */ |
|
||||||
#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000Cu /*!< 11: Alternate function output Open-drain */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
/* Private macro -------------------------------------------------------------*/ |
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/* Private function prototypes -----------------------------------------------*/ |
|
||||||
/* Private functions ---------------------------------------------------------*/ |
|
||||||
/* Exported functions --------------------------------------------------------*/ |
|
||||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @brief Initialization and Configuration functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### Initialization and de-initialization functions ##### |
|
||||||
=============================================================================== |
|
||||||
[..] |
|
||||||
This section provides functions allowing to initialize and de-initialize the GPIOs |
|
||||||
to be ready for use. |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. |
|
||||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
|
||||||
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains |
|
||||||
* the configuration information for the specified GPIO peripheral. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) |
|
||||||
{ |
|
||||||
uint32_t position = 0x00u; |
|
||||||
uint32_t ioposition; |
|
||||||
uint32_t iocurrent; |
|
||||||
uint32_t temp; |
|
||||||
uint32_t config = 0x00u; |
|
||||||
__IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ |
|
||||||
uint32_t registeroffset; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); |
|
||||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); |
|
||||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); |
|
||||||
|
|
||||||
/* Configure the port pins */ |
|
||||||
while (((GPIO_Init->Pin) >> position) != 0x00u) |
|
||||||
{ |
|
||||||
/* Get the IO position */ |
|
||||||
ioposition = (0x01uL << position); |
|
||||||
|
|
||||||
/* Get the current IO position */ |
|
||||||
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; |
|
||||||
|
|
||||||
if (iocurrent == ioposition) |
|
||||||
{ |
|
||||||
/* Check the Alternate function parameters */ |
|
||||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); |
|
||||||
|
|
||||||
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ |
|
||||||
switch (GPIO_Init->Mode) |
|
||||||
{ |
|
||||||
/* If we are configuring the pin in OUTPUT push-pull mode */ |
|
||||||
case GPIO_MODE_OUTPUT_PP: |
|
||||||
/* Check the GPIO speed parameter */ |
|
||||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
|
||||||
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; |
|
||||||
break; |
|
||||||
|
|
||||||
/* If we are configuring the pin in OUTPUT open-drain mode */ |
|
||||||
case GPIO_MODE_OUTPUT_OD: |
|
||||||
/* Check the GPIO speed parameter */ |
|
||||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
|
||||||
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; |
|
||||||
break; |
|
||||||
|
|
||||||
/* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ |
|
||||||
case GPIO_MODE_AF_PP: |
|
||||||
/* Check the GPIO speed parameter */ |
|
||||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
|
||||||
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; |
|
||||||
break; |
|
||||||
|
|
||||||
/* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ |
|
||||||
case GPIO_MODE_AF_OD: |
|
||||||
/* Check the GPIO speed parameter */ |
|
||||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
|
||||||
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; |
|
||||||
break; |
|
||||||
|
|
||||||
/* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ |
|
||||||
case GPIO_MODE_INPUT: |
|
||||||
case GPIO_MODE_IT_RISING: |
|
||||||
case GPIO_MODE_IT_FALLING: |
|
||||||
case GPIO_MODE_IT_RISING_FALLING: |
|
||||||
case GPIO_MODE_EVT_RISING: |
|
||||||
case GPIO_MODE_EVT_FALLING: |
|
||||||
case GPIO_MODE_EVT_RISING_FALLING: |
|
||||||
/* Check the GPIO pull parameter */ |
|
||||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); |
|
||||||
if (GPIO_Init->Pull == GPIO_NOPULL) |
|
||||||
{ |
|
||||||
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; |
|
||||||
} |
|
||||||
else if (GPIO_Init->Pull == GPIO_PULLUP) |
|
||||||
{ |
|
||||||
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; |
|
||||||
|
|
||||||
/* Set the corresponding ODR bit */ |
|
||||||
GPIOx->BSRR = ioposition; |
|
||||||
} |
|
||||||
else /* GPIO_PULLDOWN */ |
|
||||||
{ |
|
||||||
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; |
|
||||||
|
|
||||||
/* Reset the corresponding ODR bit */ |
|
||||||
GPIOx->BRR = ioposition; |
|
||||||
} |
|
||||||
break; |
|
||||||
|
|
||||||
/* If we are configuring the pin in INPUT analog mode */ |
|
||||||
case GPIO_MODE_ANALOG: |
|
||||||
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; |
|
||||||
break; |
|
||||||
|
|
||||||
/* Parameters are checked with assert_param */ |
|
||||||
default: |
|
||||||
break; |
|
||||||
} |
|
||||||
|
|
||||||
/* Check if the current bit belongs to first half or last half of the pin count number
|
|
||||||
in order to address CRH or CRL register*/ |
|
||||||
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; |
|
||||||
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); |
|
||||||
|
|
||||||
/* Apply the new configuration of the pin to the register */ |
|
||||||
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); |
|
||||||
|
|
||||||
/*--------------------- EXTI Mode Configuration ------------------------*/ |
|
||||||
/* Configure the External Interrupt or event for the current IO */ |
|
||||||
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) |
|
||||||
{ |
|
||||||
/* Enable AFIO Clock */ |
|
||||||
__HAL_RCC_AFIO_CLK_ENABLE(); |
|
||||||
temp = AFIO->EXTICR[position >> 2u]; |
|
||||||
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); |
|
||||||
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); |
|
||||||
AFIO->EXTICR[position >> 2u] = temp; |
|
||||||
|
|
||||||
|
|
||||||
/* Configure the interrupt mask */ |
|
||||||
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) |
|
||||||
{ |
|
||||||
SET_BIT(EXTI->IMR, iocurrent); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
CLEAR_BIT(EXTI->IMR, iocurrent); |
|
||||||
} |
|
||||||
|
|
||||||
/* Configure the event mask */ |
|
||||||
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) |
|
||||||
{ |
|
||||||
SET_BIT(EXTI->EMR, iocurrent); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
CLEAR_BIT(EXTI->EMR, iocurrent); |
|
||||||
} |
|
||||||
|
|
||||||
/* Enable or disable the rising trigger */ |
|
||||||
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) |
|
||||||
{ |
|
||||||
SET_BIT(EXTI->RTSR, iocurrent); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
CLEAR_BIT(EXTI->RTSR, iocurrent); |
|
||||||
} |
|
||||||
|
|
||||||
/* Enable or disable the falling trigger */ |
|
||||||
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) |
|
||||||
{ |
|
||||||
SET_BIT(EXTI->FTSR, iocurrent); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
CLEAR_BIT(EXTI->FTSR, iocurrent); |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
position++; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values. |
|
||||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
|
||||||
* @param GPIO_Pin: specifies the port bit to be written. |
|
||||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) |
|
||||||
{ |
|
||||||
uint32_t position = 0x00u; |
|
||||||
uint32_t iocurrent; |
|
||||||
uint32_t tmp; |
|
||||||
__IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ |
|
||||||
uint32_t registeroffset; |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); |
|
||||||
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
|
||||||
|
|
||||||
/* Configure the port pins */ |
|
||||||
while ((GPIO_Pin >> position) != 0u) |
|
||||||
{ |
|
||||||
/* Get current io position */ |
|
||||||
iocurrent = (GPIO_Pin) & (1uL << position); |
|
||||||
|
|
||||||
if (iocurrent) |
|
||||||
{ |
|
||||||
/*------------------------- EXTI Mode Configuration --------------------*/ |
|
||||||
/* Clear the External Interrupt or Event for the current IO */ |
|
||||||
|
|
||||||
tmp = AFIO->EXTICR[position >> 2u]; |
|
||||||
tmp &= 0x0FuL << (4u * (position & 0x03u)); |
|
||||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) |
|
||||||
{ |
|
||||||
tmp = 0x0FuL << (4u * (position & 0x03u)); |
|
||||||
CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp); |
|
||||||
|
|
||||||
/* Clear EXTI line configuration */ |
|
||||||
CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); |
|
||||||
CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); |
|
||||||
|
|
||||||
/* Clear Rising Falling edge configuration */ |
|
||||||
CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); |
|
||||||
CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); |
|
||||||
} |
|
||||||
/*------------------------- GPIO Mode Configuration --------------------*/ |
|
||||||
/* Check if the current bit belongs to first half or last half of the pin count number
|
|
||||||
in order to address CRH or CRL register */ |
|
||||||
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; |
|
||||||
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); |
|
||||||
|
|
||||||
/* CRL/CRH default value is floating input(0x04) shifted to correct position */ |
|
||||||
MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset); |
|
||||||
|
|
||||||
/* ODR default value is 0 */ |
|
||||||
CLEAR_BIT(GPIOx->ODR, iocurrent); |
|
||||||
} |
|
||||||
|
|
||||||
position++; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
|
||||||
* @brief GPIO Read and Write |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### IO operation functions ##### |
|
||||||
=============================================================================== |
|
||||||
[..] |
|
||||||
This subsection provides a set of functions allowing to manage the GPIOs. |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Reads the specified input port pin. |
|
||||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
|
||||||
* @param GPIO_Pin: specifies the port bit to read. |
|
||||||
* This parameter can be GPIO_PIN_x where x can be (0..15). |
|
||||||
* @retval The input port pin value. |
|
||||||
*/ |
|
||||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) |
|
||||||
{ |
|
||||||
GPIO_PinState bitstatus; |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
|
||||||
|
|
||||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) |
|
||||||
{ |
|
||||||
bitstatus = GPIO_PIN_SET; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
bitstatus = GPIO_PIN_RESET; |
|
||||||
} |
|
||||||
return bitstatus; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Sets or clears the selected data port bit. |
|
||||||
* |
|
||||||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify |
|
||||||
* accesses. In this way, there is no risk of an IRQ occurring between |
|
||||||
* the read and the modify access. |
|
||||||
* |
|
||||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
|
||||||
* @param GPIO_Pin: specifies the port bit to be written. |
|
||||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15). |
|
||||||
* @param PinState: specifies the value to be written to the selected bit. |
|
||||||
* This parameter can be one of the GPIO_PinState enum values: |
|
||||||
* @arg GPIO_PIN_RESET: to clear the port pin |
|
||||||
* @arg GPIO_PIN_SET: to set the port pin |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
|
||||||
assert_param(IS_GPIO_PIN_ACTION(PinState)); |
|
||||||
|
|
||||||
if (PinState != GPIO_PIN_RESET) |
|
||||||
{ |
|
||||||
GPIOx->BSRR = GPIO_Pin; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Toggles the specified GPIO pin |
|
||||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
|
||||||
* @param GPIO_Pin: Specifies the pins to be toggled. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) |
|
||||||
{ |
|
||||||
uint32_t odr; |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
|
||||||
|
|
||||||
/* get current Ouput Data Register value */ |
|
||||||
odr = GPIOx->ODR; |
|
||||||
|
|
||||||
/* Set selected pins that were at low level, and reset ones that were high */ |
|
||||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Locks GPIO Pins configuration registers. |
|
||||||
* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence |
|
||||||
* has been applied on a port bit, it is no longer possible to modify the value of the port bit until |
|
||||||
* the next reset. |
|
||||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
|
||||||
* @param GPIO_Pin: specifies the port bit to be locked. |
|
||||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) |
|
||||||
{ |
|
||||||
__IO uint32_t tmp = GPIO_LCKR_LCKK; |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); |
|
||||||
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
|
||||||
|
|
||||||
/* Apply lock key write sequence */ |
|
||||||
SET_BIT(tmp, GPIO_Pin); |
|
||||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
|
||||||
GPIOx->LCKR = tmp; |
|
||||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ |
|
||||||
GPIOx->LCKR = GPIO_Pin; |
|
||||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
|
||||||
GPIOx->LCKR = tmp; |
|
||||||
/* Read LCKK register. This read is mandatory to complete key lock sequence */ |
|
||||||
tmp = GPIOx->LCKR; |
|
||||||
|
|
||||||
/* read again in order to confirm lock is active */ |
|
||||||
if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) |
|
||||||
{ |
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function handles EXTI interrupt request. |
|
||||||
* @param GPIO_Pin: Specifies the pins connected EXTI line |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) |
|
||||||
{ |
|
||||||
/* EXTI line interrupt detected */ |
|
||||||
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) |
|
||||||
{ |
|
||||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); |
|
||||||
HAL_GPIO_EXTI_Callback(GPIO_Pin); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief EXTI line detection callbacks. |
|
||||||
* @param GPIO_Pin: Specifies the pins connected EXTI line |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) |
|
||||||
{ |
|
||||||
/* Prevent unused argument(s) compilation warning */ |
|
||||||
UNUSED(GPIO_Pin); |
|
||||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
|
||||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file |
|
||||||
*/ |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* HAL_GPIO_MODULE_ENABLED */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,127 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_gpio_ex.c |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief GPIO Extension HAL module driver. |
|
||||||
* This file provides firmware functions to manage the following |
|
||||||
* functionalities of the General Purpose Input/Output (GPIO) extension peripheral. |
|
||||||
* + Extended features functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
============================================================================== |
|
||||||
##### GPIO Peripheral extension features ##### |
|
||||||
============================================================================== |
|
||||||
[..] GPIO module on STM32F1 family, manage also the AFIO register: |
|
||||||
(+) Possibility to use the EVENTOUT Cortex feature |
|
||||||
|
|
||||||
##### How to use this driver ##### |
|
||||||
============================================================================== |
|
||||||
[..] This driver provides functions to use EVENTOUT Cortex feature |
|
||||||
(#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() |
|
||||||
(#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() |
|
||||||
(#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIOEx GPIOEx
|
|
||||||
* @brief GPIO HAL module driver |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef HAL_GPIO_MODULE_ENABLED |
|
||||||
|
|
||||||
/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
|
|
||||||
* @brief Extended features functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
============================================================================== |
|
||||||
##### Extended features functions ##### |
|
||||||
============================================================================== |
|
||||||
[..] This section provides functions allowing to: |
|
||||||
(+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() |
|
||||||
(+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() |
|
||||||
(+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. |
|
||||||
* @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. |
|
||||||
* This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. |
|
||||||
* @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. |
|
||||||
* This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) |
|
||||||
{ |
|
||||||
/* Verify the parameters */ |
|
||||||
assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); |
|
||||||
assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); |
|
||||||
|
|
||||||
/* Apply the new configuration */ |
|
||||||
MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource)); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables the Event Output. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_GPIOEx_EnableEventout(void) |
|
||||||
{ |
|
||||||
SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables the Event Output. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_GPIOEx_DisableEventout(void) |
|
||||||
{ |
|
||||||
CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* HAL_GPIO_MODULE_ENABLED */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
@ -1,621 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_pwr.c |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief PWR HAL module driver. |
|
||||||
* |
|
||||||
* This file provides firmware functions to manage the following |
|
||||||
* functionalities of the Power Controller (PWR) peripheral: |
|
||||||
* + Initialization/de-initialization functions |
|
||||||
* + Peripheral Control functions
|
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR PWR
|
|
||||||
* @brief PWR HAL module driver |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef HAL_PWR_MODULE_ENABLED |
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/ |
|
||||||
/* Private define ------------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_Private_Constants PWR Private Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
#define PVD_MODE_IT 0x00010000U |
|
||||||
#define PVD_MODE_EVT 0x00020000U |
|
||||||
#define PVD_RISING_EDGE 0x00000001U |
|
||||||
#define PVD_FALLING_EDGE 0x00000002U |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup PWR_register_alias_address PWR Register alias address
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
/* ------------- PWR registers bit address in the alias region ---------------*/ |
|
||||||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) |
|
||||||
#define PWR_CR_OFFSET 0x00U |
|
||||||
#define PWR_CSR_OFFSET 0x04U |
|
||||||
#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) |
|
||||||
#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_CR_register_alias PWR CR Register alias address
|
|
||||||
* @{ |
|
||||||
*/
|
|
||||||
/* --- CR Register ---*/ |
|
||||||
/* Alias word address of LPSDSR bit */ |
|
||||||
#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos |
|
||||||
#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) |
|
||||||
|
|
||||||
/* Alias word address of DBP bit */ |
|
||||||
#define DBP_BIT_NUMBER PWR_CR_DBP_Pos |
|
||||||
#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) |
|
||||||
|
|
||||||
/* Alias word address of PVDE bit */ |
|
||||||
#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos |
|
||||||
#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* --- CSR Register ---*/ |
|
||||||
/* Alias word address of EWUP1 bit */ |
|
||||||
#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/* Private function prototypes -----------------------------------------------*/ |
|
||||||
/** @defgroup PWR_Private_Functions PWR Private Functions
|
|
||||||
* brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
static void PWR_OverloadWfe(void); |
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/ |
|
||||||
__NOINLINE |
|
||||||
static void PWR_OverloadWfe(void) |
|
||||||
{ |
|
||||||
__asm volatile( "wfe" ); |
|
||||||
__asm volatile( "nop" ); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
|
||||||
* @brief Initialization and de-initialization functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### Initialization and de-initialization functions ##### |
|
||||||
=============================================================================== |
|
||||||
[..] |
|
||||||
After reset, the backup domain (RTC registers, RTC backup data |
|
||||||
registers) is protected against possible unwanted |
|
||||||
write accesses. |
|
||||||
To enable access to the RTC Domain and RTC registers, proceed as follows: |
|
||||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the |
|
||||||
__HAL_RCC_PWR_CLK_ENABLE() macro. |
|
||||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_DeInit(void) |
|
||||||
{ |
|
||||||
__HAL_RCC_PWR_FORCE_RESET(); |
|
||||||
__HAL_RCC_PWR_RELEASE_RESET(); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables access to the backup domain (RTC registers, RTC |
|
||||||
* backup data registers ). |
|
||||||
* @note If the HSE divided by 128 is used as the RTC clock, the |
|
||||||
* Backup Domain Access should be kept enabled. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_EnableBkUpAccess(void) |
|
||||||
{ |
|
||||||
/* Enable access to RTC and backup registers */ |
|
||||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables access to the backup domain (RTC registers, RTC |
|
||||||
* backup data registers). |
|
||||||
* @note If the HSE divided by 128 is used as the RTC clock, the |
|
||||||
* Backup Domain Access should be kept enabled. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_DisableBkUpAccess(void) |
|
||||||
{ |
|
||||||
/* Disable access to RTC and backup registers */ |
|
||||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
|
||||||
* @brief Low Power modes configuration functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### Peripheral Control functions ##### |
|
||||||
=============================================================================== |
|
||||||
|
|
||||||
*** PVD configuration *** |
|
||||||
========================= |
|
||||||
[..] |
|
||||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a |
|
||||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). |
|
||||||
|
|
||||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower |
|
||||||
than the PVD threshold. This event is internally connected to the EXTI |
|
||||||
line16 and can generate an interrupt if enabled. This is done through |
|
||||||
__HAL_PVD_EXTI_ENABLE_IT() macro. |
|
||||||
(+) The PVD is stopped in Standby mode. |
|
||||||
|
|
||||||
*** WakeUp pin configuration *** |
|
||||||
================================ |
|
||||||
[..] |
|
||||||
(+) WakeUp pin is used to wake up the system from Standby mode. This pin is |
|
||||||
forced in input pull-down configuration and is active on rising edges. |
|
||||||
(+) There is one WakeUp pin: |
|
||||||
WakeUp Pin 1 on PA.00. |
|
||||||
|
|
||||||
[..] |
|
||||||
|
|
||||||
*** Low Power modes configuration *** |
|
||||||
===================================== |
|
||||||
[..] |
|
||||||
The device features 3 low-power modes: |
|
||||||
(+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
|
|
||||||
NVIC, SysTick, etc. are kept running |
|
||||||
(+) Stop mode: All clocks are stopped |
|
||||||
(+) Standby mode: 1.8V domain powered off |
|
||||||
|
|
||||||
|
|
||||||
*** Sleep mode *** |
|
||||||
================== |
|
||||||
[..] |
|
||||||
(+) Entry: |
|
||||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
|
||||||
functions with |
|
||||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
|
||||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
|
||||||
|
|
||||||
(+) Exit: |
|
||||||
(++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt |
|
||||||
controller (NVIC) can wake up the device from Sleep mode. |
|
||||||
(++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. |
|
||||||
(+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend) |
|
||||||
(+++) Any EXTI Line (Internal or External) configured in Event mode |
|
||||||
|
|
||||||
*** Stop mode *** |
|
||||||
================= |
|
||||||
[..] |
|
||||||
The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral |
|
||||||
clock gating. The voltage regulator can be configured either in normal or low-power mode. |
|
||||||
In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
|
|
||||||
oscillators are disabled. SRAM and register contents are preserved. |
|
||||||
In Stop mode, all I/O pins keep the same state as in Run mode. |
|
||||||
|
|
||||||
(+) Entry: |
|
||||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx ) |
|
||||||
function with: |
|
||||||
(++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. |
|
||||||
(++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. |
|
||||||
(++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction |
|
||||||
(++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction |
|
||||||
(+) Exit: |
|
||||||
(++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured |
|
||||||
(++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. |
|
||||||
|
|
||||||
*** Standby mode *** |
|
||||||
==================== |
|
||||||
[..] |
|
||||||
The Standby mode allows to achieve the lowest power consumption. It is based on the |
|
||||||
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
|
|
||||||
consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
|
|
||||||
switched off. SRAM and register contents are lost except for registers in the Backup domain
|
|
||||||
and Standby circuitry |
|
||||||
|
|
||||||
(+) Entry: |
|
||||||
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. |
|
||||||
(+) Exit: |
|
||||||
(++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
|
|
||||||
NRSTpin, IWDG Reset |
|
||||||
|
|
||||||
*** Auto-wakeup (AWU) from low-power mode *** |
|
||||||
============================================= |
|
||||||
[..] |
|
||||||
|
|
||||||
(+) The MCU can be woken up from low-power mode by an RTC Alarm event,
|
|
||||||
without depending on an external interrupt (Auto-wakeup mode). |
|
||||||
|
|
||||||
(+) RTC auto-wakeup (AWU) from the Stop and Standby modes |
|
||||||
|
|
||||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
|
||||||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. |
|
||||||
|
|
||||||
*** PWR Workarounds linked to Silicon Limitation *** |
|
||||||
==================================================== |
|
||||||
[..] |
|
||||||
Below the list of all silicon limitations known on STM32F1xx prouct. |
|
||||||
|
|
||||||
(#)Workarounds Implemented inside PWR HAL Driver |
|
||||||
(##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
|
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). |
|
||||||
* @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration |
|
||||||
* information for the PVD. |
|
||||||
* @note Refer to the electrical characteristics of your device datasheet for |
|
||||||
* more details about the voltage threshold corresponding to each |
|
||||||
* detection level. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); |
|
||||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); |
|
||||||
|
|
||||||
/* Set PLS[7:5] bits according to PVDLevel value */ |
|
||||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); |
|
||||||
|
|
||||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
|
||||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT(); |
|
||||||
__HAL_PWR_PVD_EXTI_DISABLE_IT(); |
|
||||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
|
||||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); |
|
||||||
|
|
||||||
/* Configure interrupt mode */ |
|
||||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) |
|
||||||
{ |
|
||||||
__HAL_PWR_PVD_EXTI_ENABLE_IT(); |
|
||||||
} |
|
||||||
|
|
||||||
/* Configure event mode */ |
|
||||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) |
|
||||||
{ |
|
||||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT(); |
|
||||||
} |
|
||||||
|
|
||||||
/* Configure the edge */ |
|
||||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) |
|
||||||
{ |
|
||||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); |
|
||||||
} |
|
||||||
|
|
||||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) |
|
||||||
{ |
|
||||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables the Power Voltage Detector(PVD). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_EnablePVD(void) |
|
||||||
{ |
|
||||||
/* Enable the power voltage detector */ |
|
||||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables the Power Voltage Detector(PVD). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_DisablePVD(void) |
|
||||||
{ |
|
||||||
/* Disable the power voltage detector */ |
|
||||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables the WakeUp PINx functionality. |
|
||||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg PWR_WAKEUP_PIN1 |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) |
|
||||||
{ |
|
||||||
/* Check the parameter */ |
|
||||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
|
||||||
/* Enable the EWUPx pin */ |
|
||||||
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables the WakeUp PINx functionality. |
|
||||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg PWR_WAKEUP_PIN1 |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) |
|
||||||
{ |
|
||||||
/* Check the parameter */ |
|
||||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
|
||||||
/* Disable the EWUPx pin */ |
|
||||||
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enters Sleep mode. |
|
||||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode. |
|
||||||
* @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software |
|
||||||
* @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. |
|
||||||
* When WFI entry is used, tick interrupt have to be disabled if not desired as
|
|
||||||
* the interrupt wake up source. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
|
||||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
/* No check on Regulator because parameter not used in SLEEP mode */ |
|
||||||
/* Prevent unused argument(s) compilation warning */ |
|
||||||
UNUSED(Regulator); |
|
||||||
|
|
||||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); |
|
||||||
|
|
||||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */ |
|
||||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
|
||||||
|
|
||||||
/* Select SLEEP mode entry -------------------------------------------------*/ |
|
||||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI) |
|
||||||
{ |
|
||||||
/* Request Wait For Interrupt */ |
|
||||||
__WFI(); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Request Wait For Event */ |
|
||||||
__SEV(); |
|
||||||
__WFE(); |
|
||||||
__WFE(); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enters Stop mode.
|
|
||||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode. |
|
||||||
* @note When exiting Stop mode by using an interrupt or a wakeup event, |
|
||||||
* HSI RC oscillator is selected as system clock. |
|
||||||
* @note When the voltage regulator operates in low power mode, an additional |
|
||||||
* startup delay is incurred when waking up from Stop mode.
|
|
||||||
* By keeping the internal regulator ON during Stop mode, the consumption |
|
||||||
* is higher although the startup time is reduced.
|
|
||||||
* @param Regulator: Specifies the regulator state in Stop mode. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON |
|
||||||
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON |
|
||||||
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction |
|
||||||
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_PWR_REGULATOR(Regulator)); |
|
||||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
|
||||||
|
|
||||||
/* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
|
|
||||||
CLEAR_BIT(PWR->CR, PWR_CR_PDDS); |
|
||||||
|
|
||||||
/* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ |
|
||||||
MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); |
|
||||||
|
|
||||||
/* Set SLEEPDEEP bit of Cortex System Control Register */ |
|
||||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
|
||||||
|
|
||||||
/* Select Stop mode entry --------------------------------------------------*/ |
|
||||||
if(STOPEntry == PWR_STOPENTRY_WFI) |
|
||||||
{ |
|
||||||
/* Request Wait For Interrupt */ |
|
||||||
__WFI(); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Request Wait For Event */ |
|
||||||
__SEV(); |
|
||||||
PWR_OverloadWfe(); /* WFE redefine locally */ |
|
||||||
PWR_OverloadWfe(); /* WFE redefine locally */ |
|
||||||
} |
|
||||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */ |
|
||||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enters Standby mode. |
|
||||||
* @note In Standby mode, all I/O pins are high impedance except for: |
|
||||||
* - Reset pad (still available)
|
|
||||||
* - TAMPER pin if configured for tamper or calibration out. |
|
||||||
* - WKUP pin (PA0) if enabled. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_EnterSTANDBYMode(void) |
|
||||||
{ |
|
||||||
/* Select Standby mode */ |
|
||||||
SET_BIT(PWR->CR, PWR_CR_PDDS); |
|
||||||
|
|
||||||
/* Set SLEEPDEEP bit of Cortex System Control Register */ |
|
||||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
|
||||||
|
|
||||||
/* This option is used to ensure that store operations are completed */ |
|
||||||
#if defined ( __CC_ARM) |
|
||||||
__force_stores(); |
|
||||||
#endif |
|
||||||
/* Request Wait For Interrupt */ |
|
||||||
__WFI(); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
|
||||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
|
||||||
* re-enters SLEEP mode when an interruption handling is over. |
|
||||||
* Setting this bit is useful when the processor is expected to run only on |
|
||||||
* interruptions handling.
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_EnableSleepOnExit(void) |
|
||||||
{ |
|
||||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */ |
|
||||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
|
||||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
|
||||||
* re-enters SLEEP mode when an interruption handling is over.
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_DisableSleepOnExit(void) |
|
||||||
{ |
|
||||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
|
||||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enables CORTEX M3 SEVONPEND bit.
|
|
||||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
|
||||||
* WFE to wake up when an interrupt moves from inactive to pended. |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_EnableSEVOnPend(void) |
|
||||||
{ |
|
||||||
/* Set SEVONPEND bit of Cortex System Control Register */ |
|
||||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disables CORTEX M3 SEVONPEND bit.
|
|
||||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
|
||||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_DisableSEVOnPend(void) |
|
||||||
{ |
|
||||||
/* Clear SEVONPEND bit of Cortex System Control Register */ |
|
||||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief This function handles the PWR PVD interrupt request. |
|
||||||
* @note This API should be called under the PVD_IRQHandler(). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_PWR_PVD_IRQHandler(void) |
|
||||||
{ |
|
||||||
/* Check PWR exti flag */ |
|
||||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) |
|
||||||
{ |
|
||||||
/* PWR PVD interrupt user callback */ |
|
||||||
HAL_PWR_PVDCallback(); |
|
||||||
|
|
||||||
/* Clear PWR Exti pending bit */ |
|
||||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG(); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief PWR PVD interrupt callback |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
__weak void HAL_PWR_PVDCallback(void) |
|
||||||
{ |
|
||||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
||||||
the HAL_PWR_PVDCallback could be implemented in the user file |
|
||||||
*/
|
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* HAL_PWR_MODULE_ENABLED */ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
File diff suppressed because it is too large
Load Diff
@ -1,863 +0,0 @@ |
|||||||
/**
|
|
||||||
****************************************************************************** |
|
||||||
* @file stm32f1xx_hal_rcc_ex.c |
|
||||||
* @author MCD Application Team |
|
||||||
* @brief Extended RCC HAL module driver. |
|
||||||
* This file provides firmware functions to manage the following |
|
||||||
* functionalities RCC extension peripheral: |
|
||||||
* + Extended Peripheral Control functions |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
* @attention |
|
||||||
* |
|
||||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
|
||||||
* All rights reserved.</center></h2> |
|
||||||
* |
|
||||||
* This software component is licensed by ST under BSD 3-Clause license, |
|
||||||
* the "License"; You may not use this file except in compliance with the |
|
||||||
* License. You may obtain a copy of the License at: |
|
||||||
* opensource.org/licenses/BSD-3-Clause |
|
||||||
* |
|
||||||
****************************************************************************** |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/ |
|
||||||
#include "stm32f1xx_hal.h" |
|
||||||
|
|
||||||
/** @addtogroup STM32F1xx_HAL_Driver
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifdef HAL_RCC_MODULE_ENABLED |
|
||||||
|
|
||||||
/** @defgroup RCCEx RCCEx
|
|
||||||
* @brief RCC Extension HAL module driver. |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/ |
|
||||||
/* Private define ------------------------------------------------------------*/ |
|
||||||
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/ |
|
||||||
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Private variables ---------------------------------------------------------*/ |
|
||||||
/* Private function prototypes -----------------------------------------------*/ |
|
||||||
/* Private functions ---------------------------------------------------------*/ |
|
||||||
|
|
||||||
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
|
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
|
|
||||||
* @brief Extended Peripheral Control functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### Extended Peripheral Control functions ##### |
|
||||||
=============================================================================== |
|
||||||
[..] |
|
||||||
This subsection provides a set of functions allowing to control the RCC Clocks |
|
||||||
frequencies. |
|
||||||
[..] |
|
||||||
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
|
||||||
select the RTC clock source; in this case the Backup domain will be reset in |
|
||||||
order to modify the RTC Clock source, as consequence RTC registers (including |
|
||||||
the backup registers) are set to their reset values. |
|
||||||
|
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the |
|
||||||
* RCC_PeriphCLKInitTypeDef. |
|
||||||
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that |
|
||||||
* contains the configuration information for the Extended Peripherals clocks(RTC clock). |
|
||||||
* |
|
||||||
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select |
|
||||||
* the RTC clock source; in this case the Backup domain will be reset in |
|
||||||
* order to modify the RTC Clock source, as consequence RTC registers (including |
|
||||||
* the backup registers) are set to their reset values. |
|
||||||
* |
|
||||||
* @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on |
|
||||||
* one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to |
|
||||||
* manually disable it. |
|
||||||
* |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
|
||||||
{ |
|
||||||
uint32_t tickstart = 0U, temp_reg = 0U; |
|
||||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
uint32_t pllactive = 0U; |
|
||||||
#endif /* STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
|
||||||
|
|
||||||
/*------------------------------- RTC/LCD Configuration ------------------------*/ |
|
||||||
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
|
||||||
{ |
|
||||||
FlagStatus pwrclkchanged = RESET; |
|
||||||
|
|
||||||
/* check for RTC Parameters used to output RTCCLK */ |
|
||||||
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); |
|
||||||
|
|
||||||
/* As soon as function is called to change RTC clock source, activation of the
|
|
||||||
power domain is done. */ |
|
||||||
/* Requires to enable write access to Backup Domain of necessary */ |
|
||||||
if (__HAL_RCC_PWR_IS_CLK_DISABLED()) |
|
||||||
{ |
|
||||||
__HAL_RCC_PWR_CLK_ENABLE(); |
|
||||||
pwrclkchanged = SET; |
|
||||||
} |
|
||||||
|
|
||||||
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) |
|
||||||
{ |
|
||||||
/* Enable write access to Backup domain */ |
|
||||||
SET_BIT(PWR->CR, PWR_CR_DBP); |
|
||||||
|
|
||||||
/* Wait for Backup domain Write protection disable */ |
|
||||||
tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) |
|
||||||
{ |
|
||||||
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ |
|
||||||
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); |
|
||||||
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) |
|
||||||
{ |
|
||||||
/* Store the content of BDCR register before the reset of Backup Domain */ |
|
||||||
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
|
||||||
/* RTC Clock selection can be changed only if the Backup Domain is reset */ |
|
||||||
__HAL_RCC_BACKUPRESET_FORCE(); |
|
||||||
__HAL_RCC_BACKUPRESET_RELEASE(); |
|
||||||
/* Restore the Content of BDCR register */ |
|
||||||
RCC->BDCR = temp_reg; |
|
||||||
|
|
||||||
/* Wait for LSERDY if LSE was enabled */ |
|
||||||
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) |
|
||||||
{ |
|
||||||
/* Get Start Tick */ |
|
||||||
tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
/* Wait till LSE is ready */ |
|
||||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
|
||||||
{ |
|
||||||
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
|
||||||
|
|
||||||
/* Require to disable power clock if necessary */ |
|
||||||
if (pwrclkchanged == SET) |
|
||||||
{ |
|
||||||
__HAL_RCC_PWR_CLK_DISABLE(); |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/*------------------------------ ADC clock Configuration ------------------*/ |
|
||||||
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); |
|
||||||
|
|
||||||
/* Configure the ADC clock source */ |
|
||||||
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); |
|
||||||
} |
|
||||||
|
|
||||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
/*------------------------------ I2S2 Configuration ------------------------*/ |
|
||||||
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); |
|
||||||
|
|
||||||
/* Configure the I2S2 clock source */ |
|
||||||
__HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); |
|
||||||
} |
|
||||||
|
|
||||||
/*------------------------------ I2S3 Configuration ------------------------*/ |
|
||||||
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); |
|
||||||
|
|
||||||
/* Configure the I2S3 clock source */ |
|
||||||
__HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); |
|
||||||
} |
|
||||||
|
|
||||||
/*------------------------------ PLL I2S Configuration ----------------------*/ |
|
||||||
/* Check that PLLI2S need to be enabled */ |
|
||||||
if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) |
|
||||||
{ |
|
||||||
/* Update flag to indicate that PLL I2S should be active */ |
|
||||||
pllactive = 1; |
|
||||||
} |
|
||||||
|
|
||||||
/* Check if PLL I2S need to be enabled */ |
|
||||||
if (pllactive == 1) |
|
||||||
{ |
|
||||||
/* Enable PLL I2S only if not active */ |
|
||||||
if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); |
|
||||||
assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); |
|
||||||
|
|
||||||
/* Prediv2 can be written only when the PLL2 is disabled. */ |
|
||||||
/* Return an error only if new value is different from the programmed value */ |
|
||||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \
|
|
||||||
(__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Configure the HSE prediv2 factor --------------------------------*/ |
|
||||||
__HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); |
|
||||||
|
|
||||||
/* Configure the main PLLI2S multiplication factors. */ |
|
||||||
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); |
|
||||||
|
|
||||||
/* Enable the main PLLI2S. */ |
|
||||||
__HAL_RCC_PLLI2S_ENABLE(); |
|
||||||
|
|
||||||
/* Get Start Tick*/ |
|
||||||
tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
/* Wait till PLLI2S is ready */ |
|
||||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
|
||||||
{ |
|
||||||
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ |
|
||||||
if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
#endif /* STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
|
||||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
|
||||||
|| defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
/*------------------------------ USB clock Configuration ------------------*/ |
|
||||||
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); |
|
||||||
|
|
||||||
/* Configure the USB clock source */ |
|
||||||
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); |
|
||||||
} |
|
||||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the PeriphClkInit according to the internal |
|
||||||
* RCC configuration registers. |
|
||||||
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that |
|
||||||
* returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). |
|
||||||
* @retval None |
|
||||||
*/ |
|
||||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
|
||||||
{ |
|
||||||
uint32_t srcclk = 0U; |
|
||||||
|
|
||||||
/* Set all possible values for the extended clock type parameter------------*/ |
|
||||||
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; |
|
||||||
|
|
||||||
/* Get the RTC configuration -----------------------------------------------*/ |
|
||||||
srcclk = __HAL_RCC_GET_RTC_SOURCE(); |
|
||||||
/* Source clock is LSE or LSI*/ |
|
||||||
PeriphClkInit->RTCClockSelection = srcclk; |
|
||||||
|
|
||||||
/* Get the ADC clock configuration -----------------------------------------*/ |
|
||||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC; |
|
||||||
PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); |
|
||||||
|
|
||||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
/* Get the I2S2 clock configuration -----------------------------------------*/ |
|
||||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; |
|
||||||
PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); |
|
||||||
|
|
||||||
/* Get the I2S3 clock configuration -----------------------------------------*/ |
|
||||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; |
|
||||||
PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE(); |
|
||||||
|
|
||||||
#endif /* STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
#if defined(STM32F103xE) || defined(STM32F103xG) |
|
||||||
/* Get the I2S2 clock configuration -----------------------------------------*/ |
|
||||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; |
|
||||||
PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK; |
|
||||||
|
|
||||||
/* Get the I2S3 clock configuration -----------------------------------------*/ |
|
||||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; |
|
||||||
PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK; |
|
||||||
|
|
||||||
#endif /* STM32F103xE || STM32F103xG */ |
|
||||||
|
|
||||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
|
||||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
|
||||||
|| defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
/* Get the USB clock configuration -----------------------------------------*/ |
|
||||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; |
|
||||||
PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); |
|
||||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Returns the peripheral clock frequency |
|
||||||
* @note Returns 0 if peripheral clock is unknown |
|
||||||
* @param PeriphClk Peripheral clock identifier |
|
||||||
* This parameter can be one of the following values: |
|
||||||
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock |
|
||||||
@if STM32F103xE |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
@endif |
|
||||||
@if STM32F103xG |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
|
||||||
@endif |
|
||||||
@if STM32F105xC |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock |
|
||||||
@endif |
|
||||||
@if STM32F107xC |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
|
||||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock |
|
||||||
@endif |
|
||||||
@if STM32F102xx |
|
||||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock |
|
||||||
@endif |
|
||||||
@if STM32F103xx |
|
||||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock |
|
||||||
@endif |
|
||||||
* @retval Frequency in Hz (0: means that no available frequency for the peripheral) |
|
||||||
*/ |
|
||||||
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) |
|
||||||
{ |
|
||||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; |
|
||||||
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; |
|
||||||
|
|
||||||
uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; |
|
||||||
uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; |
|
||||||
#endif /* STM32F105xC || STM32F107xC */ |
|
||||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \ |
|
||||||
defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) |
|
||||||
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; |
|
||||||
const uint8_t aPredivFactorTable[2] = {1, 2}; |
|
||||||
|
|
||||||
uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; |
|
||||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ |
|
||||||
uint32_t temp_reg = 0U, frequency = 0U; |
|
||||||
|
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); |
|
||||||
|
|
||||||
switch (PeriphClk) |
|
||||||
{ |
|
||||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
|
||||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
|
||||||
|| defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
case RCC_PERIPHCLK_USB: |
|
||||||
{ |
|
||||||
/* Get RCC configuration ------------------------------------------------------*/ |
|
||||||
temp_reg = RCC->CFGR; |
|
||||||
|
|
||||||
/* Check if PLL is enabled */ |
|
||||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) |
|
||||||
{ |
|
||||||
pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; |
|
||||||
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) |
|
||||||
{ |
|
||||||
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ |
|
||||||
|| defined(STM32F100xE) |
|
||||||
prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; |
|
||||||
#else |
|
||||||
prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; |
|
||||||
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ |
|
||||||
|
|
||||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) |
|
||||||
{ |
|
||||||
/* PLL2 selected as Prediv1 source */ |
|
||||||
/* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ |
|
||||||
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; |
|
||||||
pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; |
|
||||||
pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ |
|
||||||
pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); |
|
||||||
} |
|
||||||
|
|
||||||
/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ |
|
||||||
/* In this case need to divide pllclk by 2 */ |
|
||||||
if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) |
|
||||||
{ |
|
||||||
pllclk = pllclk / 2; |
|
||||||
} |
|
||||||
#else |
|
||||||
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) |
|
||||||
{ |
|
||||||
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ |
|
||||||
pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); |
|
||||||
} |
|
||||||
#endif /* STM32F105xC || STM32F107xC */ |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ |
|
||||||
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); |
|
||||||
} |
|
||||||
|
|
||||||
/* Calcul of the USB frequency*/ |
|
||||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
/* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ |
|
||||||
if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) |
|
||||||
{ |
|
||||||
/* Prescaler of 2 selected for USB */ |
|
||||||
frequency = pllclk; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Prescaler of 3 selected for USB */ |
|
||||||
frequency = (2 * pllclk) / 3; |
|
||||||
} |
|
||||||
#else |
|
||||||
/* USBCLK = PLLCLK / USB prescaler */ |
|
||||||
if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) |
|
||||||
{ |
|
||||||
/* No prescaler selected for USB */ |
|
||||||
frequency = pllclk; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Prescaler of 1.5 selected for USB */ |
|
||||||
frequency = (pllclk * 2) / 3; |
|
||||||
} |
|
||||||
#endif |
|
||||||
} |
|
||||||
break; |
|
||||||
} |
|
||||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
|
||||||
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
case RCC_PERIPHCLK_I2S2: |
|
||||||
{ |
|
||||||
#if defined(STM32F103xE) || defined(STM32F103xG) |
|
||||||
/* SYSCLK used as source clock for I2S2 */ |
|
||||||
frequency = HAL_RCC_GetSysClockFreq(); |
|
||||||
#else |
|
||||||
if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) |
|
||||||
{ |
|
||||||
/* SYSCLK used as source clock for I2S2 */ |
|
||||||
frequency = HAL_RCC_GetSysClockFreq(); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Check if PLLI2S is enabled */ |
|
||||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) |
|
||||||
{ |
|
||||||
/* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ |
|
||||||
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; |
|
||||||
pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; |
|
||||||
frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); |
|
||||||
} |
|
||||||
} |
|
||||||
#endif /* STM32F103xE || STM32F103xG */ |
|
||||||
break; |
|
||||||
} |
|
||||||
case RCC_PERIPHCLK_I2S3: |
|
||||||
{ |
|
||||||
#if defined(STM32F103xE) || defined(STM32F103xG) |
|
||||||
/* SYSCLK used as source clock for I2S3 */ |
|
||||||
frequency = HAL_RCC_GetSysClockFreq(); |
|
||||||
#else |
|
||||||
if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) |
|
||||||
{ |
|
||||||
/* SYSCLK used as source clock for I2S3 */ |
|
||||||
frequency = HAL_RCC_GetSysClockFreq(); |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Check if PLLI2S is enabled */ |
|
||||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) |
|
||||||
{ |
|
||||||
/* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ |
|
||||||
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; |
|
||||||
pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; |
|
||||||
frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); |
|
||||||
} |
|
||||||
} |
|
||||||
#endif /* STM32F103xE || STM32F103xG */ |
|
||||||
break; |
|
||||||
} |
|
||||||
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
|
||||||
case RCC_PERIPHCLK_RTC: |
|
||||||
{ |
|
||||||
/* Get RCC BDCR configuration ------------------------------------------------------*/ |
|
||||||
temp_reg = RCC->BDCR; |
|
||||||
|
|
||||||
/* Check if LSE is ready if RTC clock selection is LSE */ |
|
||||||
if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) |
|
||||||
{ |
|
||||||
frequency = LSE_VALUE; |
|
||||||
} |
|
||||||
/* Check if LSI is ready if RTC clock selection is LSI */ |
|
||||||
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) |
|
||||||
{ |
|
||||||
frequency = LSI_VALUE; |
|
||||||
} |
|
||||||
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) |
|
||||||
{ |
|
||||||
frequency = HSE_VALUE / 128U; |
|
||||||
} |
|
||||||
/* Clock not enabled for RTC*/ |
|
||||||
else |
|
||||||
{ |
|
||||||
/* nothing to do: frequency already initialized to 0U */ |
|
||||||
} |
|
||||||
break; |
|
||||||
} |
|
||||||
case RCC_PERIPHCLK_ADC: |
|
||||||
{ |
|
||||||
frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); |
|
||||||
break; |
|
||||||
} |
|
||||||
default: |
|
||||||
{ |
|
||||||
break; |
|
||||||
} |
|
||||||
} |
|
||||||
return (frequency); |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
|
||||||
/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
|
|
||||||
* @brief PLLI2S Management functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### Extended PLLI2S Management functions ##### |
|
||||||
=============================================================================== |
|
||||||
[..] |
|
||||||
This subsection provides a set of functions allowing to control the PLLI2S |
|
||||||
activation or deactivation |
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable PLLI2S |
|
||||||
* @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that |
|
||||||
* contains the configuration information for the PLLI2S |
|
||||||
* @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) |
|
||||||
{ |
|
||||||
uint32_t tickstart = 0U; |
|
||||||
|
|
||||||
/* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/ |
|
||||||
if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL)); |
|
||||||
assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value)); |
|
||||||
|
|
||||||
/* Prediv2 can be written only when the PLL2 is disabled. */ |
|
||||||
/* Return an error only if new value is different from the programmed value */ |
|
||||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \
|
|
||||||
(__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Disable the main PLLI2S. */ |
|
||||||
__HAL_RCC_PLLI2S_DISABLE(); |
|
||||||
|
|
||||||
/* Get Start Tick*/ |
|
||||||
tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
/* Wait till PLLI2S is ready */ |
|
||||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
|
||||||
{ |
|
||||||
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* Configure the HSE prediv2 factor --------------------------------*/ |
|
||||||
__HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); |
|
||||||
|
|
||||||
|
|
||||||
/* Configure the main PLLI2S multiplication factors. */ |
|
||||||
__HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); |
|
||||||
|
|
||||||
/* Enable the main PLLI2S. */ |
|
||||||
__HAL_RCC_PLLI2S_ENABLE(); |
|
||||||
|
|
||||||
/* Get Start Tick*/ |
|
||||||
tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
/* Wait till PLLI2S is ready */ |
|
||||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
|
||||||
{ |
|
||||||
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* PLLI2S cannot be modified as already used by I2S2 or I2S3 */ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable PLLI2S |
|
||||||
* @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) |
|
||||||
{ |
|
||||||
uint32_t tickstart = 0U; |
|
||||||
|
|
||||||
/* Disable PLL I2S as not requested by I2S2 or I2S3*/ |
|
||||||
if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) |
|
||||||
{ |
|
||||||
/* Disable the main PLLI2S. */ |
|
||||||
__HAL_RCC_PLLI2S_DISABLE(); |
|
||||||
|
|
||||||
/* Get Start Tick*/ |
|
||||||
tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
/* Wait till PLLI2S is ready */ |
|
||||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
|
||||||
{ |
|
||||||
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
|
|
||||||
* @brief PLL2 Management functions |
|
||||||
* |
|
||||||
@verbatim |
|
||||||
=============================================================================== |
|
||||||
##### Extended PLL2 Management functions ##### |
|
||||||
=============================================================================== |
|
||||||
[..] |
|
||||||
This subsection provides a set of functions allowing to control the PLL2 |
|
||||||
activation or deactivation |
|
||||||
@endverbatim |
|
||||||
* @{ |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Enable PLL2 |
|
||||||
* @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that |
|
||||||
* contains the configuration information for the PLL2 |
|
||||||
* @note The PLL2 configuration not modified if used indirectly as system clock. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) |
|
||||||
{ |
|
||||||
uint32_t tickstart = 0U; |
|
||||||
|
|
||||||
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
|
|
||||||
clock (i.e. it is used as PLL clock entry that is used as system clock). */ |
|
||||||
if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
|
|
||||||
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
|
|
||||||
((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Check the parameters */ |
|
||||||
assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL)); |
|
||||||
assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value)); |
|
||||||
|
|
||||||
/* Prediv2 can be written only when the PLLI2S is disabled. */ |
|
||||||
/* Return an error only if new value is different from the programmed value */ |
|
||||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \
|
|
||||||
(__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
|
|
||||||
/* Disable the main PLL2. */ |
|
||||||
__HAL_RCC_PLL2_DISABLE(); |
|
||||||
|
|
||||||
/* Get Start Tick*/ |
|
||||||
tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
/* Wait till PLL2 is disabled */ |
|
||||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) |
|
||||||
{ |
|
||||||
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* Configure the HSE prediv2 factor --------------------------------*/ |
|
||||||
__HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); |
|
||||||
|
|
||||||
/* Configure the main PLL2 multiplication factors. */ |
|
||||||
__HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); |
|
||||||
|
|
||||||
/* Enable the main PLL2. */ |
|
||||||
__HAL_RCC_PLL2_ENABLE(); |
|
||||||
|
|
||||||
/* Get Start Tick*/ |
|
||||||
tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
/* Wait till PLL2 is ready */ |
|
||||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) |
|
||||||
{ |
|
||||||
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Disable PLL2 |
|
||||||
* @note PLL2 is not disabled if used indirectly as system clock. |
|
||||||
* @retval HAL status |
|
||||||
*/ |
|
||||||
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) |
|
||||||
{ |
|
||||||
uint32_t tickstart = 0U; |
|
||||||
|
|
||||||
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
|
|
||||||
clock (i.e. it is used as PLL clock entry that is used as system clock). */ |
|
||||||
if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
|
|
||||||
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
|
|
||||||
((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) |
|
||||||
{ |
|
||||||
return HAL_ERROR; |
|
||||||
} |
|
||||||
else |
|
||||||
{ |
|
||||||
/* Disable the main PLL2. */ |
|
||||||
__HAL_RCC_PLL2_DISABLE(); |
|
||||||
|
|
||||||
/* Get Start Tick*/ |
|
||||||
tickstart = HAL_GetTick(); |
|
||||||
|
|
||||||
/* Wait till PLL2 is disabled */ |
|
||||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) |
|
||||||
{ |
|
||||||
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) |
|
||||||
{ |
|
||||||
return HAL_TIMEOUT; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
return HAL_OK; |
|
||||||
} |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
#endif /* STM32F105xC || STM32F107xC */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
#endif /* HAL_RCC_MODULE_ENABLED */ |
|
||||||
|
|
||||||
/**
|
|
||||||
* @} |
|
||||||
*/ |
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,86 @@ |
|||||||
|
/**
|
||||||
|
****************************************************************************** |
||||||
|
* @file stm32f1xx_ll_pwr.c |
||||||
|
* @author MCD Application Team |
||||||
|
* @brief PWR LL module driver. |
||||||
|
****************************************************************************** |
||||||
|
* @attention |
||||||
|
* |
||||||
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||||
|
* All rights reserved.</center></h2> |
||||||
|
* |
||||||
|
* This software component is licensed by ST under BSD 3-Clause license, |
||||||
|
* the "License"; You may not use this file except in compliance with the |
||||||
|
* License. You may obtain a copy of the License at: |
||||||
|
* opensource.org/licenses/BSD-3-Clause |
||||||
|
* |
||||||
|
****************************************************************************** |
||||||
|
*/ |
||||||
|
|
||||||
|
#if defined(USE_FULL_LL_DRIVER) |
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/ |
||||||
|
#include "stm32f1xx_ll_pwr.h" |
||||||
|
#include "stm32f1xx_ll_bus.h" |
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
#if defined(PWR) |
||||||
|
|
||||||
|
/** @defgroup PWR_LL PWR
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/ |
||||||
|
/* Private variables ---------------------------------------------------------*/ |
||||||
|
/* Private constants ---------------------------------------------------------*/ |
||||||
|
/* Private macros ------------------------------------------------------------*/ |
||||||
|
/* Private function prototypes -----------------------------------------------*/ |
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/ |
||||||
|
/** @addtogroup PWR_LL_Exported_Functions
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/** @addtogroup PWR_LL_EF_Init
|
||||||
|
* @{ |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize the PWR registers to their default reset values. |
||||||
|
* @retval An ErrorStatus enumeration value: |
||||||
|
* - SUCCESS: PWR registers are de-initialized |
||||||
|
* - ERROR: not applicable |
||||||
|
*/ |
||||||
|
ErrorStatus LL_PWR_DeInit(void) |
||||||
|
{ |
||||||
|
/* Force reset of PWR clock */ |
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR); |
||||||
|
|
||||||
|
/* Release reset of PWR clock */ |
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR); |
||||||
|
|
||||||
|
return SUCCESS; |
||||||
|
} |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
#endif /* defined(PWR) */ |
||||||
|
/**
|
||||||
|
* @} |
||||||
|
*/ |
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */ |
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||||
Loading…
Reference in new issue