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588 lines
20 KiB
588 lines
20 KiB
2 years ago
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/**
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******************************************************************************
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* @file stm32f1xx_hal_gpio.c
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* @author MCD Application Team
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* @brief GPIO HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the General Purpose Input/Output (GPIO) peripheral:
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* + Initialization and de-initialization functions
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* + IO operation functions
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*
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@verbatim
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==============================================================================
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##### GPIO Peripheral features #####
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==============================================================================
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[..]
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Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
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port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
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in several modes:
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(+) Input mode
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(+) Analog mode
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(+) Output mode
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(+) Alternate function mode
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(+) External interrupt/event lines
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[..]
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During and just after reset, the alternate functions and external interrupt
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lines are not active and the I/O ports are configured in input floating mode.
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[..]
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All GPIO pins have weak internal pull-up and pull-down resistors, which can be
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activated or not.
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[..]
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In Output or Alternate mode, each IO can be configured on open-drain or push-pull
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type and the IO speed can be selected depending on the VDD value.
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[..]
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All ports have external interrupt/event capability. To use external interrupt
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lines, the port must be configured in input mode. All available GPIO pins are
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connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
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[..]
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The external interrupt/event controller consists of up to 20 edge detectors in connectivity
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line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
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Each input line can be independently configured to select the type (event or interrupt) and
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the corresponding trigger event (rising or falling or both). Each line can also masked
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independently. A pending register maintains the status line of the interrupt requests
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##### How to use this driver #####
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==============================================================================
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[..]
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(#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
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(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
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(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
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(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
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structure.
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(++) In case of Output or alternate function mode selection: the speed is
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configured through "Speed" member from GPIO_InitTypeDef structure
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(++) Analog mode is required when a pin is to be used as ADC channel
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or DAC output.
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(++) In case of external interrupt/event selection the "Mode" member from
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GPIO_InitTypeDef structure select the type (interrupt or event) and
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the corresponding trigger event (rising or falling or both).
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(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
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mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
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HAL_NVIC_EnableIRQ().
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(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
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(#) To set/reset the level of a pin configured in output mode use
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HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
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(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
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(#) During and just after reset, the alternate functions are not
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active and the GPIO pins are configured in input floating mode (except JTAG
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pins).
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(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
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(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
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priority over the GPIO function.
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(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
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general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
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The HSE has priority over the GPIO function.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @defgroup GPIO GPIO
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* @brief GPIO HAL module driver
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* @{
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*/
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#ifdef HAL_GPIO_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @addtogroup GPIO_Private_Constants GPIO Private Constants
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* @{
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*/
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#define GPIO_MODE 0x00000003u
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#define EXTI_MODE 0x10000000u
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#define GPIO_MODE_IT 0x00010000u
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#define GPIO_MODE_EVT 0x00020000u
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#define RISING_EDGE 0x00100000u
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#define FALLING_EDGE 0x00200000u
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#define GPIO_OUTPUT_TYPE 0x00000010u
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#define GPIO_NUMBER 16u
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/* Definitions for bit manipulation of CRL and CRH register */
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#define GPIO_CR_MODE_INPUT 0x00000000u /*!< 00: Input mode (reset state) */
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#define GPIO_CR_CNF_ANALOG 0x00000000u /*!< 00: Analog mode */
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#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004u /*!< 01: Floating input (reset state) */
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#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008u /*!< 10: Input with pull-up / pull-down */
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#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000u /*!< 00: General purpose output push-pull */
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#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004u /*!< 01: General purpose output Open-drain */
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#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008u /*!< 10: Alternate function output Push-pull */
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#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000Cu /*!< 11: Alternate function output Open-drain */
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
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* @{
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*/
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/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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This section provides functions allowing to initialize and de-initialize the GPIOs
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to be ready for use.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
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* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
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* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
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* the configuration information for the specified GPIO peripheral.
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* @retval None
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*/
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void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
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{
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uint32_t position = 0x00u;
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uint32_t ioposition;
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uint32_t iocurrent;
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uint32_t temp;
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uint32_t config = 0x00u;
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__IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
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uint32_t registeroffset; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
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/* Check the parameters */
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assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
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assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
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assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
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/* Configure the port pins */
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while (((GPIO_Init->Pin) >> position) != 0x00u)
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{
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/* Get the IO position */
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ioposition = (0x01uL << position);
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/* Get the current IO position */
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iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
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if (iocurrent == ioposition)
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{
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/* Check the Alternate function parameters */
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assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
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/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
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switch (GPIO_Init->Mode)
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{
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/* If we are configuring the pin in OUTPUT push-pull mode */
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case GPIO_MODE_OUTPUT_PP:
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/* Check the GPIO speed parameter */
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assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
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config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
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break;
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/* If we are configuring the pin in OUTPUT open-drain mode */
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case GPIO_MODE_OUTPUT_OD:
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/* Check the GPIO speed parameter */
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assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
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config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
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break;
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/* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
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case GPIO_MODE_AF_PP:
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/* Check the GPIO speed parameter */
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assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
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config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
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break;
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/* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
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case GPIO_MODE_AF_OD:
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/* Check the GPIO speed parameter */
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assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
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config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
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break;
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/* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
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case GPIO_MODE_INPUT:
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case GPIO_MODE_IT_RISING:
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case GPIO_MODE_IT_FALLING:
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case GPIO_MODE_IT_RISING_FALLING:
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case GPIO_MODE_EVT_RISING:
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case GPIO_MODE_EVT_FALLING:
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case GPIO_MODE_EVT_RISING_FALLING:
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/* Check the GPIO pull parameter */
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assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
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if (GPIO_Init->Pull == GPIO_NOPULL)
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{
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config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
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}
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else if (GPIO_Init->Pull == GPIO_PULLUP)
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{
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config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
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/* Set the corresponding ODR bit */
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GPIOx->BSRR = ioposition;
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}
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else /* GPIO_PULLDOWN */
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{
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config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
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/* Reset the corresponding ODR bit */
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GPIOx->BRR = ioposition;
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}
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break;
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/* If we are configuring the pin in INPUT analog mode */
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case GPIO_MODE_ANALOG:
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config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
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break;
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/* Parameters are checked with assert_param */
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default:
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break;
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}
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/* Check if the current bit belongs to first half or last half of the pin count number
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in order to address CRH or CRL register*/
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configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
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registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
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/* Apply the new configuration of the pin to the register */
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MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
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/*--------------------- EXTI Mode Configuration ------------------------*/
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/* Configure the External Interrupt or event for the current IO */
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if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
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{
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/* Enable AFIO Clock */
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__HAL_RCC_AFIO_CLK_ENABLE();
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temp = AFIO->EXTICR[position >> 2u];
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CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
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SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
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AFIO->EXTICR[position >> 2u] = temp;
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/* Configure the interrupt mask */
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if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
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{
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SET_BIT(EXTI->IMR, iocurrent);
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}
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else
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{
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CLEAR_BIT(EXTI->IMR, iocurrent);
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}
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/* Configure the event mask */
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if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
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{
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SET_BIT(EXTI->EMR, iocurrent);
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}
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else
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{
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CLEAR_BIT(EXTI->EMR, iocurrent);
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}
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/* Enable or disable the rising trigger */
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if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
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{
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SET_BIT(EXTI->RTSR, iocurrent);
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}
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else
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{
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CLEAR_BIT(EXTI->RTSR, iocurrent);
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}
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/* Enable or disable the falling trigger */
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if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
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{
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SET_BIT(EXTI->FTSR, iocurrent);
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}
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else
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{
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CLEAR_BIT(EXTI->FTSR, iocurrent);
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}
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}
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}
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position++;
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}
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}
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/**
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* @brief De-initializes the GPIOx peripheral registers to their default reset values.
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* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
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* @param GPIO_Pin: specifies the port bit to be written.
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* This parameter can be one of GPIO_PIN_x where x can be (0..15).
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* @retval None
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*/
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void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
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{
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uint32_t position = 0x00u;
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uint32_t iocurrent;
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uint32_t tmp;
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__IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
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uint32_t registeroffset;
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|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||
|
|
|
||
|
|
/* Configure the port pins */
|
||
|
|
while ((GPIO_Pin >> position) != 0u)
|
||
|
|
{
|
||
|
|
/* Get current io position */
|
||
|
|
iocurrent = (GPIO_Pin) & (1uL << position);
|
||
|
|
|
||
|
|
if (iocurrent)
|
||
|
|
{
|
||
|
|
/*------------------------- EXTI Mode Configuration --------------------*/
|
||
|
|
/* Clear the External Interrupt or Event for the current IO */
|
||
|
|
|
||
|
|
tmp = AFIO->EXTICR[position >> 2u];
|
||
|
|
tmp &= 0x0FuL << (4u * (position & 0x03u));
|
||
|
|
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
|
||
|
|
{
|
||
|
|
tmp = 0x0FuL << (4u * (position & 0x03u));
|
||
|
|
CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp);
|
||
|
|
|
||
|
|
/* Clear EXTI line configuration */
|
||
|
|
CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
|
||
|
|
CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
|
||
|
|
|
||
|
|
/* Clear Rising Falling edge configuration */
|
||
|
|
CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
|
||
|
|
CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
|
||
|
|
}
|
||
|
|
/*------------------------- GPIO Mode Configuration --------------------*/
|
||
|
|
/* Check if the current bit belongs to first half or last half of the pin count number
|
||
|
|
in order to address CRH or CRL register */
|
||
|
|
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
|
||
|
|
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
|
||
|
|
|
||
|
|
/* CRL/CRH default value is floating input(0x04) shifted to correct position */
|
||
|
|
MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset);
|
||
|
|
|
||
|
|
/* ODR default value is 0 */
|
||
|
|
CLEAR_BIT(GPIOx->ODR, iocurrent);
|
||
|
|
}
|
||
|
|
|
||
|
|
position++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||
|
|
* @brief GPIO Read and Write
|
||
|
|
*
|
||
|
|
@verbatim
|
||
|
|
===============================================================================
|
||
|
|
##### IO operation functions #####
|
||
|
|
===============================================================================
|
||
|
|
[..]
|
||
|
|
This subsection provides a set of functions allowing to manage the GPIOs.
|
||
|
|
|
||
|
|
@endverbatim
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Reads the specified input port pin.
|
||
|
|
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
|
||
|
|
* @param GPIO_Pin: specifies the port bit to read.
|
||
|
|
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||
|
|
* @retval The input port pin value.
|
||
|
|
*/
|
||
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||
|
|
{
|
||
|
|
GPIO_PinState bitstatus;
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||
|
|
|
||
|
|
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
||
|
|
{
|
||
|
|
bitstatus = GPIO_PIN_SET;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
bitstatus = GPIO_PIN_RESET;
|
||
|
|
}
|
||
|
|
return bitstatus;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Sets or clears the selected data port bit.
|
||
|
|
*
|
||
|
|
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
|
||
|
|
* accesses. In this way, there is no risk of an IRQ occurring between
|
||
|
|
* the read and the modify access.
|
||
|
|
*
|
||
|
|
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
|
||
|
|
* @param GPIO_Pin: specifies the port bit to be written.
|
||
|
|
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||
|
|
* @param PinState: specifies the value to be written to the selected bit.
|
||
|
|
* This parameter can be one of the GPIO_PinState enum values:
|
||
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
||
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||
|
|
|
||
|
|
if (PinState != GPIO_PIN_RESET)
|
||
|
|
{
|
||
|
|
GPIOx->BSRR = GPIO_Pin;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Toggles the specified GPIO pin
|
||
|
|
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
|
||
|
|
* @param GPIO_Pin: Specifies the pins to be toggled.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||
|
|
{
|
||
|
|
uint32_t odr;
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||
|
|
|
||
|
|
/* get current Ouput Data Register value */
|
||
|
|
odr = GPIOx->ODR;
|
||
|
|
|
||
|
|
/* Set selected pins that were at low level, and reset ones that were high */
|
||
|
|
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Locks GPIO Pins configuration registers.
|
||
|
|
* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
|
||
|
|
* has been applied on a port bit, it is no longer possible to modify the value of the port bit until
|
||
|
|
* the next reset.
|
||
|
|
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
|
||
|
|
* @param GPIO_Pin: specifies the port bit to be locked.
|
||
|
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||
|
|
{
|
||
|
|
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||
|
|
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
|
||
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||
|
|
|
||
|
|
/* Apply lock key write sequence */
|
||
|
|
SET_BIT(tmp, GPIO_Pin);
|
||
|
|
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||
|
|
GPIOx->LCKR = tmp;
|
||
|
|
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||
|
|
GPIOx->LCKR = GPIO_Pin;
|
||
|
|
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||
|
|
GPIOx->LCKR = tmp;
|
||
|
|
/* Read LCKK register. This read is mandatory to complete key lock sequence */
|
||
|
|
tmp = GPIOx->LCKR;
|
||
|
|
|
||
|
|
/* read again in order to confirm lock is active */
|
||
|
|
if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
|
||
|
|
{
|
||
|
|
return HAL_OK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return HAL_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function handles EXTI interrupt request.
|
||
|
|
* @param GPIO_Pin: Specifies the pins connected EXTI line
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||
|
|
{
|
||
|
|
/* EXTI line interrupt detected */
|
||
|
|
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
||
|
|
{
|
||
|
|
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||
|
|
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief EXTI line detection callbacks.
|
||
|
|
* @param GPIO_Pin: Specifies the pins connected EXTI line
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||
|
|
{
|
||
|
|
/* Prevent unused argument(s) compilation warning */
|
||
|
|
UNUSED(GPIO_Pin);
|
||
|
|
/* NOTE: This function Should not be modified, when the callback is needed,
|
||
|
|
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||
|
|
*/
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|