commit
8260fb60f8
@ -0,0 +1,11 @@ |
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cmake-build-debug/ |
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.idea/ |
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CMakeLists.txt |
||||
*.o |
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*.elf |
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*.out |
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*.hex |
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*.bin |
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*.lst |
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*.d |
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build/ |
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File diff suppressed because one or more lines are too long
@ -0,0 +1,258 @@ |
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#MicroXplorer Configuration settings - do not modify |
||||
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_0 |
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ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_1 |
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ADC1.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_TEMPSENSOR |
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ADC1.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_VREFINT |
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ADC1.ContinuousConvMode=ENABLE |
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ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master,ContinuousConvMode,Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,Rank-3\#ChannelRegularConversion,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,NbrOfConversion |
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ADC1.NbrOfConversion=4 |
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ADC1.NbrOfConversionFlag=1 |
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ADC1.Rank-0\#ChannelRegularConversion=1 |
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ADC1.Rank-1\#ChannelRegularConversion=2 |
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ADC1.Rank-2\#ChannelRegularConversion=3 |
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ADC1.Rank-3\#ChannelRegularConversion=4 |
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ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_41CYCLES_5 |
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ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_41CYCLES_5 |
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ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_41CYCLES_5 |
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ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_41CYCLES_5 |
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ADC1.master=1 |
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Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY |
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Dma.ADC1.0.Instance=DMA1_Channel1 |
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Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD |
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Dma.ADC1.0.MemInc=DMA_MINC_ENABLE |
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Dma.ADC1.0.Mode=DMA_CIRCULAR |
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Dma.ADC1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD |
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Dma.ADC1.0.PeriphInc=DMA_PINC_DISABLE |
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Dma.ADC1.0.Priority=DMA_PRIORITY_MEDIUM |
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Dma.ADC1.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority |
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Dma.Request0=ADC1 |
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Dma.RequestsNb=1 |
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FREERTOS.IPParameters=Tasks01,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,configUSE_NEWLIB_REENTRANT |
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FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL |
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FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2 |
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FREERTOS.configUSE_MALLOC_FAILED_HOOK=1 |
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FREERTOS.configUSE_NEWLIB_REENTRANT=1 |
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File.Version=6 |
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GPIO.groupedBy= |
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IWDG.IPParameters=Prescaler,Reload |
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IWDG.Prescaler=IWDG_PRESCALER_256 |
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IWDG.Reload=624 |
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KeepUserPlacement=false |
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Mcu.CPN=STM32F103CBT6 |
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Mcu.Family=STM32F1 |
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Mcu.IP0=ADC1 |
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Mcu.IP1=DMA |
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Mcu.IP10=USART1 |
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Mcu.IP2=FREERTOS |
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Mcu.IP3=IWDG |
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Mcu.IP4=NVIC |
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Mcu.IP5=RCC |
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Mcu.IP6=SPI1 |
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Mcu.IP7=SYS |
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Mcu.IP8=TIM2 |
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Mcu.IP9=TIM4 |
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Mcu.IPNb=11 |
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Mcu.Name=STM32F103C(8-B)Tx |
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Mcu.Package=LQFP48 |
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Mcu.Pin0=PC13-TAMPER-RTC |
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Mcu.Pin1=PC14-OSC32_IN |
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Mcu.Pin10=PA6 |
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Mcu.Pin11=PA7 |
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Mcu.Pin12=PB11 |
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Mcu.Pin13=PA9 |
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Mcu.Pin14=PA10 |
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Mcu.Pin15=PA15 |
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Mcu.Pin16=PB5 |
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Mcu.Pin17=PB6 |
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Mcu.Pin18=PB7 |
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Mcu.Pin19=VP_ADC1_TempSens_Input |
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Mcu.Pin2=PC15-OSC32_OUT |
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Mcu.Pin20=VP_ADC1_Vref_Input |
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Mcu.Pin21=VP_FREERTOS_VS_CMSIS_V2 |
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Mcu.Pin22=VP_IWDG_VS_IWDG |
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Mcu.Pin23=VP_SYS_VS_ND |
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Mcu.Pin24=VP_SYS_VS_tim1 |
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Mcu.Pin25=VP_TIM2_VS_ClockSourceINT |
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Mcu.Pin3=PD0-OSC_IN |
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Mcu.Pin4=PD1-OSC_OUT |
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Mcu.Pin5=PA0-WKUP |
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Mcu.Pin6=PA1 |
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Mcu.Pin7=PA3 |
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Mcu.Pin8=PA4 |
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Mcu.Pin9=PA5 |
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Mcu.PinsNb=26 |
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Mcu.ThirdPartyNb=0 |
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Mcu.UserConstants= |
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Mcu.UserName=STM32F103CBTx |
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MxCube.Version=6.5.0 |
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MxDb.Version=DB.6.0.50 |
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NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:true |
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NVIC.DMA1_Channel1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true |
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NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:true |
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NVIC.ForceEnableDMAVector=true |
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NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:true |
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NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:true |
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NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:true |
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NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:true |
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NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 |
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NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:true |
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NVIC.SavedPendsvIrqHandlerGenerated=true |
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NVIC.SavedSvcallIrqHandlerGenerated=true |
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NVIC.SavedSystickIrqHandlerGenerated=true |
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NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true\:true |
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NVIC.TIM1_UP_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true |
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NVIC.TimeBase=TIM1_UP_IRQn |
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NVIC.TimeBaseIP=TIM1 |
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NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:true |
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PA0-WKUP.GPIOParameters=GPIO_Label |
||||
PA0-WKUP.GPIO_Label=ADC_PT100 |
||||
PA0-WKUP.Signal=ADCx_IN0 |
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PA1.GPIOParameters=GPIO_Label |
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PA1.GPIO_Label=ADC_SENSR |
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PA1.Locked=true |
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PA1.Signal=ADCx_IN1 |
||||
PA10.Mode=Asynchronous |
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PA10.Signal=USART1_RX |
||||
PA15.GPIOParameters=GPIO_Speed,GPIO_Label |
||||
PA15.GPIO_Label=BUZZER |
||||
PA15.GPIO_Speed=GPIO_SPEED_FREQ_HIGH |
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PA15.Signal=S_TIM2_CH1_ETR |
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PA3.GPIOParameters=GPIO_Label |
||||
PA3.GPIO_Label=OLED_RST |
||||
PA3.Locked=true |
||||
PA3.Signal=GPIO_Output |
||||
PA4.GPIOParameters=GPIO_Label |
||||
PA4.GPIO_Label=OLED_DC |
||||
PA4.Locked=true |
||||
PA4.Signal=GPIO_Output |
||||
PA5.GPIOParameters=GPIO_Label |
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PA5.GPIO_Label=OLED_SCLK |
||||
PA5.Mode=TX_Only_Simplex_Unidirect_Master |
||||
PA5.Signal=SPI1_SCK |
||||
PA6.GPIOParameters=GPIO_Label |
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PA6.GPIO_Label=OLED_CS |
||||
PA6.Locked=true |
||||
PA6.Signal=GPIO_Output |
||||
PA7.GPIOParameters=GPIO_Label |
||||
PA7.GPIO_Label=OLED_MOSI |
||||
PA7.Mode=TX_Only_Simplex_Unidirect_Master |
||||
PA7.Signal=SPI1_MOSI |
||||
PA9.Mode=Asynchronous |
||||
PA9.Signal=USART1_TX |
||||
PB11.GPIOParameters=GPIO_Label |
||||
PB11.GPIO_Label=HEATER |
||||
PB11.Locked=true |
||||
PB11.Signal=GPIO_Output |
||||
PB5.GPIOParameters=GPIO_PuPd,GPIO_Label |
||||
PB5.GPIO_Label=KNOB_PUSH |
||||
PB5.GPIO_PuPd=GPIO_PULLUP |
||||
PB5.Locked=true |
||||
PB5.Signal=GPIO_Input |
||||
PB6.GPIOParameters=GPIO_PuPd,GPIO_Label |
||||
PB6.GPIO_Label=KNOB_B |
||||
PB6.GPIO_PuPd=GPIO_PULLUP |
||||
PB6.Signal=S_TIM4_CH1 |
||||
PB7.GPIOParameters=GPIO_PuPd,GPIO_Label |
||||
PB7.GPIO_Label=KNOB_A |
||||
PB7.GPIO_PuPd=GPIO_PULLUP |
||||
PB7.Signal=S_TIM4_CH2 |
||||
PC13-TAMPER-RTC.GPIOParameters=GPIO_Label |
||||
PC13-TAMPER-RTC.GPIO_Label=LED |
||||
PC13-TAMPER-RTC.Locked=true |
||||
PC13-TAMPER-RTC.Signal=GPIO_Output |
||||
PC14-OSC32_IN.Mode=LSE-External-Oscillator |
||||
PC14-OSC32_IN.Signal=RCC_OSC32_IN |
||||
PC15-OSC32_OUT.Mode=LSE-External-Oscillator |
||||
PC15-OSC32_OUT.Signal=RCC_OSC32_OUT |
||||
PD0-OSC_IN.Mode=HSE-External-Oscillator |
||||
PD0-OSC_IN.Signal=RCC_OSC_IN |
||||
PD1-OSC_OUT.Mode=HSE-External-Oscillator |
||||
PD1-OSC_OUT.Signal=RCC_OSC_OUT |
||||
PinOutPanel.RotationAngle=0 |
||||
ProjectManager.AskForMigrate=true |
||||
ProjectManager.BackupPrevious=false |
||||
ProjectManager.CompilerOptimize=6 |
||||
ProjectManager.ComputerToolchain=false |
||||
ProjectManager.CoupleFile=true |
||||
ProjectManager.CustomerFirmwarePackage= |
||||
ProjectManager.DefaultFWLocation=true |
||||
ProjectManager.DeletePrevious=true |
||||
ProjectManager.DeviceId=STM32F103CBTx |
||||
ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.4 |
||||
ProjectManager.FreePins=false |
||||
ProjectManager.HalAssertFull=true |
||||
ProjectManager.HeapSize=0x200 |
||||
ProjectManager.KeepUserCode=true |
||||
ProjectManager.LastFirmware=true |
||||
ProjectManager.LibraryCopy=1 |
||||
ProjectManager.MainLocation=Core/Src |
||||
ProjectManager.NoMain=false |
||||
ProjectManager.PreviousToolchain=STM32CubeIDE |
||||
ProjectManager.ProjectBuild=false |
||||
ProjectManager.ProjectFileName=BluepillTrouba.ioc |
||||
ProjectManager.ProjectName=BluepillTrouba |
||||
ProjectManager.RegisterCallBack= |
||||
ProjectManager.StackSize=0x400 |
||||
ProjectManager.TargetToolchain=Makefile |
||||
ProjectManager.ToolChainLocation= |
||||
ProjectManager.UnderRoot=false |
||||
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_IWDG_Init-IWDG-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_ADC1_Init-ADC1-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_DMA_Init-DMA-false-HAL-true,8-MX_TIM4_Init-TIM4-false-HAL-true,9-MX_TIM2_Init-TIM2-false-HAL-true |
||||
RCC.ADCFreqValue=12000000 |
||||
RCC.ADCPresc=RCC_ADCPCLK2_DIV6 |
||||
RCC.AHBFreq_Value=72000000 |
||||
RCC.APB1CLKDivider=RCC_HCLK_DIV2 |
||||
RCC.APB1Freq_Value=36000000 |
||||
RCC.APB1TimFreq_Value=72000000 |
||||
RCC.APB2Freq_Value=72000000 |
||||
RCC.APB2TimFreq_Value=72000000 |
||||
RCC.FCLKCortexFreq_Value=72000000 |
||||
RCC.FamilyName=M |
||||
RCC.HCLKFreq_Value=72000000 |
||||
RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value |
||||
RCC.MCOFreq_Value=72000000 |
||||
RCC.PLLCLKFreq_Value=72000000 |
||||
RCC.PLLMCOFreq_Value=36000000 |
||||
RCC.PLLMUL=RCC_PLL_MUL9 |
||||
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE |
||||
RCC.SYSCLKFreq_VALUE=72000000 |
||||
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK |
||||
RCC.TimSysFreq_Value=72000000 |
||||
RCC.USBFreq_Value=72000000 |
||||
RCC.VCOOutput2Freq_Value=8000000 |
||||
SH.ADCx_IN0.0=ADC1_IN0,IN0 |
||||
SH.ADCx_IN0.ConfNb=1 |
||||
SH.ADCx_IN1.0=ADC1_IN1,IN1 |
||||
SH.ADCx_IN1.ConfNb=1 |
||||
SH.S_TIM2_CH1_ETR.0=TIM2_CH1,PWM Generation1 CH1 |
||||
SH.S_TIM2_CH1_ETR.ConfNb=1 |
||||
SH.S_TIM4_CH1.0=TIM4_CH1,Encoder_Interface |
||||
SH.S_TIM4_CH1.ConfNb=1 |
||||
SH.S_TIM4_CH2.0=TIM4_CH2,Encoder_Interface |
||||
SH.S_TIM4_CH2.ConfNb=1 |
||||
SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8 |
||||
SPI1.CalculateBaudRate=9.0 MBits/s |
||||
SPI1.Direction=SPI_DIRECTION_2LINES |
||||
SPI1.IPParameters=VirtualType,Mode,Direction,BaudRatePrescaler,CalculateBaudRate |
||||
SPI1.Mode=SPI_MODE_MASTER |
||||
SPI1.VirtualType=VM_MASTER |
||||
TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 |
||||
TIM2.IPParameters=Channel-PWM Generation1 CH1,Prescaler |
||||
TIM2.Prescaler=2 |
||||
USART1.IPParameters=VirtualMode,Mode |
||||
USART1.Mode=MODE_TX_RX |
||||
USART1.VirtualMode=VM_ASYNC |
||||
VP_ADC1_TempSens_Input.Mode=IN-TempSens |
||||
VP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input |
||||
VP_ADC1_Vref_Input.Mode=IN-Vrefint |
||||
VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input |
||||
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 |
||||
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 |
||||
VP_IWDG_VS_IWDG.Mode=IWDG_Activate |
||||
VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG |
||||
VP_SYS_VS_ND.Mode=No_Debug |
||||
VP_SYS_VS_ND.Signal=SYS_VS_ND |
||||
VP_SYS_VS_tim1.Mode=TIM1 |
||||
VP_SYS_VS_tim1.Signal=SYS_VS_tim1 |
||||
VP_TIM2_VS_ClockSourceINT.Mode=Internal |
||||
VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT |
||||
board=custom |
||||
@ -0,0 +1,154 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1 |
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of |
||||
* this software and associated documentation files (the "Software"), to deal in |
||||
* the Software without restriction, including without limitation the rights to |
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of |
||||
* the Software, and to permit persons to whom the Software is furnished to do so, |
||||
* subject to the following conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be included in all |
||||
* copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS |
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR |
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER |
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
||||
* |
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
* |
||||
* 1 tab == 4 spaces! |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
|
||||
#ifndef FREERTOS_CONFIG_H |
||||
#define FREERTOS_CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions. |
||||
* |
||||
* These definitions should be adjusted for your particular hardware and |
||||
* application requirements. |
||||
* |
||||
* These parameters and more are described within the 'configuration' section of the |
||||
* FreeRTOS API documentation available on the FreeRTOS.org web site. |
||||
* |
||||
* See http://www.freertos.org/a00110.html
|
||||
*----------------------------------------------------------*/ |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
/* Section where include file can be added */ |
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Ensure definitions are only used by the compiler, and not by the assembler. */ |
||||
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) |
||||
#include <stdint.h> |
||||
extern uint32_t SystemCoreClock; |
||||
#endif |
||||
#define configUSE_PREEMPTION 1 |
||||
#define configSUPPORT_STATIC_ALLOCATION 1 |
||||
#define configSUPPORT_DYNAMIC_ALLOCATION 1 |
||||
#define configUSE_IDLE_HOOK 0 |
||||
#define configUSE_TICK_HOOK 0 |
||||
#define configCPU_CLOCK_HZ ( SystemCoreClock ) |
||||
#define configTICK_RATE_HZ ((TickType_t)1000) |
||||
#define configMAX_PRIORITIES ( 56 ) |
||||
#define configMINIMAL_STACK_SIZE ((uint16_t)128) |
||||
#define configTOTAL_HEAP_SIZE ((size_t)3072) |
||||
#define configMAX_TASK_NAME_LEN ( 16 ) |
||||
#define configUSE_TRACE_FACILITY 1 |
||||
#define configUSE_16_BIT_TICKS 0 |
||||
#define configUSE_MUTEXES 1 |
||||
#define configQUEUE_REGISTRY_SIZE 8 |
||||
#define configCHECK_FOR_STACK_OVERFLOW 2 |
||||
#define configUSE_RECURSIVE_MUTEXES 1 |
||||
#define configUSE_MALLOC_FAILED_HOOK 1 |
||||
#define configUSE_COUNTING_SEMAPHORES 1 |
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 |
||||
|
||||
/* Co-routine definitions. */ |
||||
#define configUSE_CO_ROUTINES 0 |
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) |
||||
|
||||
/* Software timer definitions. */ |
||||
#define configUSE_TIMERS 1 |
||||
#define configTIMER_TASK_PRIORITY ( 2 ) |
||||
#define configTIMER_QUEUE_LENGTH 10 |
||||
#define configTIMER_TASK_STACK_DEPTH 256 |
||||
|
||||
/* The following flag must be enabled only when using newlib */ |
||||
#define configUSE_NEWLIB_REENTRANT 1 |
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */ |
||||
#define INCLUDE_vTaskPrioritySet 1 |
||||
#define INCLUDE_uxTaskPriorityGet 1 |
||||
#define INCLUDE_vTaskDelete 1 |
||||
#define INCLUDE_vTaskCleanUpResources 0 |
||||
#define INCLUDE_vTaskSuspend 1 |
||||
#define INCLUDE_vTaskDelayUntil 1 |
||||
#define INCLUDE_vTaskDelay 1 |
||||
#define INCLUDE_xTaskGetSchedulerState 1 |
||||
#define INCLUDE_xTimerPendFunctionCall 1 |
||||
#define INCLUDE_xQueueGetMutexHolder 1 |
||||
#define INCLUDE_uxTaskGetStackHighWaterMark 1 |
||||
#define INCLUDE_eTaskGetState 1 |
||||
|
||||
/*
|
||||
* The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used |
||||
* by the application thus the correct define need to be enabled below |
||||
*/ |
||||
#define USE_FreeRTOS_HEAP_4 |
||||
|
||||
/* Cortex-M specific definitions. */ |
||||
#ifdef __NVIC_PRIO_BITS |
||||
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ |
||||
#define configPRIO_BITS __NVIC_PRIO_BITS |
||||
#else |
||||
#define configPRIO_BITS 4 |
||||
#endif |
||||
|
||||
/* The lowest interrupt priority that can be used in a call to a "set priority"
|
||||
function. */ |
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 |
||||
|
||||
/* The highest interrupt priority that can be used by any interrupt service
|
||||
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL |
||||
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER |
||||
PRIORITY THAN THIS! (higher priorities are lower numeric values. */ |
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 |
||||
|
||||
/* Interrupt priorities used by the kernel port layer itself. These are generic
|
||||
to all Cortex-M ports, and do not rely on any particular library functions. */ |
||||
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) |
||||
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
|
||||
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) |
||||
|
||||
/* Normal assert() semantics without relying on the provision of an assert.h
|
||||
header file. */ |
||||
/* USER CODE BEGIN 1 */ |
||||
#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} |
||||
/* USER CODE END 1 */ |
||||
|
||||
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
|
||||
standard names. */ |
||||
#define vPortSVCHandler SVC_Handler |
||||
#define xPortPendSVHandler PendSV_Handler |
||||
|
||||
/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick,
|
||||
to prevent overwriting SysTick_Handler defined within STM32Cube HAL */ |
||||
|
||||
#define xPortSysTickHandler SysTick_Handler |
||||
|
||||
/* USER CODE BEGIN Defines */ |
||||
/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ |
||||
/* USER CODE END Defines */ |
||||
|
||||
#endif /* FREERTOS_CONFIG_H */ |
||||
@ -0,0 +1,55 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file adc.h |
||||
* @brief This file contains all the function prototypes for |
||||
* the adc.c file |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __ADC_H__ |
||||
#define __ADC_H__ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
extern ADC_HandleTypeDef hadc1; |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
|
||||
extern DMA_HandleTypeDef hdma_adc1; |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
void MX_ADC1_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __ADC_H__ */ |
||||
|
||||
@ -0,0 +1,52 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file dma.h |
||||
* @brief This file contains all the function prototypes for |
||||
* the dma.c file |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __DMA_H__ |
||||
#define __DMA_H__ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
|
||||
/* DMA memory to memory transfer handles -------------------------------------*/ |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
void MX_DMA_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __DMA_H__ */ |
||||
|
||||
@ -0,0 +1,49 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file gpio.h |
||||
* @brief This file contains all the function prototypes for |
||||
* the gpio.c file |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __GPIO_H__ |
||||
#define __GPIO_H__ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
void MX_GPIO_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
#endif /*__ GPIO_H__ */ |
||||
|
||||
@ -0,0 +1,52 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file iwdg.h |
||||
* @brief This file contains all the function prototypes for |
||||
* the iwdg.c file |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __IWDG_H__ |
||||
#define __IWDG_H__ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
extern IWDG_HandleTypeDef hiwdg; |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
void MX_IWDG_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __IWDG_H__ */ |
||||
|
||||
@ -0,0 +1,94 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file : main.h |
||||
* @brief : Header for main.c file. |
||||
* This file contains the common defines of the application. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __MAIN_H |
||||
#define __MAIN_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/* Private includes ----------------------------------------------------------*/ |
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN ET */ |
||||
|
||||
/* USER CODE END ET */ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/* USER CODE BEGIN EC */ |
||||
|
||||
/* USER CODE END EC */ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN EM */ |
||||
|
||||
/* USER CODE END EM */ |
||||
|
||||
/* Exported functions prototypes ---------------------------------------------*/ |
||||
void Error_Handler(void); |
||||
|
||||
/* USER CODE BEGIN EFP */ |
||||
|
||||
/* USER CODE END EFP */ |
||||
|
||||
/* Private defines -----------------------------------------------------------*/ |
||||
#define LED_Pin GPIO_PIN_13 |
||||
#define LED_GPIO_Port GPIOC |
||||
#define ADC_PT100_Pin GPIO_PIN_0 |
||||
#define ADC_PT100_GPIO_Port GPIOA |
||||
#define ADC_SENSR_Pin GPIO_PIN_1 |
||||
#define ADC_SENSR_GPIO_Port GPIOA |
||||
#define OLED_RST_Pin GPIO_PIN_3 |
||||
#define OLED_RST_GPIO_Port GPIOA |
||||
#define OLED_DC_Pin GPIO_PIN_4 |
||||
#define OLED_DC_GPIO_Port GPIOA |
||||
#define OLED_SCLK_Pin GPIO_PIN_5 |
||||
#define OLED_SCLK_GPIO_Port GPIOA |
||||
#define OLED_CS_Pin GPIO_PIN_6 |
||||
#define OLED_CS_GPIO_Port GPIOA |
||||
#define OLED_MOSI_Pin GPIO_PIN_7 |
||||
#define OLED_MOSI_GPIO_Port GPIOA |
||||
#define HEATER_Pin GPIO_PIN_11 |
||||
#define HEATER_GPIO_Port GPIOB |
||||
#define BUZZER_Pin GPIO_PIN_15 |
||||
#define BUZZER_GPIO_Port GPIOA |
||||
#define KNOB_PUSH_Pin GPIO_PIN_5 |
||||
#define KNOB_PUSH_GPIO_Port GPIOB |
||||
#define KNOB_B_Pin GPIO_PIN_6 |
||||
#define KNOB_B_GPIO_Port GPIOB |
||||
#define KNOB_A_Pin GPIO_PIN_7 |
||||
#define KNOB_A_GPIO_Port GPIOB |
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __MAIN_H */ |
||||
@ -0,0 +1,19 @@ |
||||
//
|
||||
// Created by MightyPork on 2022/12/28.
|
||||
//
|
||||
|
||||
#ifndef TEST_PROJECT_OLED_H |
||||
#define TEST_PROJECT_OLED_H |
||||
|
||||
#include <stdint.h> |
||||
#include <stddef.h> |
||||
|
||||
void oled_init(); |
||||
void oled_reset(); |
||||
void oled_command(uint8_t cmd); |
||||
void oled_command16(uint8_t cmd, uint8_t arg); |
||||
void oled_invert(bool invert); |
||||
|
||||
void oled_data(uint8_t *data, size_t len); |
||||
|
||||
#endif //TEST_PROJECT_OLED_H
|
||||
@ -0,0 +1,52 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file spi.h |
||||
* @brief This file contains all the function prototypes for |
||||
* the spi.c file |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __SPI_H__ |
||||
#define __SPI_H__ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
extern SPI_HandleTypeDef hspi1; |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
void MX_SPI1_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __SPI_H__ */ |
||||
|
||||
@ -0,0 +1,391 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_conf.h |
||||
* @brief HAL configuration file. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2017 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_CONF_H |
||||
#define __STM32F1xx_HAL_CONF_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/* ########################## Module Selection ############################## */ |
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver |
||||
*/ |
||||
|
||||
#define HAL_MODULE_ENABLED |
||||
#define HAL_ADC_MODULE_ENABLED |
||||
/*#define HAL_CRYP_MODULE_ENABLED */ |
||||
/*#define HAL_CAN_MODULE_ENABLED */ |
||||
/*#define HAL_CAN_LEGACY_MODULE_ENABLED */ |
||||
/*#define HAL_CEC_MODULE_ENABLED */ |
||||
/*#define HAL_CORTEX_MODULE_ENABLED */ |
||||
/*#define HAL_CRC_MODULE_ENABLED */ |
||||
/*#define HAL_DAC_MODULE_ENABLED */ |
||||
#define HAL_DMA_MODULE_ENABLED |
||||
/*#define HAL_ETH_MODULE_ENABLED */ |
||||
/*#define HAL_FLASH_MODULE_ENABLED */ |
||||
#define HAL_GPIO_MODULE_ENABLED |
||||
/*#define HAL_I2C_MODULE_ENABLED */ |
||||
/*#define HAL_I2S_MODULE_ENABLED */ |
||||
/*#define HAL_IRDA_MODULE_ENABLED */ |
||||
#define HAL_IWDG_MODULE_ENABLED |
||||
/*#define HAL_NOR_MODULE_ENABLED */ |
||||
/*#define HAL_NAND_MODULE_ENABLED */ |
||||
/*#define HAL_PCCARD_MODULE_ENABLED */ |
||||
/*#define HAL_PCD_MODULE_ENABLED */ |
||||
/*#define HAL_HCD_MODULE_ENABLED */ |
||||
/*#define HAL_PWR_MODULE_ENABLED */ |
||||
/*#define HAL_RCC_MODULE_ENABLED */ |
||||
/*#define HAL_RTC_MODULE_ENABLED */ |
||||
/*#define HAL_SD_MODULE_ENABLED */ |
||||
/*#define HAL_MMC_MODULE_ENABLED */ |
||||
/*#define HAL_SDRAM_MODULE_ENABLED */ |
||||
/*#define HAL_SMARTCARD_MODULE_ENABLED */ |
||||
#define HAL_SPI_MODULE_ENABLED |
||||
/*#define HAL_SRAM_MODULE_ENABLED */ |
||||
#define HAL_TIM_MODULE_ENABLED |
||||
#define HAL_UART_MODULE_ENABLED |
||||
/*#define HAL_USART_MODULE_ENABLED */ |
||||
/*#define HAL_WWDG_MODULE_ENABLED */ |
||||
|
||||
#define HAL_CORTEX_MODULE_ENABLED |
||||
#define HAL_DMA_MODULE_ENABLED |
||||
#define HAL_FLASH_MODULE_ENABLED |
||||
#define HAL_EXTI_MODULE_ENABLED |
||||
#define HAL_GPIO_MODULE_ENABLED |
||||
#define HAL_PWR_MODULE_ENABLED |
||||
#define HAL_RCC_MODULE_ENABLED |
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/ |
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application. |
||||
* This value is used by the RCC HAL module to compute the system frequency |
||||
* (when HSE is used as system clock source, directly or through the PLL). |
||||
*/ |
||||
#if !defined (HSE_VALUE) |
||||
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ |
||||
#endif /* HSE_VALUE */ |
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT) |
||||
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ |
||||
#endif /* HSE_STARTUP_TIMEOUT */ |
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value. |
||||
* This value is used by the RCC HAL module to compute the system frequency |
||||
* (when HSI is used as system clock source, directly or through the PLL). |
||||
*/ |
||||
#if !defined (HSI_VALUE) |
||||
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/ |
||||
#endif /* HSI_VALUE */ |
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value. |
||||
*/ |
||||
#if !defined (LSI_VALUE) |
||||
#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ |
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz |
||||
The real value may vary depending on the variations |
||||
in voltage and temperature. */ |
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value. |
||||
* This value is used by the UART, RTC HAL module to compute the system frequency |
||||
*/ |
||||
#if !defined (LSE_VALUE) |
||||
#define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ |
||||
#endif /* LSE_VALUE */ |
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT) |
||||
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ |
||||
#endif /* LSE_STARTUP_TIMEOUT */ |
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */ |
||||
|
||||
/* ########################### System Configuration ######################### */ |
||||
/**
|
||||
* @brief This is the HAL system configuration section |
||||
*/ |
||||
#define VDD_VALUE 3300U /*!< Value of VDD in mv */ |
||||
#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */ |
||||
#define USE_RTOS 0U |
||||
#define PREFETCH_ENABLE 1U |
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ |
||||
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ |
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ |
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ |
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ |
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ |
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ |
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ |
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ |
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ |
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ |
||||
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ |
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ |
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ |
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ |
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ |
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ |
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ |
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ |
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ |
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ |
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ |
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ |
||||
|
||||
/* ########################## Assert Selection ############################## */ |
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the |
||||
* HAL drivers code |
||||
*/ |
||||
#define USE_FULL_ASSERT 1U |
||||
|
||||
/* ################## Ethernet peripheral configuration ##################### */ |
||||
|
||||
/* Section 1 : Ethernet peripheral configuration */ |
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ |
||||
#define MAC_ADDR0 2U |
||||
#define MAC_ADDR1 0U |
||||
#define MAC_ADDR2 0U |
||||
#define MAC_ADDR3 0U |
||||
#define MAC_ADDR4 0U |
||||
#define MAC_ADDR5 0U |
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */ |
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ |
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ |
||||
#define ETH_RXBUFNB 8U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ |
||||
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ |
||||
|
||||
/* Section 2: PHY configuration section */ |
||||
|
||||
/* DP83848_PHY_ADDRESS Address*/ |
||||
#define DP83848_PHY_ADDRESS 0x01U |
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ |
||||
#define PHY_RESET_DELAY 0x000000FFU |
||||
/* PHY Configuration delay */ |
||||
#define PHY_CONFIG_DELAY 0x00000FFFU |
||||
|
||||
#define PHY_READ_TO 0x0000FFFFU |
||||
#define PHY_WRITE_TO 0x0000FFFFU |
||||
|
||||
/* Section 3: Common PHY Registers */ |
||||
|
||||
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ |
||||
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ |
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ |
||||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ |
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ |
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ |
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ |
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ |
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ |
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ |
||||
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ |
||||
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ |
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ |
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ |
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ |
||||
|
||||
/* Section 4: Extended PHY Registers */ |
||||
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ |
||||
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ |
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ |
||||
|
||||
/* ################## SPI peripheral configuration ########################## */ |
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver |
||||
* Deactivated: CRC code cleaned from driver |
||||
*/ |
||||
|
||||
#define USE_SPI_CRC 0U |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
/**
|
||||
* @brief Include module's header file |
||||
*/ |
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_rcc.h" |
||||
#endif /* HAL_RCC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_gpio.h" |
||||
#endif /* HAL_GPIO_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_exti.h" |
||||
#endif /* HAL_EXTI_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_dma.h" |
||||
#endif /* HAL_DMA_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_eth.h" |
||||
#endif /* HAL_ETH_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_can.h" |
||||
#endif /* HAL_CAN_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED |
||||
#include "Legacy/stm32f1xx_hal_can_legacy.h" |
||||
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_cec.h" |
||||
#endif /* HAL_CEC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_cortex.h" |
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_adc.h" |
||||
#endif /* HAL_ADC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_crc.h" |
||||
#endif /* HAL_CRC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_dac.h" |
||||
#endif /* HAL_DAC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_flash.h" |
||||
#endif /* HAL_FLASH_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_sram.h" |
||||
#endif /* HAL_SRAM_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_nor.h" |
||||
#endif /* HAL_NOR_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_i2c.h" |
||||
#endif /* HAL_I2C_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_i2s.h" |
||||
#endif /* HAL_I2S_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_iwdg.h" |
||||
#endif /* HAL_IWDG_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_pwr.h" |
||||
#endif /* HAL_PWR_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_rtc.h" |
||||
#endif /* HAL_RTC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_PCCARD_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_pccard.h" |
||||
#endif /* HAL_PCCARD_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_sd.h" |
||||
#endif /* HAL_SD_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_nand.h" |
||||
#endif /* HAL_NAND_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_spi.h" |
||||
#endif /* HAL_SPI_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_tim.h" |
||||
#endif /* HAL_TIM_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_uart.h" |
||||
#endif /* HAL_UART_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_usart.h" |
||||
#endif /* HAL_USART_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_irda.h" |
||||
#endif /* HAL_IRDA_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_smartcard.h" |
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_wwdg.h" |
||||
#endif /* HAL_WWDG_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_pcd.h" |
||||
#endif /* HAL_PCD_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_hcd.h" |
||||
#endif /* HAL_HCD_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED |
||||
#include "stm32f1xx_hal_mmc.h" |
||||
#endif /* HAL_MMC_MODULE_ENABLED */ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
#ifdef USE_FULL_ASSERT |
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check. |
||||
* @param expr If expr is false, it calls assert_failed function |
||||
* which reports the name of the source file and the source |
||||
* line number of the call that failed. |
||||
* If expr is true, it returns no value. |
||||
* @retval None |
||||
*/ |
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) |
||||
/* Exported functions ------------------------------------------------------- */ |
||||
void assert_failed(uint8_t* file, uint32_t line); |
||||
#else |
||||
#define assert_param(expr) ((void)0U) |
||||
#endif /* USE_FULL_ASSERT */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F1xx_HAL_CONF_H */ |
||||
|
||||
@ -0,0 +1,65 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_it.h |
||||
* @brief This file contains the headers of the interrupt handlers. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_IT_H |
||||
#define __STM32F1xx_IT_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Private includes ----------------------------------------------------------*/ |
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN ET */ |
||||
|
||||
/* USER CODE END ET */ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/* USER CODE BEGIN EC */ |
||||
|
||||
/* USER CODE END EC */ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN EM */ |
||||
|
||||
/* USER CODE END EM */ |
||||
|
||||
/* Exported functions prototypes ---------------------------------------------*/ |
||||
void NMI_Handler(void); |
||||
void HardFault_Handler(void); |
||||
void MemManage_Handler(void); |
||||
void BusFault_Handler(void); |
||||
void UsageFault_Handler(void); |
||||
void DebugMon_Handler(void); |
||||
void DMA1_Channel1_IRQHandler(void); |
||||
void TIM1_UP_IRQHandler(void); |
||||
/* USER CODE BEGIN EFP */ |
||||
|
||||
/* USER CODE END EFP */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F1xx_IT_H */ |
||||
@ -0,0 +1,57 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file tim.h |
||||
* @brief This file contains all the function prototypes for |
||||
* the tim.c file |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __TIM_H__ |
||||
#define __TIM_H__ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
extern TIM_HandleTypeDef htim2; |
||||
|
||||
extern TIM_HandleTypeDef htim4; |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
void MX_TIM2_Init(void); |
||||
void MX_TIM4_Init(void); |
||||
|
||||
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __TIM_H__ */ |
||||
|
||||
@ -0,0 +1,52 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file usart.h |
||||
* @brief This file contains all the function prototypes for |
||||
* the usart.c file |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __USART_H__ |
||||
#define __USART_H__ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
extern UART_HandleTypeDef huart1; |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
void MX_USART1_UART_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __USART_H__ */ |
||||
|
||||
@ -0,0 +1,171 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file adc.c |
||||
* @brief This file provides code for the configuration |
||||
* of the ADC instances. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "adc.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
ADC_HandleTypeDef hadc1; |
||||
DMA_HandleTypeDef hdma_adc1; |
||||
|
||||
/* ADC1 init function */ |
||||
void MX_ADC1_Init(void) |
||||
{ |
||||
|
||||
/* USER CODE BEGIN ADC1_Init 0 */ |
||||
|
||||
/* USER CODE END ADC1_Init 0 */ |
||||
|
||||
ADC_ChannelConfTypeDef sConfig = {0}; |
||||
|
||||
/* USER CODE BEGIN ADC1_Init 1 */ |
||||
|
||||
/* USER CODE END ADC1_Init 1 */ |
||||
|
||||
/** Common config
|
||||
*/ |
||||
hadc1.Instance = ADC1; |
||||
hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; |
||||
hadc1.Init.ContinuousConvMode = ENABLE; |
||||
hadc1.Init.DiscontinuousConvMode = DISABLE; |
||||
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; |
||||
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; |
||||
hadc1.Init.NbrOfConversion = 4; |
||||
if (HAL_ADC_Init(&hadc1) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
|
||||
/** Configure Regular Channel
|
||||
*/ |
||||
sConfig.Channel = ADC_CHANNEL_0; |
||||
sConfig.Rank = ADC_REGULAR_RANK_1; |
||||
sConfig.SamplingTime = ADC_SAMPLETIME_41CYCLES_5; |
||||
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
|
||||
/** Configure Regular Channel
|
||||
*/ |
||||
sConfig.Channel = ADC_CHANNEL_1; |
||||
sConfig.Rank = ADC_REGULAR_RANK_2; |
||||
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
|
||||
/** Configure Regular Channel
|
||||
*/ |
||||
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; |
||||
sConfig.Rank = ADC_REGULAR_RANK_3; |
||||
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
|
||||
/** Configure Regular Channel
|
||||
*/ |
||||
sConfig.Channel = ADC_CHANNEL_VREFINT; |
||||
sConfig.Rank = ADC_REGULAR_RANK_4; |
||||
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
/* USER CODE BEGIN ADC1_Init 2 */ |
||||
|
||||
/* USER CODE END ADC1_Init 2 */ |
||||
|
||||
} |
||||
|
||||
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) |
||||
{ |
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0}; |
||||
if(adcHandle->Instance==ADC1) |
||||
{ |
||||
/* USER CODE BEGIN ADC1_MspInit 0 */ |
||||
|
||||
/* USER CODE END ADC1_MspInit 0 */ |
||||
/* ADC1 clock enable */ |
||||
__HAL_RCC_ADC1_CLK_ENABLE(); |
||||
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE(); |
||||
/**ADC1 GPIO Configuration
|
||||
PA0-WKUP ------> ADC1_IN0 |
||||
PA1 ------> ADC1_IN1 |
||||
*/ |
||||
GPIO_InitStruct.Pin = ADC_PT100_Pin|ADC_SENSR_Pin; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; |
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); |
||||
|
||||
/* ADC1 DMA Init */ |
||||
/* ADC1 Init */ |
||||
hdma_adc1.Instance = DMA1_Channel1; |
||||
hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; |
||||
hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; |
||||
hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; |
||||
hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; |
||||
hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; |
||||
hdma_adc1.Init.Mode = DMA_CIRCULAR; |
||||
hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; |
||||
if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
|
||||
__HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); |
||||
|
||||
/* USER CODE BEGIN ADC1_MspInit 1 */ |
||||
|
||||
/* USER CODE END ADC1_MspInit 1 */ |
||||
} |
||||
} |
||||
|
||||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) |
||||
{ |
||||
|
||||
if(adcHandle->Instance==ADC1) |
||||
{ |
||||
/* USER CODE BEGIN ADC1_MspDeInit 0 */ |
||||
|
||||
/* USER CODE END ADC1_MspDeInit 0 */ |
||||
/* Peripheral clock disable */ |
||||
__HAL_RCC_ADC1_CLK_DISABLE(); |
||||
|
||||
/**ADC1 GPIO Configuration
|
||||
PA0-WKUP ------> ADC1_IN0 |
||||
PA1 ------> ADC1_IN1 |
||||
*/ |
||||
HAL_GPIO_DeInit(GPIOA, ADC_PT100_Pin|ADC_SENSR_Pin); |
||||
|
||||
/* ADC1 DMA DeInit */ |
||||
HAL_DMA_DeInit(adcHandle->DMA_Handle); |
||||
/* USER CODE BEGIN ADC1_MspDeInit 1 */ |
||||
|
||||
/* USER CODE END ADC1_MspDeInit 1 */ |
||||
} |
||||
} |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
@ -0,0 +1,55 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file dma.c |
||||
* @brief This file provides code for the configuration |
||||
* of all the requested memory to memory DMA transfers. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "dma.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
/*----------------------------------------------------------------------------*/ |
||||
/* Configure DMA */ |
||||
/*----------------------------------------------------------------------------*/ |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
|
||||
/**
|
||||
* Enable DMA controller clock |
||||
*/ |
||||
void MX_DMA_Init(void) |
||||
{ |
||||
|
||||
/* DMA controller clock enable */ |
||||
__HAL_RCC_DMA1_CLK_ENABLE(); |
||||
|
||||
/* DMA interrupt init */ |
||||
/* DMA1_Channel1_IRQn interrupt configuration */ |
||||
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0); |
||||
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); |
||||
|
||||
} |
||||
|
||||
/* USER CODE BEGIN 2 */ |
||||
|
||||
/* USER CODE END 2 */ |
||||
|
||||
@ -0,0 +1,195 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : freertos.c |
||||
* Description : Code for freertos applications |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "FreeRTOS.h" |
||||
#include "task.h" |
||||
#include "main.h" |
||||
#include "cmsis_os.h" |
||||
|
||||
/* Private includes ----------------------------------------------------------*/ |
||||
/* USER CODE BEGIN Includes */ |
||||
#include "ufb/framebuffer.h" |
||||
#include "iwdg.h" |
||||
#include "tim.h" |
||||
#include "adc.h" |
||||
#include "oled.h" |
||||
#include <stdio.h> |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* USER CODE BEGIN PTD */ |
||||
|
||||
/* USER CODE END PTD */ |
||||
|
||||
/* Private define ------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN PD */ |
||||
|
||||
/* USER CODE END PD */ |
||||
|
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN PM */ |
||||
|
||||
/* USER CODE END PM */ |
||||
|
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* USER CODE BEGIN Variables */ |
||||
|
||||
static volatile uint16_t adc_values[4]; |
||||
|
||||
/* USER CODE END Variables */ |
||||
/* Definitions for defaultTask */ |
||||
osThreadId_t defaultTaskHandle; |
||||
const osThreadAttr_t defaultTask_attributes = { |
||||
.name = "defaultTask", |
||||
.stack_size = 128 * 4, |
||||
.priority = (osPriority_t) osPriorityNormal, |
||||
}; |
||||
|
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* USER CODE BEGIN FunctionPrototypes */ |
||||
|
||||
/* USER CODE END FunctionPrototypes */ |
||||
|
||||
void StartDefaultTask(void *argument); |
||||
|
||||
void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ |
||||
|
||||
/* Hook prototypes */ |
||||
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); |
||||
void vApplicationMallocFailedHook(void); |
||||
|
||||
/* USER CODE BEGIN 4 */ |
||||
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) |
||||
{ |
||||
/* Run time stack overflow checking is performed if
|
||||
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is |
||||
called if a stack overflow is detected. */ |
||||
} |
||||
/* USER CODE END 4 */ |
||||
|
||||
/* USER CODE BEGIN 5 */ |
||||
void vApplicationMallocFailedHook(void) |
||||
{ |
||||
/* vApplicationMallocFailedHook() will only be called if
|
||||
configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook |
||||
function that will get called if a call to pvPortMalloc() fails. |
||||
pvPortMalloc() is called internally by the kernel whenever a task, queue, |
||||
timer or semaphore is created. It is also called by various parts of the |
||||
demo application. If heap_1.c or heap_2.c are used, then the size of the |
||||
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in |
||||
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used |
||||
to query the size of free heap space that remains (although it does not |
||||
provide information on how the remaining heap might be fragmented). */ |
||||
} |
||||
/* USER CODE END 5 */ |
||||
|
||||
/**
|
||||
* @brief FreeRTOS initialization |
||||
* @param None |
||||
* @retval None |
||||
*/ |
||||
void MX_FREERTOS_Init(void) { |
||||
/* USER CODE BEGIN Init */ |
||||
|
||||
/* USER CODE END Init */ |
||||
|
||||
/* USER CODE BEGIN RTOS_MUTEX */ |
||||
/* add mutexes, ... */ |
||||
/* USER CODE END RTOS_MUTEX */ |
||||
|
||||
/* USER CODE BEGIN RTOS_SEMAPHORES */ |
||||
/* add semaphores, ... */ |
||||
/* USER CODE END RTOS_SEMAPHORES */ |
||||
|
||||
/* USER CODE BEGIN RTOS_TIMERS */ |
||||
/* start timers, add new ones, ... */ |
||||
/* USER CODE END RTOS_TIMERS */ |
||||
|
||||
/* USER CODE BEGIN RTOS_QUEUES */ |
||||
/* add queues, ... */ |
||||
/* USER CODE END RTOS_QUEUES */ |
||||
|
||||
/* Create the thread(s) */ |
||||
/* creation of defaultTask */ |
||||
defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); |
||||
|
||||
/* USER CODE BEGIN RTOS_THREADS */ |
||||
/* add threads, ... */ |
||||
/* USER CODE END RTOS_THREADS */ |
||||
|
||||
/* USER CODE BEGIN RTOS_EVENTS */ |
||||
/* add events, ... */ |
||||
/* USER CODE END RTOS_EVENTS */ |
||||
|
||||
} |
||||
|
||||
/* USER CODE BEGIN Header_StartDefaultTask */ |
||||
/**
|
||||
* @brief Function implementing the defaultTask thread. |
||||
* @param argument: Not used |
||||
* @retval None |
||||
*/ |
||||
/* USER CODE END Header_StartDefaultTask */ |
||||
void StartDefaultTask(void *argument) |
||||
{ |
||||
/* USER CODE BEGIN StartDefaultTask */ |
||||
|
||||
fb_frame(0, 0, 20, 20, 1, 1); |
||||
|
||||
fb_blit(); |
||||
|
||||
HAL_ADC_Start_DMA(&hadc1, (uint32_t*)(void*)adc_values, 4); |
||||
HAL_TIM_Encoder_Start(&htim4, TIM_CHANNEL_ALL); |
||||
|
||||
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); |
||||
|
||||
/* Infinite loop */ |
||||
bool invert = 0; |
||||
for(;;) |
||||
{ |
||||
HAL_GPIO_TogglePin(LED_GPIO_Port, LED_Pin); |
||||
|
||||
uint16_t knob = htim4.Instance->CNT; |
||||
|
||||
printf("tick. knob %d (B=%d), adc %d %d %d %d\r\n", (int) knob, HAL_GPIO_ReadPin(KNOB_PUSH_GPIO_Port, KNOB_PUSH_Pin), |
||||
adc_values[0], adc_values[1], adc_values[2], adc_values[3]); |
||||
|
||||
invert = !invert; |
||||
fb_frame(0, 0, 20, 20, 2, invert); |
||||
fb_blit(); |
||||
|
||||
osDelay(250); |
||||
|
||||
htim2.Instance->ARR = 12000 + (int16_t)knob * 100; |
||||
htim2.Instance->CCR1 = htim2.Instance->ARR/2; |
||||
osDelay(50); |
||||
htim2.Instance->ARR = 0; |
||||
|
||||
HAL_IWDG_Refresh(&hiwdg); |
||||
} |
||||
/* USER CODE END StartDefaultTask */ |
||||
} |
||||
|
||||
/* Private application code --------------------------------------------------*/ |
||||
/* USER CODE BEGIN Application */ |
||||
|
||||
/* USER CODE END Application */ |
||||
|
||||
@ -0,0 +1,93 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file gpio.c |
||||
* @brief This file provides code for the configuration |
||||
* of all used GPIO pins. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "gpio.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
/*----------------------------------------------------------------------------*/ |
||||
/* Configure GPIO */ |
||||
/*----------------------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
|
||||
/** Configure pins as
|
||||
* Analog |
||||
* Input |
||||
* Output |
||||
* EVENT_OUT |
||||
* EXTI |
||||
*/ |
||||
void MX_GPIO_Init(void) |
||||
{ |
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0}; |
||||
|
||||
/* GPIO Ports Clock Enable */ |
||||
__HAL_RCC_GPIOC_CLK_ENABLE(); |
||||
__HAL_RCC_GPIOD_CLK_ENABLE(); |
||||
__HAL_RCC_GPIOA_CLK_ENABLE(); |
||||
__HAL_RCC_GPIOB_CLK_ENABLE(); |
||||
|
||||
/*Configure GPIO pin Output Level */ |
||||
HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); |
||||
|
||||
/*Configure GPIO pin Output Level */ |
||||
HAL_GPIO_WritePin(GPIOA, OLED_RST_Pin|OLED_DC_Pin|OLED_CS_Pin, GPIO_PIN_RESET); |
||||
|
||||
/*Configure GPIO pin Output Level */ |
||||
HAL_GPIO_WritePin(HEATER_GPIO_Port, HEATER_Pin, GPIO_PIN_RESET); |
||||
|
||||
/*Configure GPIO pin : PtPin */ |
||||
GPIO_InitStruct.Pin = LED_Pin; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; |
||||
HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); |
||||
|
||||
/*Configure GPIO pins : PAPin PAPin PAPin */ |
||||
GPIO_InitStruct.Pin = OLED_RST_Pin|OLED_DC_Pin|OLED_CS_Pin; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; |
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); |
||||
|
||||
/*Configure GPIO pin : PtPin */ |
||||
GPIO_InitStruct.Pin = HEATER_Pin; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; |
||||
HAL_GPIO_Init(HEATER_GPIO_Port, &GPIO_InitStruct); |
||||
|
||||
/*Configure GPIO pin : PtPin */ |
||||
GPIO_InitStruct.Pin = KNOB_PUSH_Pin; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; |
||||
GPIO_InitStruct.Pull = GPIO_PULLUP; |
||||
HAL_GPIO_Init(KNOB_PUSH_GPIO_Port, &GPIO_InitStruct); |
||||
|
||||
} |
||||
|
||||
/* USER CODE BEGIN 2 */ |
||||
|
||||
/* USER CODE END 2 */ |
||||
@ -0,0 +1,55 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file iwdg.c |
||||
* @brief This file provides code for the configuration |
||||
* of the IWDG instances. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "iwdg.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
IWDG_HandleTypeDef hiwdg; |
||||
|
||||
/* IWDG init function */ |
||||
void MX_IWDG_Init(void) |
||||
{ |
||||
|
||||
/* USER CODE BEGIN IWDG_Init 0 */ |
||||
|
||||
/* USER CODE END IWDG_Init 0 */ |
||||
|
||||
/* USER CODE BEGIN IWDG_Init 1 */ |
||||
|
||||
/* USER CODE END IWDG_Init 1 */ |
||||
hiwdg.Instance = IWDG; |
||||
hiwdg.Init.Prescaler = IWDG_PRESCALER_256; |
||||
hiwdg.Init.Reload = 624; |
||||
if (HAL_IWDG_Init(&hiwdg) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
/* USER CODE BEGIN IWDG_Init 2 */ |
||||
|
||||
/* USER CODE END IWDG_Init 2 */ |
||||
|
||||
} |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
@ -0,0 +1,238 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file : main.c |
||||
* @brief : Main program body |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
#include "cmsis_os.h" |
||||
#include "adc.h" |
||||
#include "dma.h" |
||||
#include "iwdg.h" |
||||
#include "spi.h" |
||||
#include "tim.h" |
||||
#include "usart.h" |
||||
#include "gpio.h" |
||||
|
||||
/* Private includes ----------------------------------------------------------*/ |
||||
/* USER CODE BEGIN Includes */ |
||||
#include "ufb/framebuffer.h" |
||||
#include "oled.h" |
||||
|
||||
#include <stdio.h> |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* USER CODE BEGIN PTD */ |
||||
|
||||
/* USER CODE END PTD */ |
||||
|
||||
/* Private define ------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN PD */ |
||||
/* USER CODE END PD */ |
||||
|
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN PM */ |
||||
|
||||
/* USER CODE END PM */ |
||||
|
||||
/* Private variables ---------------------------------------------------------*/ |
||||
|
||||
/* USER CODE BEGIN PV */ |
||||
|
||||
/* USER CODE END PV */ |
||||
|
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
void SystemClock_Config(void); |
||||
void MX_FREERTOS_Init(void); |
||||
/* USER CODE BEGIN PFP */ |
||||
|
||||
/* USER CODE END PFP */ |
||||
|
||||
/* Private user code ---------------------------------------------------------*/ |
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
/**
|
||||
* @brief The application entry point. |
||||
* @retval int |
||||
*/ |
||||
int main(void) |
||||
{ |
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
|
||||
/* MCU Configuration--------------------------------------------------------*/ |
||||
|
||||
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */ |
||||
HAL_Init(); |
||||
|
||||
/* USER CODE BEGIN Init */ |
||||
|
||||
/* USER CODE END Init */ |
||||
|
||||
/* Configure the system clock */ |
||||
SystemClock_Config(); |
||||
|
||||
/* USER CODE BEGIN SysInit */ |
||||
|
||||
MX_DMA_Init(); |
||||
/* USER CODE END SysInit */ |
||||
|
||||
/* Initialize all configured peripherals */ |
||||
MX_GPIO_Init(); |
||||
MX_IWDG_Init(); |
||||
MX_USART1_UART_Init(); |
||||
MX_ADC1_Init(); |
||||
MX_SPI1_Init(); |
||||
MX_DMA_Init(); |
||||
MX_TIM4_Init(); |
||||
MX_TIM2_Init(); |
||||
/* USER CODE BEGIN 2 */ |
||||
|
||||
printf("periphs inited\r\n"); |
||||
|
||||
oled_init(); |
||||
fb_clear(); |
||||
|
||||
printf("start scheduler\r\n"); |
||||
/* USER CODE END 2 */ |
||||
|
||||
/* Init scheduler */ |
||||
osKernelInitialize(); /* Call init function for freertos objects (in freertos.c) */ |
||||
MX_FREERTOS_Init(); |
||||
|
||||
/* Start scheduler */ |
||||
osKernelStart(); |
||||
|
||||
/* We should never get here as control is now taken by the scheduler */ |
||||
/* Infinite loop */ |
||||
/* USER CODE BEGIN WHILE */ |
||||
while (1) |
||||
{ |
||||
/* USER CODE END WHILE */ |
||||
|
||||
/* USER CODE BEGIN 3 */ |
||||
} |
||||
/* USER CODE END 3 */ |
||||
} |
||||
|
||||
/**
|
||||
* @brief System Clock Configuration |
||||
* @retval None |
||||
*/ |
||||
void SystemClock_Config(void) |
||||
{ |
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
||||
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; |
||||
|
||||
/** Initializes the RCC Oscillators according to the specified parameters
|
||||
* in the RCC_OscInitTypeDef structure. |
||||
*/ |
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; |
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; |
||||
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; |
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
||||
RCC_OscInitStruct.LSIState = RCC_LSI_ON; |
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
||||
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; |
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
|
||||
/** Initializes the CPU, AHB and APB buses clocks
|
||||
*/ |
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |
||||
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; |
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; |
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; |
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; |
||||
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; |
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
} |
||||
|
||||
/* USER CODE BEGIN 4 */ |
||||
|
||||
/* USER CODE END 4 */ |
||||
|
||||
/**
|
||||
* @brief Period elapsed callback in non blocking mode |
||||
* @note This function is called when TIM1 interrupt took place, inside |
||||
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment |
||||
* a global variable "uwTick" used as application time base. |
||||
* @param htim : TIM handle |
||||
* @retval None |
||||
*/ |
||||
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) |
||||
{ |
||||
/* USER CODE BEGIN Callback 0 */ |
||||
|
||||
/* USER CODE END Callback 0 */ |
||||
if (htim->Instance == TIM1) { |
||||
HAL_IncTick(); |
||||
} |
||||
/* USER CODE BEGIN Callback 1 */ |
||||
|
||||
/* USER CODE END Callback 1 */ |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence. |
||||
* @retval None |
||||
*/ |
||||
void Error_Handler(void) |
||||
{ |
||||
/* USER CODE BEGIN Error_Handler_Debug */ |
||||
/* User can add his own implementation to report the HAL error return state */ |
||||
__disable_irq(); |
||||
while (1) |
||||
{ |
||||
} |
||||
/* USER CODE END Error_Handler_Debug */ |
||||
} |
||||
|
||||
#ifdef USE_FULL_ASSERT |
||||
/**
|
||||
* @brief Reports the name of the source file and the source line number |
||||
* where the assert_param error has occurred. |
||||
* @param file: pointer to the source file name |
||||
* @param line: assert_param error line source number |
||||
* @retval None |
||||
*/ |
||||
void assert_failed(uint8_t *file, uint32_t line) |
||||
{ |
||||
/* USER CODE BEGIN 6 */ |
||||
/* User can add his own implementation to report the file name and line number,
|
||||
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ |
||||
/* USER CODE END 6 */ |
||||
} |
||||
#endif /* USE_FULL_ASSERT */ |
||||
@ -0,0 +1,170 @@ |
||||
//
|
||||
// Created by MightyPork on 2022/12/28.
|
||||
//
|
||||
|
||||
#include <stdio.h> |
||||
|
||||
#include "ufb/framebuffer.h" |
||||
#include "gpio.h" |
||||
#include "spi.h" |
||||
|
||||
#define SSD1309_HEIGHT 64 |
||||
|
||||
static inline void cs_select() { |
||||
asm volatile("nop \n nop \n nop"); |
||||
HAL_GPIO_WritePin(OLED_CS_GPIO_Port, OLED_CS_Pin, 0); // Active low
|
||||
asm volatile("nop \n nop \n nop"); |
||||
} |
||||
|
||||
static inline void cs_deselect() { |
||||
asm volatile("nop \n nop \n nop"); |
||||
HAL_GPIO_WritePin(OLED_CS_GPIO_Port, OLED_CS_Pin, 1); |
||||
asm volatile("nop \n nop \n nop"); |
||||
} |
||||
|
||||
static inline void dc_command() { |
||||
HAL_GPIO_WritePin(OLED_DC_GPIO_Port, OLED_DC_Pin, 0); |
||||
} |
||||
|
||||
static inline void dc_data() { |
||||
HAL_GPIO_WritePin(OLED_DC_GPIO_Port, OLED_DC_Pin, 1); |
||||
} |
||||
|
||||
void oled_command16(uint8_t cmd, uint8_t arg) { |
||||
uint8_t buf[2]; |
||||
buf[0] = cmd; |
||||
buf[1] = arg; |
||||
dc_command(); |
||||
cs_select(); |
||||
HAL_SPI_Transmit(&hspi1, buf, 2, 1000); |
||||
cs_deselect(); |
||||
} |
||||
|
||||
void oled_command(uint8_t cmd) { |
||||
dc_command(); |
||||
cs_select(); |
||||
HAL_SPI_Transmit(&hspi1, &cmd, 1, 1000); |
||||
cs_deselect(); |
||||
} |
||||
|
||||
void oled_reset() { |
||||
// Issue a display reset
|
||||
HAL_GPIO_WritePin(OLED_RST_GPIO_Port, OLED_RST_Pin, 0); |
||||
HAL_Delay(1); |
||||
HAL_GPIO_WritePin(OLED_RST_GPIO_Port, OLED_RST_Pin, 1); |
||||
HAL_Delay(1); |
||||
} |
||||
|
||||
void oled_invert(bool invert) { |
||||
if (invert) { |
||||
oled_command(0xA6); |
||||
} else { |
||||
oled_command(0xA7); |
||||
} |
||||
} |
||||
|
||||
void oled_init() { |
||||
oled_reset(); |
||||
|
||||
// simplified display init
|
||||
|
||||
oled_command(0xAE); /* Display off */ |
||||
//oled_command16(0xD5, 0xF0); // set clock speed
|
||||
|
||||
oled_command16(0x20, 0b00); // page addressing mode: 00 - horizontal, 01 vertical, 10 page
|
||||
|
||||
oled_command16(0x81, 0xFF); // contrast
|
||||
|
||||
oled_command(0xAF); /*--turn on SSD1309 panel */ |
||||
|
||||
#if 0 |
||||
|
||||
/* Init OLED */ |
||||
oled_command(0xAE); /* Display off */ |
||||
|
||||
// Configure the display - only setting things that differ from the default:
|
||||
|
||||
|
||||
oled_command16(0x20, 0b10); /* Set Memory Addressing Mode */ |
||||
/* 00,Horizontal Addressing Mode; 01,Vertical Addressing Mode; */ |
||||
/* 10,Page Addressing Mode (RESET); 11,Invalid */ |
||||
|
||||
oled_command(0xB0); /*Set Page Start Address for Page Addressing Mode, B0-B7 */ |
||||
|
||||
#ifdef SSD1309_MIRROR_VERT |
||||
oled_command(0xC1); |
||||
#else |
||||
oled_command(0xC0); |
||||
#endif |
||||
|
||||
// lower nibble is value
|
||||
oled_command(0x00); /*---set low column address 00~0F */ |
||||
|
||||
oled_command(0x10); /*---set high column address 10~1F */ |
||||
|
||||
oled_command(0x40); /*--set start line address - 40~7F */ |
||||
|
||||
oled_command16(0x81, 0x7F); /*--set contrast control register - ? 0xFF */ |
||||
|
||||
#ifdef SSD1309_MIRROR_HORIZ |
||||
oled_command(0xA1); |
||||
#else |
||||
oled_command(0xA0); |
||||
#endif |
||||
|
||||
#ifdef SSD1309_INVERSE_COLOR |
||||
oled_command(0xA7); /*--set inverse color */ |
||||
#else |
||||
oled_command(0xA6); /*--set normal color */ |
||||
#endif |
||||
|
||||
/*--set multiplex ratio(1 to 64) */ |
||||
#if (SSD1309_HEIGHT == 32) |
||||
oled_command16(0xA8, 0x1F); |
||||
#elif (SSD1309_HEIGHT == 64) |
||||
oled_command16(0xA8, 0x3F); |
||||
#else |
||||
#error "bad height" |
||||
#endif |
||||
|
||||
oled_command(0xA4); /* 0xA4, Output follows RAM content;0xa5,Output ignores RAM content */ |
||||
|
||||
oled_command16(0xD3, 0x00); /*-set display offset */ |
||||
|
||||
oled_command16(0xD5, 0xF0); /*--set display clock divide ratio/oscillator frequency */ |
||||
|
||||
oled_command16(0xD9, 0x22); /*--set pre-charge period */ |
||||
|
||||
/*--set com pins hardware configuration */ |
||||
#if (SSD1309_HEIGHT == 32) |
||||
oled_command16(0xDA, 0x02); |
||||
#elif (SSD1309_HEIGHT == 64) |
||||
oled_command16(0xDA, 0x12); |
||||
#else |
||||
#error "bad height" |
||||
#endif |
||||
|
||||
oled_command16(0xDB, 0x34); /*--set vcomh */ |
||||
|
||||
// ??? not listed in the datasheet
|
||||
// oled_command(0x8D); /*--set DC-DC enable */
|
||||
// oled_command(0x14); /* */
|
||||
|
||||
oled_command(0xAF); /*--turn on SSD1309 panel */ |
||||
|
||||
|
||||
oled_command(0xA5); // entire display on - for test
|
||||
|
||||
#endif |
||||
} |
||||
|
||||
void oled_data(uint8_t *data, size_t len) { |
||||
dc_data(); |
||||
cs_select(); |
||||
HAL_SPI_Transmit(&hspi1, data, len, 1000); |
||||
cs_deselect(); |
||||
} |
||||
|
||||
void fb_blit() { |
||||
oled_data(fb, FB_LEN); |
||||
} |
||||
@ -0,0 +1,115 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file spi.c |
||||
* @brief This file provides code for the configuration |
||||
* of the SPI instances. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "spi.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
SPI_HandleTypeDef hspi1; |
||||
|
||||
/* SPI1 init function */ |
||||
void MX_SPI1_Init(void) |
||||
{ |
||||
|
||||
/* USER CODE BEGIN SPI1_Init 0 */ |
||||
|
||||
/* USER CODE END SPI1_Init 0 */ |
||||
|
||||
/* USER CODE BEGIN SPI1_Init 1 */ |
||||
|
||||
/* USER CODE END SPI1_Init 1 */ |
||||
hspi1.Instance = SPI1; |
||||
hspi1.Init.Mode = SPI_MODE_MASTER; |
||||
hspi1.Init.Direction = SPI_DIRECTION_2LINES; |
||||
hspi1.Init.DataSize = SPI_DATASIZE_8BIT; |
||||
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; |
||||
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; |
||||
hspi1.Init.NSS = SPI_NSS_SOFT; |
||||
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; |
||||
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; |
||||
hspi1.Init.TIMode = SPI_TIMODE_DISABLE; |
||||
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; |
||||
hspi1.Init.CRCPolynomial = 10; |
||||
if (HAL_SPI_Init(&hspi1) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
/* USER CODE BEGIN SPI1_Init 2 */ |
||||
|
||||
/* USER CODE END SPI1_Init 2 */ |
||||
|
||||
} |
||||
|
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) |
||||
{ |
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0}; |
||||
if(spiHandle->Instance==SPI1) |
||||
{ |
||||
/* USER CODE BEGIN SPI1_MspInit 0 */ |
||||
|
||||
/* USER CODE END SPI1_MspInit 0 */ |
||||
/* SPI1 clock enable */ |
||||
__HAL_RCC_SPI1_CLK_ENABLE(); |
||||
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE(); |
||||
/**SPI1 GPIO Configuration
|
||||
PA5 ------> SPI1_SCK |
||||
PA7 ------> SPI1_MOSI |
||||
*/ |
||||
GPIO_InitStruct.Pin = OLED_SCLK_Pin|OLED_MOSI_Pin; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; |
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); |
||||
|
||||
/* USER CODE BEGIN SPI1_MspInit 1 */ |
||||
|
||||
/* USER CODE END SPI1_MspInit 1 */ |
||||
} |
||||
} |
||||
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) |
||||
{ |
||||
|
||||
if(spiHandle->Instance==SPI1) |
||||
{ |
||||
/* USER CODE BEGIN SPI1_MspDeInit 0 */ |
||||
|
||||
/* USER CODE END SPI1_MspDeInit 0 */ |
||||
/* Peripheral clock disable */ |
||||
__HAL_RCC_SPI1_CLK_DISABLE(); |
||||
|
||||
/**SPI1 GPIO Configuration
|
||||
PA5 ------> SPI1_SCK |
||||
PA7 ------> SPI1_MOSI |
||||
*/ |
||||
HAL_GPIO_DeInit(GPIOA, OLED_SCLK_Pin|OLED_MOSI_Pin); |
||||
|
||||
/* USER CODE BEGIN SPI1_MspDeInit 1 */ |
||||
|
||||
/* USER CODE END SPI1_MspDeInit 1 */ |
||||
} |
||||
} |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
@ -0,0 +1,87 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_msp.c |
||||
* @brief This file provides code for the MSP Initialization |
||||
* and de-Initialization codes. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* USER CODE BEGIN TD */ |
||||
|
||||
/* USER CODE END TD */ |
||||
|
||||
/* Private define ------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN Define */ |
||||
|
||||
/* USER CODE END Define */ |
||||
|
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN Macro */ |
||||
|
||||
/* USER CODE END Macro */ |
||||
|
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* USER CODE BEGIN PV */ |
||||
|
||||
/* USER CODE END PV */ |
||||
|
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* USER CODE BEGIN PFP */ |
||||
|
||||
/* USER CODE END PFP */ |
||||
|
||||
/* External functions --------------------------------------------------------*/ |
||||
/* USER CODE BEGIN ExternalFunctions */ |
||||
|
||||
/* USER CODE END ExternalFunctions */ |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
/**
|
||||
* Initializes the Global MSP. |
||||
*/ |
||||
void HAL_MspInit(void) |
||||
{ |
||||
/* USER CODE BEGIN MspInit 0 */ |
||||
|
||||
/* USER CODE END MspInit 0 */ |
||||
|
||||
__HAL_RCC_AFIO_CLK_ENABLE(); |
||||
__HAL_RCC_PWR_CLK_ENABLE(); |
||||
|
||||
/* System interrupt init*/ |
||||
/* PendSV_IRQn interrupt configuration */ |
||||
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); |
||||
|
||||
/** DISABLE: JTAG-DP Disabled and SW-DP Disabled
|
||||
*/ |
||||
__HAL_AFIO_REMAP_SWJ_DISABLE(); |
||||
|
||||
/* USER CODE BEGIN MspInit 1 */ |
||||
|
||||
/* USER CODE END MspInit 1 */ |
||||
} |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
@ -0,0 +1,111 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_timebase_TIM.c |
||||
* @brief HAL time base based on the hardware TIM. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
#include "stm32f1xx_hal_tim.h" |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
TIM_HandleTypeDef htim1; |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* Private functions ---------------------------------------------------------*/ |
||||
|
||||
/**
|
||||
* @brief This function configures the TIM1 as a time base source. |
||||
* The time source is configured to have 1ms time base with a dedicated |
||||
* Tick interrupt priority. |
||||
* @note This function is called automatically at the beginning of program after |
||||
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). |
||||
* @param TickPriority: Tick interrupt priority. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) |
||||
{ |
||||
RCC_ClkInitTypeDef clkconfig; |
||||
uint32_t uwTimclock = 0; |
||||
uint32_t uwPrescalerValue = 0; |
||||
uint32_t pFLatency; |
||||
/*Configure the TIM1 IRQ priority */ |
||||
HAL_NVIC_SetPriority(TIM1_UP_IRQn, TickPriority ,0); |
||||
|
||||
/* Enable the TIM1 global Interrupt */ |
||||
HAL_NVIC_EnableIRQ(TIM1_UP_IRQn); |
||||
|
||||
/* Enable TIM1 clock */ |
||||
__HAL_RCC_TIM1_CLK_ENABLE(); |
||||
|
||||
/* Get clock configuration */ |
||||
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); |
||||
|
||||
/* Compute TIM1 clock */ |
||||
uwTimclock = HAL_RCC_GetPCLK2Freq(); |
||||
/* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */ |
||||
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); |
||||
|
||||
/* Initialize TIM1 */ |
||||
htim1.Instance = TIM1; |
||||
|
||||
/* Initialize TIMx peripheral as follow:
|
||||
+ Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base. |
||||
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. |
||||
+ ClockDivision = 0 |
||||
+ Counter direction = Up |
||||
*/ |
||||
htim1.Init.Period = (1000000U / 1000U) - 1U; |
||||
htim1.Init.Prescaler = uwPrescalerValue; |
||||
htim1.Init.ClockDivision = 0; |
||||
htim1.Init.CounterMode = TIM_COUNTERMODE_UP; |
||||
|
||||
if(HAL_TIM_Base_Init(&htim1) == HAL_OK) |
||||
{ |
||||
/* Start the TIM time Base generation in interrupt mode */ |
||||
return HAL_TIM_Base_Start_IT(&htim1); |
||||
} |
||||
|
||||
/* Return function status */ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment. |
||||
* @note Disable the tick increment by disabling TIM1 update interrupt. |
||||
* @param None |
||||
* @retval None |
||||
*/ |
||||
void HAL_SuspendTick(void) |
||||
{ |
||||
/* Disable TIM1 update Interrupt */ |
||||
__HAL_TIM_DISABLE_IT(&htim1, TIM_IT_UPDATE); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Resume Tick increment. |
||||
* @note Enable the tick increment by Enabling TIM1 update interrupt. |
||||
* @param None |
||||
* @retval None |
||||
*/ |
||||
void HAL_ResumeTick(void) |
||||
{ |
||||
/* Enable TIM1 Update interrupt */ |
||||
__HAL_TIM_ENABLE_IT(&htim1, TIM_IT_UPDATE); |
||||
} |
||||
|
||||
@ -0,0 +1,195 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_it.c |
||||
* @brief Interrupt Service Routines. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
#include "stm32f1xx_it.h" |
||||
/* Private includes ----------------------------------------------------------*/ |
||||
/* USER CODE BEGIN Includes */ |
||||
#include <stdio.h> |
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* USER CODE BEGIN TD */ |
||||
|
||||
/* USER CODE END TD */ |
||||
|
||||
/* Private define ------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN PD */ |
||||
|
||||
/* USER CODE END PD */ |
||||
|
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN PM */ |
||||
|
||||
/* USER CODE END PM */ |
||||
|
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* USER CODE BEGIN PV */ |
||||
|
||||
/* USER CODE END PV */ |
||||
|
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* USER CODE BEGIN PFP */ |
||||
|
||||
/* USER CODE END PFP */ |
||||
|
||||
/* Private user code ---------------------------------------------------------*/ |
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
/* External variables --------------------------------------------------------*/ |
||||
extern DMA_HandleTypeDef hdma_adc1; |
||||
extern TIM_HandleTypeDef htim1; |
||||
|
||||
/* USER CODE BEGIN EV */ |
||||
|
||||
/* USER CODE END EV */ |
||||
|
||||
/******************************************************************************/ |
||||
/* Cortex-M3 Processor Interruption and Exception Handlers */ |
||||
/******************************************************************************/ |
||||
/**
|
||||
* @brief This function handles Non maskable interrupt. |
||||
*/ |
||||
void NMI_Handler(void) |
||||
{ |
||||
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */ |
||||
|
||||
/* USER CODE END NonMaskableInt_IRQn 0 */ |
||||
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */ |
||||
while (1) |
||||
{ |
||||
} |
||||
/* USER CODE END NonMaskableInt_IRQn 1 */ |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles Hard fault interrupt. |
||||
*/ |
||||
void HardFault_Handler(void) |
||||
{ |
||||
/* USER CODE BEGIN HardFault_IRQn 0 */ |
||||
printf("HardFault_Handler\r\n"); |
||||
|
||||
/* USER CODE END HardFault_IRQn 0 */ |
||||
while (1) |
||||
{ |
||||
/* USER CODE BEGIN W1_HardFault_IRQn 0 */ |
||||
/* USER CODE END W1_HardFault_IRQn 0 */ |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles Memory management fault. |
||||
*/ |
||||
void MemManage_Handler(void) |
||||
{ |
||||
/* USER CODE BEGIN MemoryManagement_IRQn 0 */ |
||||
|
||||
/* USER CODE END MemoryManagement_IRQn 0 */ |
||||
while (1) |
||||
{ |
||||
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ |
||||
/* USER CODE END W1_MemoryManagement_IRQn 0 */ |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles Prefetch fault, memory access fault. |
||||
*/ |
||||
void BusFault_Handler(void) |
||||
{ |
||||
/* USER CODE BEGIN BusFault_IRQn 0 */ |
||||
|
||||
/* USER CODE END BusFault_IRQn 0 */ |
||||
while (1) |
||||
{ |
||||
/* USER CODE BEGIN W1_BusFault_IRQn 0 */ |
||||
/* USER CODE END W1_BusFault_IRQn 0 */ |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles Undefined instruction or illegal state. |
||||
*/ |
||||
void UsageFault_Handler(void) |
||||
{ |
||||
/* USER CODE BEGIN UsageFault_IRQn 0 */ |
||||
|
||||
/* USER CODE END UsageFault_IRQn 0 */ |
||||
while (1) |
||||
{ |
||||
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */ |
||||
/* USER CODE END W1_UsageFault_IRQn 0 */ |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles Debug monitor. |
||||
*/ |
||||
void DebugMon_Handler(void) |
||||
{ |
||||
/* USER CODE BEGIN DebugMonitor_IRQn 0 */ |
||||
|
||||
/* USER CODE END DebugMonitor_IRQn 0 */ |
||||
/* USER CODE BEGIN DebugMonitor_IRQn 1 */ |
||||
|
||||
/* USER CODE END DebugMonitor_IRQn 1 */ |
||||
} |
||||
|
||||
/******************************************************************************/ |
||||
/* STM32F1xx Peripheral Interrupt Handlers */ |
||||
/* Add here the Interrupt Handlers for the used peripherals. */ |
||||
/* For the available peripheral interrupt handler names, */ |
||||
/* please refer to the startup file (startup_stm32f1xx.s). */ |
||||
/******************************************************************************/ |
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 channel1 global interrupt. |
||||
*/ |
||||
void DMA1_Channel1_IRQHandler(void) |
||||
{ |
||||
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ |
||||
|
||||
/* USER CODE END DMA1_Channel1_IRQn 0 */ |
||||
HAL_DMA_IRQHandler(&hdma_adc1); |
||||
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ |
||||
|
||||
/* USER CODE END DMA1_Channel1_IRQn 1 */ |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles TIM1 update interrupt. |
||||
*/ |
||||
void TIM1_UP_IRQHandler(void) |
||||
{ |
||||
/* USER CODE BEGIN TIM1_UP_IRQn 0 */ |
||||
|
||||
/* USER CODE END TIM1_UP_IRQn 0 */ |
||||
HAL_TIM_IRQHandler(&htim1); |
||||
/* USER CODE BEGIN TIM1_UP_IRQn 1 */ |
||||
|
||||
/* USER CODE END TIM1_UP_IRQn 1 */ |
||||
} |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
@ -0,0 +1,408 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file system_stm32f1xx.c |
||||
* @author MCD Application Team |
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. |
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application: |
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier |
||||
* factors, AHB/APBx prescalers and Flash settings).
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside |
||||
* the "startup_stm32f1xx_xx.s" file. |
||||
* |
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters. |
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
||||
* be called whenever the core clock is changed |
||||
* during program execution. |
||||
* |
||||
* 2. After each device reset the HSI (8 MHz) is used as system clock source. |
||||
* Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to |
||||
* configure the system clock before to branch to main program. |
||||
* |
||||
* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on |
||||
* the product used), refer to "HSE_VALUE".
|
||||
* When HSE is used as system clock source, directly or through PLL, and you |
||||
* are using different crystal you have to adapt the HSE value to your own |
||||
* configuration. |
||||
*
|
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup stm32f1xx_system
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_Includes
|
||||
* @{ |
||||
*/ |
||||
|
||||
#include "stm32f1xx.h" |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_Defines
|
||||
* @{ |
||||
*/ |
||||
|
||||
#if !defined (HSE_VALUE) |
||||
#define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. |
||||
This value can be provided and adapted by the user application. */ |
||||
#endif /* HSE_VALUE */ |
||||
|
||||
#if !defined (HSI_VALUE) |
||||
#define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. |
||||
This value can be provided and adapted by the user application. */ |
||||
#endif /* HSI_VALUE */ |
||||
|
||||
/*!< Uncomment the following line if you need to use external SRAM */
|
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
||||
/* #define DATA_IN_ExtSRAM */ |
||||
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ |
||||
|
||||
/* Note: Following vector table addresses must be defined in line with linker
|
||||
configuration. */ |
||||
/*!< Uncomment the following line if you need to relocate the vector table
|
||||
anywhere in Flash or Sram, else the vector table is kept at the automatic |
||||
remap of boot address selected */ |
||||
/* #define USER_VECT_TAB_ADDRESS */ |
||||
|
||||
#if defined(USER_VECT_TAB_ADDRESS) |
||||
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||
in Sram else user remap will be done in Flash. */ |
||||
/* #define VECT_TAB_SRAM */ |
||||
#if defined(VECT_TAB_SRAM) |
||||
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. |
||||
This value must be a multiple of 0x200. */ |
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. |
||||
This value must be a multiple of 0x200. */ |
||||
#else |
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. |
||||
This value must be a multiple of 0x200. */ |
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. |
||||
This value must be a multiple of 0x200. */ |
||||
#endif /* VECT_TAB_SRAM */ |
||||
#endif /* USER_VECT_TAB_ADDRESS */ |
||||
|
||||
/******************************************************************************/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_Variables
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate() |
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there |
||||
is no need to call the 2 first functions listed above, since SystemCoreClock |
||||
variable is updated automatically. |
||||
*/ |
||||
uint32_t SystemCoreClock = 16000000; |
||||
const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
||||
const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
|
||||
* @{ |
||||
*/ |
||||
|
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
||||
#ifdef DATA_IN_ExtSRAM |
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSRAM */ |
||||
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system |
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemCoreClock variable. |
||||
* @note This function should be used only after reset. |
||||
* @param None |
||||
* @retval None |
||||
*/ |
||||
void SystemInit (void) |
||||
{ |
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
||||
#ifdef DATA_IN_ExtSRAM |
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM */ |
||||
#endif |
||||
|
||||
/* Configure the Vector Table location -------------------------------------*/ |
||||
#if defined(USER_VECT_TAB_ADDRESS) |
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ |
||||
#endif /* USER_VECT_TAB_ADDRESS */ |
||||
} |
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values. |
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can |
||||
* be used by the user application to setup the SysTick timer or configure |
||||
* other parameters. |
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called |
||||
* to update SystemCoreClock variable value. Otherwise, any configuration |
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source: |
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied by the PLL factors. |
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value |
||||
* 8 MHz) but the real value may vary depending on the variations |
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value |
||||
* 8 MHz or 25 MHz, depending on the product used), user has to ensure |
||||
* that HSE_VALUE is same as the real frequency of the crystal used. |
||||
* Otherwise, this function may have wrong result. |
||||
*
|
||||
* - The result of this function could be not correct when using fractional |
||||
* value for HSE crystal. |
||||
* @param None |
||||
* @retval None |
||||
*/ |
||||
void SystemCoreClockUpdate (void) |
||||
{ |
||||
uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; |
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
||||
uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; |
||||
#endif /* STM32F105xC */ |
||||
|
||||
#if defined(STM32F100xB) || defined(STM32F100xE) |
||||
uint32_t prediv1factor = 0U; |
||||
#endif /* STM32F100xB or STM32F100xE */ |
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/ |
||||
tmp = RCC->CFGR & RCC_CFGR_SWS; |
||||
|
||||
switch (tmp) |
||||
{ |
||||
case 0x00U: /* HSI used as system clock */ |
||||
SystemCoreClock = HSI_VALUE; |
||||
break; |
||||
case 0x04U: /* HSE used as system clock */ |
||||
SystemCoreClock = HSE_VALUE; |
||||
break; |
||||
case 0x08U: /* PLL used as system clock */ |
||||
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/ |
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; |
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
||||
|
||||
#if !defined(STM32F105xC) && !defined(STM32F107xC) |
||||
pllmull = ( pllmull >> 18U) + 2U; |
||||
|
||||
if (pllsource == 0x00U) |
||||
{ |
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
||||
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; |
||||
} |
||||
else |
||||
{ |
||||
#if defined(STM32F100xB) || defined(STM32F100xE) |
||||
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; |
||||
/* HSE oscillator clock selected as PREDIV1 clock entry */ |
||||
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
||||
#else |
||||
/* HSE selected as PLL clock entry */ |
||||
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) |
||||
{/* HSE oscillator clock divided by 2 */ |
||||
SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; |
||||
} |
||||
else |
||||
{ |
||||
SystemCoreClock = HSE_VALUE * pllmull; |
||||
} |
||||
#endif |
||||
} |
||||
#else |
||||
pllmull = pllmull >> 18U; |
||||
|
||||
if (pllmull != 0x0DU) |
||||
{ |
||||
pllmull += 2U; |
||||
} |
||||
else |
||||
{ /* PLL multiplication factor = PLL input clock * 6.5 */ |
||||
pllmull = 13U / 2U;
|
||||
} |
||||
|
||||
if (pllsource == 0x00U) |
||||
{ |
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
||||
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; |
||||
} |
||||
else |
||||
{/* PREDIV1 selected as PLL clock entry */ |
||||
|
||||
/* Get PREDIV1 clock source and division factor */ |
||||
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; |
||||
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; |
||||
|
||||
if (prediv1source == 0U) |
||||
{
|
||||
/* HSE oscillator clock selected as PREDIV1 clock entry */ |
||||
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
||||
} |
||||
else |
||||
{/* PLL2 clock selected as PREDIV1 clock entry */ |
||||
|
||||
/* Get PREDIV2 division factor and PLL2 multiplication factor */ |
||||
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; |
||||
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
|
||||
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
|
||||
} |
||||
} |
||||
#endif /* STM32F105xC */ |
||||
break; |
||||
|
||||
default: |
||||
SystemCoreClock = HSI_VALUE; |
||||
break; |
||||
} |
||||
|
||||
/* Compute HCLK clock frequency ----------------*/ |
||||
/* Get HCLK prescaler */ |
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; |
||||
/* HCLK clock frequency */ |
||||
SystemCoreClock >>= tmp;
|
||||
} |
||||
|
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
||||
/**
|
||||
* @brief Setup the external memory controller. Called in startup_stm32f1xx.s
|
||||
* before jump to __main |
||||
* @param None |
||||
* @retval None |
||||
*/
|
||||
#ifdef DATA_IN_ExtSRAM |
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f1xx_xx.s/.c before jump to main. |
||||
* This function configures the external SRAM mounted on STM3210E-EVAL |
||||
* board (STM32 High density devices). This SRAM will be used as program |
||||
* data memory (including heap and stack). |
||||
* @param None |
||||
* @retval None |
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{ |
||||
__IO uint32_t tmpreg; |
||||
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
|
||||
required, then adjust the Register Addresses */ |
||||
|
||||
/* Enable FSMC clock */ |
||||
RCC->AHBENR = 0x00000114U; |
||||
|
||||
/* Delay after an RCC peripheral clock enabling */ |
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); |
||||
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ |
||||
RCC->APB2ENR = 0x000001E0U; |
||||
|
||||
/* Delay after an RCC peripheral clock enabling */ |
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); |
||||
|
||||
(void)(tmpreg); |
||||
|
||||
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ |
||||
/*---------------- SRAM Address lines configuration -------------------------*/ |
||||
/*---------------- NOE and NWE configuration --------------------------------*/
|
||||
/*---------------- NE3 configuration ----------------------------------------*/ |
||||
/*---------------- NBL0, NBL1 configuration ---------------------------------*/ |
||||
|
||||
GPIOD->CRL = 0x44BB44BBU;
|
||||
GPIOD->CRH = 0xBBBBBBBBU; |
||||
|
||||
GPIOE->CRL = 0xB44444BBU;
|
||||
GPIOE->CRH = 0xBBBBBBBBU; |
||||
|
||||
GPIOF->CRL = 0x44BBBBBBU;
|
||||
GPIOF->CRH = 0xBBBB4444U; |
||||
|
||||
GPIOG->CRL = 0x44BBBBBBU;
|
||||
GPIOG->CRH = 0x444B4B44U; |
||||
|
||||
/*---------------- FSMC Configuration ---------------------------------------*/
|
||||
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ |
||||
|
||||
FSMC_Bank1->BTCR[4U] = 0x00001091U; |
||||
FSMC_Bank1->BTCR[5U] = 0x00110212U; |
||||
} |
||||
#endif /* DATA_IN_ExtSRAM */ |
||||
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,241 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file tim.c |
||||
* @brief This file provides code for the configuration |
||||
* of the TIM instances. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "tim.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
TIM_HandleTypeDef htim2; |
||||
TIM_HandleTypeDef htim4; |
||||
|
||||
/* TIM2 init function */ |
||||
void MX_TIM2_Init(void) |
||||
{ |
||||
|
||||
/* USER CODE BEGIN TIM2_Init 0 */ |
||||
|
||||
/* USER CODE END TIM2_Init 0 */ |
||||
|
||||
TIM_ClockConfigTypeDef sClockSourceConfig = {0}; |
||||
TIM_MasterConfigTypeDef sMasterConfig = {0}; |
||||
TIM_OC_InitTypeDef sConfigOC = {0}; |
||||
|
||||
/* USER CODE BEGIN TIM2_Init 1 */ |
||||
|
||||
/* USER CODE END TIM2_Init 1 */ |
||||
htim2.Instance = TIM2; |
||||
htim2.Init.Prescaler = 2; |
||||
htim2.Init.CounterMode = TIM_COUNTERMODE_UP; |
||||
htim2.Init.Period = 65535; |
||||
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; |
||||
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; |
||||
if (HAL_TIM_Base_Init(&htim2) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; |
||||
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; |
||||
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; |
||||
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
sConfigOC.OCMode = TIM_OCMODE_PWM1; |
||||
sConfigOC.Pulse = 0; |
||||
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; |
||||
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; |
||||
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
/* USER CODE BEGIN TIM2_Init 2 */ |
||||
|
||||
/* USER CODE END TIM2_Init 2 */ |
||||
HAL_TIM_MspPostInit(&htim2); |
||||
|
||||
} |
||||
/* TIM4 init function */ |
||||
void MX_TIM4_Init(void) |
||||
{ |
||||
|
||||
/* USER CODE BEGIN TIM4_Init 0 */ |
||||
|
||||
/* USER CODE END TIM4_Init 0 */ |
||||
|
||||
TIM_Encoder_InitTypeDef sConfig = {0}; |
||||
TIM_MasterConfigTypeDef sMasterConfig = {0}; |
||||
|
||||
/* USER CODE BEGIN TIM4_Init 1 */ |
||||
|
||||
/* USER CODE END TIM4_Init 1 */ |
||||
htim4.Instance = TIM4; |
||||
htim4.Init.Prescaler = 0; |
||||
htim4.Init.CounterMode = TIM_COUNTERMODE_UP; |
||||
htim4.Init.Period = 65535; |
||||
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; |
||||
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; |
||||
sConfig.EncoderMode = TIM_ENCODERMODE_TI1; |
||||
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; |
||||
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; |
||||
sConfig.IC1Prescaler = TIM_ICPSC_DIV1; |
||||
sConfig.IC1Filter = 0; |
||||
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; |
||||
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; |
||||
sConfig.IC2Prescaler = TIM_ICPSC_DIV1; |
||||
sConfig.IC2Filter = 0; |
||||
if (HAL_TIM_Encoder_Init(&htim4, &sConfig) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; |
||||
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; |
||||
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
/* USER CODE BEGIN TIM4_Init 2 */ |
||||
|
||||
/* USER CODE END TIM4_Init 2 */ |
||||
|
||||
} |
||||
|
||||
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) |
||||
{ |
||||
|
||||
if(tim_baseHandle->Instance==TIM2) |
||||
{ |
||||
/* USER CODE BEGIN TIM2_MspInit 0 */ |
||||
|
||||
/* USER CODE END TIM2_MspInit 0 */ |
||||
/* TIM2 clock enable */ |
||||
__HAL_RCC_TIM2_CLK_ENABLE(); |
||||
/* USER CODE BEGIN TIM2_MspInit 1 */ |
||||
|
||||
/* USER CODE END TIM2_MspInit 1 */ |
||||
} |
||||
} |
||||
|
||||
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle) |
||||
{ |
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0}; |
||||
if(tim_encoderHandle->Instance==TIM4) |
||||
{ |
||||
/* USER CODE BEGIN TIM4_MspInit 0 */ |
||||
|
||||
/* USER CODE END TIM4_MspInit 0 */ |
||||
/* TIM4 clock enable */ |
||||
__HAL_RCC_TIM4_CLK_ENABLE(); |
||||
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE(); |
||||
/**TIM4 GPIO Configuration
|
||||
PB6 ------> TIM4_CH1 |
||||
PB7 ------> TIM4_CH2 |
||||
*/ |
||||
GPIO_InitStruct.Pin = KNOB_B_Pin|KNOB_A_Pin; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; |
||||
GPIO_InitStruct.Pull = GPIO_PULLUP; |
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); |
||||
|
||||
/* USER CODE BEGIN TIM4_MspInit 1 */ |
||||
|
||||
/* USER CODE END TIM4_MspInit 1 */ |
||||
} |
||||
} |
||||
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) |
||||
{ |
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0}; |
||||
if(timHandle->Instance==TIM2) |
||||
{ |
||||
/* USER CODE BEGIN TIM2_MspPostInit 0 */ |
||||
|
||||
/* USER CODE END TIM2_MspPostInit 0 */ |
||||
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE(); |
||||
/**TIM2 GPIO Configuration
|
||||
PA15 ------> TIM2_CH1 |
||||
*/ |
||||
GPIO_InitStruct.Pin = BUZZER_Pin; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; |
||||
HAL_GPIO_Init(BUZZER_GPIO_Port, &GPIO_InitStruct); |
||||
|
||||
__HAL_AFIO_REMAP_TIM2_PARTIAL_1(); |
||||
|
||||
/* USER CODE BEGIN TIM2_MspPostInit 1 */ |
||||
|
||||
/* USER CODE END TIM2_MspPostInit 1 */ |
||||
} |
||||
|
||||
} |
||||
|
||||
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) |
||||
{ |
||||
|
||||
if(tim_baseHandle->Instance==TIM2) |
||||
{ |
||||
/* USER CODE BEGIN TIM2_MspDeInit 0 */ |
||||
|
||||
/* USER CODE END TIM2_MspDeInit 0 */ |
||||
/* Peripheral clock disable */ |
||||
__HAL_RCC_TIM2_CLK_DISABLE(); |
||||
/* USER CODE BEGIN TIM2_MspDeInit 1 */ |
||||
|
||||
/* USER CODE END TIM2_MspDeInit 1 */ |
||||
} |
||||
} |
||||
|
||||
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* tim_encoderHandle) |
||||
{ |
||||
|
||||
if(tim_encoderHandle->Instance==TIM4) |
||||
{ |
||||
/* USER CODE BEGIN TIM4_MspDeInit 0 */ |
||||
|
||||
/* USER CODE END TIM4_MspDeInit 0 */ |
||||
/* Peripheral clock disable */ |
||||
__HAL_RCC_TIM4_CLK_DISABLE(); |
||||
|
||||
/**TIM4 GPIO Configuration
|
||||
PB6 ------> TIM4_CH1 |
||||
PB7 ------> TIM4_CH2 |
||||
*/ |
||||
HAL_GPIO_DeInit(GPIOB, KNOB_B_Pin|KNOB_A_Pin); |
||||
|
||||
/* USER CODE BEGIN TIM4_MspDeInit 1 */ |
||||
|
||||
/* USER CODE END TIM4_MspDeInit 1 */ |
||||
} |
||||
} |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
@ -0,0 +1,126 @@ |
||||
/* USER CODE BEGIN Header */ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file usart.c |
||||
* @brief This file provides code for the configuration |
||||
* of the USART instances. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* Copyright (c) 2023 STMicroelectronics. |
||||
* All rights reserved. |
||||
* |
||||
* This software is licensed under terms that can be found in the LICENSE file |
||||
* in the root directory of this software component. |
||||
* If no LICENSE file comes with this software, it is provided AS-IS. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* USER CODE END Header */ |
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "usart.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
UART_HandleTypeDef huart1; |
||||
|
||||
/* USART1 init function */ |
||||
|
||||
void MX_USART1_UART_Init(void) |
||||
{ |
||||
|
||||
/* USER CODE BEGIN USART1_Init 0 */ |
||||
|
||||
/* USER CODE END USART1_Init 0 */ |
||||
|
||||
/* USER CODE BEGIN USART1_Init 1 */ |
||||
|
||||
/* USER CODE END USART1_Init 1 */ |
||||
huart1.Instance = USART1; |
||||
huart1.Init.BaudRate = 115200; |
||||
huart1.Init.WordLength = UART_WORDLENGTH_8B; |
||||
huart1.Init.StopBits = UART_STOPBITS_1; |
||||
huart1.Init.Parity = UART_PARITY_NONE; |
||||
huart1.Init.Mode = UART_MODE_TX_RX; |
||||
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; |
||||
huart1.Init.OverSampling = UART_OVERSAMPLING_16; |
||||
if (HAL_UART_Init(&huart1) != HAL_OK) |
||||
{ |
||||
Error_Handler(); |
||||
} |
||||
/* USER CODE BEGIN USART1_Init 2 */ |
||||
|
||||
/* USER CODE END USART1_Init 2 */ |
||||
|
||||
} |
||||
|
||||
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) |
||||
{ |
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0}; |
||||
if(uartHandle->Instance==USART1) |
||||
{ |
||||
/* USER CODE BEGIN USART1_MspInit 0 */ |
||||
|
||||
/* USER CODE END USART1_MspInit 0 */ |
||||
/* USART1 clock enable */ |
||||
__HAL_RCC_USART1_CLK_ENABLE(); |
||||
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE(); |
||||
/**USART1 GPIO Configuration
|
||||
PA9 ------> USART1_TX |
||||
PA10 ------> USART1_RX |
||||
*/ |
||||
GPIO_InitStruct.Pin = GPIO_PIN_9; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; |
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); |
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_10; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); |
||||
|
||||
/* USER CODE BEGIN USART1_MspInit 1 */ |
||||
|
||||
/* USER CODE END USART1_MspInit 1 */ |
||||
} |
||||
} |
||||
|
||||
void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) |
||||
{ |
||||
|
||||
if(uartHandle->Instance==USART1) |
||||
{ |
||||
/* USER CODE BEGIN USART1_MspDeInit 0 */ |
||||
|
||||
/* USER CODE END USART1_MspDeInit 0 */ |
||||
/* Peripheral clock disable */ |
||||
__HAL_RCC_USART1_CLK_DISABLE(); |
||||
|
||||
/**USART1 GPIO Configuration
|
||||
PA9 ------> USART1_TX |
||||
PA10 ------> USART1_RX |
||||
*/ |
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); |
||||
|
||||
/* USER CODE BEGIN USART1_MspDeInit 1 */ |
||||
|
||||
/* USER CODE END USART1_MspDeInit 1 */ |
||||
} |
||||
} |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
/**
|
||||
* @brief Retargets the C library printf function to the USART. |
||||
* @param None |
||||
* @retval None |
||||
*/ |
||||
int _write(int fd, char *pcBuffer, int iLength) { |
||||
HAL_UART_Transmit(&huart1, (uint8_t *)pcBuffer, iLength, 0xFFFF); |
||||
return iLength; |
||||
} |
||||
|
||||
/* USER CODE END 1 */ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,275 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx.h |
||||
* @author MCD Application Team |
||||
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
|
||||
* |
||||
* The file is the unique include file that the application programmer |
||||
* is using in the C source code, usually in main.c. This file contains: |
||||
* - Configuration section that allows to select: |
||||
* - The STM32F1xx device used in the target application |
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER" |
||||
*
|
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup stm32f1xx
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifndef __STM32F1XX_H |
||||
#define __STM32F1XX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif /* __cplusplus */ |
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief STM32 Family |
||||
*/ |
||||
#if !defined (STM32F1) |
||||
#define STM32F1 |
||||
#endif /* STM32F1 */ |
||||
|
||||
/* Uncomment the line below according to the target STM32L device used in your
|
||||
application
|
||||
*/ |
||||
|
||||
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ |
||||
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
|
||||
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) |
||||
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ |
||||
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ |
||||
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ |
||||
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ |
||||
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
|
||||
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ |
||||
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ |
||||
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ |
||||
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ |
||||
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ |
||||
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ |
||||
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ |
||||
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ |
||||
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
|
||||
#endif |
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor. |
||||
*/ |
||||
|
||||
#if !defined (USE_HAL_DRIVER) |
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers. |
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/ |
||||
/*#define USE_HAL_DRIVER */ |
||||
#endif /* USE_HAL_DRIVER */ |
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V4.3.3 |
||||
*/ |
||||
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ |
||||
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ |
||||
#define __STM32F1_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ |
||||
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ |
||||
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ |
||||
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F1_CMSIS_VERSION_RC)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{ |
||||
*/ |
||||
|
||||
#if defined(STM32F100xB) |
||||
#include "stm32f100xb.h" |
||||
#elif defined(STM32F100xE) |
||||
#include "stm32f100xe.h" |
||||
#elif defined(STM32F101x6) |
||||
#include "stm32f101x6.h" |
||||
#elif defined(STM32F101xB) |
||||
#include "stm32f101xb.h" |
||||
#elif defined(STM32F101xE) |
||||
#include "stm32f101xe.h" |
||||
#elif defined(STM32F101xG) |
||||
#include "stm32f101xg.h" |
||||
#elif defined(STM32F102x6) |
||||
#include "stm32f102x6.h" |
||||
#elif defined(STM32F102xB) |
||||
#include "stm32f102xb.h" |
||||
#elif defined(STM32F103x6) |
||||
#include "stm32f103x6.h" |
||||
#elif defined(STM32F103xB) |
||||
#include "stm32f103xb.h" |
||||
#elif defined(STM32F103xE) |
||||
#include "stm32f103xe.h" |
||||
#elif defined(STM32F103xG) |
||||
#include "stm32f103xg.h" |
||||
#elif defined(STM32F105xC) |
||||
#include "stm32f105xc.h" |
||||
#elif defined(STM32F107xC) |
||||
#include "stm32f107xc.h" |
||||
#else |
||||
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{ |
||||
*/
|
||||
typedef enum
|
||||
{ |
||||
RESET = 0,
|
||||
SET = !RESET |
||||
} FlagStatus, ITStatus; |
||||
|
||||
typedef enum
|
||||
{ |
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE |
||||
} FunctionalState; |
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
||||
|
||||
typedef enum |
||||
{ |
||||
SUCCESS = 0U, |
||||
ERROR = !SUCCESS |
||||
} ErrorStatus; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @addtogroup Exported_macros
|
||||
* @{ |
||||
*/ |
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) |
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT)) |
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0)) |
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) |
||||
|
||||
#define READ_REG(REG) ((REG)) |
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) |
||||
|
||||
/* Use of CMSIS compiler intrinsics for register exclusive access */ |
||||
/* Atomic 32-bit register access macro to set one or several bits */ |
||||
#define ATOMIC_SET_BIT(REG, BIT) \ |
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0) |
||||
|
||||
/* Atomic 32-bit register access macro to clear one or several bits */ |
||||
#define ATOMIC_CLEAR_BIT(REG, BIT) \ |
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0) |
||||
|
||||
/* Atomic 32-bit register access macro to clear and set one or several bits */ |
||||
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ |
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0) |
||||
|
||||
/* Atomic 16-bit register access macro to set one or several bits */ |
||||
#define ATOMIC_SETH_BIT(REG, BIT) \ |
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0) |
||||
|
||||
/* Atomic 16-bit register access macro to clear one or several bits */ |
||||
#define ATOMIC_CLEARH_BIT(REG, BIT) \ |
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0) |
||||
|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */ |
||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ |
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0) |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined (USE_HAL_DRIVER) |
||||
#include "stm32f1xx_hal.h" |
||||
#endif /* USE_HAL_DRIVER */ |
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif /* __cplusplus */ |
||||
|
||||
#endif /* __STM32F1xx_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,98 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file system_stm32f10x.h |
||||
* @author MCD Application Team |
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup stm32f10x_system
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion |
||||
*/ |
||||
#ifndef __SYSTEM_STM32F10X_H |
||||
#define __SYSTEM_STM32F10X_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/** @addtogroup STM32F10x_System_Includes
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_types
|
||||
* @{ |
||||
*/ |
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ |
||||
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ |
||||
extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
extern void SystemInit(void); |
||||
extern void SystemCoreClockUpdate(void); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /*__SYSTEM_STM32F10X_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,83 @@ |
||||
Apache License |
||||
Version 2.0, January 2004 |
||||
http://www.apache.org/licenses/ |
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION |
||||
|
||||
1. Definitions. |
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. |
||||
|
||||
"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. |
||||
|
||||
"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. |
||||
|
||||
"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License. |
||||
|
||||
"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files. |
||||
|
||||
"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types. |
||||
|
||||
"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below). |
||||
|
||||
"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof. |
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||||
"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution." |
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||||
"Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work. |
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||||
2. Grant of Copyright License. |
||||
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||||
Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form. |
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||||
3. Grant of Patent License. |
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||||
Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed. |
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||||
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||||
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||||
You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions: |
||||
1.You must give any other recipients of the Work or Derivative Works a copy of this License; and |
||||
2.You must cause any modified files to carry prominent notices stating that You changed the files; and |
||||
3.You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and |
||||
4.If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License. |
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||||
You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License. |
||||
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||||
5. Submission of Contributions. |
||||
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||||
Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions. |
||||
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||||
6. Trademarks. |
||||
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||||
This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file. |
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||||
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||||
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||||
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||||
8. Limitation of Liability. |
||||
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||||
In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages. |
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||||
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||||
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||||
|
||||
END OF TERMS AND CONDITIONS |
||||
|
||||
APPENDIX: |
||||
|
||||
Copyright [2019] [STMicroelectronics] |
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License"); |
||||
you may not use this file except in compliance with the License. |
||||
You may obtain a copy of the License at |
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0 |
||||
|
||||
Unless required by applicable law or agreed to in writing, software |
||||
distributed under the License is distributed on an "AS IS" BASIS, |
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
See the License for the specific language governing permissions and |
||||
limitations under the License. |
||||
@ -0,0 +1,865 @@ |
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h |
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file |
||||
* @version V5.0.4 |
||||
* @date 10. January 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#ifndef __CMSIS_ARMCC_H |
||||
#define __CMSIS_ARMCC_H |
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) |
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!" |
||||
#endif |
||||
|
||||
/* CMSIS compiler control architecture macros */ |
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ |
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) |
||||
#define __ARM_ARCH_6M__ 1 |
||||
#endif |
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) |
||||
#define __ARM_ARCH_7M__ 1 |
||||
#endif |
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) |
||||
#define __ARM_ARCH_7EM__ 1 |
||||
#endif |
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */ |
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */ |
||||
|
||||
|
||||
/* CMSIS compiler specific defines */ |
||||
#ifndef __ASM |
||||
#define __ASM __asm |
||||
#endif |
||||
#ifndef __INLINE |
||||
#define __INLINE __inline |
||||
#endif |
||||
#ifndef __STATIC_INLINE |
||||
#define __STATIC_INLINE static __inline |
||||
#endif |
||||
#ifndef __STATIC_FORCEINLINE |
||||
#define __STATIC_FORCEINLINE static __forceinline |
||||
#endif |
||||
#ifndef __NO_RETURN |
||||
#define __NO_RETURN __declspec(noreturn) |
||||
#endif |
||||
#ifndef __USED |
||||
#define __USED __attribute__((used)) |
||||
#endif |
||||
#ifndef __WEAK |
||||
#define __WEAK __attribute__((weak)) |
||||
#endif |
||||
#ifndef __PACKED |
||||
#define __PACKED __attribute__((packed)) |
||||
#endif |
||||
#ifndef __PACKED_STRUCT |
||||
#define __PACKED_STRUCT __packed struct |
||||
#endif |
||||
#ifndef __PACKED_UNION |
||||
#define __PACKED_UNION __packed union |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */ |
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_WRITE |
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_READ |
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_WRITE |
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_READ |
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) |
||||
#endif |
||||
#ifndef __ALIGNED |
||||
#define __ALIGNED(x) __attribute__((aligned(x))) |
||||
#endif |
||||
#ifndef __RESTRICT |
||||
#define __RESTRICT __restrict |
||||
#endif |
||||
|
||||
/* ########################### Core Function Access ########################### */ |
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts |
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR. |
||||
Can only be executed in Privileged modes. |
||||
*/ |
||||
/* intrinsic void __enable_irq(); */ |
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts |
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR. |
||||
Can only be executed in Privileged modes. |
||||
*/ |
||||
/* intrinsic void __disable_irq(); */ |
||||
|
||||
/**
|
||||
\brief Get Control Register |
||||
\details Returns the content of the Control Register. |
||||
\return Control Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_CONTROL(void) |
||||
{ |
||||
register uint32_t __regControl __ASM("control"); |
||||
return(__regControl); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register |
||||
\details Writes the given value to the Control Register. |
||||
\param [in] control Control Register value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control) |
||||
{ |
||||
register uint32_t __regControl __ASM("control"); |
||||
__regControl = control; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register |
||||
\details Returns the content of the IPSR Register. |
||||
\return IPSR Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_IPSR(void) |
||||
{ |
||||
register uint32_t __regIPSR __ASM("ipsr"); |
||||
return(__regIPSR); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register |
||||
\details Returns the content of the APSR Register. |
||||
\return APSR Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_APSR(void) |
||||
{ |
||||
register uint32_t __regAPSR __ASM("apsr"); |
||||
return(__regAPSR); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register |
||||
\details Returns the content of the xPSR Register. |
||||
\return xPSR Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_xPSR(void) |
||||
{ |
||||
register uint32_t __regXPSR __ASM("xpsr"); |
||||
return(__regXPSR); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer |
||||
\details Returns the current value of the Process Stack Pointer (PSP). |
||||
\return PSP Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_PSP(void) |
||||
{ |
||||
register uint32_t __regProcessStackPointer __ASM("psp"); |
||||
return(__regProcessStackPointer); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer |
||||
\details Assigns the given value to the Process Stack Pointer (PSP). |
||||
\param [in] topOfProcStack Process Stack Pointer value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
||||
{ |
||||
register uint32_t __regProcessStackPointer __ASM("psp"); |
||||
__regProcessStackPointer = topOfProcStack; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer |
||||
\details Returns the current value of the Main Stack Pointer (MSP). |
||||
\return MSP Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_MSP(void) |
||||
{ |
||||
register uint32_t __regMainStackPointer __ASM("msp"); |
||||
return(__regMainStackPointer); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer |
||||
\details Assigns the given value to the Main Stack Pointer (MSP). |
||||
\param [in] topOfMainStack Main Stack Pointer value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
||||
{ |
||||
register uint32_t __regMainStackPointer __ASM("msp"); |
||||
__regMainStackPointer = topOfMainStack; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask |
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register. |
||||
\return Priority Mask value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void) |
||||
{ |
||||
register uint32_t __regPriMask __ASM("primask"); |
||||
return(__regPriMask); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask |
||||
\details Assigns the given value to the Priority Mask Register. |
||||
\param [in] priMask Priority Mask |
||||
*/ |
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
||||
{ |
||||
register uint32_t __regPriMask __ASM("primask"); |
||||
__regPriMask = (priMask); |
||||
} |
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) |
||||
|
||||
/**
|
||||
\brief Enable FIQ |
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR. |
||||
Can only be executed in Privileged modes. |
||||
*/ |
||||
#define __enable_fault_irq __enable_fiq |
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ |
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR. |
||||
Can only be executed in Privileged modes. |
||||
*/ |
||||
#define __disable_fault_irq __disable_fiq |
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority |
||||
\details Returns the current value of the Base Priority register. |
||||
\return Base Priority register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void) |
||||
{ |
||||
register uint32_t __regBasePri __ASM("basepri"); |
||||
return(__regBasePri); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority |
||||
\details Assigns the given value to the Base Priority register. |
||||
\param [in] basePri Base Priority value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) |
||||
{ |
||||
register uint32_t __regBasePri __ASM("basepri"); |
||||
__regBasePri = (basePri & 0xFFU); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition |
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, |
||||
or the new value increases the BASEPRI priority level. |
||||
\param [in] basePri Base Priority value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) |
||||
{ |
||||
register uint32_t __regBasePriMax __ASM("basepri_max"); |
||||
__regBasePriMax = (basePri & 0xFFU); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask |
||||
\details Returns the current value of the Fault Mask register. |
||||
\return Fault Mask register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void) |
||||
{ |
||||
register uint32_t __regFaultMask __ASM("faultmask"); |
||||
return(__regFaultMask); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask |
||||
\details Assigns the given value to the Fault Mask register. |
||||
\param [in] faultMask Fault Mask value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
||||
{ |
||||
register uint32_t __regFaultMask __ASM("faultmask"); |
||||
__regFaultMask = (faultMask & (uint32_t)1U); |
||||
} |
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ |
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR |
||||
\details Returns the current value of the Floating Point Status/Control register. |
||||
\return Floating Point Status/Control register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_FPSCR(void) |
||||
{ |
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
||||
register uint32_t __regfpscr __ASM("fpscr"); |
||||
return(__regfpscr); |
||||
#else |
||||
return(0U); |
||||
#endif |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR |
||||
\details Assigns the given value to the Floating Point Status/Control register. |
||||
\param [in] fpscr Floating Point Status/Control value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
||||
{ |
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
||||
register uint32_t __regfpscr __ASM("fpscr"); |
||||
__regfpscr = (fpscr); |
||||
#else |
||||
(void)fpscr; |
||||
#endif |
||||
} |
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */ |
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */ |
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief No Operation |
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes. |
||||
*/ |
||||
#define __NOP __nop |
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt |
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. |
||||
*/ |
||||
#define __WFI __wfi |
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event |
||||
\details Wait For Event is a hint instruction that permits the processor to enter |
||||
a low-power state until one of a number of events occurs. |
||||
*/ |
||||
#define __WFE __wfe |
||||
|
||||
|
||||
/**
|
||||
\brief Send Event |
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
||||
*/ |
||||
#define __SEV __sev |
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier |
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor, |
||||
so that all instructions following the ISB are fetched from cache or memory, |
||||
after the instruction has been completed. |
||||
*/ |
||||
#define __ISB() do {\ |
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U) |
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier |
||||
\details Acts as a special kind of Data Memory Barrier. |
||||
It completes when all explicit memory accesses before this instruction complete. |
||||
*/ |
||||
#define __DSB() do {\ |
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U) |
||||
|
||||
/**
|
||||
\brief Data Memory Barrier |
||||
\details Ensures the apparent order of the explicit memory operations before |
||||
and after the instruction, without ensuring their completion. |
||||
*/ |
||||
#define __DMB() do {\ |
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U) |
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit) |
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#define __REV __rev |
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit) |
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#ifndef __NO_EMBEDDED_ASM |
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) |
||||
{ |
||||
rev16 r0, r0 |
||||
bx lr |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit) |
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#ifndef __NO_EMBEDDED_ASM |
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) |
||||
{ |
||||
revsh r0, r0 |
||||
bx lr |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit) |
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
||||
\param [in] op1 Value to rotate |
||||
\param [in] op2 Number of Bits to rotate |
||||
\return Rotated value |
||||
*/ |
||||
#define __ROR __ror |
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint |
||||
\details Causes the processor to enter Debug state. |
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached. |
||||
\param [in] value is ignored by the processor. |
||||
If required, a debugger can use it to store additional information about the breakpoint. |
||||
*/ |
||||
#define __BKPT(value) __breakpoint(value) |
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value |
||||
\details Reverses the bit order of the given value. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) |
||||
#define __RBIT __rbit |
||||
#else |
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) |
||||
{ |
||||
uint32_t result; |
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ |
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */ |
||||
for (value >>= 1U; value != 0U; value >>= 1U) |
||||
{ |
||||
result <<= 1U; |
||||
result |= value & 1U; |
||||
s--; |
||||
} |
||||
result <<= s; /* shift when v's highest bits are zero */ |
||||
return result; |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros |
||||
\details Counts the number of leading zeros of a data value. |
||||
\param [in] value Value to count the leading zeros |
||||
\return number of leading zeros in value |
||||
*/ |
||||
#define __CLZ __clz |
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) |
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit) |
||||
\details Executes a exclusive LDR instruction for 8 bit value. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint8_t at (*ptr) |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) |
||||
#else |
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit) |
||||
\details Executes a exclusive LDR instruction for 16 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint16_t at (*ptr) |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) |
||||
#else |
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit) |
||||
\details Executes a exclusive LDR instruction for 32 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint32_t at (*ptr) |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) |
||||
#else |
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit) |
||||
\details Executes a exclusive STR instruction for 8 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
\return 0 Function succeeded |
||||
\return 1 Function failed |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __STREXB(value, ptr) __strex(value, ptr) |
||||
#else |
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit) |
||||
\details Executes a exclusive STR instruction for 16 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
\return 0 Function succeeded |
||||
\return 1 Function failed |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __STREXH(value, ptr) __strex(value, ptr) |
||||
#else |
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit) |
||||
\details Executes a exclusive STR instruction for 32 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
\return 0 Function succeeded |
||||
\return 1 Function failed |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __STREXW(value, ptr) __strex(value, ptr) |
||||
#else |
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock |
||||
\details Removes the exclusive lock which is created by LDREX. |
||||
*/ |
||||
#define __CLREX __clrex |
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate |
||||
\details Saturates a signed value. |
||||
\param [in] value Value to be saturated |
||||
\param [in] sat Bit position to saturate to (1..32) |
||||
\return Saturated value |
||||
*/ |
||||
#define __SSAT __ssat |
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate |
||||
\details Saturates an unsigned value. |
||||
\param [in] value Value to be saturated |
||||
\param [in] sat Bit position to saturate to (0..31) |
||||
\return Saturated value |
||||
*/ |
||||
#define __USAT __usat |
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit) |
||||
\details Moves each bit of a bitstring right by one bit. |
||||
The carry input is shifted in at the left end of the bitstring. |
||||
\param [in] value Value to rotate |
||||
\return Rotated value |
||||
*/ |
||||
#ifndef __NO_EMBEDDED_ASM |
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) |
||||
{ |
||||
rrx r0, r0 |
||||
bx lr |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit) |
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint8_t at (*ptr) |
||||
*/ |
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) |
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit) |
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint16_t at (*ptr) |
||||
*/ |
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) |
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit) |
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint32_t at (*ptr) |
||||
*/ |
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) |
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit) |
||||
\details Executes a Unprivileged STRT instruction for 8 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
*/ |
||||
#define __STRBT(value, ptr) __strt(value, ptr) |
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit) |
||||
\details Executes a Unprivileged STRT instruction for 16 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
*/ |
||||
#define __STRHT(value, ptr) __strt(value, ptr) |
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit) |
||||
\details Executes a Unprivileged STRT instruction for 32 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
*/ |
||||
#define __STRT(value, ptr) __strt(value, ptr) |
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ |
||||
|
||||
/**
|
||||
\brief Signed Saturate |
||||
\details Saturates a signed value. |
||||
\param [in] value Value to be saturated |
||||
\param [in] sat Bit position to saturate to (1..32) |
||||
\return Saturated value |
||||
*/ |
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) |
||||
{ |
||||
if ((sat >= 1U) && (sat <= 32U)) |
||||
{ |
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); |
||||
const int32_t min = -1 - max ; |
||||
if (val > max) |
||||
{ |
||||
return max; |
||||
} |
||||
else if (val < min) |
||||
{ |
||||
return min; |
||||
} |
||||
} |
||||
return val; |
||||
} |
||||
|
||||
/**
|
||||
\brief Unsigned Saturate |
||||
\details Saturates an unsigned value. |
||||
\param [in] value Value to be saturated |
||||
\param [in] sat Bit position to saturate to (0..31) |
||||
\return Saturated value |
||||
*/ |
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) |
||||
{ |
||||
if (sat <= 31U) |
||||
{ |
||||
const uint32_t max = ((1U << sat) - 1U); |
||||
if (val > (int32_t)max) |
||||
{ |
||||
return max; |
||||
} |
||||
else if (val < 0) |
||||
{ |
||||
return 0U; |
||||
} |
||||
} |
||||
return (uint32_t)val; |
||||
} |
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ |
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */ |
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions |
||||
@{ |
||||
*/ |
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) |
||||
|
||||
#define __SADD8 __sadd8 |
||||
#define __QADD8 __qadd8 |
||||
#define __SHADD8 __shadd8 |
||||
#define __UADD8 __uadd8 |
||||
#define __UQADD8 __uqadd8 |
||||
#define __UHADD8 __uhadd8 |
||||
#define __SSUB8 __ssub8 |
||||
#define __QSUB8 __qsub8 |
||||
#define __SHSUB8 __shsub8 |
||||
#define __USUB8 __usub8 |
||||
#define __UQSUB8 __uqsub8 |
||||
#define __UHSUB8 __uhsub8 |
||||
#define __SADD16 __sadd16 |
||||
#define __QADD16 __qadd16 |
||||
#define __SHADD16 __shadd16 |
||||
#define __UADD16 __uadd16 |
||||
#define __UQADD16 __uqadd16 |
||||
#define __UHADD16 __uhadd16 |
||||
#define __SSUB16 __ssub16 |
||||
#define __QSUB16 __qsub16 |
||||
#define __SHSUB16 __shsub16 |
||||
#define __USUB16 __usub16 |
||||
#define __UQSUB16 __uqsub16 |
||||
#define __UHSUB16 __uhsub16 |
||||
#define __SASX __sasx |
||||
#define __QASX __qasx |
||||
#define __SHASX __shasx |
||||
#define __UASX __uasx |
||||
#define __UQASX __uqasx |
||||
#define __UHASX __uhasx |
||||
#define __SSAX __ssax |
||||
#define __QSAX __qsax |
||||
#define __SHSAX __shsax |
||||
#define __USAX __usax |
||||
#define __UQSAX __uqsax |
||||
#define __UHSAX __uhsax |
||||
#define __USAD8 __usad8 |
||||
#define __USADA8 __usada8 |
||||
#define __SSAT16 __ssat16 |
||||
#define __USAT16 __usat16 |
||||
#define __UXTB16 __uxtb16 |
||||
#define __UXTAB16 __uxtab16 |
||||
#define __SXTB16 __sxtb16 |
||||
#define __SXTAB16 __sxtab16 |
||||
#define __SMUAD __smuad |
||||
#define __SMUADX __smuadx |
||||
#define __SMLAD __smlad |
||||
#define __SMLADX __smladx |
||||
#define __SMLALD __smlald |
||||
#define __SMLALDX __smlaldx |
||||
#define __SMUSD __smusd |
||||
#define __SMUSDX __smusdx |
||||
#define __SMLSD __smlsd |
||||
#define __SMLSDX __smlsdx |
||||
#define __SMLSLD __smlsld |
||||
#define __SMLSLDX __smlsldx |
||||
#define __SEL __sel |
||||
#define __QADD __qadd |
||||
#define __QSUB __qsub |
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ |
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) |
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ |
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) |
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ |
||||
((int64_t)(ARG3) << 32U) ) >> 32U)) |
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ |
||||
/*@} end of group CMSIS_SIMD_intrinsics */ |
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,266 @@ |
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h |
||||
* @brief CMSIS compiler generic header file |
||||
* @version V5.0.4 |
||||
* @date 10. January 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#ifndef __CMSIS_COMPILER_H |
||||
#define __CMSIS_COMPILER_H |
||||
|
||||
#include <stdint.h> |
||||
|
||||
/*
|
||||
* Arm Compiler 4/5 |
||||
*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang) |
||||
*/ |
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armclang.h" |
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler |
||||
*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler |
||||
*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iccarm.h> |
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler |
||||
*/ |
||||
#elif defined ( __TI_ARM__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
#ifndef __ASM |
||||
#define __ASM __asm |
||||
#endif |
||||
#ifndef __INLINE |
||||
#define __INLINE inline |
||||
#endif |
||||
#ifndef __STATIC_INLINE |
||||
#define __STATIC_INLINE static inline |
||||
#endif |
||||
#ifndef __STATIC_FORCEINLINE |
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE |
||||
#endif |
||||
#ifndef __NO_RETURN |
||||
#define __NO_RETURN __attribute__((noreturn)) |
||||
#endif |
||||
#ifndef __USED |
||||
#define __USED __attribute__((used)) |
||||
#endif |
||||
#ifndef __WEAK |
||||
#define __WEAK __attribute__((weak)) |
||||
#endif |
||||
#ifndef __PACKED |
||||
#define __PACKED __attribute__((packed)) |
||||
#endif |
||||
#ifndef __PACKED_STRUCT |
||||
#define __PACKED_STRUCT struct __attribute__((packed)) |
||||
#endif |
||||
#ifndef __PACKED_UNION |
||||
#define __PACKED_UNION union __attribute__((packed)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */ |
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_WRITE |
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_READ |
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_WRITE |
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_READ |
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __ALIGNED |
||||
#define __ALIGNED(x) __attribute__((aligned(x))) |
||||
#endif |
||||
#ifndef __RESTRICT |
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. |
||||
#define __RESTRICT |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler |
||||
*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
#ifndef __ASM |
||||
#define __ASM __asm |
||||
#endif |
||||
#ifndef __INLINE |
||||
#define __INLINE inline |
||||
#endif |
||||
#ifndef __STATIC_INLINE |
||||
#define __STATIC_INLINE static inline |
||||
#endif |
||||
#ifndef __STATIC_FORCEINLINE |
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE |
||||
#endif |
||||
#ifndef __NO_RETURN |
||||
#define __NO_RETURN __attribute__((noreturn)) |
||||
#endif |
||||
#ifndef __USED |
||||
#define __USED __attribute__((used)) |
||||
#endif |
||||
#ifndef __WEAK |
||||
#define __WEAK __attribute__((weak)) |
||||
#endif |
||||
#ifndef __PACKED |
||||
#define __PACKED __packed__ |
||||
#endif |
||||
#ifndef __PACKED_STRUCT |
||||
#define __PACKED_STRUCT struct __packed__ |
||||
#endif |
||||
#ifndef __PACKED_UNION |
||||
#define __PACKED_UNION union __packed__ |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */ |
||||
struct __packed__ T_UINT32 { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_WRITE |
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_READ |
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_WRITE |
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_READ |
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __ALIGNED |
||||
#define __ALIGNED(x) __align(x) |
||||
#endif |
||||
#ifndef __RESTRICT |
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. |
||||
#define __RESTRICT |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler |
||||
*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#ifndef __ASM |
||||
#define __ASM _asm |
||||
#endif |
||||
#ifndef __INLINE |
||||
#define __INLINE inline |
||||
#endif |
||||
#ifndef __STATIC_INLINE |
||||
#define __STATIC_INLINE static inline |
||||
#endif |
||||
#ifndef __STATIC_FORCEINLINE |
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE |
||||
#endif |
||||
#ifndef __NO_RETURN |
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN |
||||
#endif |
||||
#ifndef __USED |
||||
#warning No compiler specific solution for __USED. __USED is ignored. |
||||
#define __USED |
||||
#endif |
||||
#ifndef __WEAK |
||||
#define __WEAK __weak |
||||
#endif |
||||
#ifndef __PACKED |
||||
#define __PACKED @packed |
||||
#endif |
||||
#ifndef __PACKED_STRUCT |
||||
#define __PACKED_STRUCT @packed struct |
||||
#endif |
||||
#ifndef __PACKED_UNION |
||||
#define __PACKED_UNION @packed union |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */ |
||||
@packed struct T_UINT32 { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_WRITE |
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT16_READ |
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; |
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_WRITE |
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) |
||||
#endif |
||||
#ifndef __UNALIGNED_UINT32_READ |
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; |
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) |
||||
#endif |
||||
#ifndef __ALIGNED |
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. |
||||
#define __ALIGNED(x) |
||||
#endif |
||||
#ifndef __RESTRICT |
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. |
||||
#define __RESTRICT |
||||
#endif |
||||
|
||||
|
||||
#else |
||||
#error Unknown compiler. |
||||
#endif |
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */ |
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,935 @@ |
||||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h |
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file |
||||
* @version V5.0.7 |
||||
* @date 19. June 2018 |
||||
******************************************************************************/ |
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2018 IAR Systems
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__ |
||||
#define __CMSIS_ICCARM_H__ |
||||
|
||||
#ifndef __ICCARM__ |
||||
#error This file should only be compiled by ICCARM |
||||
#endif |
||||
|
||||
#pragma system_include |
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic |
||||
|
||||
#if (__VER__ >= 8000000) |
||||
#define __ICCARM_V8 1 |
||||
#else |
||||
#define __ICCARM_V8 0 |
||||
#endif |
||||
|
||||
#ifndef __ALIGNED |
||||
#if __ICCARM_V8 |
||||
#define __ALIGNED(x) __attribute__((aligned(x))) |
||||
#elif (__VER__ >= 7080000) |
||||
/* Needs IAR language extensions */ |
||||
#define __ALIGNED(x) __attribute__((aligned(x))) |
||||
#else |
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. |
||||
#define __ALIGNED(x) |
||||
#endif |
||||
#endif |
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/ |
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ |
||||
/* Macros already defined */ |
||||
#else |
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) |
||||
#define __ARM_ARCH_8M_MAIN__ 1 |
||||
#elif defined(__ARM8M_BASELINE__) |
||||
#define __ARM_ARCH_8M_BASE__ 1 |
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' |
||||
#if __ARM_ARCH == 6 |
||||
#define __ARM_ARCH_6M__ 1 |
||||
#elif __ARM_ARCH == 7 |
||||
#if __ARM_FEATURE_DSP |
||||
#define __ARM_ARCH_7EM__ 1 |
||||
#else |
||||
#define __ARM_ARCH_7M__ 1 |
||||
#endif |
||||
#endif /* __ARM_ARCH */ |
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */ |
||||
#endif |
||||
|
||||
/* Alternativ core deduction for older ICCARM's */ |
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ |
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) |
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__) |
||||
#define __ARM_ARCH_6M__ 1 |
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) |
||||
#define __ARM_ARCH_7M__ 1 |
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) |
||||
#define __ARM_ARCH_7EM__ 1 |
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) |
||||
#define __ARM_ARCH_8M_BASE__ 1 |
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) |
||||
#define __ARM_ARCH_8M_MAIN__ 1 |
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) |
||||
#define __ARM_ARCH_8M_MAIN__ 1 |
||||
#else |
||||
#error "Unknown target." |
||||
#endif |
||||
#endif |
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 |
||||
#define __IAR_M0_FAMILY 1 |
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 |
||||
#define __IAR_M0_FAMILY 1 |
||||
#else |
||||
#define __IAR_M0_FAMILY 0 |
||||
#endif |
||||
|
||||
|
||||
#ifndef __ASM |
||||
#define __ASM __asm |
||||
#endif |
||||
|
||||
#ifndef __INLINE |
||||
#define __INLINE inline |
||||
#endif |
||||
|
||||
#ifndef __NO_RETURN |
||||
#if __ICCARM_V8 |
||||
#define __NO_RETURN __attribute__((__noreturn__)) |
||||
#else |
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn") |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef __PACKED |
||||
#if __ICCARM_V8 |
||||
#define __PACKED __attribute__((packed, aligned(1))) |
||||
#else |
||||
/* Needs IAR language extensions */ |
||||
#define __PACKED __packed |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef __PACKED_STRUCT |
||||
#if __ICCARM_V8 |
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) |
||||
#else |
||||
/* Needs IAR language extensions */ |
||||
#define __PACKED_STRUCT __packed struct |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef __PACKED_UNION |
||||
#if __ICCARM_V8 |
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1))) |
||||
#else |
||||
/* Needs IAR language extensions */ |
||||
#define __PACKED_UNION __packed union |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef __RESTRICT |
||||
#define __RESTRICT __restrict |
||||
#endif |
||||
|
||||
#ifndef __STATIC_INLINE |
||||
#define __STATIC_INLINE static inline |
||||
#endif |
||||
|
||||
#ifndef __FORCEINLINE |
||||
#define __FORCEINLINE _Pragma("inline=forced") |
||||
#endif |
||||
|
||||
#ifndef __STATIC_FORCEINLINE |
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE |
||||
#endif |
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ |
||||
#pragma language=save |
||||
#pragma language=extended |
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr) |
||||
{ |
||||
return *(__packed uint16_t*)(ptr); |
||||
} |
||||
#pragma language=restore |
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) |
||||
#endif |
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE |
||||
#pragma language=save |
||||
#pragma language=extended |
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) |
||||
{ |
||||
*(__packed uint16_t*)(ptr) = val;; |
||||
} |
||||
#pragma language=restore |
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) |
||||
#endif |
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ |
||||
#pragma language=save |
||||
#pragma language=extended |
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr) |
||||
{ |
||||
return *(__packed uint32_t*)(ptr); |
||||
} |
||||
#pragma language=restore |
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) |
||||
#endif |
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE |
||||
#pragma language=save |
||||
#pragma language=extended |
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) |
||||
{ |
||||
*(__packed uint32_t*)(ptr) = val;; |
||||
} |
||||
#pragma language=restore |
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) |
||||
#endif |
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */ |
||||
#pragma language=save |
||||
#pragma language=extended |
||||
__packed struct __iar_u32 { uint32_t v; }; |
||||
#pragma language=restore |
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) |
||||
#endif |
||||
|
||||
#ifndef __USED |
||||
#if __ICCARM_V8 |
||||
#define __USED __attribute__((used)) |
||||
#else |
||||
#define __USED _Pragma("__root") |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef __WEAK |
||||
#if __ICCARM_V8 |
||||
#define __WEAK __attribute__((weak)) |
||||
#else |
||||
#define __WEAK _Pragma("__weak") |
||||
#endif |
||||
#endif |
||||
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__ |
||||
#define __ICCARM_INTRINSICS_VERSION__ 0 |
||||
#endif |
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2 |
||||
|
||||
#if defined(__CLZ) |
||||
#undef __CLZ |
||||
#endif |
||||
#if defined(__REVSH) |
||||
#undef __REVSH |
||||
#endif |
||||
#if defined(__RBIT) |
||||
#undef __RBIT |
||||
#endif |
||||
#if defined(__SSAT) |
||||
#undef __SSAT |
||||
#endif |
||||
#if defined(__USAT) |
||||
#undef __USAT |
||||
#endif |
||||
|
||||
#include "iccarm_builtin.h" |
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq |
||||
#define __disable_irq __iar_builtin_disable_interrupt |
||||
#define __enable_fault_irq __iar_builtin_enable_fiq |
||||
#define __enable_irq __iar_builtin_enable_interrupt |
||||
#define __arm_rsr __iar_builtin_rsr |
||||
#define __arm_wsr __iar_builtin_wsr |
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR")) |
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI")) |
||||
#define __get_CONTROL() (__arm_rsr("CONTROL")) |
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) |
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
||||
#define __get_FPSCR() (__arm_rsr("FPSCR")) |
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) |
||||
#else |
||||
#define __get_FPSCR() ( 0 ) |
||||
#define __set_FPSCR(VALUE) ((void)VALUE) |
||||
#endif |
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR")) |
||||
#define __get_MSP() (__arm_rsr("MSP")) |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U) |
||||
#else |
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM")) |
||||
#endif |
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK")) |
||||
#define __get_PSP() (__arm_rsr("PSP")) |
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U) |
||||
#else |
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM")) |
||||
#endif |
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR")) |
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) |
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) |
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) |
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) |
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) |
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE)) |
||||
#else |
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) |
||||
#endif |
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) |
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE)) |
||||
#else |
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) |
||||
#endif |
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) |
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) |
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) |
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) |
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) |
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) |
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) |
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) |
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) |
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) |
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) |
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) |
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) |
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) |
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U) |
||||
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) |
||||
#else |
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) |
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) |
||||
#endif |
||||
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) |
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) |
||||
|
||||
#define __NOP __iar_builtin_no_operation |
||||
|
||||
#define __CLZ __iar_builtin_CLZ |
||||
#define __CLREX __iar_builtin_CLREX |
||||
|
||||
#define __DMB __iar_builtin_DMB |
||||
#define __DSB __iar_builtin_DSB |
||||
#define __ISB __iar_builtin_ISB |
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB |
||||
#define __LDREXH __iar_builtin_LDREXH |
||||
#define __LDREXW __iar_builtin_LDREX |
||||
|
||||
#define __RBIT __iar_builtin_RBIT |
||||
#define __REV __iar_builtin_REV |
||||
#define __REV16 __iar_builtin_REV16 |
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val) |
||||
{ |
||||
return (int16_t) __iar_builtin_REVSH(val); |
||||
} |
||||
|
||||
#define __ROR __iar_builtin_ROR |
||||
#define __RRX __iar_builtin_RRX |
||||
|
||||
#define __SEV __iar_builtin_SEV |
||||
|
||||
#if !__IAR_M0_FAMILY |
||||
#define __SSAT __iar_builtin_SSAT |
||||
#endif |
||||
|
||||
#define __STREXB __iar_builtin_STREXB |
||||
#define __STREXH __iar_builtin_STREXH |
||||
#define __STREXW __iar_builtin_STREX |
||||
|
||||
#if !__IAR_M0_FAMILY |
||||
#define __USAT __iar_builtin_USAT |
||||
#endif |
||||
|
||||
#define __WFE __iar_builtin_WFE |
||||
#define __WFI __iar_builtin_WFI |
||||
|
||||
#if __ARM_MEDIA__ |
||||
#define __SADD8 __iar_builtin_SADD8 |
||||
#define __QADD8 __iar_builtin_QADD8 |
||||
#define __SHADD8 __iar_builtin_SHADD8 |
||||
#define __UADD8 __iar_builtin_UADD8 |
||||
#define __UQADD8 __iar_builtin_UQADD8 |
||||
#define __UHADD8 __iar_builtin_UHADD8 |
||||
#define __SSUB8 __iar_builtin_SSUB8 |
||||
#define __QSUB8 __iar_builtin_QSUB8 |
||||
#define __SHSUB8 __iar_builtin_SHSUB8 |
||||
#define __USUB8 __iar_builtin_USUB8 |
||||
#define __UQSUB8 __iar_builtin_UQSUB8 |
||||
#define __UHSUB8 __iar_builtin_UHSUB8 |
||||
#define __SADD16 __iar_builtin_SADD16 |
||||
#define __QADD16 __iar_builtin_QADD16 |
||||
#define __SHADD16 __iar_builtin_SHADD16 |
||||
#define __UADD16 __iar_builtin_UADD16 |
||||
#define __UQADD16 __iar_builtin_UQADD16 |
||||
#define __UHADD16 __iar_builtin_UHADD16 |
||||
#define __SSUB16 __iar_builtin_SSUB16 |
||||
#define __QSUB16 __iar_builtin_QSUB16 |
||||
#define __SHSUB16 __iar_builtin_SHSUB16 |
||||
#define __USUB16 __iar_builtin_USUB16 |
||||
#define __UQSUB16 __iar_builtin_UQSUB16 |
||||
#define __UHSUB16 __iar_builtin_UHSUB16 |
||||
#define __SASX __iar_builtin_SASX |
||||
#define __QASX __iar_builtin_QASX |
||||
#define __SHASX __iar_builtin_SHASX |
||||
#define __UASX __iar_builtin_UASX |
||||
#define __UQASX __iar_builtin_UQASX |
||||
#define __UHASX __iar_builtin_UHASX |
||||
#define __SSAX __iar_builtin_SSAX |
||||
#define __QSAX __iar_builtin_QSAX |
||||
#define __SHSAX __iar_builtin_SHSAX |
||||
#define __USAX __iar_builtin_USAX |
||||
#define __UQSAX __iar_builtin_UQSAX |
||||
#define __UHSAX __iar_builtin_UHSAX |
||||
#define __USAD8 __iar_builtin_USAD8 |
||||
#define __USADA8 __iar_builtin_USADA8 |
||||
#define __SSAT16 __iar_builtin_SSAT16 |
||||
#define __USAT16 __iar_builtin_USAT16 |
||||
#define __UXTB16 __iar_builtin_UXTB16 |
||||
#define __UXTAB16 __iar_builtin_UXTAB16 |
||||
#define __SXTB16 __iar_builtin_SXTB16 |
||||
#define __SXTAB16 __iar_builtin_SXTAB16 |
||||
#define __SMUAD __iar_builtin_SMUAD |
||||
#define __SMUADX __iar_builtin_SMUADX |
||||
#define __SMMLA __iar_builtin_SMMLA |
||||
#define __SMLAD __iar_builtin_SMLAD |
||||
#define __SMLADX __iar_builtin_SMLADX |
||||
#define __SMLALD __iar_builtin_SMLALD |
||||
#define __SMLALDX __iar_builtin_SMLALDX |
||||
#define __SMUSD __iar_builtin_SMUSD |
||||
#define __SMUSDX __iar_builtin_SMUSDX |
||||
#define __SMLSD __iar_builtin_SMLSD |
||||
#define __SMLSDX __iar_builtin_SMLSDX |
||||
#define __SMLSLD __iar_builtin_SMLSLD |
||||
#define __SMLSLDX __iar_builtin_SMLSLDX |
||||
#define __SEL __iar_builtin_SEL |
||||
#define __QADD __iar_builtin_QADD |
||||
#define __QSUB __iar_builtin_QSUB |
||||
#define __PKHBT __iar_builtin_PKHBT |
||||
#define __PKHTB __iar_builtin_PKHTB |
||||
#endif |
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ |
||||
|
||||
#if __IAR_M0_FAMILY |
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ |
||||
#define __CLZ __cmsis_iar_clz_not_active |
||||
#define __SSAT __cmsis_iar_ssat_not_active |
||||
#define __USAT __cmsis_iar_usat_not_active |
||||
#define __RBIT __cmsis_iar_rbit_not_active |
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active |
||||
#endif |
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )) |
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active |
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active |
||||
#endif |
||||
|
||||
#ifdef __INTRINSICS_INCLUDED |
||||
#error intrinsics.h is already included previously! |
||||
#endif |
||||
|
||||
#include <intrinsics.h> |
||||
|
||||
#if __IAR_M0_FAMILY |
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ |
||||
#undef __CLZ |
||||
#undef __SSAT |
||||
#undef __USAT |
||||
#undef __RBIT |
||||
#undef __get_APSR |
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data) |
||||
{ |
||||
if (data == 0U) { return 32U; } |
||||
|
||||
uint32_t count = 0U; |
||||
uint32_t mask = 0x80000000U; |
||||
|
||||
while ((data & mask) == 0U) |
||||
{ |
||||
count += 1U; |
||||
mask = mask >> 1U; |
||||
} |
||||
return count; |
||||
} |
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v) |
||||
{ |
||||
uint8_t sc = 31U; |
||||
uint32_t r = v; |
||||
for (v >>= 1U; v; v >>= 1U) |
||||
{ |
||||
r <<= 1U; |
||||
r |= v & 1U; |
||||
sc--; |
||||
} |
||||
return (r << sc); |
||||
} |
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm("MRS %0,APSR" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
#endif |
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )) |
||||
#undef __get_FPSCR |
||||
#undef __set_FPSCR |
||||
#define __get_FPSCR() (0) |
||||
#define __set_FPSCR(VALUE) ((void)VALUE) |
||||
#endif |
||||
|
||||
#pragma diag_suppress=Pe940 |
||||
#pragma diag_suppress=Pe177 |
||||
|
||||
#define __enable_irq __enable_interrupt |
||||
#define __disable_irq __disable_interrupt |
||||
#define __NOP __no_operation |
||||
|
||||
#define __get_xPSR __get_PSR |
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) |
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) |
||||
{ |
||||
return __LDREX((unsigned long *)ptr); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) |
||||
{ |
||||
return __STREX(value, (unsigned long *)ptr); |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ |
||||
#if (__CORTEX_M >= 0x03) |
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value) |
||||
{ |
||||
uint32_t result; |
||||
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); |
||||
return(result); |
||||
} |
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); |
||||
} |
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq |
||||
#define __disable_fault_irq __disable_fiq |
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */ |
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) |
||||
{ |
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); |
||||
} |
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void) |
||||
{ |
||||
uint32_t res; |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U; |
||||
#else |
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res)); |
||||
#endif |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value) |
||||
{ |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value; |
||||
#else |
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value)); |
||||
#endif |
||||
} |
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void) |
||||
{ |
||||
uint32_t res; |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U; |
||||
#else |
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res)); |
||||
#endif |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value) |
||||
{ |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value; |
||||
#else |
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value)); |
||||
#endif |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U; |
||||
#else |
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); |
||||
#endif |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) |
||||
{ |
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ |
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) |
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value; |
||||
#else |
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); |
||||
#endif |
||||
} |
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) |
||||
{ |
||||
uint32_t res; |
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) |
||||
{ |
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); |
||||
} |
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ |
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ |
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) |
||||
|
||||
#if __IAR_M0_FAMILY |
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) |
||||
{ |
||||
if ((sat >= 1U) && (sat <= 32U)) |
||||
{ |
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); |
||||
const int32_t min = -1 - max ; |
||||
if (val > max) |
||||
{ |
||||
return max; |
||||
} |
||||
else if (val < min) |
||||
{ |
||||
return min; |
||||
} |
||||
} |
||||
return val; |
||||
} |
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) |
||||
{ |
||||
if (sat <= 31U) |
||||
{ |
||||
const uint32_t max = ((1U << sat) - 1U); |
||||
if (val > (int32_t)max) |
||||
{ |
||||
return max; |
||||
} |
||||
else if (val < 0) |
||||
{ |
||||
return 0U; |
||||
} |
||||
} |
||||
return (uint32_t)val; |
||||
} |
||||
#endif |
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ |
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); |
||||
return ((uint8_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); |
||||
return ((uint16_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) |
||||
{ |
||||
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); |
||||
} |
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) |
||||
{ |
||||
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); |
||||
} |
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) |
||||
{ |
||||
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); |
||||
} |
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */ |
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return ((uint8_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return ((uint16_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) |
||||
{ |
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); |
||||
} |
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) |
||||
{ |
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); |
||||
} |
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) |
||||
{ |
||||
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); |
||||
} |
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return ((uint8_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return ((uint16_t)res); |
||||
} |
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) |
||||
{ |
||||
uint32_t res; |
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); |
||||
return res; |
||||
} |
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ |
||||
|
||||
#undef __IAR_FT |
||||
#undef __IAR_M0_FAMILY |
||||
#undef __ICCARM_V8 |
||||
|
||||
#pragma diag_default=Pe940 |
||||
#pragma diag_default=Pe177 |
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */ |
||||
@ -0,0 +1,39 @@ |
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h |
||||
* @brief CMSIS Core(M) Version definitions |
||||
* @version V5.0.2 |
||||
* @date 19. April 2017 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CMSIS_VERSION_H |
||||
#define __CMSIS_VERSION_H |
||||
|
||||
/* CMSIS Version definitions */ |
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ |
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ |
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ |
||||
#endif |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,949 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h |
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File |
||||
* @version V5.0.5 |
||||
* @date 28. May 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC |
||||
#define __CORE_CM0_H_GENERIC |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
||||
CMSIS violates the following MISRA-C:2004 rules: |
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br> |
||||
Function definitions in header files are used to allow 'inlining'. |
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
||||
Unions are used for effective representation of core registers. |
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br> |
||||
Function-like macros are used to allow more efficient code. |
||||
*/ |
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions |
||||
******************************************************************************/ |
||||
/**
|
||||
\ingroup Cortex_M0 |
||||
@{ |
||||
*/ |
||||
|
||||
#include "cmsis_version.h" |
||||
|
||||
/* CMSIS CM0 definitions */ |
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ |
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ |
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ |
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */ |
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all |
||||
*/ |
||||
#define __FPU_USED 0U |
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#if defined __TARGET_FPU_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#if defined __ARM_PCS_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#if defined __ARMVFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TI_ARM__ ) |
||||
#if defined __TI_VFP_SUPPORT__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#if defined __FPU_VFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#if ( __CSMC__ & 0x400U) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */ |
||||
|
||||
#ifndef __CMSIS_GENERIC |
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT |
||||
#define __CORE_CM0_H_DEPENDANT |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* check device defines and use defaults */ |
||||
#if defined __CHECK_DEVICE_DEFINES |
||||
#ifndef __CM0_REV |
||||
#define __CM0_REV 0x0000U |
||||
#warning "__CM0_REV not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __NVIC_PRIO_BITS |
||||
#define __NVIC_PRIO_BITS 2U |
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __Vendor_SysTickConfig |
||||
#define __Vendor_SysTickConfig 0U |
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
||||
#endif |
||||
#endif |
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */ |
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines |
||||
|
||||
<strong>IO Type Qualifiers</strong> are used |
||||
\li to specify the access to peripheral variables. |
||||
\li for automatic generation of peripheral register debug information. |
||||
*/ |
||||
#ifdef __cplusplus |
||||
#define __I volatile /*!< Defines 'read only' permissions */ |
||||
#else |
||||
#define __I volatile const /*!< Defines 'read only' permissions */ |
||||
#endif |
||||
#define __O volatile /*!< Defines 'write only' permissions */ |
||||
#define __IO volatile /*!< Defines 'read / write' permissions */ |
||||
|
||||
/* following defines should be used for structure members */ |
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */ |
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */ |
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
||||
|
||||
/*@} end of group Cortex_M0 */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction |
||||
Core Register contain: |
||||
- Core Register |
||||
- Core NVIC Register |
||||
- Core SCB Register |
||||
- Core SysTick Register |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions |
||||
\brief Type definitions and defines for Cortex-M processor based devices. |
||||
*/ |
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CORE Status and Control Registers |
||||
\brief Core Register type definitions. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} APSR_Type; |
||||
|
||||
/* APSR Register Definitions */ |
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */ |
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */ |
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */ |
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} IPSR_Type; |
||||
|
||||
/* IPSR Register Definitions */ |
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} xPSR_Type; |
||||
|
||||
/* xPSR Register Definitions */ |
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} CONTROL_Type; |
||||
|
||||
/* CONTROL Register Definitions */ |
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
||||
|
||||
/*@} end of group CMSIS_CORE */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
||||
\brief Type definitions for the NVIC Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
||||
uint32_t RESERVED0[31U]; |
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
||||
uint32_t RSERVED1[31U]; |
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
||||
uint32_t RESERVED2[31U]; |
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
||||
uint32_t RESERVED3[31U]; |
||||
uint32_t RESERVED4[64U]; |
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
||||
} NVIC_Type; |
||||
|
||||
/*@} end of group CMSIS_NVIC */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCB System Control Block (SCB) |
||||
\brief Type definitions for the System Control Block Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
||||
uint32_t RESERVED0; |
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
||||
uint32_t RESERVED1; |
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
||||
} SCB_Type; |
||||
|
||||
/* SCB CPUID Register Definitions */ |
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */ |
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||||
|
||||
/* SCB System Control Register Definitions */ |
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||||
|
||||
/* SCB Configuration Control Register Definitions */ |
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||||
|
||||
/* SCB System Handler Control and State Register Definitions */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||||
\brief Type definitions for the System Timer Registers. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||||
} SysTick_Type; |
||||
|
||||
/* SysTick Control / Status Register Definitions */ |
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||||
|
||||
/* SysTick Reload Register Definitions */ |
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||||
|
||||
/* SysTick Current Register Definitions */ |
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||||
|
||||
/* SysTick Calibration Register Definitions */ |
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||||
|
||||
/*@} end of group CMSIS_SysTick */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
||||
Therefore they are not covered by the Cortex-M0 header file. |
||||
@{ |
||||
*/ |
||||
/*@} end of group CMSIS_CoreDebug */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_bitfield Core register bit field macros |
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
||||
\return Masked and shifted value. |
||||
*/ |
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
||||
\return Masked and shifted bit field value. |
||||
*/ |
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
||||
|
||||
/*@} end of group CMSIS_core_bitfield */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_base Core Definitions |
||||
\brief Definitions for base addresses, unions, and structures. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Memory mapping of Core Hardware */ |
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||||
|
||||
|
||||
/*@} */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer |
||||
Core Function Interface contains: |
||||
- Core NVIC Functions |
||||
- Core SysTick Functions |
||||
- Core Register Access Functions |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||||
*/ |
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||||
\brief Functions that manage interrupts and exceptions via the NVIC. |
||||
@{ |
||||
*/ |
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL |
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
||||
#endif |
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
||||
#else |
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping |
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping |
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ |
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ |
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ |
||||
#define NVIC_SetPriority __NVIC_SetPriority |
||||
#define NVIC_GetPriority __NVIC_GetPriority |
||||
#define NVIC_SystemReset __NVIC_SystemReset |
||||
#endif /* CMSIS_NVIC_VIRTUAL */ |
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL |
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
||||
#endif |
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
||||
#else |
||||
#define NVIC_SetVector __NVIC_SetVector |
||||
#define NVIC_GetVector __NVIC_GetVector |
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */ |
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16 |
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */ |
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */ |
||||
/* The following MACROS handle generation of the register offset and byte masks */ |
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X) |
||||
#define __NVIC_GetPriorityGrouping() (0U) |
||||
|
||||
/**
|
||||
\brief Enable Interrupt |
||||
\details Enables a device specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status |
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\return 0 Interrupt is not enabled. |
||||
\return 1 Interrupt is enabled. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
else |
||||
{ |
||||
return(0U); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt |
||||
\details Disables a device specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
__DSB(); |
||||
__ISB(); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt |
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\return 0 Interrupt status is not pending. |
||||
\return 1 Interrupt status is pending. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
else |
||||
{ |
||||
return(0U); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt |
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt |
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority |
||||
\details Sets the priority of a device specific interrupt or a processor exception. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
\param [in] IRQn Interrupt number. |
||||
\param [in] priority Priority to set. |
||||
\note The priority cannot be set for every processor exception. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
else |
||||
{ |
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority |
||||
\details Reads the priority of a device specific interrupt or a processor exception. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Interrupt Priority. |
||||
Value is aligned automatically to the implemented priority bits of the microcontroller. |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
||||
{ |
||||
|
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
else |
||||
{ |
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority |
||||
\details Encodes the priority for an interrupt with the given priority group, |
||||
preemptive priority value, and subpriority value. |
||||
In case of a conflict between priority grouping and available |
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
||||
\param [in] PriorityGroup Used priority group. |
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0). |
||||
\param [in] SubPriority Subpriority value (starting from 0). |
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
||||
{ |
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
||||
uint32_t PreemptPriorityBits; |
||||
uint32_t SubPriorityBits; |
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
||||
|
||||
return ( |
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
||||
); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority |
||||
\details Decodes an interrupt priority value with a given priority group to |
||||
preemptive priority value and subpriority value. |
||||
In case of a conflict between priority grouping and available |
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
||||
\param [in] PriorityGroup Used priority group. |
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0). |
||||
\param [out] pSubPriority Subpriority value (starting from 0). |
||||
*/ |
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) |
||||
{ |
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
||||
uint32_t PreemptPriorityBits; |
||||
uint32_t SubPriorityBits; |
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
||||
} |
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector |
||||
\details Sets an interrupt vector in SRAM based interrupt vector table. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
Address 0 must be mapped to SRAM. |
||||
\param [in] IRQn Interrupt number |
||||
\param [in] vector Address of interrupt handler function |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
||||
{ |
||||
uint32_t *vectors = (uint32_t *)0x0U; |
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector |
||||
\details Reads an interrupt vector from interrupt vector table. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Address of interrupt handler function |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
||||
{ |
||||
uint32_t *vectors = (uint32_t *)0x0U; |
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief System Reset |
||||
\details Initiates a system reset request to reset the MCU. |
||||
*/ |
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) |
||||
{ |
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */ |
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||||
SCB_AIRCR_SYSRESETREQ_Msk); |
||||
__DSB(); /* Ensure completion of memory access */ |
||||
|
||||
for(;;) /* wait until reset */ |
||||
{ |
||||
__NOP(); |
||||
} |
||||
} |
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */ |
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions |
||||
\brief Function that provides FPU type. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief get FPU type |
||||
\details returns the FPU type |
||||
\returns |
||||
- \b 0: No FPU |
||||
- \b 1: Single precision FPU |
||||
- \b 2: Double + Single precision FPU |
||||
*/ |
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void) |
||||
{ |
||||
return 0U; /* No FPU */ |
||||
} |
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */ |
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||||
\brief Functions that configure the System. |
||||
@{ |
||||
*/ |
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
||||
|
||||
/**
|
||||
\brief System Tick Configuration |
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
Counter is in free running mode to generate periodic interrupts. |
||||
\param [in] ticks Number of ticks between two interrupts. |
||||
\return 0 Function succeeded. |
||||
\return 1 Function failed. |
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||||
must contain a vendor-specific implementation of this function. |
||||
*/ |
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||||
{ |
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||||
{ |
||||
return (1UL); /* Reload value impossible */ |
||||
} |
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||||
SysTick_CTRL_TICKINT_Msk | |
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||||
return (0UL); /* Function successful */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */ |
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */ |
||||
|
||||
#endif /* __CMSIS_GENERIC */ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,976 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cm1.h |
||||
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File |
||||
* @version V1.0.0 |
||||
* @date 23. July 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CM1_H_GENERIC |
||||
#define __CORE_CM1_H_GENERIC |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
||||
CMSIS violates the following MISRA-C:2004 rules: |
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br> |
||||
Function definitions in header files are used to allow 'inlining'. |
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
||||
Unions are used for effective representation of core registers. |
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br> |
||||
Function-like macros are used to allow more efficient code. |
||||
*/ |
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions |
||||
******************************************************************************/ |
||||
/**
|
||||
\ingroup Cortex_M1 |
||||
@{ |
||||
*/ |
||||
|
||||
#include "cmsis_version.h" |
||||
|
||||
/* CMSIS CM1 definitions */ |
||||
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ |
||||
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ |
||||
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ |
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */ |
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all |
||||
*/ |
||||
#define __FPU_USED 0U |
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#if defined __TARGET_FPU_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#if defined __ARM_PCS_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#if defined __ARMVFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TI_ARM__ ) |
||||
#if defined __TI_VFP_SUPPORT__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#if defined __FPU_VFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#if ( __CSMC__ & 0x400U) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM1_H_GENERIC */ |
||||
|
||||
#ifndef __CMSIS_GENERIC |
||||
|
||||
#ifndef __CORE_CM1_H_DEPENDANT |
||||
#define __CORE_CM1_H_DEPENDANT |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* check device defines and use defaults */ |
||||
#if defined __CHECK_DEVICE_DEFINES |
||||
#ifndef __CM1_REV |
||||
#define __CM1_REV 0x0100U |
||||
#warning "__CM1_REV not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __NVIC_PRIO_BITS |
||||
#define __NVIC_PRIO_BITS 2U |
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __Vendor_SysTickConfig |
||||
#define __Vendor_SysTickConfig 0U |
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
||||
#endif |
||||
#endif |
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */ |
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines |
||||
|
||||
<strong>IO Type Qualifiers</strong> are used |
||||
\li to specify the access to peripheral variables. |
||||
\li for automatic generation of peripheral register debug information. |
||||
*/ |
||||
#ifdef __cplusplus |
||||
#define __I volatile /*!< Defines 'read only' permissions */ |
||||
#else |
||||
#define __I volatile const /*!< Defines 'read only' permissions */ |
||||
#endif |
||||
#define __O volatile /*!< Defines 'write only' permissions */ |
||||
#define __IO volatile /*!< Defines 'read / write' permissions */ |
||||
|
||||
/* following defines should be used for structure members */ |
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */ |
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */ |
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
||||
|
||||
/*@} end of group Cortex_M1 */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction |
||||
Core Register contain: |
||||
- Core Register |
||||
- Core NVIC Register |
||||
- Core SCB Register |
||||
- Core SysTick Register |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions |
||||
\brief Type definitions and defines for Cortex-M processor based devices. |
||||
*/ |
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CORE Status and Control Registers |
||||
\brief Core Register type definitions. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} APSR_Type; |
||||
|
||||
/* APSR Register Definitions */ |
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */ |
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */ |
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */ |
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} IPSR_Type; |
||||
|
||||
/* IPSR Register Definitions */ |
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} xPSR_Type; |
||||
|
||||
/* xPSR Register Definitions */ |
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} CONTROL_Type; |
||||
|
||||
/* CONTROL Register Definitions */ |
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
||||
|
||||
/*@} end of group CMSIS_CORE */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
||||
\brief Type definitions for the NVIC Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
||||
uint32_t RESERVED0[31U]; |
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
||||
uint32_t RSERVED1[31U]; |
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
||||
uint32_t RESERVED2[31U]; |
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
||||
uint32_t RESERVED3[31U]; |
||||
uint32_t RESERVED4[64U]; |
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
||||
} NVIC_Type; |
||||
|
||||
/*@} end of group CMSIS_NVIC */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCB System Control Block (SCB) |
||||
\brief Type definitions for the System Control Block Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
||||
uint32_t RESERVED0; |
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
||||
uint32_t RESERVED1; |
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
||||
} SCB_Type; |
||||
|
||||
/* SCB CPUID Register Definitions */ |
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */ |
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||||
|
||||
/* SCB System Control Register Definitions */ |
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||||
|
||||
/* SCB Configuration Control Register Definitions */ |
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||||
|
||||
/* SCB System Handler Control and State Register Definitions */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
||||
\brief Type definitions for the System Control and ID Register not in the SCB |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB. |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t RESERVED0[2U]; |
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
||||
} SCnSCB_Type; |
||||
|
||||
/* Auxiliary Control Register Definitions */ |
||||
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ |
||||
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ |
||||
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ |
||||
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||||
\brief Type definitions for the System Timer Registers. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||||
} SysTick_Type; |
||||
|
||||
/* SysTick Control / Status Register Definitions */ |
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||||
|
||||
/* SysTick Reload Register Definitions */ |
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||||
|
||||
/* SysTick Current Register Definitions */ |
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||||
|
||||
/* SysTick Calibration Register Definitions */ |
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||||
|
||||
/*@} end of group CMSIS_SysTick */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||||
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
||||
Therefore they are not covered by the Cortex-M1 header file. |
||||
@{ |
||||
*/ |
||||
/*@} end of group CMSIS_CoreDebug */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_bitfield Core register bit field macros |
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
||||
\return Masked and shifted value. |
||||
*/ |
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
||||
\return Masked and shifted bit field value. |
||||
*/ |
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
||||
|
||||
/*@} end of group CMSIS_core_bitfield */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_base Core Definitions |
||||
\brief Definitions for base addresses, unions, and structures. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Memory mapping of Core Hardware */ |
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||||
|
||||
|
||||
/*@} */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer |
||||
Core Function Interface contains: |
||||
- Core NVIC Functions |
||||
- Core SysTick Functions |
||||
- Core Register Access Functions |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||||
*/ |
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||||
\brief Functions that manage interrupts and exceptions via the NVIC. |
||||
@{ |
||||
*/ |
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL |
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
||||
#endif |
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
||||
#else |
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping |
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping |
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ |
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ |
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ |
||||
#define NVIC_SetPriority __NVIC_SetPriority |
||||
#define NVIC_GetPriority __NVIC_GetPriority |
||||
#define NVIC_SystemReset __NVIC_SystemReset |
||||
#endif /* CMSIS_NVIC_VIRTUAL */ |
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL |
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
||||
#endif |
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
||||
#else |
||||
#define NVIC_SetVector __NVIC_SetVector |
||||
#define NVIC_GetVector __NVIC_GetVector |
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */ |
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16 |
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */ |
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */ |
||||
/* The following MACROS handle generation of the register offset and byte masks */ |
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X) |
||||
#define __NVIC_GetPriorityGrouping() (0U) |
||||
|
||||
/**
|
||||
\brief Enable Interrupt |
||||
\details Enables a device specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status |
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\return 0 Interrupt is not enabled. |
||||
\return 1 Interrupt is enabled. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
else |
||||
{ |
||||
return(0U); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt |
||||
\details Disables a device specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
__DSB(); |
||||
__ISB(); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt |
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\return 0 Interrupt status is not pending. |
||||
\return 1 Interrupt status is pending. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
else |
||||
{ |
||||
return(0U); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt |
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt |
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
||||
\param [in] IRQn Device specific interrupt number. |
||||
\note IRQn must not be negative. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority |
||||
\details Sets the priority of a device specific interrupt or a processor exception. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
\param [in] IRQn Interrupt number. |
||||
\param [in] priority Priority to set. |
||||
\note The priority cannot be set for every processor exception. |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||||
{ |
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
else |
||||
{ |
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority |
||||
\details Reads the priority of a device specific interrupt or a processor exception. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Interrupt Priority. |
||||
Value is aligned automatically to the implemented priority bits of the microcontroller. |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
||||
{ |
||||
|
||||
if ((int32_t)(IRQn) >= 0) |
||||
{ |
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
else |
||||
{ |
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority |
||||
\details Encodes the priority for an interrupt with the given priority group, |
||||
preemptive priority value, and subpriority value. |
||||
In case of a conflict between priority grouping and available |
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
||||
\param [in] PriorityGroup Used priority group. |
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0). |
||||
\param [in] SubPriority Subpriority value (starting from 0). |
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
||||
{ |
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
||||
uint32_t PreemptPriorityBits; |
||||
uint32_t SubPriorityBits; |
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
||||
|
||||
return ( |
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
||||
); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority |
||||
\details Decodes an interrupt priority value with a given priority group to |
||||
preemptive priority value and subpriority value. |
||||
In case of a conflict between priority grouping and available |
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
||||
\param [in] PriorityGroup Used priority group. |
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0). |
||||
\param [out] pSubPriority Subpriority value (starting from 0). |
||||
*/ |
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) |
||||
{ |
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
||||
uint32_t PreemptPriorityBits; |
||||
uint32_t SubPriorityBits; |
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
||||
} |
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector |
||||
\details Sets an interrupt vector in SRAM based interrupt vector table. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
Address 0 must be mapped to SRAM. |
||||
\param [in] IRQn Interrupt number |
||||
\param [in] vector Address of interrupt handler function |
||||
*/ |
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
||||
{ |
||||
uint32_t *vectors = (uint32_t *)0x0U; |
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector |
||||
\details Reads an interrupt vector from interrupt vector table. |
||||
The interrupt number can be positive to specify a device specific interrupt, |
||||
or negative to specify a processor exception. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Address of interrupt handler function |
||||
*/ |
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
||||
{ |
||||
uint32_t *vectors = (uint32_t *)0x0U; |
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief System Reset |
||||
\details Initiates a system reset request to reset the MCU. |
||||
*/ |
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) |
||||
{ |
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */ |
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||||
SCB_AIRCR_SYSRESETREQ_Msk); |
||||
__DSB(); /* Ensure completion of memory access */ |
||||
|
||||
for(;;) /* wait until reset */ |
||||
{ |
||||
__NOP(); |
||||
} |
||||
} |
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */ |
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions |
||||
\brief Function that provides FPU type. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief get FPU type |
||||
\details returns the FPU type |
||||
\returns |
||||
- \b 0: No FPU |
||||
- \b 1: Single precision FPU |
||||
- \b 2: Double + Single precision FPU |
||||
*/ |
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void) |
||||
{ |
||||
return 0U; /* No FPU */ |
||||
} |
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */ |
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||||
\brief Functions that configure the System. |
||||
@{ |
||||
*/ |
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
||||
|
||||
/**
|
||||
\brief System Tick Configuration |
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
Counter is in free running mode to generate periodic interrupts. |
||||
\param [in] ticks Number of ticks between two interrupts. |
||||
\return 0 Function succeeded. |
||||
\return 1 Function failed. |
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||||
must contain a vendor-specific implementation of this function. |
||||
*/ |
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||||
{ |
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||||
{ |
||||
return (1UL); /* Reload value impossible */ |
||||
} |
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||||
SysTick_CTRL_TICKINT_Msk | |
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||||
return (0UL); /* Function successful */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */ |
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM1_H_DEPENDANT */ |
||||
|
||||
#endif /* __CMSIS_GENERIC */ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,270 @@ |
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h |
||||
* @brief CMSIS MPU API for Armv7-M MPU |
||||
* @version V5.0.4 |
||||
* @date 10. January 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef ARM_MPU_ARMV7_H |
||||
#define ARM_MPU_ARMV7_H |
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
* |
||||
* \param Region The region to be configured, number 0 to 15. |
||||
* \param BaseAddress The base address for the region. |
||||
*/ |
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \ |
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk)) |
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes |
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. |
||||
* \param IsShareable Region is shareable between multiple bus masters. |
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. |
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. |
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ |
||||
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) |
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value |
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. |
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. |
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. |
||||
* \param SubRegionDisable Sub-region disable field. |
||||
* \param Size Region size of the region to be configured, for example 4K, 8K. |
||||
*/ |
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ |
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) |
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value |
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. |
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. |
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. |
||||
* \param IsShareable Region is shareable between multiple bus masters. |
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. |
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. |
||||
* \param SubRegionDisable Sub-region disable field. |
||||
* \param Size Region size of the region to be configured, for example 4K, 8K. |
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ |
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory. |
||||
* - TEX: 000b |
||||
* - Shareable |
||||
* - Non-cacheable |
||||
* - Non-bufferable |
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory. |
||||
* - TEX: 000b (if non-shareable) or 010b (if shareable) |
||||
* - Shareable or non-shareable |
||||
* - Non-cacheable |
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable) |
||||
* |
||||
* \param IsShareable Configures the device memory as shareable or non-shareable. |
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory. |
||||
* - TEX: 1BBb (reflecting outer cacheability rules) |
||||
* - Shareable or non-shareable |
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules) |
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules) |
||||
* |
||||
* \param OuterCp Configures the outer cache policy. |
||||
* \param InnerCp Configures the inner cache policy. |
||||
* \param IsShareable Configures the memory as shareable or non-shareable. |
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy. |
||||
*/ |
||||
#define ARM_MPU_CACHEP_NOCACHE 0U |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy. |
||||
*/ |
||||
#define ARM_MPU_CACHEP_WB_WRA 1U |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy. |
||||
*/ |
||||
#define ARM_MPU_CACHEP_WT_NWA 2U |
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy. |
||||
*/ |
||||
#define ARM_MPU_CACHEP_WB_NWA 3U |
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region |
||||
*/ |
||||
typedef struct { |
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t; |
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
} |
||||
|
||||
/** Disable the MPU.
|
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Disable(void) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; |
||||
} |
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) |
||||
{ |
||||
MPU->RNR = rnr; |
||||
MPU->RASR = 0U; |
||||
} |
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register. |
||||
* \param rsar Value for RSAR register. |
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) |
||||
{ |
||||
MPU->RBAR = rbar; |
||||
MPU->RASR = rasr; |
||||
} |
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured. |
||||
* \param rbar Value for RBAR register. |
||||
* \param rsar Value for RSAR register. |
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) |
||||
{ |
||||
MPU->RNR = rnr; |
||||
MPU->RBAR = rbar; |
||||
MPU->RASR = rasr; |
||||
} |
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to. |
||||
* \param src Source data is copied from. |
||||
* \param len Amount of data words to be copied. |
||||
*/ |
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) |
||||
{ |
||||
uint32_t i; |
||||
for (i = 0U; i < len; ++i)
|
||||
{ |
||||
dst[i] = src[i]; |
||||
} |
||||
} |
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table. |
||||
* \param cnt Amount of regions to be configured. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{ |
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; |
||||
while (cnt > MPU_TYPE_RALIASES) { |
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); |
||||
table += MPU_TYPE_RALIASES; |
||||
cnt -= MPU_TYPE_RALIASES; |
||||
} |
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); |
||||
} |
||||
|
||||
#endif |
||||
@ -0,0 +1,333 @@ |
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h |
||||
* @brief CMSIS MPU API for Armv8-M MPU |
||||
* @version V5.0.4 |
||||
* @date 10. January 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef ARM_MPU_ARMV8_H |
||||
#define ARM_MPU_ARMV8_H |
||||
|
||||
/** \brief Attribute for device memory (outer only) */ |
||||
#define ARM_MPU_ATTR_DEVICE ( 0U ) |
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */ |
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) |
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data. |
||||
* \param WB Write-Back: Set to 1 to use write-back update policy. |
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. |
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. |
||||
*/ |
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ |
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) |
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ |
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) |
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ |
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) |
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ |
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U) |
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ |
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U) |
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes |
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes |
||||
*/ |
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) |
||||
|
||||
/** \brief Normal memory non-shareable */ |
||||
#define ARM_MPU_SH_NON (0U) |
||||
|
||||
/** \brief Normal memory outer shareable */ |
||||
#define ARM_MPU_SH_OUTER (2U) |
||||
|
||||
/** \brief Normal memory inner shareable */ |
||||
#define ARM_MPU_SH_INNER (3U) |
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory. |
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory. |
||||
*/ |
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) |
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. |
||||
* \param SH Defines the Shareability domain for this memory region. |
||||
* \param RO Read-Only: Set to 1 for a read-only memory region. |
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. |
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. |
||||
*/ |
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ |
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) |
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. |
||||
* \param IDX The attribute index to be associated with this memory region. |
||||
*/ |
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \ |
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk)) |
||||
|
||||
/**
|
||||
* Struct for a single MPU Region |
||||
*/ |
||||
typedef struct { |
||||
uint32_t RBAR; /*!< Region Base Address Register value */ |
||||
uint32_t RLAR; /*!< Region Limit Address Register value */ |
||||
} ARM_MPU_Region_t; |
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
} |
||||
|
||||
/** Disable the MPU.
|
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Disable(void) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; |
||||
} |
||||
|
||||
#ifdef MPU_NS |
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
} |
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void) |
||||
{ |
||||
__DSB(); |
||||
__ISB(); |
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk |
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
||||
#endif |
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; |
||||
} |
||||
#endif |
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured. |
||||
* \param idx The attribute index to be set [0-7] |
||||
* \param attr The attribute value to be set. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) |
||||
{ |
||||
const uint8_t reg = idx / 4U; |
||||
const uint32_t pos = ((idx % 4U) * 8U); |
||||
const uint32_t mask = 0xFFU << pos; |
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { |
||||
return; // invalid index
|
||||
} |
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); |
||||
} |
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7] |
||||
* \param attr The attribute value to be set. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) |
||||
{ |
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr); |
||||
} |
||||
|
||||
#ifdef MPU_NS |
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7] |
||||
* \param attr The attribute value to be set. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) |
||||
{ |
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); |
||||
} |
||||
#endif |
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used. |
||||
* \param rnr Region number to be cleared. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) |
||||
{ |
||||
mpu->RNR = rnr; |
||||
mpu->RLAR = 0U; |
||||
} |
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) |
||||
{ |
||||
ARM_MPU_ClrRegionEx(MPU, rnr); |
||||
} |
||||
|
||||
#ifdef MPU_NS |
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) |
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr); |
||||
} |
||||
#endif |
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used. |
||||
* \param rnr Region number to be configured. |
||||
* \param rbar Value for RBAR register. |
||||
* \param rlar Value for RLAR register. |
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) |
||||
{ |
||||
mpu->RNR = rnr; |
||||
mpu->RBAR = rbar; |
||||
mpu->RLAR = rlar; |
||||
} |
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured. |
||||
* \param rbar Value for RBAR register. |
||||
* \param rlar Value for RLAR register. |
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) |
||||
{ |
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); |
||||
} |
||||
|
||||
#ifdef MPU_NS |
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured. |
||||
* \param rbar Value for RBAR register. |
||||
* \param rlar Value for RLAR register. |
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) |
||||
{ |
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
} |
||||
#endif |
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to. |
||||
* \param src Source data is copied from. |
||||
* \param len Amount of data words to be copied. |
||||
*/ |
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) |
||||
{ |
||||
uint32_t i; |
||||
for (i = 0U; i < len; ++i)
|
||||
{ |
||||
dst[i] = src[i]; |
||||
} |
||||
} |
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used. |
||||
* \param rnr First region number to be configured. |
||||
* \param table Pointer to the MPU configuration table. |
||||
* \param cnt Amount of regions to be configured. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{ |
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; |
||||
if (cnt == 1U) { |
||||
mpu->RNR = rnr; |
||||
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); |
||||
} else { |
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); |
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; |
||||
|
||||
mpu->RNR = rnrBase; |
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { |
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset; |
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); |
||||
table += c; |
||||
cnt -= c; |
||||
rnrOffset = 0U; |
||||
rnrBase += MPU_TYPE_RALIASES; |
||||
mpu->RNR = rnrBase; |
||||
} |
||||
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); |
||||
} |
||||
} |
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured. |
||||
* \param table Pointer to the MPU configuration table. |
||||
* \param cnt Amount of regions to be configured. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{ |
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt); |
||||
} |
||||
|
||||
#ifdef MPU_NS |
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured. |
||||
* \param table Pointer to the MPU configuration table. |
||||
* \param cnt Amount of regions to be configured. |
||||
*/ |
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{ |
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); |
||||
} |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
@ -0,0 +1,70 @@ |
||||
/******************************************************************************
|
||||
* @file tz_context.h |
||||
* @brief Context Management for Armv8-M TrustZone |
||||
* @version V1.0.1 |
||||
* @date 10. January 2018 |
||||
******************************************************************************/ |
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
* |
||||
* Licensed under the Apache License, Version 2.0 (the License); you may |
||||
* not use this file except in compliance with the License. |
||||
* You may obtain a copy of the License at |
||||
* |
||||
* www.apache.org/licenses/LICENSE-2.0 |
||||
* |
||||
* Unless required by applicable law or agreed to in writing, software |
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||||
* See the License for the specific language governing permissions and |
||||
* limitations under the License. |
||||
*/ |
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined (__clang__) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef TZ_CONTEXT_H |
||||
#define TZ_CONTEXT_H |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifndef TZ_MODULEID_T |
||||
#define TZ_MODULEID_T |
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t; |
||||
#endif |
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t; |
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void); |
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); |
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); |
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); |
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); |
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
@ -0,0 +1,201 @@ |
||||
Apache License |
||||
Version 2.0, January 2004 |
||||
http://www.apache.org/licenses/ |
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION |
||||
|
||||
1. Definitions. |
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction, |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,358 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal.h |
||||
* @author MCD Application Team |
||||
* @brief This file contains all the functions prototypes for the HAL |
||||
* module driver. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_H |
||||
#define __STM32F1xx_HAL_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_conf.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup HAL
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||
* @{ |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_TICK_FREQ_10HZ = 100U, |
||||
HAL_TICK_FREQ_100HZ = 10U, |
||||
HAL_TICK_FREQ_1KHZ = 1U, |
||||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ |
||||
} HAL_TickFreqTypeDef; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Exported types ------------------------------------------------------------*/ |
||||
extern __IO uint32_t uwTick; |
||||
extern uint32_t uwTickPrio; |
||||
extern HAL_TickFreqTypeDef uwTickFreq; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
|
||||
* @brief Freeze/Unfreeze Peripherals in Debug mode |
||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
||||
* STM32F101xF/G and STM32F103xF/G |
||||
* STM32F10xx4 and STM32F10xx6 |
||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
||||
* debug mode (not accessible by the user software in normal mode). |
||||
* Refer to errata sheet of these devices for more details. |
||||
* @{ |
||||
*/ |
||||
|
||||
/* Peripherals on APB1 */ |
||||
/**
|
||||
* @brief TIM2 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) |
||||
|
||||
/**
|
||||
* @brief TIM3 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM4_STOP) |
||||
/**
|
||||
* @brief TIM4 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM5_STOP) |
||||
/**
|
||||
* @brief TIM5 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM6_STOP) |
||||
/**
|
||||
* @brief TIM6 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM7_STOP) |
||||
/**
|
||||
* @brief TIM7 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM12_STOP) |
||||
/**
|
||||
* @brief TIM12 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM13_STOP) |
||||
/**
|
||||
* @brief TIM13 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM14_STOP) |
||||
/**
|
||||
* @brief TIM14 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) |
||||
#endif |
||||
|
||||
/**
|
||||
* @brief WWDG Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) |
||||
|
||||
/**
|
||||
* @brief IWDG Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) |
||||
|
||||
/**
|
||||
* @brief I2C1 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) |
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) |
||||
|
||||
#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
||||
/**
|
||||
* @brief I2C2 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
||||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_CAN1_STOP) |
||||
/**
|
||||
* @brief CAN1 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_CAN2_STOP) |
||||
/**
|
||||
* @brief CAN2 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) |
||||
#endif |
||||
|
||||
/* Peripherals on APB2 */ |
||||
#if defined (DBGMCU_CR_DBG_TIM1_STOP) |
||||
/**
|
||||
* @brief TIM1 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM8_STOP) |
||||
/**
|
||||
* @brief TIM8 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM9_STOP) |
||||
/**
|
||||
* @brief TIM9 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM10_STOP) |
||||
/**
|
||||
* @brief TIM10 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM11_STOP) |
||||
/**
|
||||
* @brief TIM11 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) |
||||
#endif |
||||
|
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM15_STOP) |
||||
/**
|
||||
* @brief TIM15 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM16_STOP) |
||||
/**
|
||||
* @brief TIM16 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_CR_DBG_TIM17_STOP) |
||||
/**
|
||||
* @brief TIM17 Peripherals Debug mode |
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{ |
||||
*/ |
||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ |
||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_1KHZ)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
/* Initialization and de-initialization functions ******************************/ |
||||
HAL_StatusTypeDef HAL_Init(void); |
||||
HAL_StatusTypeDef HAL_DeInit(void); |
||||
void HAL_MspInit(void); |
||||
void HAL_MspDeInit(void); |
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral Control functions ************************************************/ |
||||
void HAL_IncTick(void); |
||||
void HAL_Delay(uint32_t Delay); |
||||
uint32_t HAL_GetTick(void); |
||||
uint32_t HAL_GetTickPrio(void); |
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); |
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void); |
||||
void HAL_SuspendTick(void); |
||||
void HAL_ResumeTick(void); |
||||
uint32_t HAL_GetHalVersion(void); |
||||
uint32_t HAL_GetREVID(void); |
||||
uint32_t HAL_GetDEVID(void); |
||||
uint32_t HAL_GetUIDw0(void); |
||||
uint32_t HAL_GetUIDw1(void); |
||||
uint32_t HAL_GetUIDw2(void); |
||||
void HAL_DBGMCU_EnableDBGSleepMode(void); |
||||
void HAL_DBGMCU_DisableDBGSleepMode(void); |
||||
void HAL_DBGMCU_EnableDBGStopMode(void); |
||||
void HAL_DBGMCU_DisableDBGStopMode(void); |
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void); |
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Private types -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/** @defgroup HAL_Private_Variables HAL Private Variables
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/* Private functions ---------------------------------------------------------*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F1xx_HAL_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,710 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_adc_ex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of ADC HAL extension module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_ADC_EX_H |
||||
#define __STM32F1xx_HAL_ADC_EX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup ADCEx
|
||||
* @{ |
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief ADC Configuration injected Channel structure definition |
||||
* @note Parameters of this structure are shared within 2 scopes: |
||||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset |
||||
* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, |
||||
* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. |
||||
* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. |
||||
* ADC state can be either: |
||||
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv') |
||||
* - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group. |
||||
*/ |
||||
typedef struct
|
||||
{ |
||||
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
|
||||
This parameter can be a value of @ref ADC_channels |
||||
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. |
||||
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) |
||||
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. |
||||
It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. |
||||
Refer to errata sheet of these devices for more details. */ |
||||
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
|
||||
This parameter must be a value of @ref ADCEx_injected_rank |
||||
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ |
||||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles |
||||
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). |
||||
This parameter can be a value of @ref ADC_sampling_times |
||||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. |
||||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. |
||||
Note: In case of usage of internal measurement channels (VrefInt/TempSensor), |
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
||||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */ |
||||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
|
||||
Offset value must be a positive number. |
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), |
||||
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. |
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4. |
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
||||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
||||
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
||||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
||||
This parameter can be set to ENABLE or DISABLE. |
||||
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. |
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
||||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
||||
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
|
||||
This parameter can be set to ENABLE or DISABLE. |
||||
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) |
||||
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) |
||||
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. |
||||
To maintain JAUTO always enabled, DMA must be configured in circular mode. |
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
||||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
||||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
|
||||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. |
||||
If set to external trigger source, triggering is on event rising edge. |
||||
This parameter can be a value of @ref ADCEx_External_trigger_source_Injected |
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). |
||||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) |
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
||||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
||||
}ADC_InjectionConfTypeDef; |
||||
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
/**
|
||||
* @brief Structure definition of ADC multimode |
||||
* @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). |
||||
* State of ADCs of the common group must be: disabled. |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
|
||||
This parameter can be a value of @ref ADCEx_Common_mode |
||||
Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. |
||||
Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2. |
||||
Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode. |
||||
Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters). |
||||
The equivalences are: |
||||
- Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'. |
||||
- Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */ |
||||
|
||||
|
||||
}ADC_MultiModeTypeDef;
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
|
||||
* @{ |
||||
*/ |
||||
#define ADC_INJECTED_RANK_1 0x00000001U |
||||
#define ADC_INJECTED_RANK_2 0x00000002U |
||||
#define ADC_INJECTED_RANK_3 0x00000003U |
||||
#define ADC_INJECTED_RANK_4 0x00000004U |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
|
||||
* @{ |
||||
*/ |
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U |
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
|
||||
* @{ |
||||
*/ |
||||
/*!< List of external triggers with generic trigger name, independently of */ |
||||
/* ADC target, sorted by trigger name: */ |
||||
|
||||
/*!< External triggers of regular group for ADC1&ADC2 only */ |
||||
#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 |
||||
#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 |
||||
#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 |
||||
#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO |
||||
#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 |
||||
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 |
||||
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG) |
||||
/*!< External triggers of regular group for ADC3 only */ |
||||
#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3 |
||||
#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1 |
||||
#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1 |
||||
#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3 |
||||
#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1 |
||||
#endif /* STM32F103xE || defined STM32F103xG */ |
||||
|
||||
/*!< External triggers of regular group for all ADC instances */ |
||||
#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3 |
||||
|
||||
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) |
||||
/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ |
||||
/* XL-density devices. */ |
||||
/* To use it on ADC or ADC2, a remap of trigger must be done from */ |
||||
/* EXTI line 11 to TIM8_TRGO with macro: */ |
||||
/* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */ |
||||
/* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */ |
||||
|
||||
/* Note for internal constant value management: If TIM8_TRGO is available, */ |
||||
/* its definition is set to value for ADC1&ADC2 by default and changed to */ |
||||
/* value for ADC3 by HAL ADC driver if ADC3 is selected. */ |
||||
#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO |
||||
#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||||
|
||||
#define ADC_SOFTWARE_START ADC1_2_3_SWSTART |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
|
||||
* @{ |
||||
*/ |
||||
/*!< List of external triggers with generic trigger name, independently of */ |
||||
/* ADC target, sorted by trigger name: */ |
||||
|
||||
/*!< External triggers of injected group for ADC1&ADC2 only */ |
||||
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO |
||||
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 |
||||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 |
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO |
||||
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 |
||||
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG) |
||||
/*!< External triggers of injected group for ADC3 only */ |
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3 |
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2 |
||||
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO |
||||
#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4 |
||||
#endif /* STM32F103xE || defined STM32F103xG */ |
||||
|
||||
/*!< External triggers of injected group for all ADC instances */ |
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 |
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO |
||||
|
||||
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) |
||||
/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ |
||||
/* XL-density devices. */ |
||||
/* To use it on ADC1 or ADC2, a remap of trigger must be done from */ |
||||
/* EXTI line 11 to TIM8_CC4 with macro: */ |
||||
/* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */ |
||||
/* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */ |
||||
|
||||
/* Note for internal constant value management: If TIM8_CC4 is available, */ |
||||
/* its definition is set to value for ADC1&ADC2 by default and changed to */ |
||||
/* value for ADC3 by HAL ADC driver if ADC3 is selected. */ |
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 |
||||
#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||||
|
||||
#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
|
||||
* @{ |
||||
*/ |
||||
#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ |
||||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */ |
||||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */ |
||||
#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ |
||||
#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ |
||||
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */ |
||||
#define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */ |
||||
#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ |
||||
#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ |
||||
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
|
||||
* @{ |
||||
*/ |
||||
/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */ |
||||
/* instance is available on the selected device). */ |
||||
/* (used internally by HAL driver. To not use into HAL structure parameters) */ |
||||
|
||||
/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */ |
||||
#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U |
||||
#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0)) |
||||
#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
||||
#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 )) |
||||
#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
||||
#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) |
||||
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ |
||||
/* XL-density devices. */ |
||||
#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11 |
||||
#endif |
||||
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG) |
||||
/* External triggers of regular group for ADC3 */ |
||||
#define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 |
||||
#define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2 |
||||
#define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2 |
||||
#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO |
||||
#define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4 |
||||
#define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11 |
||||
#endif |
||||
|
||||
/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */ |
||||
#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) |
||||
#define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
|
||||
* @{ |
||||
*/ |
||||
/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */ |
||||
/* instance is available on the selected device). */ |
||||
/* (used internally by HAL driver. To not use into HAL structure parameters) */ |
||||
|
||||
/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */ |
||||
#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) |
||||
#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
||||
#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 )) |
||||
#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) |
||||
#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) |
||||
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ |
||||
/* XL-density devices. */ |
||||
#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 |
||||
#endif |
||||
|
||||
#if defined (STM32F103xE) || defined (STM32F103xG) |
||||
/* External triggers of injected group for ADC3 */ |
||||
#define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO |
||||
#define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 |
||||
#define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 |
||||
#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO |
||||
#define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 |
||||
#endif /* STM32F103xE || defined STM32F103xG */ |
||||
|
||||
/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */ |
||||
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U |
||||
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0)) |
||||
#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
|
||||
/* Private macro -------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
|
||||
* @{ |
||||
*/ |
||||
/* Macro reserved for internal HAL driver usage, not intended to be used in */ |
||||
/* code of final user. */ |
||||
|
||||
|
||||
/**
|
||||
* @brief For devices with 3 ADCs: Defines the external trigger source
|
||||
* for regular group according to ADC into common group ADC1&ADC2 or
|
||||
* ADC3 (some triggers with same source have different value to |
||||
* be programmed into ADC EXTSEL bits of CR2 register). |
||||
* For devices with 2 ADCs or less: this macro makes no change. |
||||
* @param __HANDLE__: ADC handle |
||||
* @param __EXT_TRIG_CONV__: External trigger selected for regular group. |
||||
* @retval External trigger to be programmed into EXTSEL bits of CR2 register |
||||
*/ |
||||
#if defined (STM32F103xE) || defined (STM32F103xG) |
||||
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ |
||||
(( (((__HANDLE__)->Instance) == ADC3) \
|
||||
)? \
|
||||
( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
|
||||
)? \
|
||||
(ADC3_EXTERNALTRIG_T8_TRGO) \
|
||||
: \
|
||||
(__EXT_TRIG_CONV__) \
|
||||
) \
|
||||
: \
|
||||
(__EXT_TRIG_CONV__) \
|
||||
) |
||||
#else |
||||
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \ |
||||
(__EXT_TRIG_CONV__) |
||||
#endif /* STM32F103xE || STM32F103xG */ |
||||
|
||||
/**
|
||||
* @brief For devices with 3 ADCs: Defines the external trigger source
|
||||
* for injected group according to ADC into common group ADC1&ADC2 or
|
||||
* ADC3 (some triggers with same source have different value to |
||||
* be programmed into ADC JEXTSEL bits of CR2 register). |
||||
* For devices with 2 ADCs or less: this macro makes no change. |
||||
* @param __HANDLE__: ADC handle |
||||
* @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group. |
||||
* @retval External trigger to be programmed into JEXTSEL bits of CR2 register |
||||
*/ |
||||
#if defined (STM32F103xE) || defined (STM32F103xG) |
||||
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ |
||||
(( (((__HANDLE__)->Instance) == ADC3) \
|
||||
)? \
|
||||
( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
|
||||
)? \
|
||||
(ADC3_EXTERNALTRIGINJEC_T8_CC4) \
|
||||
: \
|
||||
(__EXT_TRIG_INJECTCONV__) \
|
||||
) \
|
||||
: \
|
||||
(__EXT_TRIG_INJECTCONV__) \
|
||||
) |
||||
#else |
||||
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ |
||||
(__EXT_TRIG_INJECTCONV__) |
||||
#endif /* STM32F103xE || STM32F103xG */ |
||||
|
||||
|
||||
/**
|
||||
* @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs) |
||||
* @param __HANDLE__: ADC handle |
||||
* @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled |
||||
*/ |
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ |
||||
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
|
||||
)? \
|
||||
(ADC1->CR1 & ADC_CR1_DUALMOD) \
|
||||
: \
|
||||
(RESET) \
|
||||
) |
||||
#else |
||||
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ |
||||
(RESET) |
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ |
||||
|
||||
/**
|
||||
* @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs) |
||||
* @param __HANDLE__: ADC handle |
||||
* @retval None |
||||
*/ |
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ |
||||
(( (((__HANDLE__)->Instance) == ADC2) \
|
||||
)? \
|
||||
((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \
|
||||
: \
|
||||
(!RESET) \
|
||||
) |
||||
#else |
||||
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ |
||||
(!RESET) |
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ |
||||
|
||||
/**
|
||||
* @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs) |
||||
* @param __HANDLE__: ADC handle |
||||
* @retval None |
||||
*/ |
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ |
||||
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
|
||||
)? \
|
||||
(ADC1->CR1 & ADC_CR1_JAUTO) \
|
||||
: \
|
||||
(RESET) \
|
||||
) |
||||
#else |
||||
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ |
||||
(RESET) |
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ |
||||
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
/**
|
||||
* @brief Set handle of the other ADC sharing the common multimode settings |
||||
* @param __HANDLE__: ADC handle |
||||
* @param __HANDLE_OTHER_ADC__: other ADC handle |
||||
* @retval None |
||||
*/ |
||||
#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ |
||||
((__HANDLE_OTHER_ADC__)->Instance = ADC2) |
||||
|
||||
/**
|
||||
* @brief Set handle of the ADC slave associated to the ADC master |
||||
* On STM32F1 devices, ADC slave is always ADC2 (this can be different |
||||
* on other STM32 devices) |
||||
* @param __HANDLE_MASTER__: ADC master handle |
||||
* @param __HANDLE_SLAVE__: ADC slave handle |
||||
* @retval None |
||||
*/ |
||||
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ |
||||
((__HANDLE_SLAVE__)->Instance = ADC2) |
||||
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ |
||||
|
||||
#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ |
||||
((CHANNEL) == ADC_INJECTED_RANK_2) || \
|
||||
((CHANNEL) == ADC_INJECTED_RANK_3) || \
|
||||
((CHANNEL) == ADC_INJECTED_RANK_4)) |
||||
|
||||
#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ |
||||
((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)) |
||||
|
||||
/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
|
||||
* @{ |
||||
*/ |
||||
#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) |
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ |
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START)) |
||||
#endif |
||||
#if defined (STM32F101xE) |
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ |
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START)) |
||||
#endif |
||||
#if defined (STM32F101xG) |
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ |
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START)) |
||||
#endif |
||||
#if defined (STM32F103xE) || defined (STM32F103xG) |
||||
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ |
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_SOFTWARE_START)) |
||||
#endif |
||||
|
||||
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) |
||||
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ |
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) |
||||
#endif |
||||
#if defined (STM32F101xE) |
||||
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ |
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
|
||||
((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) |
||||
#endif |
||||
#if defined (STM32F101xG) |
||||
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ |
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) |
||||
#endif |
||||
#if defined (STM32F103xE) || defined (STM32F103xG) |
||||
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ |
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
|
||||
((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) |
||||
#endif |
||||
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ |
||||
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
|
||||
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
|
||||
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
|
||||
((MODE) == ADC_DUALMODE_INJECSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_INTERLFAST) || \
|
||||
((MODE) == ADC_DUALMODE_INTERLSLOW) || \
|
||||
((MODE) == ADC_DUALMODE_ALTERTRIG) ) |
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup ADCEx_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* IO operation functions *****************************************************/ |
||||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* ADC calibration */ |
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc); |
||||
|
||||
/* Blocking mode: Polling */ |
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); |
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); |
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
||||
|
||||
/* Non-blocking mode: Interruption */ |
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); |
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); |
||||
|
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
/* ADC multimode */ |
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); |
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ |
||||
|
||||
/* ADC retrieve conversion value intended to be used with polling or interruption */ |
||||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); |
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); |
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ |
||||
|
||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ |
||||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Peripheral Control functions ***********************************************/ |
||||
/** @addtogroup ADCEx_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); |
||||
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) |
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); |
||||
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F1xx_HAL_ADC_EX_H */ |
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,410 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_cortex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of CORTEX HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_CORTEX_H |
||||
#define __STM32F1xx_HAL_CORTEX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @{ |
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @brief MPU Region initialization structure
|
||||
* @{ |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
||||
}MPU_Region_InitTypeDef; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{ |
||||
*/ |
||||
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority |
||||
4 bits for subpriority */ |
||||
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority |
||||
3 bits for subpriority */ |
||||
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority |
||||
2 bits for subpriority */ |
||||
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority |
||||
1 bits for subpriority */ |
||||
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority |
||||
0 bits for subpriority */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
|
||||
* @{ |
||||
*/ |
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U |
||||
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if (__MPU_PRESENT == 1) |
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
|
||||
* @{ |
||||
*/ |
||||
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U |
||||
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk |
||||
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk |
||||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01) |
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{ |
||||
*/ |
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) |
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) |
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) |
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) |
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
|
||||
* @{ |
||||
*/ |
||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00) |
||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01) |
||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04) |
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05) |
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06) |
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07) |
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08) |
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) |
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) |
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) |
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) |
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) |
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) |
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) |
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) |
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) |
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) |
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) |
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) |
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) |
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) |
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) |
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) |
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) |
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) |
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) |
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) |
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) |
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) |
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) |
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01) |
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) |
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) |
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05) |
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00) |
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01) |
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02) |
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03) |
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04) |
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05) |
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06) |
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup CORTEX_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
/* Initialization and de-initialization functions *****************************/ |
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); |
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_SystemReset(void); |
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral Control functions ***********************************************/ |
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void); |
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); |
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); |
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
||||
void HAL_SYSTICK_IRQHandler(void); |
||||
void HAL_SYSTICK_Callback(void); |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
void HAL_MPU_Enable(uint32_t MPU_Control); |
||||
void HAL_MPU_Disable(void); |
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
||||
#endif /* __MPU_PRESENT */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private types -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{ |
||||
*/ |
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ |
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4)) |
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) |
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ |
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
||||
((STATE) == MPU_REGION_DISABLE)) |
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
||||
|
||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ |
||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||
((TYPE) == MPU_TEX_LEVEL2)) |
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO)) |
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7)) |
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ |
||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB)) |
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
/**
|
||||
* @}
|
||||
*/ |
||||
|
||||
/* Private functions ---------------------------------------------------------*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F1xx_HAL_CORTEX_H */ |
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,210 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_def.h |
||||
* @author MCD Application Team |
||||
* @brief This file contains HAL common defines, enumeration, macros and |
||||
* structures definitions. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_DEF |
||||
#define __STM32F1xx_HAL_DEF |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx.h" |
||||
#include "Legacy/stm32_hal_legacy.h" |
||||
#include <stddef.h> |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_OK = 0x00U, |
||||
HAL_ERROR = 0x01U, |
||||
HAL_BUSY = 0x02U, |
||||
HAL_TIMEOUT = 0x03U |
||||
} HAL_StatusTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_UNLOCKED = 0x00U, |
||||
HAL_LOCKED = 0x01U |
||||
} HAL_LockTypeDef; |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU |
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) |
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) |
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ |
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0U) |
||||
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ |
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__ specifies the Peripheral Handle. |
||||
* @note This macro can be used for the following purpose: |
||||
* - When the Handle is declared as local variable; before passing it as parameter |
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro |
||||
* to set to 0 the Handle's "State" field. |
||||
* Otherwise, "State" field may have any random value and the first time the function |
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed |
||||
* (i.e. HAL_PPP_MspInit() will not be executed). |
||||
* - When there is a need to reconfigure the low level hardware: instead of calling |
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). |
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function |
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) |
||||
|
||||
#if (USE_RTOS == 1U) |
||||
/* Reserved for future use */ |
||||
#error "USE_RTOS should be 0 in the current HAL release" |
||||
#else |
||||
#define __HAL_LOCK(__HANDLE__) \ |
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0U) |
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \ |
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0U) |
||||
#endif /* USE_RTOS */ |
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ |
||||
#ifndef __weak |
||||
#define __weak __attribute__((weak)) |
||||
#endif |
||||
#ifndef __packed |
||||
#define __packed __attribute__((packed)) |
||||
#endif |
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ |
||||
#ifndef __weak |
||||
#define __weak __attribute__((weak)) |
||||
#endif /* __weak */ |
||||
#ifndef __packed |
||||
#define __packed __attribute__((__packed__)) |
||||
#endif /* __packed */ |
||||
#endif /* __GNUC__ */ |
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ |
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ |
||||
#ifndef __ALIGN_BEGIN |
||||
#define __ALIGN_BEGIN |
||||
#endif |
||||
#ifndef __ALIGN_END |
||||
#define __ALIGN_END __attribute__ ((aligned (4))) |
||||
#endif |
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ |
||||
#ifndef __ALIGN_END |
||||
#define __ALIGN_END __attribute__ ((aligned (4))) |
||||
#endif /* __ALIGN_END */ |
||||
#ifndef __ALIGN_BEGIN |
||||
#define __ALIGN_BEGIN |
||||
#endif /* __ALIGN_BEGIN */ |
||||
#else |
||||
#ifndef __ALIGN_END |
||||
#define __ALIGN_END |
||||
#endif /* __ALIGN_END */ |
||||
#ifndef __ALIGN_BEGIN |
||||
#if defined (__CC_ARM) /* ARM Compiler V5*/ |
||||
#define __ALIGN_BEGIN __align(4) |
||||
#elif defined (__ICCARM__) /* IAR Compiler */ |
||||
#define __ALIGN_BEGIN |
||||
#endif /* __CC_ARM */ |
||||
#endif /* __ALIGN_BEGIN */ |
||||
#endif /* __GNUC__ */ |
||||
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition |
||||
*/ |
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) |
||||
/* ARM Compiler V4/V5 and V6
|
||||
-------------------------- |
||||
RAM functions are defined using the toolchain options. |
||||
Functions that are executed in RAM should reside in a separate source module. |
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const' |
||||
area of a module to a memory space in physical RAM. |
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target' |
||||
dialog. |
||||
*/ |
||||
#define __RAM_FUNC |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
/* ICCARM Compiler
|
||||
--------------- |
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc". |
||||
*/ |
||||
#define __RAM_FUNC __ramfunc |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
/* GNU Compiler
|
||||
------------ |
||||
RAM functions are defined using a specific toolchain attribute |
||||
"__attribute__((section(".RamFunc")))". |
||||
*/ |
||||
#define __RAM_FUNC __attribute__((section(".RamFunc"))) |
||||
|
||||
#endif |
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition |
||||
*/ |
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) |
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
------------------------------- |
||||
*/ |
||||
#define __NOINLINE __attribute__ ( (noinline) ) |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
/* ICCARM Compiler
|
||||
--------------- |
||||
*/ |
||||
#define __NOINLINE _Pragma("optimize = no_inline") |
||||
|
||||
#endif |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* ___STM32F1xx_HAL_DEF */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,457 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_dma.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of DMA HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_DMA_H |
||||
#define __STM32F1xx_HAL_DMA_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup DMA
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory. |
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */ |
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */ |
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */ |
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_mode |
||||
@note The circular buffer mode cannot be used if the memory-to-memory |
||||
data transfer is configured on the selected Channel */ |
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */ |
||||
} DMA_InitTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ |
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ |
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ |
||||
HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ |
||||
}HAL_DMA_StateTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ |
||||
}HAL_DMA_LevelCompleteTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL DMA Callback ID structure definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ |
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ |
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
||||
|
||||
}HAL_DMA_CallbackIDTypeDef; |
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition |
||||
*/ |
||||
typedef struct __DMA_HandleTypeDef |
||||
{ |
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
||||
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
||||
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
||||
|
||||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */ |
||||
|
||||
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ |
||||
|
||||
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
||||
|
||||
} DMA_HandleTypeDef;
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @{ |
||||
*/ |
||||
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ |
||||
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ |
||||
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ |
||||
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ |
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @{ |
||||
*/ |
||||
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ |
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||
* @{ |
||||
*/ |
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
||||
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||
* @{ |
||||
*/ |
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
||||
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @{ |
||||
*/ |
||||
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ |
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @{ |
||||
*/ |
||||
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ |
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_mode DMA mode
|
||||
* @{ |
||||
*/ |
||||
#define DMA_NORMAL 0x00000000U /*!< Normal mode */ |
||||
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @{ |
||||
*/ |
||||
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ |
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||
* @{ |
||||
*/ |
||||
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
||||
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
||||
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @{ |
||||
*/ |
||||
#define DMA_FLAG_GL1 0x00000001U |
||||
#define DMA_FLAG_TC1 0x00000002U |
||||
#define DMA_FLAG_HT1 0x00000004U |
||||
#define DMA_FLAG_TE1 0x00000008U |
||||
#define DMA_FLAG_GL2 0x00000010U |
||||
#define DMA_FLAG_TC2 0x00000020U |
||||
#define DMA_FLAG_HT2 0x00000040U |
||||
#define DMA_FLAG_TE2 0x00000080U |
||||
#define DMA_FLAG_GL3 0x00000100U |
||||
#define DMA_FLAG_TC3 0x00000200U |
||||
#define DMA_FLAG_HT3 0x00000400U |
||||
#define DMA_FLAG_TE3 0x00000800U |
||||
#define DMA_FLAG_GL4 0x00001000U |
||||
#define DMA_FLAG_TC4 0x00002000U |
||||
#define DMA_FLAG_HT4 0x00004000U |
||||
#define DMA_FLAG_TE4 0x00008000U |
||||
#define DMA_FLAG_GL5 0x00010000U |
||||
#define DMA_FLAG_TC5 0x00020000U |
||||
#define DMA_FLAG_HT5 0x00040000U |
||||
#define DMA_FLAG_TE5 0x00080000U |
||||
#define DMA_FLAG_GL6 0x00100000U |
||||
#define DMA_FLAG_TC6 0x00200000U |
||||
#define DMA_FLAG_HT6 0x00400000U |
||||
#define DMA_FLAG_TE6 0x00800000U |
||||
#define DMA_FLAG_GL7 0x01000000U |
||||
#define DMA_FLAG_TC7 0x02000000U |
||||
#define DMA_FLAG_HT7 0x04000000U |
||||
#define DMA_FLAG_TE7 0x08000000U |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/ |
||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Reset DMA handle state.
|
||||
* @param __HANDLE__: DMA handle |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
||||
|
||||
|
||||
/* Interrupt & Flag management */ |
||||
|
||||
/**
|
||||
* @brief Enables the specified DMA Channel interrupts. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) |
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel interrupts. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) |
||||
|
||||
/**
|
||||
* @brief Check whether the specified DMA Channel interrupt is enabled or not. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __INTERRUPT__: specifies the DMA interrupt source to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
||||
* @retval The state of DMA_IT (SET or RESET). |
||||
*/ |
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
||||
|
||||
/**
|
||||
* @brief Return the number of remaining data units in the current DMA Channel transfer. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The number of remaining data units in the current DMA Channel transfer. |
||||
*/ |
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Include DMA HAL Extension module */ |
||||
#include "stm32f1xx_hal_dma_ex.h" |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup DMA_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
/* Initialization and de-initialization functions *****************************/ |
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
||||
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
/* IO operation functions *****************************************************/ |
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); |
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group3
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral State and Error functions ***************************************/ |
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) |
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
||||
((STATE) == DMA_PINC_DISABLE)) |
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
||||
((STATE) == DMA_MINC_DISABLE)) |
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD)) |
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD )) |
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
||||
((MODE) == DMA_CIRCULAR)) |
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F1xx_HAL_DMA_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,277 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_dma_ex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of DMA HAL extension module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_DMA_EX_H |
||||
#define __STM32F1xx_HAL_DMA_EX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMAEx DMAEx
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
|
||||
* @{ |
||||
*/ |
||||
/* Interrupt & Flag management */ |
||||
#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ |
||||
defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) |
||||
/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer complete flag index. |
||||
*/ |
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5) |
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified half transfer complete flag index. |
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5) |
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer error flag index. |
||||
*/ |
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5) |
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer error flag index. |
||||
*/ |
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
|
||||
DMA_FLAG_GL5) |
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __FLAG__: Get the specified flag. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_FLAG_TCx: Transfer complete flag |
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag |
||||
* @arg DMA_FLAG_TEx: Transfer error flag |
||||
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET). |
||||
*/ |
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
|
||||
(DMA1->ISR & (__FLAG__))) |
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __FLAG__: specifies the flag to clear. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_FLAG_TCx: Transfer complete flag |
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag |
||||
* @arg DMA_FLAG_TEx: Transfer error flag |
||||
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
|
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
|
||||
(DMA1->IFCR = (__FLAG__))) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#else |
||||
/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer complete flag index. |
||||
*/ |
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7) |
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel half transfer complete flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified half transfer complete flag index. |
||||
*/ |
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7) |
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel transfer error flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer error flag index. |
||||
*/ |
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7) |
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer error flag index. |
||||
*/ |
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
|
||||
DMA_FLAG_GL7) |
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __FLAG__: Get the specified flag. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_FLAG_TCx: Transfer complete flag |
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag |
||||
* @arg DMA_FLAG_TEx: Transfer error flag |
||||
* @arg DMA_FLAG_GLx: Global interrupt flag |
||||
* Where x can be 1_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET). |
||||
*/ |
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
||||
|
||||
/**
|
||||
* @brief Clear the DMA Channel pending flags. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __FLAG__: specifies the flag to clear. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_FLAG_TCx: Transfer complete flag |
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag |
||||
* @arg DMA_FLAG_TEx: Transfer error flag |
||||
* @arg DMA_FLAG_GLx: Global interrupt flag |
||||
* Where x can be 1_7 to select the DMA Channel flag.
|
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */ |
||||
/* STM32F103xG || STM32F105xC || STM32F107xC */ |
||||
|
||||
#endif /* __STM32F1xx_HAL_DMA_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,320 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_exti.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of EXTI HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef STM32F1xx_HAL_EXTI_H |
||||
#define STM32F1xx_HAL_EXTI_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief HAL EXTI common Callback ID enumeration definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_EXTI_COMMON_CB_ID = 0x00U |
||||
} EXTI_CallbackIDTypeDef; |
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Line; /*!< Exti line number */ |
||||
void (* PendingCallback)(void); /*!< Exti pending callback */ |
||||
} EXTI_HandleTypeDef; |
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */ |
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */ |
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */ |
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It |
||||
can be a value of @ref EXTI_GPIOSel */ |
||||
} EXTI_ConfigTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{ |
||||
*/ |
||||
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ |
||||
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ |
||||
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ |
||||
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ |
||||
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ |
||||
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ |
||||
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ |
||||
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ |
||||
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ |
||||
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ |
||||
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ |
||||
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ |
||||
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ |
||||
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ |
||||
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ |
||||
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ |
||||
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ |
||||
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ |
||||
#if defined(EXTI_IMR_IM18) |
||||
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */ |
||||
#endif /* EXTI_IMR_IM18 */ |
||||
#if defined(EXTI_IMR_IM19) |
||||
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ |
||||
#endif /* EXTI_IMR_IM19 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{ |
||||
*/ |
||||
#define EXTI_MODE_NONE 0x00000000u |
||||
#define EXTI_MODE_INTERRUPT 0x00000001u |
||||
#define EXTI_MODE_EVENT 0x00000002u |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{ |
||||
*/ |
||||
#define EXTI_TRIGGER_NONE 0x00000000u |
||||
#define EXTI_TRIGGER_RISING 0x00000001u |
||||
#define EXTI_TRIGGER_FALLING 0x00000002u |
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief |
||||
* @{ |
||||
*/ |
||||
#define EXTI_GPIOA 0x00000000u |
||||
#define EXTI_GPIOB 0x00000001u |
||||
#define EXTI_GPIOC 0x00000002u |
||||
#define EXTI_GPIOD 0x00000003u |
||||
#if defined (GPIOE) |
||||
#define EXTI_GPIOE 0x00000004u |
||||
#endif /* GPIOE */ |
||||
#if defined (GPIOF) |
||||
#define EXTI_GPIOF 0x00000005u |
||||
#endif /* GPIOF */ |
||||
#if defined (GPIOG) |
||||
#define EXTI_GPIOG 0x00000006u |
||||
#endif /* GPIOG */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private constants --------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @brief EXTI Line property definition |
||||
*/ |
||||
#define EXTI_PROPERTY_SHIFT 24u |
||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) |
||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) |
||||
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) |
||||
|
||||
/**
|
||||
* @brief EXTI bit usage |
||||
*/ |
||||
#define EXTI_PIN_MASK 0x0000001Fu |
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode |
||||
*/ |
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) |
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities |
||||
*/ |
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) |
||||
|
||||
/**
|
||||
* @brief EXTI Line number |
||||
*/ |
||||
#if defined(EXTI_IMR_IM19) |
||||
#define EXTI_LINE_NB 20UL |
||||
#elif defined(EXTI_IMR_IM18) |
||||
#define EXTI_LINE_NB 19UL |
||||
#else /* EXTI_IMR_IM17 */ |
||||
#define EXTI_LINE_NB 18UL |
||||
#endif /* EXTI_IMR_IM19 */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{ |
||||
*/ |
||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ |
||||
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) |
||||
|
||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ |
||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) |
||||
|
||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) |
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) |
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) |
||||
|
||||
#if defined (GPIOG) |
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF) || \
|
||||
((__PORT__) == EXTI_GPIOG)) |
||||
#elif defined (GPIOF) |
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF)) |
||||
#elif defined (GPIOE) |
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE)) |
||||
#else |
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ |
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD)) |
||||
#endif /* GPIOG */ |
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions |
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions |
||||
* @{ |
||||
*/ |
||||
/* Configuration functions ****************************************************/ |
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); |
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); |
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); |
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); |
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions |
||||
* @{ |
||||
*/ |
||||
/* IO operation functions *****************************************************/ |
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); |
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); |
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); |
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* STM32F1xx_HAL_EXTI_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,328 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_flash.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of Flash HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_FLASH_H |
||||
#define __STM32F1xx_HAL_FLASH_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Private_Constants
|
||||
* @{ |
||||
*/ |
||||
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Private_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ |
||||
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
|
||||
|
||||
#if defined(FLASH_ACR_LATENCY) |
||||
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ |
||||
((__LATENCY__) == FLASH_LATENCY_1) || \
|
||||
((__LATENCY__) == FLASH_LATENCY_2)) |
||||
|
||||
#else |
||||
#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) |
||||
#endif /* FLASH_ACR_LATENCY */ |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition |
||||
*/ |
||||
typedef enum
|
||||
{ |
||||
FLASH_PROC_NONE = 0U,
|
||||
FLASH_PROC_PAGEERASE = 1U, |
||||
FLASH_PROC_MASSERASE = 2U, |
||||
FLASH_PROC_PROGRAMHALFWORD = 3U, |
||||
FLASH_PROC_PROGRAMWORD = 4U, |
||||
FLASH_PROC_PROGRAMDOUBLEWORD = 5U |
||||
} FLASH_ProcedureTypeDef; |
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ |
||||
|
||||
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ |
||||
|
||||
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ |
||||
|
||||
__IO uint64_t Data; /*!< Internal variable to save data to be programmed */ |
||||
|
||||
HAL_LockTypeDef Lock; /*!< FLASH locking object */ |
||||
|
||||
__IO uint32_t ErrorCode; /*!< FLASH error code
|
||||
This parameter can be a value of @ref FLASH_Error_Codes */ |
||||
} FLASH_ProcessTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error_Codes FLASH Error Codes
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ |
||||
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ |
||||
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ |
||||
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{ |
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!<Program a half-word (16-bit) at a specified address.*/ |
||||
#define FLASH_TYPEPROGRAM_WORD 0x02U /*!<Program a word (32-bit) at a specified address.*/ |
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined(FLASH_ACR_LATENCY) |
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{ |
||||
*/ |
||||
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ |
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#else |
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{ |
||||
*/ |
||||
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* FLASH_ACR_LATENCY */ |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
|
||||
* @brief macros to handle FLASH half cycle |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Enable the FLASH half cycle access. |
||||
* @note half cycle access can only be used with a low-frequency clock of less than |
||||
8 MHz that can be obtained with the use of HSI or HSE but not of PLL. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA) |
||||
|
||||
/**
|
||||
* @brief Disable the FLASH half cycle access. |
||||
* @note half cycle access can only be used with a low-frequency clock of less than |
||||
8 MHz that can be obtained with the use of HSI or HSE but not of PLL. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined(FLASH_ACR_LATENCY) |
||||
/** @defgroup FLASH_EM_Latency FLASH Latency
|
||||
* @brief macros to handle FLASH Latency |
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency. |
||||
* @param __LATENCY__ FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series |
||||
* @retval None |
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) |
||||
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency. |
||||
* @retval FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series |
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* FLASH_ACR_LATENCY */ |
||||
/** @defgroup FLASH_Prefetch FLASH Prefetch
|
||||
* @brief macros to handle FLASH Prefetch buffer |
||||
* @{ |
||||
*/
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer. |
||||
* @retval None |
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) |
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extended module */ |
||||
#include "stm32f1xx_hal_flash_ex.h" |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
/* IO operation functions *****************************************************/ |
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); |
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); |
||||
|
||||
/* FLASH IRQ handler function */ |
||||
void HAL_FLASH_IRQHandler(void); |
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); |
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral Control functions ***********************************************/ |
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); |
||||
void HAL_FLASH_OB_Launch(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral State and Error functions ***************************************/ |
||||
uint32_t HAL_FLASH_GetError(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private function -------------------------------------------------*/ |
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{ |
||||
*/ |
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); |
||||
#if defined(FLASH_BANK2_END) |
||||
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F1xx_HAL_FLASH_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,786 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_flash_ex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of Flash HAL Extended module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_FLASH_EX_H |
||||
#define __STM32F1xx_HAL_FLASH_EX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U |
||||
#define OBR_REG_INDEX 1U |
||||
#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE)) |
||||
|
||||
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) |
||||
|
||||
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) |
||||
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) |
||||
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) |
||||
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) |
||||
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) |
||||
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
/* Low Density */ |
||||
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) |
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \ |
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU)) |
||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
||||
|
||||
/* Medium Density */ |
||||
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) |
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ |
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
|
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU)))) |
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ |
||||
|
||||
/* High Density */ |
||||
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) |
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \ |
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU))) |
||||
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ |
||||
|
||||
/* XL Density */ |
||||
#if defined(FLASH_BANK2_END) |
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \ |
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU)) |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
/* Connectivity Line */ |
||||
#if (defined(STM32F105xC) || defined(STM32F107xC)) |
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \ |
||||
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
|
||||
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU))) |
||||
#endif /* STM32F105xC || STM32F107xC */ |
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ |
||||
((BANK) == FLASH_BANK_2) || \
|
||||
((BANK) == FLASH_BANK_BOTH)) |
||||
#else |
||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)) |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
/* Low Density */ |
||||
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) |
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ |
||||
((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU))) |
||||
|
||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
||||
|
||||
/* Medium Density */ |
||||
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) |
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ |
||||
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
|
||||
((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
|
||||
((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) |
||||
|
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ |
||||
|
||||
/* High Density */ |
||||
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) |
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \ |
||||
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
|
||||
((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) |
||||
|
||||
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ |
||||
|
||||
/* XL Density */ |
||||
#if defined(FLASH_BANK2_END) |
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \ |
||||
((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU))) |
||||
|
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
/* Connectivity Line */ |
||||
#if (defined(STM32F105xC) || defined(STM32F107xC)) |
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ |
||||
((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
|
||||
((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) |
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
|
||||
This parameter can be a value of @ref FLASHEx_Type_Erase */ |
||||
|
||||
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
|
||||
This parameter must be a value of @ref FLASHEx_Banks */
|
||||
|
||||
uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
|
||||
This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
|
||||
(x = 1 or 2 depending on devices)*/ |
||||
|
||||
uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
|
||||
This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ |
||||
|
||||
} FLASH_EraseInitTypeDef; |
||||
|
||||
/**
|
||||
* @brief FLASH Options bytes program structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASHEx_OB_Type */ |
||||
|
||||
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASHEx_OB_WRP_State */ |
||||
|
||||
uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
|
||||
This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ |
||||
|
||||
uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
|
||||
This parameter must be a value of @ref FLASHEx_Banks */
|
||||
|
||||
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
|
||||
This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
|
||||
IWDG / STOP / STDBY / BOOT1 |
||||
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
|
||||
@ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */ |
||||
#else |
||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
|
||||
IWDG / STOP / STDBY |
||||
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
|
||||
@ref FLASHEx_OB_nRST_STDBY */ |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
|
||||
This parameter can be a value of @ref FLASHEx_OB_Data_Address */ |
||||
|
||||
uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
||||
} FLASH_OBProgramInitTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Constants FLASH Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Page_Size Page Size
|
||||
* @{ |
||||
*/
|
||||
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) |
||||
#define FLASH_PAGE_SIZE 0x400U |
||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
||||
/* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
||||
|
||||
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) |
||||
#define FLASH_PAGE_SIZE 0x800U |
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
||||
/* STM32F101xG || STM32F103xG */
|
||||
/* STM32F105xC || STM32F107xC */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_Type_Erase Type Erase
|
||||
* @{ |
||||
*/
|
||||
#define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/ |
||||
#define FLASH_TYPEERASE_MASSERASE 0x02U /*!<Flash mass erase activation*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_Banks Banks
|
||||
* @{ |
||||
*/ |
||||
#if defined(FLASH_BANK2_END) |
||||
#define FLASH_BANK_1 1U /*!< Bank 1 */ |
||||
#define FLASH_BANK_2 2U /*!< Bank 2 */ |
||||
#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ |
||||
|
||||
#else |
||||
#define FLASH_BANK_1 1U /*!< Bank 1 */ |
||||
#endif |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Type Option Bytes Type
|
||||
* @{ |
||||
*/ |
||||
#define OPTIONBYTE_WRP 0x01U /*!<WRP option byte configuration*/ |
||||
#define OPTIONBYTE_RDP 0x02U /*!<RDP option byte configuration*/ |
||||
#define OPTIONBYTE_USER 0x04U /*!<USER option byte configuration*/ |
||||
#define OPTIONBYTE_DATA 0x08U /*!<DATA option byte configuration*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
|
||||
* @{ |
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE 0x00U /*!<Disable the write protection of the desired pages*/ |
||||
#define OB_WRPSTATE_ENABLE 0x01U /*!<Enable the write protection of the desired pagess*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
|
||||
* @{ |
||||
*/ |
||||
/* STM32 Low and Medium density devices */ |
||||
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \ |
||||
|| defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
|
||||
|| defined(STM32F103xB) |
||||
#define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */ |
||||
#define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */ |
||||
#define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */ |
||||
#define OB_WRP_PAGES12TO15 0x00000008U /*!< Write protection of page 12 to 15 */ |
||||
#define OB_WRP_PAGES16TO19 0x00000010U /*!< Write protection of page 16 to 19 */ |
||||
#define OB_WRP_PAGES20TO23 0x00000020U /*!< Write protection of page 20 to 23 */ |
||||
#define OB_WRP_PAGES24TO27 0x00000040U /*!< Write protection of page 24 to 27 */ |
||||
#define OB_WRP_PAGES28TO31 0x00000080U /*!< Write protection of page 28 to 31 */ |
||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
||||
/* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
||||
|
||||
/* STM32 Medium-density devices */ |
||||
#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) |
||||
#define OB_WRP_PAGES32TO35 0x00000100U /*!< Write protection of page 32 to 35 */ |
||||
#define OB_WRP_PAGES36TO39 0x00000200U /*!< Write protection of page 36 to 39 */ |
||||
#define OB_WRP_PAGES40TO43 0x00000400U /*!< Write protection of page 40 to 43 */ |
||||
#define OB_WRP_PAGES44TO47 0x00000800U /*!< Write protection of page 44 to 47 */ |
||||
#define OB_WRP_PAGES48TO51 0x00001000U /*!< Write protection of page 48 to 51 */ |
||||
#define OB_WRP_PAGES52TO55 0x00002000U /*!< Write protection of page 52 to 55 */ |
||||
#define OB_WRP_PAGES56TO59 0x00004000U /*!< Write protection of page 56 to 59 */ |
||||
#define OB_WRP_PAGES60TO63 0x00008000U /*!< Write protection of page 60 to 63 */ |
||||
#define OB_WRP_PAGES64TO67 0x00010000U /*!< Write protection of page 64 to 67 */ |
||||
#define OB_WRP_PAGES68TO71 0x00020000U /*!< Write protection of page 68 to 71 */ |
||||
#define OB_WRP_PAGES72TO75 0x00040000U /*!< Write protection of page 72 to 75 */ |
||||
#define OB_WRP_PAGES76TO79 0x00080000U /*!< Write protection of page 76 to 79 */ |
||||
#define OB_WRP_PAGES80TO83 0x00100000U /*!< Write protection of page 80 to 83 */ |
||||
#define OB_WRP_PAGES84TO87 0x00200000U /*!< Write protection of page 84 to 87 */ |
||||
#define OB_WRP_PAGES88TO91 0x00400000U /*!< Write protection of page 88 to 91 */ |
||||
#define OB_WRP_PAGES92TO95 0x00800000U /*!< Write protection of page 92 to 95 */ |
||||
#define OB_WRP_PAGES96TO99 0x01000000U /*!< Write protection of page 96 to 99 */ |
||||
#define OB_WRP_PAGES100TO103 0x02000000U /*!< Write protection of page 100 to 103 */ |
||||
#define OB_WRP_PAGES104TO107 0x04000000U /*!< Write protection of page 104 to 107 */ |
||||
#define OB_WRP_PAGES108TO111 0x08000000U /*!< Write protection of page 108 to 111 */ |
||||
#define OB_WRP_PAGES112TO115 0x10000000U /*!< Write protection of page 112 to 115 */ |
||||
#define OB_WRP_PAGES116TO119 0x20000000U /*!< Write protection of page 115 to 119 */ |
||||
#define OB_WRP_PAGES120TO123 0x40000000U /*!< Write protection of page 120 to 123 */ |
||||
#define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */ |
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
||||
|
||||
|
||||
/* STM32 High-density, XL-density and Connectivity line devices */ |
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \ |
||||
|| defined(STM32F101xG) || defined(STM32F103xG) \
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC) |
||||
#define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */ |
||||
#define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */ |
||||
#define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */ |
||||
#define OB_WRP_PAGES6TO7 0x00000008U /*!< Write protection of page 6 TO 7 */ |
||||
#define OB_WRP_PAGES8TO9 0x00000010U /*!< Write protection of page 8 TO 9 */ |
||||
#define OB_WRP_PAGES10TO11 0x00000020U /*!< Write protection of page 10 TO 11 */ |
||||
#define OB_WRP_PAGES12TO13 0x00000040U /*!< Write protection of page 12 TO 13 */ |
||||
#define OB_WRP_PAGES14TO15 0x00000080U /*!< Write protection of page 14 TO 15 */ |
||||
#define OB_WRP_PAGES16TO17 0x00000100U /*!< Write protection of page 16 TO 17 */ |
||||
#define OB_WRP_PAGES18TO19 0x00000200U /*!< Write protection of page 18 TO 19 */ |
||||
#define OB_WRP_PAGES20TO21 0x00000400U /*!< Write protection of page 20 TO 21 */ |
||||
#define OB_WRP_PAGES22TO23 0x00000800U /*!< Write protection of page 22 TO 23 */ |
||||
#define OB_WRP_PAGES24TO25 0x00001000U /*!< Write protection of page 24 TO 25 */ |
||||
#define OB_WRP_PAGES26TO27 0x00002000U /*!< Write protection of page 26 TO 27 */ |
||||
#define OB_WRP_PAGES28TO29 0x00004000U /*!< Write protection of page 28 TO 29 */ |
||||
#define OB_WRP_PAGES30TO31 0x00008000U /*!< Write protection of page 30 TO 31 */ |
||||
#define OB_WRP_PAGES32TO33 0x00010000U /*!< Write protection of page 32 TO 33 */ |
||||
#define OB_WRP_PAGES34TO35 0x00020000U /*!< Write protection of page 34 TO 35 */ |
||||
#define OB_WRP_PAGES36TO37 0x00040000U /*!< Write protection of page 36 TO 37 */ |
||||
#define OB_WRP_PAGES38TO39 0x00080000U /*!< Write protection of page 38 TO 39 */ |
||||
#define OB_WRP_PAGES40TO41 0x00100000U /*!< Write protection of page 40 TO 41 */ |
||||
#define OB_WRP_PAGES42TO43 0x00200000U /*!< Write protection of page 42 TO 43 */ |
||||
#define OB_WRP_PAGES44TO45 0x00400000U /*!< Write protection of page 44 TO 45 */ |
||||
#define OB_WRP_PAGES46TO47 0x00800000U /*!< Write protection of page 46 TO 47 */ |
||||
#define OB_WRP_PAGES48TO49 0x01000000U /*!< Write protection of page 48 TO 49 */ |
||||
#define OB_WRP_PAGES50TO51 0x02000000U /*!< Write protection of page 50 TO 51 */ |
||||
#define OB_WRP_PAGES52TO53 0x04000000U /*!< Write protection of page 52 TO 53 */ |
||||
#define OB_WRP_PAGES54TO55 0x08000000U /*!< Write protection of page 54 TO 55 */ |
||||
#define OB_WRP_PAGES56TO57 0x10000000U /*!< Write protection of page 56 TO 57 */ |
||||
#define OB_WRP_PAGES58TO59 0x20000000U /*!< Write protection of page 58 TO 59 */ |
||||
#define OB_WRP_PAGES60TO61 0x40000000U /*!< Write protection of page 60 TO 61 */ |
||||
#define OB_WRP_PAGES62TO127 0x80000000U /*!< Write protection of page 62 TO 127 */ |
||||
#define OB_WRP_PAGES62TO255 0x80000000U /*!< Write protection of page 62 TO 255 */ |
||||
#define OB_WRP_PAGES62TO511 0x80000000U /*!< Write protection of page 62 TO 511 */ |
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ |
||||
/* STM32F101xG || STM32F103xG */
|
||||
/* STM32F105xC || STM32F107xC */ |
||||
|
||||
#define OB_WRP_ALLPAGES 0xFFFFFFFFU /*!< Write protection of all Pages */ |
||||
|
||||
/* Low Density */ |
||||
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) |
||||
#define OB_WRP_PAGES0TO31MASK 0x000000FFU |
||||
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ |
||||
|
||||
/* Medium Density */ |
||||
#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB) |
||||
#define OB_WRP_PAGES0TO31MASK 0x000000FFU |
||||
#define OB_WRP_PAGES32TO63MASK 0x0000FF00U |
||||
#define OB_WRP_PAGES64TO95MASK 0x00FF0000U |
||||
#define OB_WRP_PAGES96TO127MASK 0xFF000000U |
||||
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ |
||||
|
||||
/* High Density */ |
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) |
||||
#define OB_WRP_PAGES0TO15MASK 0x000000FFU |
||||
#define OB_WRP_PAGES16TO31MASK 0x0000FF00U |
||||
#define OB_WRP_PAGES32TO47MASK 0x00FF0000U |
||||
#define OB_WRP_PAGES48TO255MASK 0xFF000000U |
||||
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */ |
||||
|
||||
/* XL Density */ |
||||
#if defined(STM32F101xG) || defined(STM32F103xG) |
||||
#define OB_WRP_PAGES0TO15MASK 0x000000FFU |
||||
#define OB_WRP_PAGES16TO31MASK 0x0000FF00U |
||||
#define OB_WRP_PAGES32TO47MASK 0x00FF0000U |
||||
#define OB_WRP_PAGES48TO511MASK 0xFF000000U |
||||
#endif /* STM32F101xG || STM32F103xG */ |
||||
|
||||
/* Connectivity line devices */ |
||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
||||
#define OB_WRP_PAGES0TO15MASK 0x000000FFU |
||||
#define OB_WRP_PAGES16TO31MASK 0x0000FF00U |
||||
#define OB_WRP_PAGES32TO47MASK 0x00FF0000U |
||||
#define OB_WRP_PAGES48TO127MASK 0xFF000000U |
||||
#endif /* STM32F105xC || STM32F107xC */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
|
||||
* @{ |
||||
*/ |
||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xA5) |
||||
#define OB_RDP_LEVEL_1 ((uint8_t)0x00) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
|
||||
* @{ |
||||
*/
|
||||
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ |
||||
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
|
||||
* @{ |
||||
*/
|
||||
#define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ |
||||
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
|
||||
* @{ |
||||
*/
|
||||
#define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ |
||||
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
|
||||
* @{ |
||||
*/ |
||||
#define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */ |
||||
#define OB_BOOT1_SET ((uint16_t)0x0008) /*!< BOOT1 Set */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
|
||||
* @{ |
||||
*/ |
||||
#define OB_DATA_ADDRESS_DATA0 0x1FFFF804U |
||||
#define OB_DATA_ADDRESS_DATA1 0x1FFFF806U |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASHEx_Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flag_definition Flag definition
|
||||
* @brief Flag definition |
||||
* @{ |
||||
*/ |
||||
#if defined(FLASH_BANK2_END) |
||||
#define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */ |
||||
#define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */ |
||||
#define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */ |
||||
#define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */ |
||||
|
||||
#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */ |
||||
#define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */ |
||||
#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */ |
||||
#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */ |
||||
|
||||
#define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U) /*!< FLASH Bank2 Busy flag */ |
||||
#define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U) /*!< FLASH Bank2 Programming error flag */ |
||||
#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag */ |
||||
#define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U) /*!< FLASH Bank2 End of Operation flag */ |
||||
|
||||
#else |
||||
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ |
||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */ |
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */ |
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ |
||||
|
||||
#endif |
||||
#define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Interrupt_definition Interrupt definition
|
||||
* @brief FLASH Interrupt definition |
||||
* @{ |
||||
*/ |
||||
#if defined(FLASH_BANK2_END) |
||||
#define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */ |
||||
#define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */ |
||||
|
||||
#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */ |
||||
#define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */ |
||||
|
||||
#define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */ |
||||
#define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2 */ |
||||
|
||||
#else |
||||
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ |
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */ |
||||
|
||||
#endif |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Interrupt Interrupt
|
||||
* @brief macros to handle FLASH interrupts |
||||
* @{ |
||||
*/
|
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt. |
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 |
||||
* @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 |
||||
* @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 |
||||
* @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \ |
||||
/* Enable Bank1 IT */ \
|
||||
SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
|
||||
/* Enable Bank2 IT */ \
|
||||
SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
|
||||
} while(0U) |
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt. |
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1 |
||||
* @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1 |
||||
* @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2 |
||||
* @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2 |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ |
||||
/* Disable Bank1 IT */ \
|
||||
CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
|
||||
/* Disable Bank2 IT */ \
|
||||
CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
|
||||
} while(0U) |
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__ specifies the FLASH flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 |
||||
* @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 |
||||
* @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 |
||||
* @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 |
||||
* @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 |
||||
* @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 |
||||
* @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 |
||||
* @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 |
||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
||||
* @retval The new state of __FLAG__ (SET or RESET). |
||||
*/ |
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ |
||||
(FLASH->OBR & FLASH_OBR_OPTERR) : \
|
||||
((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
|
||||
(FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
|
||||
(FLASH->SR2 & ((__FLAG__) >> 16U)))) |
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag. |
||||
* @param __FLAG__ specifies the FLASH flags to clear. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1 |
||||
* @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1 |
||||
* @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1 |
||||
* @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1 |
||||
* @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2 |
||||
* @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2 |
||||
* @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2 |
||||
* @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2 |
||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
||||
* @retval none |
||||
*/ |
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ |
||||
/* Clear FLASH_FLAG_OPTVERR flag */ \
|
||||
if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
|
||||
{ \
|
||||
CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
|
||||
} \
|
||||
else { \
|
||||
/* Clear Flag in Bank1 */ \
|
||||
if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
|
||||
{ \
|
||||
FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
|
||||
} \
|
||||
/* Clear Flag in Bank2 */ \
|
||||
if (((__FLAG__) >> 16U) != RESET) \
|
||||
{ \
|
||||
FLASH->SR2 = ((__FLAG__) >> 16U); \
|
||||
} \
|
||||
} \
|
||||
} while(0U) |
||||
#else |
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt. |
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt |
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt. |
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt |
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__ specifies the FLASH flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag |
||||
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag |
||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
||||
* @retval The new state of __FLAG__ (SET or RESET). |
||||
*/ |
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \ |
||||
(FLASH->OBR & FLASH_OBR_OPTERR) : \
|
||||
(FLASH->SR & (__FLAG__))) |
||||
/**
|
||||
* @brief Clear the specified FLASH flag. |
||||
* @param __FLAG__ specifies the FLASH flags to clear. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
|
||||
* @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match |
||||
* @retval none |
||||
*/ |
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \ |
||||
/* Clear FLASH_FLAG_OPTVERR flag */ \
|
||||
if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
|
||||
{ \
|
||||
CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
|
||||
} \
|
||||
else { \
|
||||
/* Clear Flag in Bank1 */ \
|
||||
FLASH->SR = (__FLAG__); \
|
||||
} \
|
||||
} while(0U) |
||||
|
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
/* IO operation functions *****************************************************/ |
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); |
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral Control functions ***********************************************/ |
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void); |
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); |
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); |
||||
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F1xx_HAL_FLASH_EX_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,308 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_gpio.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of GPIO HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef STM32F1xx_HAL_GPIO_H |
||||
#define STM32F1xx_HAL_GPIO_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */ |
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode_define */ |
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull_define */ |
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed_define */ |
||||
} GPIO_InitTypeDef; |
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
GPIO_PIN_RESET = 0u, |
||||
GPIO_PIN_SET |
||||
} GPIO_PinState; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_pins_define GPIO pins define
|
||||
* @{ |
||||
*/ |
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ |
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ |
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ |
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ |
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ |
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ |
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ |
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ |
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ |
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ |
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ |
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ |
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ |
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ |
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ |
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ |
||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ |
||||
|
||||
#define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_mode_define GPIO mode define
|
||||
* @brief GPIO Configuration Mode |
||||
* Elements values convention: 0xX0yz00YZ |
||||
* - X : GPIO mode or EXTI Mode |
||||
* - y : External IT or Event trigger detection |
||||
* - z : IO configuration on External IT or Event |
||||
* - Y : Output type (Push Pull or Open Drain) |
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog) |
||||
* @{ |
||||
*/ |
||||
#define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */ |
||||
#define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */ |
||||
#define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */ |
||||
#define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */ |
||||
#define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */ |
||||
#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ |
||||
|
||||
#define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */ |
||||
|
||||
#define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */ |
||||
#define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */ |
||||
#define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
||||
|
||||
#define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */ |
||||
#define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */ |
||||
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_speed_define GPIO speed define
|
||||
* @brief GPIO Output Maximum frequency |
||||
* @{ |
||||
*/ |
||||
#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ |
||||
#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ |
||||
#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_pull_define GPIO pull define
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation |
||||
* @{ |
||||
*/ |
||||
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ |
||||
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ |
||||
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not. |
||||
* @param __EXTI_LINE__: specifies the EXTI line flag to check. |
||||
* This parameter can be GPIO_PIN_x where x can be(0..15) |
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET). |
||||
*/ |
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) |
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags. |
||||
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear. |
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) |
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not. |
||||
* @param __EXTI_LINE__: specifies the EXTI line to check. |
||||
* This parameter can be GPIO_PIN_x where x can be(0..15) |
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET). |
||||
*/ |
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) |
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits. |
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear. |
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) |
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line. |
||||
* @param __EXTI_LINE__: specifies the EXTI line to check. |
||||
* This parameter can be GPIO_PIN_x where x can be(0..15) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Include GPIO HAL Extension module */ |
||||
#include "stm32f1xx_hal_gpio_ex.h" |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
/* Initialization and de-initialization functions *****************************/ |
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); |
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
/* IO operation functions *****************************************************/ |
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); |
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); |
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); |
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); |
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); |
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Private types -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{ |
||||
*/ |
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) |
||||
#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u)) |
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ |
||||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((MODE) == GPIO_MODE_AF_PP) ||\
|
||||
((MODE) == GPIO_MODE_AF_OD) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_IT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_ANALOG)) |
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ |
||||
((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) |
||||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ |
||||
((PULL) == GPIO_PULLDOWN)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private functions ---------------------------------------------------------*/ |
||||
/** @defgroup GPIO_Private_Functions GPIO Private Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* STM32F1xx_HAL_GPIO_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,894 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_gpio_ex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of GPIO HAL Extension module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef STM32F1xx_HAL_GPIO_EX_H |
||||
#define STM32F1xx_HAL_GPIO_EX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @{ |
||||
*/ |
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
|
||||
* @brief This section propose definition to use the Cortex EVENTOUT signal. |
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ |
||||
#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ |
||||
#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ |
||||
#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ |
||||
#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ |
||||
#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ |
||||
#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ |
||||
#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ |
||||
#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ |
||||
#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ |
||||
#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ |
||||
#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ |
||||
#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ |
||||
#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ |
||||
#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ |
||||
#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ |
||||
|
||||
#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ |
||||
((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
|
||||
((__PIN__) == AFIO_EVENTOUT_PIN_15)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ |
||||
#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ |
||||
#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ |
||||
#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ |
||||
#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ |
||||
|
||||
#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ |
||||
((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
|
||||
((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
|
||||
((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
|
||||
((__PORT__) == AFIO_EVENTOUT_PORT_E)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
|
||||
* @brief This section propose definition to remap the alternate function to some other port/pins. |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
||||
* @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
||||
* @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of I2C1 alternate function SCL and SDA. |
||||
* @note ENABLE: Remap (SCL/PB8, SDA/PB9) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of I2C1 alternate function SCL and SDA. |
||||
* @note DISABLE: No remap (SCL/PB6, SDA/PB7) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of USART1 alternate function TX and RX. |
||||
* @note ENABLE: Remap (TX/PB6, RX/PB7) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of USART1 alternate function TX and RX. |
||||
* @note DISABLE: No remap (TX/PA9, RX/PA10) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
||||
* @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
||||
* @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
||||
* @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
||||
* @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
||||
* @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
||||
* @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
||||
* @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
||||
* @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
||||
* @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
||||
* @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
||||
* @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
||||
* @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
||||
* @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) |
||||
* @note TIM3_ETR on PE0 is not re-mapped. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
||||
* @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) |
||||
* @note TIM3_ETR on PE0 is not re-mapped. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM3 alternate function channels 1 to 4 |
||||
* @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) |
||||
* @note TIM3_ETR on PE0 is not re-mapped. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM4 alternate function channels 1 to 4. |
||||
* @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) |
||||
* @note TIM4_ETR on PE0 is not re-mapped. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM4 alternate function channels 1 to 4. |
||||
* @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) |
||||
* @note TIM4_ETR on PE0 is not re-mapped. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP) |
||||
|
||||
#if defined(AFIO_MAPR_CAN_REMAP_REMAP1) |
||||
|
||||
/**
|
||||
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
||||
* @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
||||
* @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
||||
* @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP) |
||||
|
||||
#endif |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used |
||||
* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
||||
* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
||||
* on 100-pin and 144-pin packages, no need for remapping). |
||||
* @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used |
||||
* (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
||||
* OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
||||
* on 100-pin and 144-pin packages, no need for remapping). |
||||
* @note DISABLE: No remapping of PD0 and PD1 |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP) |
||||
|
||||
#if defined(AFIO_MAPR_TIM5CH4_IREMAP) |
||||
/**
|
||||
* @brief Enable the remapping of TIM5CH4. |
||||
* @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. |
||||
* @note This function is available only in high density value line devices. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM5CH4. |
||||
* @note DISABLE: TIM5_CH4 is connected to PA3 |
||||
* @note This function is available only in high density value line devices. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR_ETH_REMAP) |
||||
/**
|
||||
* @brief Enable the remapping of Ethernet MAC connections with the PHY. |
||||
* @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of Ethernet MAC connections with the PHY. |
||||
* @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR_CAN2_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
||||
* @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
||||
* @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR_MII_RMII_SEL) |
||||
/**
|
||||
* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
||||
* @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL) |
||||
|
||||
/**
|
||||
* @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
||||
* @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL) |
||||
#endif |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
||||
* @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
||||
* @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
||||
* @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
||||
* @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
||||
|
||||
#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
||||
* @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
||||
* @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
||||
#endif |
||||
|
||||
#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
||||
* @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
||||
* @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) |
||||
#endif |
||||
|
||||
/**
|
||||
* @brief Enable the Serial wire JTAG configuration |
||||
* @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET) |
||||
|
||||
/**
|
||||
* @brief Enable the Serial wire JTAG configuration |
||||
* @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST) |
||||
|
||||
/**
|
||||
* @brief Enable the Serial wire JTAG configuration |
||||
* @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled |
||||
* @retval None |
||||
*/ |
||||
|
||||
#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE) |
||||
|
||||
/**
|
||||
* @brief Disable the Serial wire JTAG configuration |
||||
* @note DISABLE: JTAG-DP Disabled and SW-DP Disabled |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE) |
||||
|
||||
#if defined(AFIO_MAPR_SPI3_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
||||
* @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
||||
* @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR_TIM2ITR1_IREMAP) |
||||
|
||||
/**
|
||||
* @brief Control of TIM2_ITR1 internal mapping. |
||||
* @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP) |
||||
|
||||
/**
|
||||
* @brief Control of TIM2_ITR1 internal mapping. |
||||
* @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR_PTP_PPS_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
||||
* @note ENABLE: PTP_PPS is output on PB5 pin. |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
||||
* @note DISABLE: PTP_PPS not output on PB5 pin. |
||||
* @note This bit is available only in connectivity line devices and is reserved otherwise. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM9_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. |
||||
* @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. |
||||
* @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM10_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM10_CH1. |
||||
* @note ENABLE: Remap (TIM10_CH1 on PF6). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM10_CH1. |
||||
* @note DISABLE: No remap (TIM10_CH1 on PB8). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM11_REMAP) |
||||
/**
|
||||
* @brief Enable the remapping of TIM11_CH1. |
||||
* @note ENABLE: Remap (TIM11_CH1 on PF7). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM11_CH1. |
||||
* @note DISABLE: No remap (TIM11_CH1 on PB9). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM13_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM13_CH1. |
||||
* @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM13_CH1. |
||||
* @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM14_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM14_CH1. |
||||
* @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM14_CH1. |
||||
* @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_FSMC_NADV_REMAP) |
||||
|
||||
/**
|
||||
* @brief Controls the use of the optional FSMC_NADV signal. |
||||
* @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
||||
|
||||
/**
|
||||
* @brief Controls the use of the optional FSMC_NADV signal. |
||||
* @note CONNECTED: The NADV signal is connected to the output (default). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM15_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. |
||||
* @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. |
||||
* @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM16_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM16_CH1. |
||||
* @note ENABLE: Remap (TIM16_CH1 on PA6). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM16_CH1. |
||||
* @note DISABLE: No remap (TIM16_CH1 on PB8). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM17_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM17_CH1. |
||||
* @note ENABLE: Remap (TIM17_CH1 on PA7). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM17_CH1. |
||||
* @note DISABLE: No remap (TIM17_CH1 on PB9). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_CEC_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of CEC. |
||||
* @note ENABLE: Remap (CEC on PB10). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of CEC. |
||||
* @note DISABLE: No remap (CEC on PB8). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM1_DMA_REMAP) |
||||
|
||||
/**
|
||||
* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
||||
* @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
||||
|
||||
/**
|
||||
* @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
||||
* @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
||||
|
||||
/**
|
||||
* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
||||
* @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
||||
|
||||
/**
|
||||
* @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
||||
* @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_TIM12_REMAP) |
||||
|
||||
/**
|
||||
* @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. |
||||
* @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). |
||||
* @note This bit is available only in high density value line devices. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
||||
|
||||
/**
|
||||
* @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. |
||||
* @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). |
||||
* @note This bit is available only in high density value line devices. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
||||
#endif |
||||
|
||||
#if defined(AFIO_MAPR2_MISC_REMAP) |
||||
|
||||
/**
|
||||
* @brief Miscellaneous features remapping. |
||||
* This bit is set and cleared by software. It controls miscellaneous features. |
||||
* The DMA2 channel 5 interrupt position in the vector table. |
||||
* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
||||
* @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is |
||||
* selected as DAC Trigger 3, TIM15 triggers TIM1/3. |
||||
* @note This bit is available only in high density value line devices. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
||||
|
||||
/**
|
||||
* @brief Miscellaneous features remapping. |
||||
* This bit is set and cleared by software. It controls miscellaneous features. |
||||
* The DMA2 channel 5 interrupt position in the vector table. |
||||
* The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
||||
* @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO |
||||
* event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. |
||||
* @note This bit is available only in high density value line devices. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
|
||||
* @{ |
||||
*/ |
||||
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) |
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
||||
((__GPIOx__) == (GPIOC))? 2uL :3uL) |
||||
#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) |
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
||||
((__GPIOx__) == (GPIOC))? 2uL :\
|
||||
((__GPIOx__) == (GPIOD))? 3uL :4uL) |
||||
#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
||||
((__GPIOx__) == (GPIOC))? 2uL :\
|
||||
((__GPIOx__) == (GPIOD))? 3uL :\
|
||||
((__GPIOx__) == (GPIOE))? 4uL :\
|
||||
((__GPIOx__) == (GPIOF))? 5uL :6uL) |
||||
#endif |
||||
|
||||
#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ |
||||
tmpreg |= AFIO_MAPR_SWJ_CFG; \
|
||||
tmpreg |= REMAP_PIN; \
|
||||
AFIO->MAPR = tmpreg; \
|
||||
}while(0u) |
||||
|
||||
#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ |
||||
tmpreg |= AFIO_MAPR_SWJ_CFG; \
|
||||
tmpreg &= ~REMAP_PIN; \
|
||||
AFIO->MAPR = tmpreg; \
|
||||
}while(0u) |
||||
|
||||
#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \ |
||||
tmpreg &= ~REMAP_PIN_MASK; \
|
||||
tmpreg |= AFIO_MAPR_SWJ_CFG; \
|
||||
tmpreg |= REMAP_PIN; \
|
||||
AFIO->MAPR = tmpreg; \
|
||||
}while(0u) |
||||
|
||||
#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \ |
||||
tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
|
||||
tmpreg |= DBGAFR_SWJCFG; \
|
||||
AFIO->MAPR = tmpreg; \
|
||||
}while(0u) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup GPIOEx_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup GPIOEx_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); |
||||
void HAL_GPIOEx_EnableEventout(void); |
||||
void HAL_GPIOEx_DisableEventout(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* STM32F1xx_HAL_GPIO_EX_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,223 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_iwdg.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of IWDG HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef STM32F1xx_HAL_IWDG_H |
||||
#define STM32F1xx_HAL_IWDG_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup IWDG IWDG
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief IWDG Init structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
||||
This parameter can be a value of @ref IWDG_Prescaler */ |
||||
|
||||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ |
||||
|
||||
} IWDG_InitTypeDef; |
||||
|
||||
/**
|
||||
* @brief IWDG Handle Structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
IWDG_TypeDef *Instance; /*!< Register base address */ |
||||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */ |
||||
} IWDG_HandleTypeDef; |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||
* @{ |
||||
*/ |
||||
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */ |
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ |
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ |
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ |
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ |
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ |
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macros -----------------------------------------------------------*/ |
||||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Enable the IWDG peripheral. |
||||
* @param __HANDLE__ IWDG handle |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) |
||||
|
||||
/**
|
||||
* @brief Reload IWDG counter with value defined in the reload register |
||||
* (write access to IWDG_PR and IWDG_RLR registers disabled). |
||||
* @param __HANDLE__ IWDG handle |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
||||
* @{ |
||||
*/ |
||||
/* Initialization/Start functions ********************************************/ |
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||
* @{ |
||||
*/ |
||||
/* I/O operation functions ****************************************************/ |
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief IWDG Key Register BitMask |
||||
*/ |
||||
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */ |
||||
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */ |
||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */ |
||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR and IWDG_RLR registers. |
||||
* @param __HANDLE__ IWDG handle |
||||
* @retval None |
||||
*/ |
||||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) |
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR and IWDG_RLR registers. |
||||
* @param __HANDLE__ IWDG handle |
||||
* @retval None |
||||
*/ |
||||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) |
||||
|
||||
/**
|
||||
* @brief Check IWDG prescaler value. |
||||
* @param __PRESCALER__ IWDG prescaler value |
||||
* @retval None |
||||
*/ |
||||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ |
||||
((__PRESCALER__) == IWDG_PRESCALER_8) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_16) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_32) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_64) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_256)) |
||||
|
||||
/**
|
||||
* @brief Check IWDG reload value. |
||||
* @param __RELOAD__ IWDG reload value |
||||
* @retval None |
||||
*/ |
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) |
||||
|
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* STM32F1xx_HAL_IWDG_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,388 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_pwr.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of PWR HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_PWR_H |
||||
#define __STM32F1xx_HAL_PWR_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup PWR
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
||||
This parameter can be a value of @ref PWR_PVD_detection_level */ |
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode */ |
||||
}PWR_PVDTypeDef; |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Internal constants --------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup PWR_Private_Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
|
||||
* @{ |
||||
*/ |
||||
#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 |
||||
#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 |
||||
#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 |
||||
#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 |
||||
#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 |
||||
#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 |
||||
#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 |
||||
#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_PVD_Mode PWR PVD Mode
|
||||
* @{ |
||||
*/ |
||||
#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ |
||||
#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ |
||||
#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ |
||||
#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
||||
#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ |
||||
#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ |
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
|
||||
* @{ |
||||
*/ |
||||
#define PWR_MAINREGULATOR_ON 0x00000000U |
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{ |
||||
*/ |
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) |
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{ |
||||
*/ |
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) |
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Flag PWR Flag
|
||||
* @{ |
||||
*/ |
||||
#define PWR_FLAG_WU PWR_CSR_WUF |
||||
#define PWR_FLAG_SB PWR_CSR_SBF |
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup PWR_Exported_Macros PWR Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
||||
* was received from the WKUP pin or from the RTC alarm |
||||
* An additional wakeup event is detected if the WKUP pin is enabled |
||||
* (by setting the EWUP bit) when the WKUP pin level is already high. |
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
||||
* resumed from StandBy mode. |
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode |
||||
* For this reason, this bit is equal to 0 after Standby or reset |
||||
* until the PVDE bit is set. |
||||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
||||
*/ |
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
||||
|
||||
/** @brief Clear the PWR's pending flags.
|
||||
* @param __FLAG__: specifies the flag to clear. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_FLAG_WU: Wake Up flag |
||||
* @arg PWR_FLAG_SB: StandBy flag |
||||
*/ |
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) |
||||
|
||||
/**
|
||||
* @brief Enable interrupt on PVD Exti Line 16. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief Disable interrupt on PVD Exti Line 16.
|
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief Enable event on PVD Exti Line 16. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief Disable event on PVD Exti Line 16. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set falling edge trigger.
|
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising edge trigger. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger. |
||||
* This parameter can be: |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising & falling edge trigger. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
||||
* This parameter can be: |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); |
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
||||
* @retval EXTI PVD Line Status. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
||||
|
||||
/**
|
||||
* @brief Clear the PVD EXTI flag. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/** @defgroup PWR_Private_Macros PWR Private Macros
|
||||
* @{ |
||||
*/ |
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
||||
|
||||
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_NORMAL))
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) |
||||
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
||||
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
||||
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Initialization and de-initialization functions *******************************/ |
||||
void HAL_PWR_DeInit(void); |
||||
void HAL_PWR_EnableBkUpAccess(void); |
||||
void HAL_PWR_DisableBkUpAccess(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Peripheral Control functions ************************************************/ |
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
||||
/* #define HAL_PWR_ConfigPVD 12*/ |
||||
void HAL_PWR_EnablePVD(void); |
||||
void HAL_PWR_DisablePVD(void); |
||||
|
||||
/* WakeUp pins configuration functions ****************************************/ |
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
||||
|
||||
/* Low Power modes configuration functions ************************************/ |
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
||||
void HAL_PWR_EnterSTANDBYMode(void); |
||||
|
||||
void HAL_PWR_EnableSleepOnExit(void); |
||||
void HAL_PWR_DisableSleepOnExit(void); |
||||
void HAL_PWR_EnableSEVOnPend(void); |
||||
void HAL_PWR_DisableSEVOnPend(void); |
||||
|
||||
|
||||
|
||||
void HAL_PWR_PVD_IRQHandler(void); |
||||
void HAL_PWR_PVDCallback(void); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
|
||||
#endif /* __STM32F1xx_HAL_PWR_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,731 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_spi.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of SPI HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef STM32F1xx_HAL_SPI_H |
||||
#define STM32F1xx_HAL_SPI_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup SPI
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/** @defgroup SPI_Exported_Types SPI Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief SPI Configuration Structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_Mode */ |
||||
|
||||
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
|
||||
This parameter can be a value of @ref SPI_Direction */ |
||||
|
||||
uint32_t DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_Data_Size */ |
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */ |
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */ |
||||
|
||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit. |
||||
This parameter can be a value of @ref SPI_Slave_Select_management */ |
||||
|
||||
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock. |
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler |
||||
@note The communication clock is derived from the master |
||||
clock. The slave clock does not need to be set. */ |
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
||||
|
||||
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
|
||||
This parameter can be a value of @ref SPI_TI_mode */ |
||||
|
||||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
||||
This parameter can be a value of @ref SPI_CRC_Calculation */ |
||||
|
||||
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
||||
This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ |
||||
} SPI_InitTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL SPI State structure definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ |
||||
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
||||
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
||||
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ |
||||
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ |
||||
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ |
||||
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ |
||||
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ |
||||
} HAL_SPI_StateTypeDef; |
||||
|
||||
/**
|
||||
* @brief SPI handle Structure definition |
||||
*/ |
||||
typedef struct __SPI_HandleTypeDef |
||||
{ |
||||
SPI_TypeDef *Instance; /*!< SPI registers base address */ |
||||
|
||||
SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
||||
|
||||
uint16_t TxXferSize; /*!< SPI Tx Transfer size */ |
||||
|
||||
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
||||
|
||||
uint16_t RxXferSize; /*!< SPI Rx Transfer size */ |
||||
|
||||
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
||||
|
||||
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ |
||||
|
||||
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ |
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ |
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ |
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */ |
||||
|
||||
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
||||
|
||||
__IO uint32_t ErrorCode; /*!< SPI Error code */ |
||||
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
||||
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ |
||||
void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ |
||||
void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ |
||||
void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ |
||||
void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ |
||||
void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ |
||||
void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ |
||||
void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ |
||||
void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ |
||||
void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ |
||||
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
||||
} SPI_HandleTypeDef; |
||||
|
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
||||
/**
|
||||
* @brief HAL SPI Callback ID enumeration definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ |
||||
HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ |
||||
HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ |
||||
HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ |
||||
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ |
||||
HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ |
||||
HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ |
||||
HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ |
||||
HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ |
||||
HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ |
||||
|
||||
} HAL_SPI_CallbackIDTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL SPI Callback pointer definition |
||||
*/ |
||||
typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ |
||||
|
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup SPI_Exported_Constants SPI Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Error_Code SPI Error Code
|
||||
* @{ |
||||
*/ |
||||
#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ |
||||
#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ |
||||
#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ |
||||
#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ |
||||
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ |
||||
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */ |
||||
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ |
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
||||
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ |
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Mode SPI Mode
|
||||
* @{ |
||||
*/ |
||||
#define SPI_MODE_SLAVE (0x00000000U) |
||||
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Direction SPI Direction Mode
|
||||
* @{ |
||||
*/ |
||||
#define SPI_DIRECTION_2LINES (0x00000000U) |
||||
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
||||
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Data_Size SPI Data Size
|
||||
* @{ |
||||
*/ |
||||
#define SPI_DATASIZE_8BIT (0x00000000U) |
||||
#define SPI_DATASIZE_16BIT SPI_CR1_DFF |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
|
||||
* @{ |
||||
*/ |
||||
#define SPI_POLARITY_LOW (0x00000000U) |
||||
#define SPI_POLARITY_HIGH SPI_CR1_CPOL |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Clock_Phase SPI Clock Phase
|
||||
* @{ |
||||
*/ |
||||
#define SPI_PHASE_1EDGE (0x00000000U) |
||||
#define SPI_PHASE_2EDGE SPI_CR1_CPHA |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
|
||||
* @{ |
||||
*/ |
||||
#define SPI_NSS_SOFT SPI_CR1_SSM |
||||
#define SPI_NSS_HARD_INPUT (0x00000000U) |
||||
#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
|
||||
* @{ |
||||
*/ |
||||
#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) |
||||
#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) |
||||
#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) |
||||
#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) |
||||
#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) |
||||
#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) |
||||
#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) |
||||
#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
|
||||
* @{ |
||||
*/ |
||||
#define SPI_FIRSTBIT_MSB (0x00000000U) |
||||
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_TI_mode SPI TI Mode
|
||||
* @{ |
||||
*/ |
||||
#define SPI_TIMODE_DISABLE (0x00000000U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
|
||||
* @{ |
||||
*/ |
||||
#define SPI_CRCCALCULATION_DISABLE (0x00000000U) |
||||
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
|
||||
* @{ |
||||
*/ |
||||
#define SPI_IT_TXE SPI_CR2_TXEIE |
||||
#define SPI_IT_RXNE SPI_CR2_RXNEIE |
||||
#define SPI_IT_ERR SPI_CR2_ERRIE |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Flags_definition SPI Flags Definition
|
||||
* @{ |
||||
*/ |
||||
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ |
||||
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ |
||||
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ |
||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ |
||||
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ |
||||
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ |
||||
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY\ |
||||
| SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macros -----------------------------------------------------------*/ |
||||
/** @defgroup SPI_Exported_Macros SPI Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Reset SPI handle state.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
||||
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0) |
||||
#else |
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
||||
|
||||
/** @brief Enable the specified SPI interrupts.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @param __INTERRUPT__ specifies the interrupt source to enable. |
||||
* This parameter can be one of the following values: |
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||||
* @arg SPI_IT_ERR: Error interrupt enable |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
||||
|
||||
/** @brief Disable the specified SPI interrupts.
|
||||
* @param __HANDLE__ specifies the SPI handle. |
||||
* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @param __INTERRUPT__ specifies the interrupt source to disable. |
||||
* This parameter can be one of the following values: |
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||||
* @arg SPI_IT_ERR: Error interrupt enable |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
||||
|
||||
/** @brief Check whether the specified SPI interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||||
* @arg SPI_IT_ERR: Error interrupt enable |
||||
* @retval The new state of __IT__ (TRUE or FALSE). |
||||
*/ |
||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ |
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @param __FLAG__ specifies the flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag |
||||
* @arg SPI_FLAG_CRCERR: CRC error flag |
||||
* @arg SPI_FLAG_MODF: Mode fault flag |
||||
* @arg SPI_FLAG_OVR: Overrun flag |
||||
* @arg SPI_FLAG_BSY: Busy flag |
||||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
||||
*/ |
||||
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
||||
|
||||
/** @brief Clear the SPI CRCERR pending flag.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) |
||||
|
||||
/** @brief Clear the SPI MODF pending flag.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
||||
do{ \
|
||||
__IO uint32_t tmpreg_modf = 0x00U; \
|
||||
tmpreg_modf = (__HANDLE__)->Instance->SR; \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
|
||||
UNUSED(tmpreg_modf); \
|
||||
} while(0U) |
||||
|
||||
/** @brief Clear the SPI OVR pending flag.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
||||
do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
} while(0U) |
||||
|
||||
/** @brief Enable the SPI peripheral.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
||||
|
||||
/** @brief Disable the SPI peripheral.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/** @defgroup SPI_Private_Constants SPI Private Constants
|
||||
* @{ |
||||
*/ |
||||
#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */ |
||||
#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Set the SPI transmit-only mode.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
||||
|
||||
/** @brief Set the SPI receive-only mode.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
||||
|
||||
/** @brief Reset the CRC calculation of the SPI.
|
||||
* @param __HANDLE__ specifies the SPI Handle. |
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) |
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __SR__ copy of SPI SR register. |
||||
* @param __FLAG__ specifies the flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag |
||||
* @arg SPI_FLAG_CRCERR: CRC error flag |
||||
* @arg SPI_FLAG_MODF: Mode fault flag |
||||
* @arg SPI_FLAG_OVR: Overrun flag |
||||
* @arg SPI_FLAG_BSY: Busy flag |
||||
* @retval SET or RESET. |
||||
*/ |
||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ |
||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) |
||||
|
||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
||||
* @param __CR2__ copy of SPI CR2 register. |
||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||||
* @arg SPI_IT_ERR: Error interrupt enable |
||||
* @retval SET or RESET. |
||||
*/ |
||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ |
||||
(__INTERRUPT__)) ? SET : RESET) |
||||
|
||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Mode. |
||||
* This parameter can be a value of @ref SPI_Mode |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ |
||||
((__MODE__) == SPI_MODE_MASTER)) |
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
||||
* @param __MODE__ specifies the SPI Direction Mode. |
||||
* This parameter can be a value of @ref SPI_Direction |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
||||
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
|
||||
((__MODE__) == SPI_DIRECTION_1LINE)) |
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
|
||||
* @param __MODE__ specifies the SPI Direction Mode. |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) |
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
|
||||
* @param __MODE__ specifies the SPI Direction Mode. |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
||||
((__MODE__) == SPI_DIRECTION_1LINE)) |
||||
|
||||
/** @brief Checks if SPI Data Size parameter is in allowed range.
|
||||
* @param __DATASIZE__ specifies the SPI Data Size. |
||||
* This parameter can be a value of @ref SPI_Data_Size |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ |
||||
((__DATASIZE__) == SPI_DATASIZE_8BIT)) |
||||
|
||||
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
|
||||
* @param __CPOL__ specifies the SPI serial clock steady state. |
||||
* This parameter can be a value of @ref SPI_Clock_Polarity |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ |
||||
((__CPOL__) == SPI_POLARITY_HIGH)) |
||||
|
||||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
||||
* @param __CPHA__ specifies the SPI Clock Phase. |
||||
* This parameter can be a value of @ref SPI_Clock_Phase |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ |
||||
((__CPHA__) == SPI_PHASE_2EDGE)) |
||||
|
||||
/** @brief Checks if SPI Slave Select parameter is in allowed range.
|
||||
* @param __NSS__ specifies the SPI Slave Select management parameter. |
||||
* This parameter can be a value of @ref SPI_Slave_Select_management |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ |
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT)) |
||||
|
||||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
||||
* @param __PRESCALER__ specifies the SPI Baudrate prescaler. |
||||
* This parameter can be a value of @ref SPI_BaudRate_Prescaler |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ |
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) |
||||
|
||||
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
|
||||
* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). |
||||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ |
||||
((__BIT__) == SPI_FIRSTBIT_LSB)) |
||||
|
||||
/** @brief Checks if SPI TI mode parameter is disabled.
|
||||
* @param __MODE__ SPI_TIMODE_DISABLE. Device not support Ti Mode. |
||||
* This parameter can be a value of @ref SPI_TI_mode |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) |
||||
|
||||
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
|
||||
* @param __CALCULATION__ specifies the SPI CRC calculation enable state. |
||||
* This parameter can be a value of @ref SPI_CRC_Calculation |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ |
||||
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) |
||||
|
||||
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
|
||||
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. |
||||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535 |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ |
||||
((__POLYNOMIAL__) <= 0xFFFFU) && \
|
||||
(((__POLYNOMIAL__)&0x1U) != 0U)) |
||||
|
||||
/** @brief Checks if DMA handle is valid.
|
||||
* @param __HANDLE__ specifies a DMA Handle. |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private functions ---------------------------------------------------------*/ |
||||
/** @defgroup SPI_Private_Functions SPI Private Functions
|
||||
* @{ |
||||
*/ |
||||
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup SPI_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
/* Initialization/de-initialization functions ********************************/ |
||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
||||
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/ |
||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
||||
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); |
||||
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); |
||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
/* I/O operation functions ***************************************************/ |
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, |
||||
uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
||||
uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
||||
uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
||||
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
||||
/* Transfer Abort functions */ |
||||
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); |
||||
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); |
||||
|
||||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group3
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral State and Error functions ***************************************/ |
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
||||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* STM32F1xx_HAL_SPI_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,262 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_tim_ex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of TIM HAL Extended module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef STM32F1xx_HAL_TIM_EX_H |
||||
#define STM32F1xx_HAL_TIM_EX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup TIMEx
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief TIM Hall sensor Configuration Structure definition |
||||
*/ |
||||
|
||||
typedef struct |
||||
{ |
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
||||
|
||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
||||
} TIM_HallSensor_InitTypeDef; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* End of exported types -----------------------------------------------------*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* End of exported constants -------------------------------------------------*/ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* End of exported macro -----------------------------------------------------*/ |
||||
|
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* End of private macro ------------------------------------------------------*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
||||
* @brief Timer Hall Sensor functions |
||||
* @{ |
||||
*/ |
||||
/* Timer Hall Sensor functions **********************************************/ |
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); |
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); |
||||
|
||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); |
||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); |
||||
|
||||
/* Blocking mode: Polling */ |
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); |
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); |
||||
/* Non-Blocking mode: Interrupt */ |
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); |
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); |
||||
/* Non-Blocking mode: DMA */ |
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
||||
* @brief Timer Complementary Output Compare functions |
||||
* @{ |
||||
*/ |
||||
/* Timer Complementary Output Compare functions *****************************/ |
||||
/* Blocking mode: Polling */ |
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
||||
|
||||
/* Non-Blocking mode: Interrupt */ |
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||||
|
||||
/* Non-Blocking mode: DMA */ |
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
||||
* @brief Timer Complementary PWM functions |
||||
* @{ |
||||
*/ |
||||
/* Timer Complementary PWM functions ****************************************/ |
||||
/* Blocking mode: Polling */ |
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
||||
|
||||
/* Non-Blocking mode: Interrupt */ |
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
||||
/* Non-Blocking mode: DMA */ |
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
||||
* @brief Timer Complementary One Pulse functions |
||||
* @{ |
||||
*/ |
||||
/* Timer Complementary One Pulse functions **********************************/ |
||||
/* Blocking mode: Polling */ |
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||||
|
||||
/* Non-Blocking mode: Interrupt */ |
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||
* @brief Peripheral Control functions |
||||
* @{ |
||||
*/ |
||||
/* Extended Control functions ************************************************/ |
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, |
||||
uint32_t CommutationSource); |
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, |
||||
uint32_t CommutationSource); |
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, |
||||
uint32_t CommutationSource); |
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, |
||||
TIM_MasterConfigTypeDef *sMasterConfig); |
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, |
||||
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); |
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
||||
* @brief Extended Callbacks functions |
||||
* @{ |
||||
*/ |
||||
/* Extended Callback **********************************************************/ |
||||
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); |
||||
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); |
||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
||||
* @brief Extended Peripheral State functions |
||||
* @{ |
||||
*/ |
||||
/* Extended Peripheral State functions ***************************************/ |
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); |
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* End of exported functions -------------------------------------------------*/ |
||||
|
||||
/* Private functions----------------------------------------------------------*/ |
||||
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
|
||||
* @{ |
||||
*/ |
||||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); |
||||
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* End of private functions --------------------------------------------------*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
|
||||
#endif /* STM32F1xx_HAL_TIM_EX_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,887 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_uart.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of UART HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32F1xx_HAL_UART_H |
||||
#define __STM32F1xx_HAL_UART_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup UART
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/** @defgroup UART_Exported_Types UART Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief UART Init Structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
|
||||
The baud rate is computed using the following formula: |
||||
- IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate))) |
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */ |
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref UART_Word_Length */ |
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref UART_Stop_Bits */ |
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref UART_Parity |
||||
@note When parity is enabled, the computed parity is inserted |
||||
at the MSB position of the transmitted data (9th bit when |
||||
the word length is set to 9 data bits; 8th bit when the |
||||
word length is set to 8 data bits). */ |
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref UART_Mode */ |
||||
|
||||
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
|
||||
This parameter can be a value of @ref UART_Hardware_Flow_Control */ |
||||
|
||||
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
|
||||
This parameter can be a value of @ref UART_Over_Sampling. This feature is only available
|
||||
on STM32F100xx family, so OverSampling parameter should always be set to 16. */ |
||||
} UART_InitTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL UART State structures definition |
||||
* @note HAL UART State value is a combination of 2 different substates: gState and RxState. |
||||
* - gState contains UART state information related to global Handle management |
||||
* and also information related to Tx operations. |
||||
* gState value coding follow below described bitmap : |
||||
* b7-b6 Error information |
||||
* 00 : No Error |
||||
* 01 : (Not Used) |
||||
* 10 : Timeout |
||||
* 11 : Error |
||||
* b5 Peripheral initialization status |
||||
* 0 : Reset (Peripheral not initialized) |
||||
* 1 : Init done (Peripheral initialized. HAL UART Init function already called) |
||||
* b4-b3 (not used) |
||||
* xx : Should be set to 00 |
||||
* b2 Intrinsic process state |
||||
* 0 : Ready |
||||
* 1 : Busy (Peripheral busy with some configuration or internal operations) |
||||
* b1 (not used) |
||||
* x : Should be set to 0 |
||||
* b0 Tx state |
||||
* 0 : Ready (no Tx operation ongoing) |
||||
* 1 : Busy (Tx operation ongoing) |
||||
* - RxState contains information related to Rx operations. |
||||
* RxState value coding follow below described bitmap : |
||||
* b7-b6 (not used) |
||||
* xx : Should be set to 00 |
||||
* b5 Peripheral initialization status |
||||
* 0 : Reset (Peripheral not initialized) |
||||
* 1 : Init done (Peripheral initialized) |
||||
* b4-b2 (not used) |
||||
* xxx : Should be set to 000 |
||||
* b1 Rx state |
||||
* 0 : Ready (no Rx operation ongoing) |
||||
* 1 : Busy (Rx operation ongoing) |
||||
* b0 (not used) |
||||
* x : Should be set to 0. |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */ |
||||
HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */ |
||||
HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */ |
||||
HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */ |
||||
HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */ |
||||
HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState. |
||||
Value is result of combination (Or) between gState and RxState values */ |
||||
HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
||||
Value is allowed for gState only */ |
||||
HAL_UART_STATE_ERROR = 0xE0U /*!< Error
|
||||
Value is allowed for gState only */ |
||||
} HAL_UART_StateTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL UART Reception type definition |
||||
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing. |
||||
* It is expected to admit following values : |
||||
* HAL_UART_RECEPTION_STANDARD = 0x00U, |
||||
* HAL_UART_RECEPTION_TOIDLE = 0x01U, |
||||
*/ |
||||
typedef uint32_t HAL_UART_RxTypeTypeDef; |
||||
|
||||
/**
|
||||
* @brief UART handle Structure definition |
||||
*/ |
||||
typedef struct __UART_HandleTypeDef |
||||
{ |
||||
USART_TypeDef *Instance; /*!< UART registers base address */ |
||||
|
||||
UART_InitTypeDef Init; /*!< UART communication parameters */ |
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ |
||||
|
||||
uint16_t TxXferSize; /*!< UART Tx Transfer size */ |
||||
|
||||
__IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ |
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ |
||||
|
||||
uint16_t RxXferSize; /*!< UART Rx Transfer size */ |
||||
|
||||
__IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ |
||||
|
||||
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ |
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ |
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ |
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */ |
||||
|
||||
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
|
||||
and also related to Tx operations. |
||||
This parameter can be a value of @ref HAL_UART_StateTypeDef */ |
||||
|
||||
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_UART_StateTypeDef */ |
||||
|
||||
__IO uint32_t ErrorCode; /*!< UART Error code */ |
||||
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
||||
void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ |
||||
void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ |
||||
void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ |
||||
void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ |
||||
void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ |
||||
void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ |
||||
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ |
||||
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ |
||||
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ |
||||
void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ |
||||
|
||||
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ |
||||
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ |
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
||||
|
||||
} UART_HandleTypeDef; |
||||
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
||||
/**
|
||||
* @brief HAL UART Callback ID enumeration definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ |
||||
HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ |
||||
HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ |
||||
HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ |
||||
HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ |
||||
HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ |
||||
HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ |
||||
HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ |
||||
HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ |
||||
|
||||
HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ |
||||
HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ |
||||
|
||||
} HAL_UART_CallbackIDTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL UART Callback pointer definition |
||||
*/ |
||||
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ |
||||
typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ |
||||
|
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup UART_Exported_Constants UART Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup UART_Error_Code UART Error Code
|
||||
* @{ |
||||
*/ |
||||
#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ |
||||
#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ |
||||
#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ |
||||
#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ |
||||
#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ |
||||
#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ |
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
||||
#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ |
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_Word_Length UART Word Length
|
||||
* @{ |
||||
*/ |
||||
#define UART_WORDLENGTH_8B 0x00000000U |
||||
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
|
||||
* @{ |
||||
*/ |
||||
#define UART_STOPBITS_1 0x00000000U |
||||
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_Parity UART Parity
|
||||
* @{ |
||||
*/ |
||||
#define UART_PARITY_NONE 0x00000000U |
||||
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) |
||||
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
|
||||
* @{ |
||||
*/ |
||||
#define UART_HWCONTROL_NONE 0x00000000U |
||||
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) |
||||
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) |
||||
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_Mode UART Transfer Mode
|
||||
* @{ |
||||
*/ |
||||
#define UART_MODE_RX ((uint32_t)USART_CR1_RE) |
||||
#define UART_MODE_TX ((uint32_t)USART_CR1_TE) |
||||
#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_State UART State
|
||||
* @{ |
||||
*/ |
||||
#define UART_STATE_DISABLE 0x00000000U |
||||
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_Over_Sampling UART Over Sampling
|
||||
* @{ |
||||
*/ |
||||
#define UART_OVERSAMPLING_16 0x00000000U |
||||
#if defined(USART_CR1_OVER8) |
||||
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) |
||||
#endif /* USART_CR1_OVER8 */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
|
||||
* @{ |
||||
*/ |
||||
#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U |
||||
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_WakeUp_functions UART Wakeup Functions
|
||||
* @{ |
||||
*/ |
||||
#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U |
||||
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_Flags UART FLags
|
||||
* Elements values convention: 0xXXXX |
||||
* - 0xXXXX : Flag mask in the SR register |
||||
* @{ |
||||
*/ |
||||
#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) |
||||
#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) |
||||
#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) |
||||
#define UART_FLAG_TC ((uint32_t)USART_SR_TC) |
||||
#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) |
||||
#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) |
||||
#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) |
||||
#define UART_FLAG_NE ((uint32_t)USART_SR_NE) |
||||
#define UART_FLAG_FE ((uint32_t)USART_SR_FE) |
||||
#define UART_FLAG_PE ((uint32_t)USART_SR_PE) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
|
||||
* Elements values convention: 0xY000XXXX |
||||
* - XXXX : Interrupt mask (16 bits) in the Y register |
||||
* - Y : Interrupt source register (2bits) |
||||
* - 0001: CR1 register |
||||
* - 0010: CR2 register |
||||
* - 0011: CR3 register |
||||
* @{ |
||||
*/ |
||||
|
||||
#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) |
||||
#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) |
||||
#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) |
||||
#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) |
||||
#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) |
||||
|
||||
#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) |
||||
|
||||
#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) |
||||
#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
|
||||
* @{ |
||||
*/ |
||||
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ |
||||
#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup UART_Exported_Macros UART Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Reset UART handle gstate & RxState
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @retval None |
||||
*/ |
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
||||
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
||||
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U) |
||||
#else |
||||
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
||||
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
|
||||
} while(0U) |
||||
#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ |
||||
|
||||
/** @brief Flushes the UART DR register
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
*/ |
||||
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) |
||||
|
||||
/** @brief Checks whether the specified UART flag is set or not.
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @param __FLAG__ specifies the flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) |
||||
* @arg UART_FLAG_LBD: LIN Break detection flag |
||||
* @arg UART_FLAG_TXE: Transmit data register empty flag |
||||
* @arg UART_FLAG_TC: Transmission Complete flag |
||||
* @arg UART_FLAG_RXNE: Receive data register not empty flag |
||||
* @arg UART_FLAG_IDLE: Idle Line detection flag |
||||
* @arg UART_FLAG_ORE: Overrun Error flag |
||||
* @arg UART_FLAG_NE: Noise Error flag |
||||
* @arg UART_FLAG_FE: Framing Error flag |
||||
* @arg UART_FLAG_PE: Parity Error flag |
||||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
||||
*/ |
||||
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) |
||||
|
||||
/** @brief Clears the specified UART pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @param __FLAG__ specifies the flag to check. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). |
||||
* @arg UART_FLAG_LBD: LIN Break detection flag. |
||||
* @arg UART_FLAG_TC: Transmission Complete flag. |
||||
* @arg UART_FLAG_RXNE: Receive data register not empty flag. |
||||
* |
||||
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun |
||||
* error) and IDLE (Idle line detected) flags are cleared by software |
||||
* sequence: a read operation to USART_SR register followed by a read |
||||
* operation to USART_DR register. |
||||
* @note RXNE flag can be also cleared by a read to the USART_DR register. |
||||
* @note TC flag can be also cleared by software sequence: a read operation to |
||||
* USART_SR register followed by a write operation to USART_DR register. |
||||
* @note TXE flag is cleared only by a write to the USART_DR register. |
||||
* |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
||||
|
||||
/** @brief Clears the UART PE pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ |
||||
do{ \
|
||||
__IO uint32_t tmpreg = 0x00U; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||
tmpreg = (__HANDLE__)->Instance->DR; \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0U) |
||||
|
||||
/** @brief Clears the UART FE pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) |
||||
|
||||
/** @brief Clears the UART NE pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) |
||||
|
||||
/** @brief Clears the UART ORE pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) |
||||
|
||||
/** @brief Clears the UART IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) |
||||
|
||||
/** @brief Enable the specified UART interrupt.
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @param __INTERRUPT__ specifies the UART interrupt source to enable. |
||||
* This parameter can be one of the following values: |
||||
* @arg UART_IT_CTS: CTS change interrupt |
||||
* @arg UART_IT_LBD: LIN Break detection interrupt |
||||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt |
||||
* @arg UART_IT_TC: Transmission complete interrupt |
||||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt |
||||
* @arg UART_IT_IDLE: Idle line detection interrupt |
||||
* @arg UART_IT_PE: Parity Error interrupt |
||||
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ |
||||
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) |
||||
|
||||
/** @brief Disable the specified UART interrupt.
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @param __INTERRUPT__ specifies the UART interrupt source to disable. |
||||
* This parameter can be one of the following values: |
||||
* @arg UART_IT_CTS: CTS change interrupt |
||||
* @arg UART_IT_LBD: LIN Break detection interrupt |
||||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt |
||||
* @arg UART_IT_TC: Transmission complete interrupt |
||||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt |
||||
* @arg UART_IT_IDLE: Idle line detection interrupt |
||||
* @arg UART_IT_PE: Parity Error interrupt |
||||
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ |
||||
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) |
||||
|
||||
/** @brief Checks whether the specified UART interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* UART Handle selects the USARTx or UARTy peripheral |
||||
* (USART,UART availability and x,y values depending on device). |
||||
* @param __IT__ specifies the UART interrupt source to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) |
||||
* @arg UART_IT_LBD: LIN Break detection interrupt |
||||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt |
||||
* @arg UART_IT_TC: Transmission complete interrupt |
||||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt |
||||
* @arg UART_IT_IDLE: Idle line detection interrupt |
||||
* @arg UART_IT_ERR: Error interrupt |
||||
* @retval The new state of __IT__ (TRUE or FALSE). |
||||
*/ |
||||
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ |
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) |
||||
|
||||
/** @brief Enable CTS flow control
|
||||
* @note This macro allows to enable CTS hardware flow control for a given UART instance, |
||||
* without need to call HAL_UART_Init() function. |
||||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
||||
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need |
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
||||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) |
||||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). |
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). |
||||
* It is used to select the USART peripheral (USART availability and x value depending on device). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ |
||||
do{ \
|
||||
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
|
||||
} while(0U) |
||||
|
||||
/** @brief Disable CTS flow control
|
||||
* @note This macro allows to disable CTS hardware flow control for a given UART instance, |
||||
* without need to call HAL_UART_Init() function. |
||||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
||||
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need |
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
||||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) |
||||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). |
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). |
||||
* It is used to select the USART peripheral (USART availability and x value depending on device). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ |
||||
do{ \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
|
||||
} while(0U) |
||||
|
||||
/** @brief Enable RTS flow control
|
||||
* This macro allows to enable RTS hardware flow control for a given UART instance, |
||||
* without need to call HAL_UART_Init() function. |
||||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
||||
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need |
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
||||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) |
||||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). |
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). |
||||
* It is used to select the USART peripheral (USART availability and x value depending on device). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ |
||||
do{ \
|
||||
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
|
||||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
|
||||
} while(0U) |
||||
|
||||
/** @brief Disable RTS flow control
|
||||
* This macro allows to disable RTS hardware flow control for a given UART instance, |
||||
* without need to call HAL_UART_Init() function. |
||||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
||||
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need |
||||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
||||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
||||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) |
||||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). |
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). |
||||
* It is used to select the USART peripheral (USART availability and x value depending on device). |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ |
||||
do{ \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
|
||||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
|
||||
} while(0U) |
||||
#if defined(USART_CR3_ONEBIT) |
||||
|
||||
/** @brief Macro to enable the UART's one bit sample method
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) |
||||
|
||||
/** @brief Macro to disable the UART's one bit sample method
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) |
||||
#endif /* UART_ONE_BIT_SAMPLE_Feature */ |
||||
|
||||
/** @brief Enable UART
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) |
||||
|
||||
/** @brief Disable UART
|
||||
* @param __HANDLE__ specifies the UART Handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup UART_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Initialization/de-initialization functions **********************************/ |
||||
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); |
||||
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); |
||||
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); |
||||
void HAL_UART_MspInit(UART_HandleTypeDef *huart); |
||||
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); |
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/ |
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
||||
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); |
||||
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); |
||||
|
||||
HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); |
||||
HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); |
||||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* IO operation functions *******************************************************/ |
||||
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); |
||||
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||||
|
||||
/* Transfer Abort functions */ |
||||
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); |
||||
|
||||
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); |
||||
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); |
||||
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); |
||||
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); |
||||
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); |
||||
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); |
||||
void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); |
||||
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); |
||||
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); |
||||
|
||||
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup UART_Exported_Functions_Group3
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral Control functions ************************************************/ |
||||
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup UART_Exported_Functions_Group4
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral State functions **************************************************/ |
||||
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); |
||||
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Private types -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/** @defgroup UART_Private_Constants UART Private Constants
|
||||
* @{ |
||||
*/ |
||||
/** @brief UART interruptions flag mask
|
||||
* |
||||
*/ |
||||
#define UART_IT_MASK 0x0000FFFFU |
||||
|
||||
#define UART_CR1_REG_INDEX 1U |
||||
#define UART_CR2_REG_INDEX 2U |
||||
#define UART_CR3_REG_INDEX 3U |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup UART_Private_Macros UART Private Macros
|
||||
* @{ |
||||
*/ |
||||
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ |
||||
((LENGTH) == UART_WORDLENGTH_9B)) |
||||
#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) |
||||
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ |
||||
((STOPBITS) == UART_STOPBITS_2)) |
||||
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ |
||||
((PARITY) == UART_PARITY_EVEN) || \
|
||||
((PARITY) == UART_PARITY_ODD)) |
||||
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ |
||||
(((CONTROL) == UART_HWCONTROL_NONE) || \
|
||||
((CONTROL) == UART_HWCONTROL_RTS) || \
|
||||
((CONTROL) == UART_HWCONTROL_CTS) || \
|
||||
((CONTROL) == UART_HWCONTROL_RTS_CTS)) |
||||
#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) |
||||
#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ |
||||
((STATE) == UART_STATE_ENABLE)) |
||||
#if defined(USART_CR1_OVER8) |
||||
#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ |
||||
((SAMPLING) == UART_OVERSAMPLING_8)) |
||||
#endif /* USART_CR1_OVER8 */ |
||||
#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) |
||||
#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ |
||||
((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) |
||||
#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ |
||||
((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) |
||||
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4500000U) |
||||
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) |
||||
|
||||
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) |
||||
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) |
||||
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) |
||||
/* UART BRR = mantissa + overflow + fraction
|
||||
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ |
||||
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ |
||||
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
|
||||
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) |
||||
|
||||
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_))) |
||||
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) |
||||
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) |
||||
/* UART BRR = mantissa + overflow + fraction
|
||||
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ |
||||
#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ |
||||
((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
|
||||
(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private functions ---------------------------------------------------------*/ |
||||
/** @defgroup UART_Private_Functions UART Private Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32F1xx_HAL_UART_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,27 @@ |
||||
Copyright 2016(-2021) STMicroelectronics. |
||||
All rights reserved. |
||||
|
||||
Redistribution and use in source and binary forms, with or without modification, |
||||
are permitted provided that the following conditions are met: |
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this |
||||
list of conditions and the following disclaimer. |
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice, |
||||
this list of conditions and the following disclaimer in the documentation and/or |
||||
other materials provided with the distribution. |
||||
|
||||
3. Neither the name of the copyright holder nor the names of its contributors |
||||
may be used to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
||||
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
||||
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
@ -0,0 +1,606 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal.c |
||||
* @author MCD Application Team |
||||
* @brief HAL module driver. |
||||
* This is the common part of the HAL initialization |
||||
* |
||||
@verbatim |
||||
============================================================================== |
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..] |
||||
The common HAL driver contains a set of generic and common APIs that can be |
||||
used by the PPP peripheral drivers and the user to start using the HAL. |
||||
[..] |
||||
The HAL contains two APIs' categories: |
||||
(+) Common HAL APIs |
||||
(+) Services HAL APIs |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup HAL HAL
|
||||
* @brief HAL module driver. |
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_MODULE_ENABLED |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @brief STM32F1xx HAL Driver version number V1.1.8 |
||||
*/ |
||||
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ |
||||
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ |
||||
#define __STM32F1xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */ |
||||
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ |
||||
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\ |
||||
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
|
||||
|(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F1xx_HAL_VERSION_RC)) |
||||
|
||||
#define IDCODE_DEVID_MASK 0x00000FFFU |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
|
||||
/** @defgroup HAL_Private_Variables HAL Private Variables
|
||||
* @{ |
||||
*/ |
||||
__IO uint32_t uwTick; |
||||
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ |
||||
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* Exported functions ---------------------------------------------------------*/ |
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
|
||||
* @brief Initialization and de-initialization functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Initialization and de-initialization functions ##### |
||||
=============================================================================== |
||||
[..] This section provides functions allowing to: |
||||
(+) Initializes the Flash interface, the NVIC allocation and initial clock |
||||
configuration. It initializes the systick also when timeout is needed |
||||
and the backup domain when enabled. |
||||
(+) de-Initializes common part of the HAL. |
||||
(+) Configure The time base source to have 1ms time base with a dedicated |
||||
Tick interrupt priority. |
||||
(++) SysTick timer is used by default as source of time base, but user |
||||
can eventually implement his proper time base source (a general purpose |
||||
timer for example or other time source), keeping in mind that Time base |
||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and |
||||
handled in milliseconds basis. |
||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically |
||||
at the beginning of the program after reset by HAL_Init() or at any time |
||||
when clock is configured, by HAL_RCC_ClockConfig(). |
||||
(++) Source of time base is configured to generate interrupts at regular |
||||
time intervals. Care must be taken if HAL_Delay() is called from a |
||||
peripheral ISR process, the Tick interrupt line must have higher priority |
||||
(numerically lower) than the peripheral interrupt. Otherwise the caller |
||||
ISR process will be blocked. |
||||
(++) functions affecting time base configurations are declared as __weak |
||||
to make override possible in case of other implementations in user file. |
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief This function is used to initialize the HAL Library; it must be the first |
||||
* instruction to be executed in the main program (before to call any other |
||||
* HAL function), it performs the following: |
||||
* Configure the Flash prefetch. |
||||
* Configures the SysTick to generate an interrupt each 1 millisecond, |
||||
* which is clocked by the HSI (at this stage, the clock is not yet |
||||
* configured and thus the system is running from the internal HSI at 16 MHz). |
||||
* Set NVIC Group Priority to 4. |
||||
* Calls the HAL_MspInit() callback function defined in user file |
||||
* "stm32f1xx_hal_msp.c" to do the global low level hardware initialization |
||||
* |
||||
* @note SysTick is used as time base for the HAL_Delay() function, the application |
||||
* need to ensure that the SysTick time base is always set to 1 millisecond |
||||
* to have correct HAL operation. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_Init(void) |
||||
{ |
||||
/* Configure Flash prefetch */ |
||||
#if (PREFETCH_ENABLE != 0) |
||||
#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \ |
||||
defined(STM32F102x6) || defined(STM32F102xB) || \
|
||||
defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
|
||||
defined(STM32F105xC) || defined(STM32F107xC) |
||||
|
||||
/* Prefetch buffer is not available on value line devices */ |
||||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE(); |
||||
#endif |
||||
#endif /* PREFETCH_ENABLE */ |
||||
|
||||
/* Set Interrupt Group Priority */ |
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); |
||||
|
||||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ |
||||
HAL_InitTick(TICK_INT_PRIORITY); |
||||
|
||||
/* Init the low level hardware */ |
||||
HAL_MspInit(); |
||||
|
||||
/* Return function status */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function de-Initializes common part of the HAL and stops the systick. |
||||
* of time base. |
||||
* @note This function is optional. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DeInit(void) |
||||
{ |
||||
/* Reset of all peripherals */ |
||||
__HAL_RCC_APB1_FORCE_RESET(); |
||||
__HAL_RCC_APB1_RELEASE_RESET(); |
||||
|
||||
__HAL_RCC_APB2_FORCE_RESET(); |
||||
__HAL_RCC_APB2_RELEASE_RESET(); |
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
||||
__HAL_RCC_AHB_FORCE_RESET(); |
||||
__HAL_RCC_AHB_RELEASE_RESET(); |
||||
#endif |
||||
|
||||
/* De-Init the low level hardware */ |
||||
HAL_MspDeInit(); |
||||
|
||||
/* Return function status */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Initialize the MSP. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_MspInit(void) |
||||
{ |
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_MspInit could be implemented in the user file |
||||
*/ |
||||
} |
||||
|
||||
/**
|
||||
* @brief DeInitializes the MSP. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_MspDeInit(void) |
||||
{ |
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_MspDeInit could be implemented in the user file |
||||
*/ |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function configures the source of the time base. |
||||
* The time source is configured to have 1ms time base with a dedicated |
||||
* Tick interrupt priority. |
||||
* @note This function is called automatically at the beginning of program after |
||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). |
||||
* @note In the default implementation, SysTick timer is the source of time base. |
||||
* It is used to generate interrupts at regular time intervals. |
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process, |
||||
* The SysTick interrupt must have higher priority (numerically lower) |
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked. |
||||
* The function is declared as __weak to be overwritten in case of other |
||||
* implementation in user file. |
||||
* @param TickPriority Tick interrupt priority. |
||||
* @retval HAL status |
||||
*/ |
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) |
||||
{ |
||||
/* Configure the SysTick to have interrupt in 1ms time basis*/ |
||||
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Configure the SysTick IRQ priority */ |
||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS)) |
||||
{ |
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); |
||||
uwTickPrio = TickPriority; |
||||
} |
||||
else |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Return function status */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
||||
* @brief HAL Control functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### HAL Control functions ##### |
||||
=============================================================================== |
||||
[..] This section provides functions allowing to: |
||||
(+) Provide a tick value in millisecond |
||||
(+) Provide a blocking delay in millisecond |
||||
(+) Suspend the time base source interrupt |
||||
(+) Resume the time base source interrupt |
||||
(+) Get the HAL API driver version |
||||
(+) Get the device identifier |
||||
(+) Get the device revision identifier |
||||
(+) Enable/Disable Debug module during SLEEP mode |
||||
(+) Enable/Disable Debug module during STOP mode |
||||
(+) Enable/Disable Debug module during STANDBY mode |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief This function is called to increment a global variable "uwTick" |
||||
* used as application time base. |
||||
* @note In the default implementation, this variable is incremented each 1ms |
||||
* in SysTick ISR. |
||||
* @note This function is declared as __weak to be overwritten in case of other |
||||
* implementations in user file. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_IncTick(void) |
||||
{ |
||||
uwTick += uwTickFreq; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Provides a tick value in millisecond. |
||||
* @note This function is declared as __weak to be overwritten in case of other |
||||
* implementations in user file. |
||||
* @retval tick value |
||||
*/ |
||||
__weak uint32_t HAL_GetTick(void) |
||||
{ |
||||
return uwTick; |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function returns a tick priority. |
||||
* @retval tick priority |
||||
*/ |
||||
uint32_t HAL_GetTickPrio(void) |
||||
{ |
||||
return uwTickPrio; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Set new tick Freq. |
||||
* @retval status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
HAL_TickFreqTypeDef prevTickFreq; |
||||
|
||||
assert_param(IS_TICKFREQ(Freq)); |
||||
|
||||
if (uwTickFreq != Freq) |
||||
{ |
||||
/* Back up uwTickFreq frequency */ |
||||
prevTickFreq = uwTickFreq; |
||||
|
||||
/* Update uwTickFreq global variable used by HAL_InitTick() */ |
||||
uwTickFreq = Freq; |
||||
|
||||
/* Apply the new tick Freq */ |
||||
status = HAL_InitTick(uwTickPrio); |
||||
|
||||
if (status != HAL_OK) |
||||
{ |
||||
/* Restore previous tick frequency */ |
||||
uwTickFreq = prevTickFreq; |
||||
} |
||||
} |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return tick frequency. |
||||
* @retval tick period in Hz |
||||
*/ |
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void) |
||||
{ |
||||
return uwTickFreq; |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function provides minimum delay (in milliseconds) based |
||||
* on variable incremented. |
||||
* @note In the default implementation , SysTick timer is the source of time base. |
||||
* It is used to generate interrupts at regular time intervals where uwTick |
||||
* is incremented. |
||||
* @note This function is declared as __weak to be overwritten in case of other |
||||
* implementations in user file. |
||||
* @param Delay specifies the delay time length, in milliseconds. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_Delay(uint32_t Delay) |
||||
{ |
||||
uint32_t tickstart = HAL_GetTick(); |
||||
uint32_t wait = Delay; |
||||
|
||||
/* Add a freq to guarantee minimum wait */ |
||||
if (wait < HAL_MAX_DELAY) |
||||
{ |
||||
wait += (uint32_t)(uwTickFreq); |
||||
} |
||||
|
||||
while ((HAL_GetTick() - tickstart) < wait) |
||||
{ |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment. |
||||
* @note In the default implementation , SysTick timer is the source of time base. It is |
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick() |
||||
* is called, the SysTick interrupt will be disabled and so Tick increment |
||||
* is suspended. |
||||
* @note This function is declared as __weak to be overwritten in case of other |
||||
* implementations in user file. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_SuspendTick(void) |
||||
{ |
||||
/* Disable SysTick Interrupt */ |
||||
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Resume Tick increment. |
||||
* @note In the default implementation , SysTick timer is the source of time base. It is |
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick() |
||||
* is called, the SysTick interrupt will be enabled and so Tick increment |
||||
* is resumed. |
||||
* @note This function is declared as __weak to be overwritten in case of other |
||||
* implementations in user file. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_ResumeTick(void) |
||||
{ |
||||
/* Enable SysTick Interrupt */ |
||||
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns the HAL revision |
||||
* @retval version 0xXYZR (8bits for each decimal, R for RC) |
||||
*/ |
||||
uint32_t HAL_GetHalVersion(void) |
||||
{ |
||||
return __STM32F1xx_HAL_VERSION; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier. |
||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
||||
* STM32F101xF/G and STM32F103xF/G |
||||
* STM32F10xx4 and STM32F10xx6 |
||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
||||
* debug mode (not accessible by the user software in normal mode). |
||||
* Refer to errata sheet of these devices for more details. |
||||
* @retval Device revision identifier |
||||
*/ |
||||
uint32_t HAL_GetREVID(void) |
||||
{ |
||||
return ((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns the device identifier. |
||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
||||
* STM32F101xF/G and STM32F103xF/G |
||||
* STM32F10xx4 and STM32F10xx6 |
||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
||||
* debug mode (not accessible by the user software in normal mode). |
||||
* Refer to errata sheet of these devices for more details. |
||||
* @retval Device identifier |
||||
*/ |
||||
uint32_t HAL_GetDEVID(void) |
||||
{ |
||||
return ((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns first word of the unique device identifier (UID based on 96 bits) |
||||
* @retval Device identifier |
||||
*/ |
||||
uint32_t HAL_GetUIDw0(void) |
||||
{ |
||||
return(READ_REG(*((uint32_t *)UID_BASE))); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns second word of the unique device identifier (UID based on 96 bits) |
||||
* @retval Device identifier |
||||
*/ |
||||
uint32_t HAL_GetUIDw1(void) |
||||
{ |
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns third word of the unique device identifier (UID based on 96 bits) |
||||
* @retval Device identifier |
||||
*/ |
||||
uint32_t HAL_GetUIDw2(void) |
||||
{ |
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during SLEEP mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_EnableDBGSleepMode(void) |
||||
{ |
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during SLEEP mode |
||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
||||
* STM32F101xF/G and STM32F103xF/G |
||||
* STM32F10xx4 and STM32F10xx6 |
||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
||||
* debug mode (not accessible by the user software in normal mode). |
||||
* Refer to errata sheet of these devices for more details. |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_DisableDBGSleepMode(void) |
||||
{ |
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode |
||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
||||
* STM32F101xF/G and STM32F103xF/G |
||||
* STM32F10xx4 and STM32F10xx6 |
||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
||||
* debug mode (not accessible by the user software in normal mode). |
||||
* Refer to errata sheet of these devices for more details. |
||||
* Note: On all STM32F1 devices: |
||||
* If the system tick timer interrupt is enabled during the Stop mode |
||||
* debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup |
||||
* the system from Stop mode. |
||||
* Workaround: To debug the Stop mode, disable the system tick timer |
||||
* interrupt. |
||||
* Refer to errata sheet of these devices for more details. |
||||
* Note: On all STM32F1 devices: |
||||
* If the system tick timer interrupt is enabled during the Stop mode |
||||
* debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup |
||||
* the system from Stop mode. |
||||
* Workaround: To debug the Stop mode, disable the system tick timer |
||||
* interrupt. |
||||
* Refer to errata sheet of these devices for more details. |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_EnableDBGStopMode(void) |
||||
{ |
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode |
||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
||||
* STM32F101xF/G and STM32F103xF/G |
||||
* STM32F10xx4 and STM32F10xx6 |
||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
||||
* debug mode (not accessible by the user software in normal mode). |
||||
* Refer to errata sheet of these devices for more details. |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_DisableDBGStopMode(void) |
||||
{ |
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode |
||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
||||
* STM32F101xF/G and STM32F103xF/G |
||||
* STM32F10xx4 and STM32F10xx6 |
||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
||||
* debug mode (not accessible by the user software in normal mode). |
||||
* Refer to errata sheet of these devices for more details. |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void) |
||||
{ |
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode |
||||
* Note: On devices STM32F10xx8 and STM32F10xxB, |
||||
* STM32F101xC/D/E and STM32F103xC/D/E, |
||||
* STM32F101xF/G and STM32F103xF/G |
||||
* STM32F10xx4 and STM32F10xx6 |
||||
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in |
||||
* debug mode (not accessible by the user software in normal mode). |
||||
* Refer to errata sheet of these devices for more details. |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void) |
||||
{ |
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,505 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_cortex.c |
||||
* @author MCD Application Team |
||||
* @brief CORTEX HAL module driver. |
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX: |
||||
* + Initialization and de-initialization functions |
||||
* + Peripheral Control functions
|
||||
* |
||||
@verbatim
|
||||
============================================================================== |
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using CORTEX HAL driver *** |
||||
=========================================================== |
||||
[..]
|
||||
This section provides functions allowing to configure the NVIC interrupts (IRQ). |
||||
The Cortex-M3 exceptions are managed by CMSIS functions. |
||||
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() |
||||
function according to the following table. |
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). |
||||
(#) please refer to programming manual for details in how to configure priority.
|
||||
|
||||
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
|
||||
The pending IRQ priority will be managed only by the sub priority. |
||||
|
||||
-@- IRQ priority order (sorted by highest to lowest priority): |
||||
(+@) Lowest preemption priority |
||||
(+@) Lowest sub priority |
||||
(+@) Lowest hardware priority (IRQ number) |
||||
|
||||
[..]
|
||||
*** How to configure Systick using CORTEX HAL driver *** |
||||
======================================================== |
||||
[..] |
||||
Setup SysTick Timer for time base. |
||||
|
||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which |
||||
is a CMSIS function that: |
||||
(++) Configures the SysTick Reload register with value passed as function parameter. |
||||
(++) Configures the SysTick IRQ priority to the lowest value 0x0F. |
||||
(++) Resets the SysTick Counter register. |
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). |
||||
(++) Enables the SysTick Interrupt. |
||||
(++) Starts the SysTick Counter. |
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro |
||||
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the |
||||
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined |
||||
inside the stm32f1xx_hal_cortex.h file. |
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the |
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. |
||||
|
||||
(+) To adjust the SysTick time base, use the following formula: |
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) |
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function |
||||
(++) Reload Value should not exceed 0xFFFFFF |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED |
||||
|
||||
/* Private types -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/* Private functions ---------------------------------------------------------*/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* |
||||
@verbatim
|
||||
============================================================================== |
||||
##### Initialization and de-initialization functions ##### |
||||
============================================================================== |
||||
[..] |
||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts |
||||
Systick functionalities
|
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
/**
|
||||
* @brief Sets the priority grouping field (preemption priority and subpriority) |
||||
* using the required unlock sequence. |
||||
* @param PriorityGroup: The priority grouping bits length.
|
||||
* This parameter can be one of the following values: |
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority |
||||
* 4 bits for subpriority |
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority |
||||
* 3 bits for subpriority |
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority |
||||
* 2 bits for subpriority |
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority |
||||
* 1 bits for subpriority |
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority |
||||
* 0 bits for subpriority |
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); |
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ |
||||
NVIC_SetPriorityGrouping(PriorityGroup); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt. |
||||
* @param IRQn: External interrupt number. |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h)) |
||||
* @param PreemptPriority: The preemption priority for the IRQn channel. |
||||
* This parameter can be a value between 0 and 15 |
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority: the subpriority level for the IRQ channel. |
||||
* This parameter can be a value between 0 and 15 |
||||
* A lower priority value indicates a higher priority.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) |
||||
{
|
||||
uint32_t prioritygroup = 0x00U; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); |
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); |
||||
|
||||
prioritygroup = NVIC_GetPriorityGrouping(); |
||||
|
||||
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller. |
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() |
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number. |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) |
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||||
|
||||
/* Enable interrupt */ |
||||
NVIC_EnableIRQ(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller. |
||||
* @param IRQn External interrupt number. |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||||
|
||||
/* Disable interrupt */ |
||||
NVIC_DisableIRQ(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU. |
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_SystemReset(void) |
||||
{ |
||||
/* System Reset */ |
||||
NVIC_SystemReset(); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
* Counter is in free running mode to generate periodic interrupts. |
||||
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. |
||||
* @retval status: - 0 Function succeeded. |
||||
* - 1 Function failed. |
||||
*/ |
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) |
||||
{ |
||||
return SysTick_Config(TicksNumb); |
||||
} |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
* |
||||
@verbatim
|
||||
============================================================================== |
||||
##### Peripheral Control functions ##### |
||||
============================================================================== |
||||
[..] |
||||
This subsection provides a set of functions allowing to control the CORTEX |
||||
(NVIC, SYSTICK, MPU) functionalities.
|
||||
|
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
/**
|
||||
* @brief Disables the MPU |
||||
* @retval None |
||||
*/ |
||||
void HAL_MPU_Disable(void) |
||||
{ |
||||
/* Make sure outstanding transfers are done */ |
||||
__DMB(); |
||||
|
||||
/* Disable fault exceptions */ |
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
||||
|
||||
/* Disable the MPU and clear the control register*/ |
||||
MPU->CTRL = 0U; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable the MPU. |
||||
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
|
||||
* NMI, FAULTMASK and privileged access to the default memory
|
||||
* This parameter can be one of the following values: |
||||
* @arg MPU_HFNMI_PRIVDEF_NONE |
||||
* @arg MPU_HARDFAULT_NMI |
||||
* @arg MPU_PRIVILEGED_DEFAULT |
||||
* @arg MPU_HFNMI_PRIVDEF |
||||
* @retval None |
||||
*/ |
||||
void HAL_MPU_Enable(uint32_t MPU_Control) |
||||
{ |
||||
/* Enable the MPU */ |
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
||||
|
||||
/* Enable fault exceptions */ |
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
||||
|
||||
/* Ensure MPU setting take effects */ |
||||
__DSB(); |
||||
__ISB(); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Initializes and configures the Region and the memory to be protected. |
||||
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains |
||||
* the initialization and configuration information. |
||||
* @retval None |
||||
*/ |
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); |
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); |
||||
|
||||
/* Set the Region number */ |
||||
MPU->RNR = MPU_Init->Number; |
||||
|
||||
if ((MPU_Init->Enable) != RESET) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); |
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); |
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); |
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); |
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); |
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); |
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); |
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); |
||||
|
||||
MPU->RBAR = MPU_Init->BaseAddress; |
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | |
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | |
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | |
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | |
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | |
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | |
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | |
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | |
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); |
||||
} |
||||
else |
||||
{ |
||||
MPU->RBAR = 0x00U; |
||||
MPU->RASR = 0x00U; |
||||
} |
||||
} |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
/**
|
||||
* @brief Gets the priority grouping field from the NVIC Interrupt Controller. |
||||
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) |
||||
*/ |
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void) |
||||
{ |
||||
/* Get the PRIGROUP[10:8] field value */ |
||||
return NVIC_GetPriorityGrouping(); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt. |
||||
* @param IRQn: External interrupt number. |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) |
||||
* @param PriorityGroup: the priority grouping bits length. |
||||
* This parameter can be one of the following values: |
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority |
||||
* 4 bits for subpriority |
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority |
||||
* 3 bits for subpriority |
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority |
||||
* 2 bits for subpriority |
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority |
||||
* 1 bits for subpriority |
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority |
||||
* 0 bits for subpriority |
||||
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). |
||||
* @param pSubPriority: Pointer on the Subpriority value (starting from 0). |
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); |
||||
/* Get priority for Cortex-M system or device specific interrupts */ |
||||
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt. |
||||
* @param IRQn External interrupt number |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||||
|
||||
/* Set interrupt pending */ |
||||
NVIC_SetPendingIRQ(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt). |
||||
* @param IRQn External interrupt number. |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending. |
||||
* - 1 Interrupt status is pending. |
||||
*/ |
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||||
|
||||
/* Return 1 if pending else 0 */ |
||||
return NVIC_GetPendingIRQ(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt. |
||||
* @param IRQn External interrupt number. |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||||
|
||||
/* Clear pending interrupt */ |
||||
NVIC_ClearPendingIRQ(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). |
||||
* @param IRQn External interrupt number |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending. |
||||
* - 1 Interrupt status is pending. |
||||
*/ |
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||||
|
||||
/* Return 1 if active else 0 */ |
||||
return NVIC_GetActive(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source. |
||||
* @param CLKSource: specifies the SysTick clock source. |
||||
* This parameter can be one of the following values: |
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. |
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. |
||||
* @retval None |
||||
*/ |
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); |
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK) |
||||
{ |
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; |
||||
} |
||||
else |
||||
{ |
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request. |
||||
* @retval None |
||||
*/ |
||||
void HAL_SYSTICK_IRQHandler(void) |
||||
{ |
||||
HAL_SYSTICK_Callback(); |
||||
} |
||||
|
||||
/**
|
||||
* @brief SYSTICK callback. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_SYSTICK_Callback(void) |
||||
{ |
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file |
||||
*/ |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,899 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_dma.c |
||||
* @author MCD Application Team |
||||
* @brief DMA HAL module driver. |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities of the Direct Memory Access (DMA) peripheral: |
||||
* + Initialization and de-initialization functions |
||||
* + IO operation functions |
||||
* + Peripheral State and errors functions |
||||
@verbatim |
||||
============================================================================== |
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..] |
||||
(#) Enable and configure the peripheral to be connected to the DMA Channel |
||||
(except for internal SRAM / FLASH memories: no initialization is
|
||||
necessary). Please refer to the Reference manual for connection between peripherals |
||||
and DMA requests. |
||||
|
||||
(#) For a given Channel, program the required configuration through the following parameters: |
||||
Channel request, Transfer Direction, Source and Destination data formats, |
||||
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode |
||||
using HAL_DMA_Init() function. |
||||
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection. |
||||
|
||||
(#) Use HAL_DMA_Abort() function to abort the current transfer |
||||
|
||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed. |
||||
*** Polling mode IO operation *** |
||||
================================= |
||||
[..] |
||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source |
||||
address and destination address and the Length of data to be transferred |
||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this |
||||
case a fixed Timeout can be configured by User depending from his application. |
||||
|
||||
*** Interrupt mode IO operation *** |
||||
=================================== |
||||
[..] |
||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() |
||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() |
||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of |
||||
Source address and destination address and the Length of data to be transferred. |
||||
In this case the DMA interrupt is configured |
||||
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine |
||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can |
||||
add his own function by customization of function pointer XferCpltCallback and |
||||
XferErrorCallback (i.e. a member of DMA handle structure). |
||||
|
||||
*** DMA HAL driver macros list *** |
||||
=============================================
|
||||
[..] |
||||
Below the list of most used macros in DMA HAL driver. |
||||
|
||||
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. |
||||
(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. |
||||
(+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. |
||||
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. |
||||
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. |
||||
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. |
||||
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DMA HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMA DMA
|
||||
* @brief DMA HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
||||
* @{ |
||||
*/ |
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions ---------------------------------------------------------*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Initialization and de-initialization functions ##### |
||||
=============================================================================== |
||||
[..] |
||||
This section provides functions allowing to initialize the DMA Channel source |
||||
and destination addresses, incrementation and data sizes, transfer direction,
|
||||
circular/normal mode selection, memory-to-memory mode selection and Channel priority value. |
||||
[..] |
||||
The HAL_DMA_Init() function follows the DMA configuration procedures as described in |
||||
reference manual.
|
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Initialize the DMA according to the specified |
||||
* parameters in the DMA_InitTypeDef and initialize the associated handle. |
||||
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) |
||||
{ |
||||
uint32_t tmp = 0U; |
||||
|
||||
/* Check the DMA handle allocation */ |
||||
if(hdma == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); |
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); |
||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); |
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
||||
|
||||
#if defined (DMA2) |
||||
/* calculation of the channel index */ |
||||
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
||||
{ |
||||
/* DMA1 */ |
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
||||
hdma->DmaBaseAddress = DMA1; |
||||
} |
||||
else
|
||||
{ |
||||
/* DMA2 */ |
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; |
||||
hdma->DmaBaseAddress = DMA2; |
||||
} |
||||
#else |
||||
/* DMA1 */ |
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
||||
hdma->DmaBaseAddress = DMA1; |
||||
#endif /* DMA2 */ |
||||
|
||||
/* Change DMA peripheral state */ |
||||
hdma->State = HAL_DMA_STATE_BUSY; |
||||
|
||||
/* Get the CR register value */ |
||||
tmp = hdma->Instance->CCR; |
||||
|
||||
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ |
||||
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
||||
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
|
||||
DMA_CCR_DIR)); |
||||
|
||||
/* Prepare the DMA Channel configuration */ |
||||
tmp |= hdma->Init.Direction | |
||||
hdma->Init.PeriphInc | hdma->Init.MemInc | |
||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | |
||||
hdma->Init.Mode | hdma->Init.Priority; |
||||
|
||||
/* Write to DMA Channel CR register */ |
||||
hdma->Instance->CCR = tmp; |
||||
|
||||
/* Initialise the error code */ |
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
||||
|
||||
/* Initialize the DMA state*/ |
||||
hdma->State = HAL_DMA_STATE_READY; |
||||
/* Allocate lock resource and initialize it */ |
||||
hdma->Lock = HAL_UNLOCKED; |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief DeInitialize the DMA peripheral. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) |
||||
{ |
||||
/* Check the DMA handle allocation */ |
||||
if(hdma == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
||||
|
||||
/* Disable the selected DMA Channelx */ |
||||
__HAL_DMA_DISABLE(hdma); |
||||
|
||||
/* Reset DMA Channel control register */ |
||||
hdma->Instance->CCR = 0U; |
||||
|
||||
/* Reset DMA Channel Number of Data to Transfer register */ |
||||
hdma->Instance->CNDTR = 0U; |
||||
|
||||
/* Reset DMA Channel peripheral address register */ |
||||
hdma->Instance->CPAR = 0U; |
||||
|
||||
/* Reset DMA Channel memory address register */ |
||||
hdma->Instance->CMAR = 0U; |
||||
|
||||
#if defined (DMA2) |
||||
/* calculation of the channel index */ |
||||
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
||||
{ |
||||
/* DMA1 */ |
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
||||
hdma->DmaBaseAddress = DMA1; |
||||
} |
||||
else |
||||
{ |
||||
/* DMA2 */ |
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; |
||||
hdma->DmaBaseAddress = DMA2; |
||||
} |
||||
#else |
||||
/* DMA1 */ |
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
||||
hdma->DmaBaseAddress = DMA1; |
||||
#endif /* DMA2 */ |
||||
|
||||
/* Clear all flags */ |
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); |
||||
|
||||
/* Clean all callbacks */ |
||||
hdma->XferCpltCallback = NULL; |
||||
hdma->XferHalfCpltCallback = NULL; |
||||
hdma->XferErrorCallback = NULL; |
||||
hdma->XferAbortCallback = NULL; |
||||
|
||||
/* Reset the error code */ |
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
||||
|
||||
/* Reset the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_RESET; |
||||
|
||||
/* Release Lock */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief Input and Output operation functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### IO operation functions ##### |
||||
=============================================================================== |
||||
[..] This section provides functions allowing to: |
||||
(+) Configure the source, destination address and data length and Start DMA transfer |
||||
(+) Configure the source, destination address and data length and |
||||
Start DMA transfer with interrupt |
||||
(+) Abort DMA transfer |
||||
(+) Poll for transfer complete |
||||
(+) Handle DMA interrupt request |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @param SrcAddress: The source memory Buffer address |
||||
* @param DstAddress: The destination memory Buffer address |
||||
* @param DataLength: The length of data to be transferred from source to destination |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
||||
|
||||
/* Process locked */ |
||||
__HAL_LOCK(hdma); |
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State) |
||||
{ |
||||
/* Change DMA peripheral state */ |
||||
hdma->State = HAL_DMA_STATE_BUSY; |
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
||||
|
||||
/* Disable the peripheral */ |
||||
__HAL_DMA_DISABLE(hdma); |
||||
|
||||
/* Configure the source, destination address and the data length & clear flags*/ |
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
||||
|
||||
/* Enable the Peripheral */ |
||||
__HAL_DMA_ENABLE(hdma); |
||||
} |
||||
else |
||||
{ |
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma);
|
||||
status = HAL_BUSY; |
||||
}
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer with interrupt enabled. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @param SrcAddress: The source memory Buffer address |
||||
* @param DstAddress: The destination memory Buffer address |
||||
* @param DataLength: The length of data to be transferred from source to destination |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
||||
|
||||
/* Process locked */ |
||||
__HAL_LOCK(hdma); |
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State) |
||||
{ |
||||
/* Change DMA peripheral state */ |
||||
hdma->State = HAL_DMA_STATE_BUSY; |
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
||||
|
||||
/* Disable the peripheral */ |
||||
__HAL_DMA_DISABLE(hdma); |
||||
|
||||
/* Configure the source, destination address and the data length & clear flags*/ |
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
||||
|
||||
/* Enable the transfer complete interrupt */ |
||||
/* Enable the transfer Error interrupt */ |
||||
if(NULL != hdma->XferHalfCpltCallback) |
||||
{ |
||||
/* Enable the Half transfer complete interrupt as well */ |
||||
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
||||
} |
||||
else |
||||
{ |
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
||||
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); |
||||
} |
||||
/* Enable the Peripheral */ |
||||
__HAL_DMA_ENABLE(hdma); |
||||
} |
||||
else |
||||
{
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Remain BUSY */ |
||||
status = HAL_BUSY; |
||||
}
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Abort the DMA Transfer. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
if(hdma->State != HAL_DMA_STATE_BUSY) |
||||
{ |
||||
/* no transfer ongoing */ |
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
return HAL_ERROR; |
||||
} |
||||
else |
||||
|
||||
{ |
||||
/* Disable DMA IT */ |
||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
||||
|
||||
/* Disable the channel */ |
||||
__HAL_DMA_DISABLE(hdma); |
||||
|
||||
/* Clear all flags */ |
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||||
} |
||||
/* Change the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Aborts the DMA Transfer in Interrupt mode. |
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) |
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State) |
||||
{ |
||||
/* no transfer ongoing */ |
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
||||
|
||||
status = HAL_ERROR; |
||||
} |
||||
else |
||||
{
|
||||
/* Disable DMA IT */ |
||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
||||
|
||||
/* Disable the channel */ |
||||
__HAL_DMA_DISABLE(hdma); |
||||
|
||||
/* Clear all flags */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); |
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
/* Call User Abort callback */ |
||||
if(hdma->XferAbortCallback != NULL) |
||||
{ |
||||
hdma->XferAbortCallback(hdma); |
||||
}
|
||||
} |
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Polling for transfer complete. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @param CompleteLevel: Specifies the DMA level complete. |
||||
* @param Timeout: Timeout duration. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) |
||||
{ |
||||
uint32_t temp; |
||||
uint32_t tickstart = 0U; |
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State) |
||||
{ |
||||
/* no transfer ongoing */ |
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
||||
__HAL_UNLOCK(hdma); |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Polling mode not supported in circular mode */ |
||||
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) |
||||
{ |
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Get the level transfer complete flag */ |
||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
||||
{ |
||||
/* Transfer Complete flag */ |
||||
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); |
||||
} |
||||
else |
||||
{ |
||||
/* Half Transfer Complete flag */ |
||||
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); |
||||
} |
||||
|
||||
/* Get tick */ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) |
||||
{ |
||||
if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) |
||||
{ |
||||
/* When a DMA transfer error occurs */ |
||||
/* A hardware clear of its EN bits is performed */ |
||||
/* Clear all flags */ |
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||||
|
||||
/* Update error code */ |
||||
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); |
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State= HAL_DMA_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
return HAL_ERROR; |
||||
} |
||||
/* Check for the Timeout */ |
||||
if(Timeout != HAL_MAX_DELAY) |
||||
{ |
||||
if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) |
||||
{ |
||||
/* Update error code */ |
||||
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); |
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
return HAL_ERROR; |
||||
} |
||||
} |
||||
} |
||||
|
||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
||||
{ |
||||
/* Clear the transfer complete flag */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
||||
|
||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||||
all transfers are complete) */ |
||||
hdma->State = HAL_DMA_STATE_READY; |
||||
} |
||||
else |
||||
{ |
||||
/* Clear the half transfer complete flag */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
||||
} |
||||
|
||||
/* Process unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Handles DMA interrupt request. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) |
||||
{ |
||||
uint32_t flag_it = hdma->DmaBaseAddress->ISR; |
||||
uint32_t source_it = hdma->Instance->CCR; |
||||
|
||||
/* Half Transfer Complete Interrupt management ******************************/ |
||||
if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) |
||||
{ |
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ |
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
||||
{ |
||||
/* Disable the half transfer interrupt */ |
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
||||
} |
||||
/* Clear the half transfer complete flag */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
||||
|
||||
/* DMA peripheral state is not updated in Half Transfer */ |
||||
/* but in Transfer Complete case */ |
||||
|
||||
if(hdma->XferHalfCpltCallback != NULL) |
||||
{ |
||||
/* Half transfer callback */ |
||||
hdma->XferHalfCpltCallback(hdma); |
||||
} |
||||
} |
||||
|
||||
/* Transfer Complete Interrupt management ***********************************/ |
||||
else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) |
||||
{ |
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
||||
{ |
||||
/* Disable the transfer complete and error interrupt */ |
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
|
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_READY; |
||||
} |
||||
/* Clear the transfer complete flag */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
if(hdma->XferCpltCallback != NULL) |
||||
{ |
||||
/* Transfer complete callback */ |
||||
hdma->XferCpltCallback(hdma); |
||||
} |
||||
} |
||||
|
||||
/* Transfer Error Interrupt management **************************************/ |
||||
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) |
||||
{ |
||||
/* When a DMA transfer error occurs */ |
||||
/* A hardware clear of its EN bits is performed */ |
||||
/* Disable ALL DMA IT */ |
||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
||||
|
||||
/* Clear all flags */ |
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||||
|
||||
/* Update error code */ |
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE; |
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
if (hdma->XferErrorCallback != NULL) |
||||
{ |
||||
/* Transfer error callback */ |
||||
hdma->XferErrorCallback(hdma); |
||||
} |
||||
} |
||||
return; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Register callbacks |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @param CallbackID: User Callback identifer |
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
||||
* @param pCallback: pointer to private callbacsk function which has pointer to
|
||||
* a DMA_HandleTypeDef structure as parameter. |
||||
* @retval HAL status |
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
/* Process locked */ |
||||
__HAL_LOCK(hdma); |
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State) |
||||
{ |
||||
switch (CallbackID) |
||||
{ |
||||
case HAL_DMA_XFER_CPLT_CB_ID: |
||||
hdma->XferCpltCallback = pCallback; |
||||
break; |
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID: |
||||
hdma->XferHalfCpltCallback = pCallback; |
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID: |
||||
hdma->XferErrorCallback = pCallback; |
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID: |
||||
hdma->XferAbortCallback = pCallback; |
||||
break;
|
||||
|
||||
default: |
||||
status = HAL_ERROR; |
||||
break;
|
||||
} |
||||
} |
||||
else |
||||
{ |
||||
status = HAL_ERROR; |
||||
}
|
||||
|
||||
/* Release Lock */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief UnRegister callbacks |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @param CallbackID: User Callback identifer |
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. |
||||
* @retval HAL status |
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
/* Process locked */ |
||||
__HAL_LOCK(hdma); |
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State) |
||||
{ |
||||
switch (CallbackID) |
||||
{ |
||||
case HAL_DMA_XFER_CPLT_CB_ID: |
||||
hdma->XferCpltCallback = NULL; |
||||
break; |
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID: |
||||
hdma->XferHalfCpltCallback = NULL; |
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID: |
||||
hdma->XferErrorCallback = NULL; |
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID: |
||||
hdma->XferAbortCallback = NULL; |
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ALL_CB_ID: |
||||
hdma->XferCpltCallback = NULL; |
||||
hdma->XferHalfCpltCallback = NULL; |
||||
hdma->XferErrorCallback = NULL; |
||||
hdma->XferAbortCallback = NULL; |
||||
break;
|
||||
|
||||
default: |
||||
status = HAL_ERROR; |
||||
break; |
||||
} |
||||
} |
||||
else |
||||
{ |
||||
status = HAL_ERROR; |
||||
}
|
||||
|
||||
/* Release Lock */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral State and Errors functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Peripheral State and Errors functions ##### |
||||
===============================================================================
|
||||
[..] |
||||
This subsection provides functions allowing to |
||||
(+) Check the DMA state |
||||
(+) Get error code |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Return the DMA hande state. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @retval HAL state |
||||
*/ |
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) |
||||
{ |
||||
/* Return DMA handle state */ |
||||
return hdma->State; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the DMA error code. |
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @retval DMA Error Code |
||||
*/ |
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) |
||||
{ |
||||
return hdma->ErrorCode; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup DMA_Private_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Sets the DMA Transfer parameter. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @param SrcAddress: The source memory Buffer address |
||||
* @param DstAddress: The destination memory Buffer address |
||||
* @param DataLength: The length of data to be transferred from source to destination |
||||
* @retval HAL status |
||||
*/ |
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
||||
{ |
||||
/* Clear all flags */ |
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
||||
|
||||
/* Configure DMA Channel data length */ |
||||
hdma->Instance->CNDTR = DataLength; |
||||
|
||||
/* Memory to Peripheral */ |
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) |
||||
{ |
||||
/* Configure DMA Channel destination address */ |
||||
hdma->Instance->CPAR = DstAddress; |
||||
|
||||
/* Configure DMA Channel source address */ |
||||
hdma->Instance->CMAR = SrcAddress; |
||||
} |
||||
/* Peripheral to Memory */ |
||||
else |
||||
{ |
||||
/* Configure DMA Channel source address */ |
||||
hdma->Instance->CPAR = SrcAddress; |
||||
|
||||
/* Configure DMA Channel destination address */ |
||||
hdma->Instance->CMAR = DstAddress; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,555 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_exti.c |
||||
* @author MCD Application Team |
||||
* @brief EXTI HAL module driver. |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral: |
||||
* + Initialization and de-initialization functions |
||||
* + IO operation functions |
||||
* |
||||
@verbatim |
||||
============================================================================== |
||||
##### EXTI Peripheral features ##### |
||||
============================================================================== |
||||
[..] |
||||
(+) Each Exti line can be configured within this driver. |
||||
|
||||
(+) Exti line can be configured in 3 different modes |
||||
(++) Interrupt |
||||
(++) Event |
||||
(++) Both of them |
||||
|
||||
(+) Configurable Exti lines can be configured with 3 different triggers |
||||
(++) Rising |
||||
(++) Falling |
||||
(++) Both of them |
||||
|
||||
(+) When set in interrupt mode, configurable Exti lines have two different |
||||
interrupts pending registers which allow to distinguish which transition |
||||
occurs: |
||||
(++) Rising edge pending interrupt |
||||
(++) Falling |
||||
|
||||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can |
||||
be selected through multiplexer. |
||||
|
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..] |
||||
|
||||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). |
||||
(++) Choose the interrupt line number by setting "Line" member from |
||||
EXTI_ConfigTypeDef structure. |
||||
(++) Configure the interrupt and/or event mode using "Mode" member from |
||||
EXTI_ConfigTypeDef structure. |
||||
(++) For configurable lines, configure rising and/or falling trigger |
||||
"Trigger" member from EXTI_ConfigTypeDef structure. |
||||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" |
||||
member from GPIO_InitTypeDef structure. |
||||
|
||||
(#) Get current Exti configuration of a dedicated line using |
||||
HAL_EXTI_GetConfigLine(). |
||||
(++) Provide exiting handle as parameter. |
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. |
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). |
||||
(++) Provide exiting handle as parameter. |
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). |
||||
(++) Provide exiting handle as first parameter. |
||||
(++) Provide which callback will be registered using one value from |
||||
EXTI_CallbackIDTypeDef. |
||||
(++) Provide callback function pointer. |
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending(). |
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending(). |
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI(). |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{ |
||||
*/ |
||||
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out |
||||
* of bounds [0,3] in following API : |
||||
* HAL_EXTI_SetConfigLine |
||||
* HAL_EXTI_GetConfigLine |
||||
* HAL_EXTI_ClearConfigLine |
||||
*/ |
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private defines -----------------------------------------------------------*/ |
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup EXTI_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||
* @brief Configuration functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Configuration functions ##### |
||||
=============================================================================== |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Set configuration of a dedicated Exti line. |
||||
* @param hexti Exti handle. |
||||
* @param pExtiConfig Pointer on EXTI configuration to be set. |
||||
* @retval HAL Status. |
||||
*/ |
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) |
||||
{ |
||||
uint32_t regval; |
||||
uint32_t linepos; |
||||
uint32_t maskline; |
||||
|
||||
/* Check null pointer */ |
||||
if ((hexti == NULL) || (pExtiConfig == NULL)) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check parameters */ |
||||
assert_param(IS_EXTI_LINE(pExtiConfig->Line)); |
||||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); |
||||
|
||||
/* Assign line number to handle */ |
||||
hexti->Line = pExtiConfig->Line; |
||||
|
||||
/* Compute line mask */ |
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK); |
||||
maskline = (1uL << linepos); |
||||
|
||||
/* Configure triggers for configurable lines */ |
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) |
||||
{ |
||||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); |
||||
|
||||
/* Configure rising trigger */ |
||||
/* Mask or set line */ |
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) |
||||
{ |
||||
EXTI->RTSR |= maskline; |
||||
} |
||||
else |
||||
{ |
||||
EXTI->RTSR &= ~maskline; |
||||
} |
||||
|
||||
/* Configure falling trigger */ |
||||
/* Mask or set line */ |
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) |
||||
{ |
||||
EXTI->FTSR |= maskline; |
||||
} |
||||
else |
||||
{ |
||||
EXTI->FTSR &= ~maskline; |
||||
} |
||||
|
||||
|
||||
/* Configure gpio port selection in case of gpio exti line */ |
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) |
||||
{ |
||||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); |
||||
assert_param(IS_EXTI_GPIO_PIN(linepos)); |
||||
|
||||
regval = AFIO->EXTICR[linepos >> 2u]; |
||||
regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); |
||||
regval |= (pExtiConfig->GPIOSel << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); |
||||
AFIO->EXTICR[linepos >> 2u] = regval; |
||||
} |
||||
} |
||||
|
||||
/* Configure interrupt mode : read current mode */ |
||||
/* Mask or set line */ |
||||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) |
||||
{ |
||||
EXTI->IMR |= maskline; |
||||
} |
||||
else |
||||
{ |
||||
EXTI->IMR &= ~maskline; |
||||
} |
||||
|
||||
/* Configure event mode : read current mode */ |
||||
/* Mask or set line */ |
||||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) |
||||
{ |
||||
EXTI->EMR |= maskline; |
||||
} |
||||
else |
||||
{ |
||||
EXTI->EMR &= ~maskline; |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Get configuration of a dedicated Exti line. |
||||
* @param hexti Exti handle. |
||||
* @param pExtiConfig Pointer on structure to store Exti configuration. |
||||
* @retval HAL Status. |
||||
*/ |
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) |
||||
{ |
||||
uint32_t regval; |
||||
uint32_t linepos; |
||||
uint32_t maskline; |
||||
|
||||
/* Check null pointer */ |
||||
if ((hexti == NULL) || (pExtiConfig == NULL)) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the parameter */ |
||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
||||
|
||||
/* Store handle line number to configuration structure */ |
||||
pExtiConfig->Line = hexti->Line; |
||||
|
||||
/* Compute line mask */ |
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK); |
||||
maskline = (1uL << linepos); |
||||
|
||||
/* 1] Get core mode : interrupt */ |
||||
|
||||
/* Check if selected line is enable */ |
||||
if ((EXTI->IMR & maskline) != 0x00u) |
||||
{ |
||||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT; |
||||
} |
||||
else |
||||
{ |
||||
pExtiConfig->Mode = EXTI_MODE_NONE; |
||||
} |
||||
|
||||
/* Get event mode */ |
||||
/* Check if selected line is enable */ |
||||
if ((EXTI->EMR & maskline) != 0x00u) |
||||
{ |
||||
pExtiConfig->Mode |= EXTI_MODE_EVENT; |
||||
} |
||||
|
||||
/* Get default Trigger and GPIOSel configuration */ |
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE; |
||||
pExtiConfig->GPIOSel = 0x00u; |
||||
|
||||
/* 2] Get trigger for configurable lines : rising */ |
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) |
||||
{ |
||||
/* Check if configuration of selected line is enable */ |
||||
if ((EXTI->RTSR & maskline) != 0x00u) |
||||
{ |
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING; |
||||
} |
||||
|
||||
/* Get falling configuration */ |
||||
/* Check if configuration of selected line is enable */ |
||||
if ((EXTI->FTSR & maskline) != 0x00u) |
||||
{ |
||||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; |
||||
} |
||||
|
||||
/* Get Gpio port selection for gpio lines */ |
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) |
||||
{ |
||||
assert_param(IS_EXTI_GPIO_PIN(linepos)); |
||||
|
||||
regval = AFIO->EXTICR[linepos >> 2u]; |
||||
pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); |
||||
} |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Clear whole configuration of a dedicated Exti line. |
||||
* @param hexti Exti handle. |
||||
* @retval HAL Status. |
||||
*/ |
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) |
||||
{ |
||||
uint32_t regval; |
||||
uint32_t linepos; |
||||
uint32_t maskline; |
||||
|
||||
/* Check null pointer */ |
||||
if (hexti == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the parameter */ |
||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
||||
|
||||
/* compute line mask */ |
||||
linepos = (hexti->Line & EXTI_PIN_MASK); |
||||
maskline = (1uL << linepos); |
||||
|
||||
/* 1] Clear interrupt mode */ |
||||
EXTI->IMR = (EXTI->IMR & ~maskline); |
||||
|
||||
/* 2] Clear event mode */ |
||||
EXTI->EMR = (EXTI->EMR & ~maskline); |
||||
|
||||
/* 3] Clear triggers in case of configurable lines */ |
||||
if ((hexti->Line & EXTI_CONFIG) != 0x00u) |
||||
{ |
||||
EXTI->RTSR = (EXTI->RTSR & ~maskline); |
||||
EXTI->FTSR = (EXTI->FTSR & ~maskline); |
||||
|
||||
/* Get Gpio port selection for gpio lines */ |
||||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) |
||||
{ |
||||
assert_param(IS_EXTI_GPIO_PIN(linepos)); |
||||
|
||||
regval = AFIO->EXTICR[linepos >> 2u]; |
||||
regval &= ~(AFIO_EXTICR1_EXTI0 << (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); |
||||
AFIO->EXTICR[linepos >> 2u] = regval; |
||||
} |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Register callback for a dedicated Exti line. |
||||
* @param hexti Exti handle. |
||||
* @param CallbackID User callback identifier. |
||||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. |
||||
* @param pPendingCbfn function pointer to be stored as callback. |
||||
* @retval HAL Status. |
||||
*/ |
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
switch (CallbackID) |
||||
{ |
||||
case HAL_EXTI_COMMON_CB_ID: |
||||
hexti->PendingCallback = pPendingCbfn; |
||||
break; |
||||
|
||||
default: |
||||
status = HAL_ERROR; |
||||
break; |
||||
} |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Store line number as handle private field. |
||||
* @param hexti Exti handle. |
||||
* @param ExtiLine Exti line number. |
||||
* This parameter can be from 0 to @ref EXTI_LINE_NB. |
||||
* @retval HAL Status. |
||||
*/ |
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_EXTI_LINE(ExtiLine)); |
||||
|
||||
/* Check null pointer */ |
||||
if (hexti == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
else |
||||
{ |
||||
/* Store line number as handle private field */ |
||||
hexti->Line = ExtiLine; |
||||
|
||||
return HAL_OK; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||
* @brief EXTI IO functions. |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### IO operation functions ##### |
||||
=============================================================================== |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request. |
||||
* @param hexti Exti handle. |
||||
* @retval none. |
||||
*/ |
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) |
||||
{ |
||||
uint32_t regval; |
||||
uint32_t maskline; |
||||
|
||||
/* Compute line mask */ |
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); |
||||
|
||||
/* Get pending bit */ |
||||
regval = (EXTI->PR & maskline); |
||||
if (regval != 0x00u) |
||||
{ |
||||
/* Clear pending bit */ |
||||
EXTI->PR = maskline; |
||||
|
||||
/* Call callback */ |
||||
if (hexti->PendingCallback != NULL) |
||||
{ |
||||
hexti->PendingCallback(); |
||||
} |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Get interrupt pending bit of a dedicated line. |
||||
* @param hexti Exti handle. |
||||
* @param Edge Specify which pending edge as to be checked. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING |
||||
* This parameter is kept for compatibility with other series. |
||||
* @retval 1 if interrupt is pending else 0. |
||||
*/ |
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) |
||||
{ |
||||
uint32_t regval; |
||||
uint32_t maskline; |
||||
uint32_t linepos; |
||||
|
||||
/* Check parameters */ |
||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); |
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge)); |
||||
|
||||
/* Prevent unused argument compilation warning */ |
||||
UNUSED(Edge); |
||||
|
||||
/* Compute line mask */ |
||||
linepos = (hexti->Line & EXTI_PIN_MASK); |
||||
maskline = (1uL << linepos); |
||||
|
||||
/* return 1 if bit is set else 0 */ |
||||
regval = ((EXTI->PR & maskline) >> linepos); |
||||
return regval; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Clear interrupt pending bit of a dedicated line. |
||||
* @param hexti Exti handle. |
||||
* @param Edge Specify which pending edge as to be clear. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING |
||||
* This parameter is kept for compatibility with other series. |
||||
* @retval None. |
||||
*/ |
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) |
||||
{ |
||||
uint32_t maskline; |
||||
|
||||
/* Check parameters */ |
||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); |
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge)); |
||||
|
||||
/* Prevent unused argument compilation warning */ |
||||
UNUSED(Edge); |
||||
|
||||
/* Compute line mask */ |
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); |
||||
|
||||
/* Clear Pending bit */ |
||||
EXTI->PR = maskline; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt for a dedicated line. |
||||
* @param hexti Exti handle. |
||||
* @retval None. |
||||
*/ |
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) |
||||
{ |
||||
uint32_t maskline; |
||||
|
||||
/* Check parameters */ |
||||
assert_param(IS_EXTI_LINE(hexti->Line)); |
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); |
||||
|
||||
/* Compute line mask */ |
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); |
||||
|
||||
/* Generate Software interrupt */ |
||||
EXTI->SWIER = maskline; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,967 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_flash.c |
||||
* @author MCD Application Team |
||||
* @brief FLASH HAL module driver. |
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory: |
||||
* + Program operations functions |
||||
* + Memory Control functions
|
||||
* + Peripheral State functions |
||||
*
|
||||
@verbatim |
||||
============================================================================== |
||||
##### FLASH peripheral features ##### |
||||
============================================================================== |
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms. |
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction |
||||
prefetch.
|
||||
|
||||
[..] The FLASH main features are: |
||||
(+) Flash memory read operations |
||||
(+) Flash memory program/erase operations |
||||
(+) Read / write protections |
||||
(+) Prefetch on I-Code |
||||
(+) Option Bytes programming |
||||
|
||||
|
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32F1xx devices. |
||||
|
||||
(#) FLASH Memory I/O Programming functions: this group includes all needed |
||||
functions to erase and program the main memory: |
||||
(++) Lock and Unlock the FLASH interface |
||||
(++) Erase function: Erase page, erase all pages |
||||
(++) Program functions: half word, word and doubleword |
||||
(#) FLASH Option Bytes Programming functions: this group includes all needed |
||||
functions to manage the Option Bytes: |
||||
(++) Lock and Unlock the Option Bytes |
||||
(++) Set/Reset the write protection |
||||
(++) Set the Read protection Level |
||||
(++) Program the user Option Bytes |
||||
(++) Launch the Option Bytes loader |
||||
(++) Erase Option Bytes |
||||
(++) Program the data Option Bytes |
||||
(++) Get the Write protection. |
||||
(++) Get the user option bytes. |
||||
|
||||
(#) Interrupts and flags management functions : this group
|
||||
includes all needed functions to: |
||||
(++) Handle FLASH interrupts |
||||
(++) Wait for last FLASH operation according to its status |
||||
(++) Get error flag status |
||||
|
||||
[..] In addition to these function, this driver includes a set of macros allowing |
||||
to handle the following operations: |
||||
|
||||
(+) Set/Get the latency |
||||
(+) Enable/Disable the prefetch buffer |
||||
(+) Enable/Disable the half cycle access |
||||
(+) Enable/Disable the FLASH interrupts |
||||
(+) Monitor the FLASH flags status |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED |
||||
|
||||
/** @defgroup FLASH FLASH
|
||||
* @brief FLASH HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macro ---------------------------- ---------------------------------*/ |
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{ |
||||
*/ |
||||
/* Variables used for Erase pages under interruption*/ |
||||
FLASH_ProcessTypeDef pFlash; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{ |
||||
*/ |
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); |
||||
static void FLASH_SetErrorCode(void); |
||||
extern void FLASH_PageErase(uint32_t PageAddress); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions ---------------------------------------------------------*/ |
||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
* |
||||
@verbatim
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address |
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface |
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface |
||||
* |
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one. |
||||
*
|
||||
* @note FLASH should be previously erased before new programmation (only exception to this
|
||||
* is when 0x0000 is programmed) |
||||
* |
||||
* @param TypeProgram: Indicate the way to program at a specified address. |
||||
* This parameter can be a value of @ref FLASH_Type_Program |
||||
* @param Address: Specifies the address to be programmed. |
||||
* @param Data: Specifies the data to be programmed |
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_ERROR; |
||||
uint8_t index = 0; |
||||
uint8_t nbiterations = 0; |
||||
|
||||
/* Process Locked */ |
||||
__HAL_LOCK(&pFlash); |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); |
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
if(Address <= FLASH_BANK1_END) |
||||
{ |
||||
#endif /* FLASH_BANK2_END */ |
||||
/* Wait for last operation to be completed */ |
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
#if defined(FLASH_BANK2_END) |
||||
} |
||||
else |
||||
{ |
||||
/* Wait for last operation to be completed */ |
||||
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); |
||||
} |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
if(status == HAL_OK) |
||||
{ |
||||
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) |
||||
{ |
||||
/* Program halfword (16-bit) at a specified address. */ |
||||
nbiterations = 1U; |
||||
} |
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) |
||||
{ |
||||
/* Program word (32-bit = 2*16-bit) at a specified address. */ |
||||
nbiterations = 2U; |
||||
} |
||||
else |
||||
{ |
||||
/* Program double word (64-bit = 4*16-bit) at a specified address. */ |
||||
nbiterations = 4U; |
||||
} |
||||
|
||||
for (index = 0U; index < nbiterations; index++) |
||||
{ |
||||
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
if(Address <= FLASH_BANK1_END) |
||||
{ |
||||
#endif /* FLASH_BANK2_END */ |
||||
/* Wait for last operation to be completed */ |
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
|
||||
/* If the program operation is completed, disable the PG Bit */ |
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG); |
||||
#if defined(FLASH_BANK2_END) |
||||
} |
||||
else |
||||
{ |
||||
/* Wait for last operation to be completed */ |
||||
status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); |
||||
|
||||
/* If the program operation is completed, disable the PG Bit */ |
||||
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); |
||||
} |
||||
#endif /* FLASH_BANK2_END */ |
||||
/* In case of error, stop programation procedure */ |
||||
if (status != HAL_OK) |
||||
{ |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(&pFlash); |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address with interrupt enabled. |
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface |
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface |
||||
* |
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one. |
||||
* |
||||
* @param TypeProgram: Indicate the way to program at a specified address. |
||||
* This parameter can be a value of @ref FLASH_Type_Program |
||||
* @param Address: Specifies the address to be programmed. |
||||
* @param Data: Specifies the data to be programmed |
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
/* Process Locked */ |
||||
__HAL_LOCK(&pFlash); |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); |
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
/* If procedure already ongoing, reject the next one */ |
||||
if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
if(Address <= FLASH_BANK1_END) |
||||
{ |
||||
/* Enable End of FLASH Operation and Error source interrupts */ |
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1); |
||||
|
||||
}else |
||||
{ |
||||
/* Enable End of FLASH Operation and Error source interrupts */ |
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); |
||||
} |
||||
#else |
||||
/* Enable End of FLASH Operation and Error source interrupts */ |
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
pFlash.Address = Address; |
||||
pFlash.Data = Data; |
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) |
||||
{ |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; |
||||
/* Program halfword (16-bit) at a specified address. */ |
||||
pFlash.DataRemaining = 1U; |
||||
} |
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) |
||||
{ |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; |
||||
/* Program word (32-bit : 2*16-bit) at a specified address. */ |
||||
pFlash.DataRemaining = 2U; |
||||
} |
||||
else |
||||
{ |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; |
||||
/* Program double word (64-bit : 4*16-bit) at a specified address. */ |
||||
pFlash.DataRemaining = 4U; |
||||
} |
||||
|
||||
/* Program halfword (16-bit) at a specified address. */ |
||||
FLASH_Program_HalfWord(Address, (uint16_t)Data); |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request. |
||||
* @retval None |
||||
*/ |
||||
void HAL_FLASH_IRQHandler(void) |
||||
{ |
||||
uint32_t addresstmp = 0U; |
||||
|
||||
/* Check FLASH operation error flags */ |
||||
#if defined(FLASH_BANK2_END) |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \
|
||||
(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))) |
||||
#else |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) |
||||
#endif /* FLASH_BANK2_END */ |
||||
{ |
||||
/* Return the faulty address */ |
||||
addresstmp = pFlash.Address; |
||||
/* Reset address */ |
||||
pFlash.Address = 0xFFFFFFFFU; |
||||
|
||||
/* Save the Error code */ |
||||
FLASH_SetErrorCode(); |
||||
|
||||
/* FLASH error interrupt user callback */ |
||||
HAL_FLASH_OperationErrorCallback(addresstmp); |
||||
|
||||
/* Stop the procedure ongoing */ |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
||||
} |
||||
|
||||
/* Check FLASH End of Operation flag */ |
||||
#if defined(FLASH_BANK2_END) |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1)) |
||||
{ |
||||
/* Clear FLASH End of Operation pending bit */ |
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1); |
||||
#else |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) |
||||
{ |
||||
/* Clear FLASH End of Operation pending bit */ |
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
/* Process can continue only if no error detected */ |
||||
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) |
||||
{ |
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) |
||||
{ |
||||
/* Nb of pages to erased can be decreased */ |
||||
pFlash.DataRemaining--; |
||||
|
||||
/* Check if there are still pages to erase */ |
||||
if(pFlash.DataRemaining != 0U) |
||||
{ |
||||
addresstmp = pFlash.Address; |
||||
/*Indicate user which sector has been erased */ |
||||
HAL_FLASH_EndOfOperationCallback(addresstmp); |
||||
|
||||
/*Increment sector number*/ |
||||
addresstmp = pFlash.Address + FLASH_PAGE_SIZE; |
||||
pFlash.Address = addresstmp; |
||||
|
||||
/* If the erase operation is completed, disable the PER Bit */ |
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PER); |
||||
|
||||
FLASH_PageErase(addresstmp); |
||||
} |
||||
else |
||||
{ |
||||
/* No more pages to Erase, user callback can be called. */ |
||||
/* Reset Sector and stop Erase pages procedure */ |
||||
pFlash.Address = addresstmp = 0xFFFFFFFFU; |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
||||
/* FLASH EOP interrupt user callback */ |
||||
HAL_FLASH_EndOfOperationCallback(addresstmp); |
||||
} |
||||
} |
||||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) |
||||
{ |
||||
/* Operation is completed, disable the MER Bit */ |
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_MER); |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
/* Stop Mass Erase procedure if no pending mass erase on other bank */ |
||||
if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) |
||||
{ |
||||
#endif /* FLASH_BANK2_END */ |
||||
/* MassErase ended. Return the selected bank */ |
||||
/* FLASH EOP interrupt user callback */ |
||||
HAL_FLASH_EndOfOperationCallback(0U); |
||||
|
||||
/* Stop Mass Erase procedure*/ |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
||||
} |
||||
#if defined(FLASH_BANK2_END) |
||||
} |
||||
#endif /* FLASH_BANK2_END */ |
||||
else |
||||
{ |
||||
/* Nb of 16-bit data to program can be decreased */ |
||||
pFlash.DataRemaining--; |
||||
|
||||
/* Check if there are still 16-bit data to program */ |
||||
if(pFlash.DataRemaining != 0U) |
||||
{ |
||||
/* Increment address to 16-bit */ |
||||
pFlash.Address += 2U; |
||||
addresstmp = pFlash.Address; |
||||
|
||||
/* Shift to have next 16-bit data */ |
||||
pFlash.Data = (pFlash.Data >> 16U); |
||||
|
||||
/* Operation is completed, disable the PG Bit */ |
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG); |
||||
|
||||
/*Program halfword (16-bit) at a specified address.*/ |
||||
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); |
||||
} |
||||
else |
||||
{ |
||||
/* Program ended. Return the selected address */ |
||||
/* FLASH EOP interrupt user callback */ |
||||
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) |
||||
{ |
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address); |
||||
} |
||||
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) |
||||
{ |
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); |
||||
} |
||||
else
|
||||
{ |
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); |
||||
} |
||||
|
||||
/* Reset Address and stop Program procedure */ |
||||
pFlash.Address = 0xFFFFFFFFU; |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
/* Check FLASH End of Operation flag */ |
||||
if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2)) |
||||
{ |
||||
/* Clear FLASH End of Operation pending bit */ |
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); |
||||
|
||||
/* Process can continue only if no error detected */ |
||||
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) |
||||
{ |
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) |
||||
{ |
||||
/* Nb of pages to erased can be decreased */ |
||||
pFlash.DataRemaining--; |
||||
|
||||
/* Check if there are still pages to erase*/ |
||||
if(pFlash.DataRemaining != 0U) |
||||
{ |
||||
/* Indicate user which page address has been erased*/ |
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address); |
||||
|
||||
/* Increment page address to next page */ |
||||
pFlash.Address += FLASH_PAGE_SIZE; |
||||
addresstmp = pFlash.Address; |
||||
|
||||
/* Operation is completed, disable the PER Bit */ |
||||
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER); |
||||
|
||||
FLASH_PageErase(addresstmp); |
||||
} |
||||
else |
||||
{ |
||||
/*No more pages to Erase*/ |
||||
|
||||
/*Reset Address and stop Erase pages procedure*/ |
||||
pFlash.Address = 0xFFFFFFFFU; |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
||||
|
||||
/* FLASH EOP interrupt user callback */ |
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address); |
||||
} |
||||
} |
||||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) |
||||
{ |
||||
/* Operation is completed, disable the MER Bit */ |
||||
CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER); |
||||
|
||||
if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER)) |
||||
{ |
||||
/* MassErase ended. Return the selected bank*/ |
||||
/* FLASH EOP interrupt user callback */ |
||||
HAL_FLASH_EndOfOperationCallback(0U); |
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
||||
} |
||||
} |
||||
else |
||||
{ |
||||
/* Nb of 16-bit data to program can be decreased */ |
||||
pFlash.DataRemaining--; |
||||
|
||||
/* Check if there are still 16-bit data to program */ |
||||
if(pFlash.DataRemaining != 0U) |
||||
{ |
||||
/* Increment address to 16-bit */ |
||||
pFlash.Address += 2U; |
||||
addresstmp = pFlash.Address; |
||||
|
||||
/* Shift to have next 16-bit data */ |
||||
pFlash.Data = (pFlash.Data >> 16U); |
||||
|
||||
/* Operation is completed, disable the PG Bit */ |
||||
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); |
||||
|
||||
/*Program halfword (16-bit) at a specified address.*/ |
||||
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); |
||||
} |
||||
else |
||||
{ |
||||
/*Program ended. Return the selected address*/ |
||||
/* FLASH EOP interrupt user callback */ |
||||
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) |
||||
{ |
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address); |
||||
} |
||||
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) |
||||
{ |
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U); |
||||
} |
||||
else
|
||||
{ |
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U); |
||||
} |
||||
|
||||
/* Reset Address and stop Program procedure*/ |
||||
pFlash.Address = 0xFFFFFFFFU; |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) |
||||
{ |
||||
#if defined(FLASH_BANK2_END) |
||||
/* Operation is completed, disable the PG, PER and MER Bits for both bank */ |
||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); |
||||
CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER));
|
||||
|
||||
/* Disable End of FLASH Operation and Error source interrupts for both banks */ |
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2); |
||||
#else |
||||
/* Operation is completed, disable the PG, PER and MER Bits */ |
||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); |
||||
|
||||
/* Disable End of FLASH Operation and Error source interrupts */ |
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(&pFlash); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback |
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure |
||||
* - Mass Erase: No return value expected |
||||
* - Pages Erase: Address of the page which has been erased
|
||||
* (if 0xFFFFFFFF, it means that all the selected pages have been erased) |
||||
* - Program: Address which was selected for data program |
||||
* @retval none |
||||
*/ |
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) |
||||
{ |
||||
/* Prevent unused argument(s) compilation warning */ |
||||
UNUSED(ReturnValue); |
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file |
||||
*/
|
||||
} |
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback |
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure |
||||
* - Mass Erase: No return value expected |
||||
* - Pages Erase: Address of the page which returned an error |
||||
* - Program: Address which was selected for data program |
||||
* @retval none |
||||
*/ |
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) |
||||
{ |
||||
/* Prevent unused argument(s) compilation warning */ |
||||
UNUSED(ReturnValue); |
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file |
||||
*/
|
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions
|
||||
* |
||||
@verbatim
|
||||
=============================================================================== |
||||
##### Peripheral Control functions ##### |
||||
===============================================================================
|
||||
[..] |
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access |
||||
* @retval HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) |
||||
{ |
||||
/* Authorize the FLASH Registers access */ |
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY1); |
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY2); |
||||
|
||||
/* Verify Flash is unlocked */ |
||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) |
||||
{ |
||||
status = HAL_ERROR; |
||||
} |
||||
} |
||||
#if defined(FLASH_BANK2_END) |
||||
if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) |
||||
{ |
||||
/* Authorize the FLASH BANK2 Registers access */ |
||||
WRITE_REG(FLASH->KEYR2, FLASH_KEY1); |
||||
WRITE_REG(FLASH->KEYR2, FLASH_KEY2); |
||||
|
||||
/* Verify Flash BANK2 is unlocked */ |
||||
if(READ_BIT(FLASH->CR2, FLASH_CR2_LOCK) != RESET) |
||||
{ |
||||
status = HAL_ERROR; |
||||
} |
||||
} |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access |
||||
* @retval HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void) |
||||
{ |
||||
/* Set the LOCK Bit to lock the FLASH Registers access */ |
||||
SET_BIT(FLASH->CR, FLASH_CR_LOCK); |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
/* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ |
||||
SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); |
||||
|
||||
#endif /* FLASH_BANK2_END */ |
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access. |
||||
* @retval HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) |
||||
{ |
||||
if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) |
||||
{ |
||||
/* Authorizes the Option Byte register programming */ |
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); |
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); |
||||
} |
||||
else |
||||
{ |
||||
return HAL_ERROR; |
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access. |
||||
* @retval HAL Status
|
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) |
||||
{ |
||||
/* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ |
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); |
||||
|
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading. |
||||
* @note This function will reset automatically the MCU. |
||||
* @retval None |
||||
*/ |
||||
void HAL_FLASH_OB_Launch(void) |
||||
{ |
||||
/* Initiates a system reset request to launch the option byte loading */ |
||||
HAL_NVIC_SystemReset(); |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
|
||||
* @brief Peripheral errors functions
|
||||
* |
||||
@verbatim
|
||||
=============================================================================== |
||||
##### Peripheral Errors functions ##### |
||||
===============================================================================
|
||||
[..] |
||||
This subsection permit to get in run-time errors of the FLASH peripheral. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag. |
||||
* @retval FLASH_ErrorCode The returned value can be: |
||||
* @ref FLASH_Error_Codes |
||||
*/ |
||||
uint32_t HAL_FLASH_GetError(void) |
||||
{ |
||||
return pFlash.ErrorCode; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Program a half-word (16-bit) at a specified address. |
||||
* @param Address specify the address to be programmed. |
||||
* @param Data specify the data to be programmed. |
||||
* @retval None |
||||
*/ |
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) |
||||
{ |
||||
/* Clean the error context */ |
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
if(Address <= FLASH_BANK1_END) |
||||
{ |
||||
#endif /* FLASH_BANK2_END */ |
||||
/* Proceed to program the new data */ |
||||
SET_BIT(FLASH->CR, FLASH_CR_PG); |
||||
#if defined(FLASH_BANK2_END) |
||||
} |
||||
else |
||||
{ |
||||
/* Proceed to program the new data */ |
||||
SET_BIT(FLASH->CR2, FLASH_CR2_PG); |
||||
} |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
/* Write data in the address */ |
||||
*(__IO uint16_t*)Address = Data; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete. |
||||
* @param Timeout maximum flash operation timeout |
||||
* @retval HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) |
||||
{ |
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error |
||||
flag will be set */ |
||||
|
||||
uint32_t tickstart = HAL_GetTick(); |
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY) |
||||
{ |
||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* Check FLASH End of Operation flag */ |
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) |
||||
{ |
||||
/* Clear FLASH End of Operation pending bit */ |
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); |
||||
} |
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) |
||||
{ |
||||
/*Save the error code*/ |
||||
FLASH_SetErrorCode(); |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* There is no error flag set */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
/**
|
||||
* @brief Wait for a FLASH BANK2 operation to complete. |
||||
* @param Timeout maximum flash operation timeout |
||||
* @retval HAL_StatusTypeDef HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) |
||||
{
|
||||
/* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error |
||||
flag will be set */ |
||||
|
||||
uint32_t tickstart = HAL_GetTick(); |
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY) |
||||
{ |
||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* Check FLASH End of Operation flag */ |
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2)) |
||||
{ |
||||
/* Clear FLASH End of Operation pending bit */ |
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2); |
||||
} |
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) |
||||
{ |
||||
/*Save the error code*/ |
||||
FLASH_SetErrorCode(); |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* If there is an error flag set */ |
||||
return HAL_OK; |
||||
|
||||
} |
||||
#endif /* FLASH_BANK2_END */ |
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag. |
||||
* @retval None |
||||
*/ |
||||
static void FLASH_SetErrorCode(void) |
||||
{ |
||||
uint32_t flags = 0U; |
||||
|
||||
#if defined(FLASH_BANK2_END) |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) |
||||
#else |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) |
||||
#endif /* FLASH_BANK2_END */ |
||||
{ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; |
||||
#if defined(FLASH_BANK2_END) |
||||
flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; |
||||
#else |
||||
flags |= FLASH_FLAG_WRPERR; |
||||
#endif /* FLASH_BANK2_END */ |
||||
} |
||||
#if defined(FLASH_BANK2_END) |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) |
||||
#else |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) |
||||
#endif /* FLASH_BANK2_END */ |
||||
{ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; |
||||
#if defined(FLASH_BANK2_END) |
||||
flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; |
||||
#else |
||||
flags |= FLASH_FLAG_PGERR; |
||||
#endif /* FLASH_BANK2_END */ |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) |
||||
{ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; |
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); |
||||
} |
||||
|
||||
/* Clear FLASH error pending bits */ |
||||
__HAL_FLASH_CLEAR_FLAG(flags); |
||||
}
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,587 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_gpio.c |
||||
* @author MCD Application Team |
||||
* @brief GPIO HAL module driver. |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral: |
||||
* + Initialization and de-initialization functions |
||||
* + IO operation functions |
||||
* |
||||
@verbatim |
||||
============================================================================== |
||||
##### GPIO Peripheral features ##### |
||||
============================================================================== |
||||
[..] |
||||
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each |
||||
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software |
||||
in several modes: |
||||
(+) Input mode |
||||
(+) Analog mode |
||||
(+) Output mode |
||||
(+) Alternate function mode |
||||
(+) External interrupt/event lines |
||||
|
||||
[..] |
||||
During and just after reset, the alternate functions and external interrupt |
||||
lines are not active and the I/O ports are configured in input floating mode. |
||||
|
||||
[..] |
||||
All GPIO pins have weak internal pull-up and pull-down resistors, which can be |
||||
activated or not. |
||||
|
||||
[..] |
||||
In Output or Alternate mode, each IO can be configured on open-drain or push-pull |
||||
type and the IO speed can be selected depending on the VDD value. |
||||
|
||||
[..] |
||||
All ports have external interrupt/event capability. To use external interrupt |
||||
lines, the port must be configured in input mode. All available GPIO pins are |
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. |
||||
|
||||
[..] |
||||
The external interrupt/event controller consists of up to 20 edge detectors in connectivity |
||||
line devices, or 19 edge detectors in other devices for generating event/interrupt requests. |
||||
Each input line can be independently configured to select the type (event or interrupt) and |
||||
the corresponding trigger event (rising or falling or both). Each line can also masked |
||||
independently. A pending register maintains the status line of the interrupt requests |
||||
|
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..] |
||||
(#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). |
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init(). |
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure |
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef |
||||
structure. |
||||
(++) In case of Output or alternate function mode selection: the speed is |
||||
configured through "Speed" member from GPIO_InitTypeDef structure |
||||
(++) Analog mode is required when a pin is to be used as ADC channel |
||||
or DAC output. |
||||
(++) In case of external interrupt/event selection the "Mode" member from |
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and |
||||
the corresponding trigger event (rising or falling or both). |
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority |
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using |
||||
HAL_NVIC_EnableIRQ(). |
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). |
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use |
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). |
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). |
||||
|
||||
(#) During and just after reset, the alternate functions are not |
||||
active and the GPIO pins are configured in input floating mode (except JTAG |
||||
pins). |
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose |
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has |
||||
priority over the GPIO function. |
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as |
||||
general purpose PD0 and PD1, respectively, when the HSE oscillator is off. |
||||
The HSE has priority over the GPIO function. |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{ |
||||
*/ |
||||
#define GPIO_MODE 0x00000003u |
||||
#define EXTI_MODE 0x10000000u |
||||
#define GPIO_MODE_IT 0x00010000u |
||||
#define GPIO_MODE_EVT 0x00020000u |
||||
#define RISING_EDGE 0x00100000u |
||||
#define FALLING_EDGE 0x00200000u |
||||
#define GPIO_OUTPUT_TYPE 0x00000010u |
||||
|
||||
#define GPIO_NUMBER 16u |
||||
|
||||
/* Definitions for bit manipulation of CRL and CRH register */ |
||||
#define GPIO_CR_MODE_INPUT 0x00000000u /*!< 00: Input mode (reset state) */ |
||||
#define GPIO_CR_CNF_ANALOG 0x00000000u /*!< 00: Analog mode */ |
||||
#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004u /*!< 01: Floating input (reset state) */ |
||||
#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008u /*!< 10: Input with pull-up / pull-down */ |
||||
#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000u /*!< 00: General purpose output push-pull */ |
||||
#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004u /*!< 01: General purpose output Open-drain */ |
||||
#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008u /*!< 10: Alternate function output Push-pull */ |
||||
#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000Cu /*!< 11: Alternate function output Open-drain */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* Private functions ---------------------------------------------------------*/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Initialization and de-initialization functions ##### |
||||
=============================================================================== |
||||
[..] |
||||
This section provides functions allowing to initialize and de-initialize the GPIOs |
||||
to be ready for use. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. |
||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||||
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains |
||||
* the configuration information for the specified GPIO peripheral. |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) |
||||
{ |
||||
uint32_t position = 0x00u; |
||||
uint32_t ioposition; |
||||
uint32_t iocurrent; |
||||
uint32_t temp; |
||||
uint32_t config = 0x00u; |
||||
__IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ |
||||
uint32_t registeroffset; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); |
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); |
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); |
||||
|
||||
/* Configure the port pins */ |
||||
while (((GPIO_Init->Pin) >> position) != 0x00u) |
||||
{ |
||||
/* Get the IO position */ |
||||
ioposition = (0x01uL << position); |
||||
|
||||
/* Get the current IO position */ |
||||
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; |
||||
|
||||
if (iocurrent == ioposition) |
||||
{ |
||||
/* Check the Alternate function parameters */ |
||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); |
||||
|
||||
/* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ |
||||
switch (GPIO_Init->Mode) |
||||
{ |
||||
/* If we are configuring the pin in OUTPUT push-pull mode */ |
||||
case GPIO_MODE_OUTPUT_PP: |
||||
/* Check the GPIO speed parameter */ |
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
||||
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; |
||||
break; |
||||
|
||||
/* If we are configuring the pin in OUTPUT open-drain mode */ |
||||
case GPIO_MODE_OUTPUT_OD: |
||||
/* Check the GPIO speed parameter */ |
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
||||
config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; |
||||
break; |
||||
|
||||
/* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */ |
||||
case GPIO_MODE_AF_PP: |
||||
/* Check the GPIO speed parameter */ |
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
||||
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; |
||||
break; |
||||
|
||||
/* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */ |
||||
case GPIO_MODE_AF_OD: |
||||
/* Check the GPIO speed parameter */ |
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
||||
config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; |
||||
break; |
||||
|
||||
/* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */ |
||||
case GPIO_MODE_INPUT: |
||||
case GPIO_MODE_IT_RISING: |
||||
case GPIO_MODE_IT_FALLING: |
||||
case GPIO_MODE_IT_RISING_FALLING: |
||||
case GPIO_MODE_EVT_RISING: |
||||
case GPIO_MODE_EVT_FALLING: |
||||
case GPIO_MODE_EVT_RISING_FALLING: |
||||
/* Check the GPIO pull parameter */ |
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); |
||||
if (GPIO_Init->Pull == GPIO_NOPULL) |
||||
{ |
||||
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; |
||||
} |
||||
else if (GPIO_Init->Pull == GPIO_PULLUP) |
||||
{ |
||||
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; |
||||
|
||||
/* Set the corresponding ODR bit */ |
||||
GPIOx->BSRR = ioposition; |
||||
} |
||||
else /* GPIO_PULLDOWN */ |
||||
{ |
||||
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; |
||||
|
||||
/* Reset the corresponding ODR bit */ |
||||
GPIOx->BRR = ioposition; |
||||
} |
||||
break; |
||||
|
||||
/* If we are configuring the pin in INPUT analog mode */ |
||||
case GPIO_MODE_ANALOG: |
||||
config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; |
||||
break; |
||||
|
||||
/* Parameters are checked with assert_param */ |
||||
default: |
||||
break; |
||||
} |
||||
|
||||
/* Check if the current bit belongs to first half or last half of the pin count number
|
||||
in order to address CRH or CRL register*/ |
||||
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; |
||||
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); |
||||
|
||||
/* Apply the new configuration of the pin to the register */ |
||||
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); |
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/ |
||||
/* Configure the External Interrupt or event for the current IO */ |
||||
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) |
||||
{ |
||||
/* Enable AFIO Clock */ |
||||
__HAL_RCC_AFIO_CLK_ENABLE(); |
||||
temp = AFIO->EXTICR[position >> 2u]; |
||||
CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); |
||||
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); |
||||
AFIO->EXTICR[position >> 2u] = temp; |
||||
|
||||
|
||||
/* Configure the interrupt mask */ |
||||
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) |
||||
{ |
||||
SET_BIT(EXTI->IMR, iocurrent); |
||||
} |
||||
else |
||||
{ |
||||
CLEAR_BIT(EXTI->IMR, iocurrent); |
||||
} |
||||
|
||||
/* Configure the event mask */ |
||||
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) |
||||
{ |
||||
SET_BIT(EXTI->EMR, iocurrent); |
||||
} |
||||
else |
||||
{ |
||||
CLEAR_BIT(EXTI->EMR, iocurrent); |
||||
} |
||||
|
||||
/* Enable or disable the rising trigger */ |
||||
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) |
||||
{ |
||||
SET_BIT(EXTI->RTSR, iocurrent); |
||||
} |
||||
else |
||||
{ |
||||
CLEAR_BIT(EXTI->RTSR, iocurrent); |
||||
} |
||||
|
||||
/* Enable or disable the falling trigger */ |
||||
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) |
||||
{ |
||||
SET_BIT(EXTI->FTSR, iocurrent); |
||||
} |
||||
else |
||||
{ |
||||
CLEAR_BIT(EXTI->FTSR, iocurrent); |
||||
} |
||||
} |
||||
} |
||||
|
||||
position++; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values. |
||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||||
* @param GPIO_Pin: specifies the port bit to be written. |
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15). |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) |
||||
{ |
||||
uint32_t position = 0x00u; |
||||
uint32_t iocurrent; |
||||
uint32_t tmp; |
||||
__IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ |
||||
uint32_t registeroffset; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); |
||||
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
||||
|
||||
/* Configure the port pins */ |
||||
while ((GPIO_Pin >> position) != 0u) |
||||
{ |
||||
/* Get current io position */ |
||||
iocurrent = (GPIO_Pin) & (1uL << position); |
||||
|
||||
if (iocurrent) |
||||
{ |
||||
/*------------------------- EXTI Mode Configuration --------------------*/ |
||||
/* Clear the External Interrupt or Event for the current IO */ |
||||
|
||||
tmp = AFIO->EXTICR[position >> 2u]; |
||||
tmp &= 0x0FuL << (4u * (position & 0x03u)); |
||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) |
||||
{ |
||||
tmp = 0x0FuL << (4u * (position & 0x03u)); |
||||
CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp); |
||||
|
||||
/* Clear EXTI line configuration */ |
||||
CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); |
||||
CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); |
||||
|
||||
/* Clear Rising Falling edge configuration */ |
||||
CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); |
||||
CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); |
||||
} |
||||
/*------------------------- GPIO Mode Configuration --------------------*/ |
||||
/* Check if the current bit belongs to first half or last half of the pin count number
|
||||
in order to address CRH or CRL register */ |
||||
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; |
||||
registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); |
||||
|
||||
/* CRL/CRH default value is floating input(0x04) shifted to correct position */ |
||||
MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), GPIO_CRL_CNF0_0 << registeroffset); |
||||
|
||||
/* ODR default value is 0 */ |
||||
CLEAR_BIT(GPIOx->ODR, iocurrent); |
||||
} |
||||
|
||||
position++; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief GPIO Read and Write |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### IO operation functions ##### |
||||
=============================================================================== |
||||
[..] |
||||
This subsection provides a set of functions allowing to manage the GPIOs. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin. |
||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||||
* @param GPIO_Pin: specifies the port bit to read. |
||||
* This parameter can be GPIO_PIN_x where x can be (0..15). |
||||
* @retval The input port pin value. |
||||
*/ |
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) |
||||
{ |
||||
GPIO_PinState bitstatus; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) |
||||
{ |
||||
bitstatus = GPIO_PIN_SET; |
||||
} |
||||
else |
||||
{ |
||||
bitstatus = GPIO_PIN_RESET; |
||||
} |
||||
return bitstatus; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit. |
||||
* |
||||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify |
||||
* accesses. In this way, there is no risk of an IRQ occurring between |
||||
* the read and the modify access. |
||||
* |
||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||||
* @param GPIO_Pin: specifies the port bit to be written. |
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15). |
||||
* @param PinState: specifies the value to be written to the selected bit. |
||||
* This parameter can be one of the GPIO_PinState enum values: |
||||
* @arg GPIO_PIN_RESET: to clear the port pin |
||||
* @arg GPIO_PIN_SET: to set the port pin |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
||||
assert_param(IS_GPIO_PIN_ACTION(PinState)); |
||||
|
||||
if (PinState != GPIO_PIN_RESET) |
||||
{ |
||||
GPIOx->BSRR = GPIO_Pin; |
||||
} |
||||
else |
||||
{ |
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pin |
||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||||
* @param GPIO_Pin: Specifies the pins to be toggled. |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) |
||||
{ |
||||
uint32_t odr; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
||||
|
||||
/* get current Ouput Data Register value */ |
||||
odr = GPIOx->ODR; |
||||
|
||||
/* Set selected pins that were at low level, and reset ones that were high */ |
||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers. |
||||
* @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence |
||||
* has been applied on a port bit, it is no longer possible to modify the value of the port bit until |
||||
* the next reset. |
||||
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral |
||||
* @param GPIO_Pin: specifies the port bit to be locked. |
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). |
||||
* @retval None |
||||
*/ |
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) |
||||
{ |
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); |
||||
assert_param(IS_GPIO_PIN(GPIO_Pin)); |
||||
|
||||
/* Apply lock key write sequence */ |
||||
SET_BIT(tmp, GPIO_Pin); |
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
||||
GPIOx->LCKR = tmp; |
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ |
||||
GPIOx->LCKR = GPIO_Pin; |
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
||||
GPIOx->LCKR = tmp; |
||||
/* Read LCKK register. This read is mandatory to complete key lock sequence */ |
||||
tmp = GPIOx->LCKR; |
||||
|
||||
/* read again in order to confirm lock is active */ |
||||
if ((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK)) |
||||
{ |
||||
return HAL_OK; |
||||
} |
||||
else |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles EXTI interrupt request. |
||||
* @param GPIO_Pin: Specifies the pins connected EXTI line |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) |
||||
{ |
||||
/* EXTI line interrupt detected */ |
||||
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) |
||||
{ |
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); |
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief EXTI line detection callbacks. |
||||
* @param GPIO_Pin: Specifies the pins connected EXTI line |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) |
||||
{ |
||||
/* Prevent unused argument(s) compilation warning */ |
||||
UNUSED(GPIO_Pin); |
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file |
||||
*/ |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,127 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_gpio_ex.c |
||||
* @author MCD Application Team |
||||
* @brief GPIO Extension HAL module driver. |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities of the General Purpose Input/Output (GPIO) extension peripheral. |
||||
* + Extended features functions |
||||
* |
||||
@verbatim |
||||
============================================================================== |
||||
##### GPIO Peripheral extension features ##### |
||||
============================================================================== |
||||
[..] GPIO module on STM32F1 family, manage also the AFIO register: |
||||
(+) Possibility to use the EVENTOUT Cortex feature |
||||
|
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..] This driver provides functions to use EVENTOUT Cortex feature |
||||
(#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() |
||||
(#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() |
||||
(#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @brief GPIO HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED |
||||
|
||||
/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions |
||||
* |
||||
@verbatim |
||||
============================================================================== |
||||
##### Extended features functions ##### |
||||
============================================================================== |
||||
[..] This section provides functions allowing to: |
||||
(+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() |
||||
(+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() |
||||
(+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. |
||||
* @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. |
||||
* This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. |
||||
* @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. |
||||
* This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) |
||||
{ |
||||
/* Verify the parameters */ |
||||
assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); |
||||
assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); |
||||
|
||||
/* Apply the new configuration */ |
||||
MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource)); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables the Event Output. |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIOEx_EnableEventout(void) |
||||
{ |
||||
SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables the Event Output. |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIOEx_DisableEventout(void) |
||||
{ |
||||
CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,265 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_iwdg.c |
||||
* @author MCD Application Team |
||||
* @brief IWDG HAL module driver. |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities of the Independent Watchdog (IWDG) peripheral: |
||||
* + Initialization and Start functions |
||||
* + IO operation functions |
||||
* |
||||
@verbatim |
||||
============================================================================== |
||||
##### IWDG Generic features ##### |
||||
============================================================================== |
||||
[..] |
||||
(+) The IWDG can be started by either software or hardware (configurable |
||||
through option byte). |
||||
|
||||
(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays |
||||
active even if the main clock fails. |
||||
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both cannot be |
||||
disabled. The counter starts counting down from the reset value (0xFFF). |
||||
When it reaches the end of count value (0x000) a reset signal is |
||||
generated (IWDG reset). |
||||
|
||||
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, |
||||
the IWDG_RLR value is reloaded into the counter and the watchdog reset |
||||
is prevented. |
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional |
||||
in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY). |
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG |
||||
reset occurs. |
||||
|
||||
(+) Debug mode: When the microcontroller enters debug mode (core halted), |
||||
the IWDG counter either continues to work normally or stops, depending |
||||
on DBG_IWDG_STOP configuration bit in DBG module, accessible through |
||||
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. |
||||
|
||||
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s |
||||
The IWDG timeout may vary due to LSI clock frequency dispersion. |
||||
STM32F1xx devices provide the capability to measure the LSI clock |
||||
frequency (LSI clock is internally connected to TIM5 CH4 input capture). |
||||
The measured value can be used to have an IWDG timeout with an |
||||
acceptable accuracy. |
||||
|
||||
[..] Default timeout value (necessary for IWDG_SR status register update): |
||||
Constant LSI_VALUE is defined based on the nominal LSI clock frequency. |
||||
This frequency being subject to variations as mentioned above, the |
||||
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT |
||||
below) may become too short or too long. |
||||
In such cases, this default timeout value can be tuned by redefining |
||||
the constant LSI_VALUE at user-application level (based, for instance, |
||||
on the measured LSI clock frequency as explained above). |
||||
|
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..] |
||||
(#) Use IWDG using HAL_IWDG_Init() function to : |
||||
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI |
||||
clock is forced ON and IWDG counter starts counting down. |
||||
(++) Enable write access to configuration registers: |
||||
IWDG_PR and IWDG_RLR. |
||||
(++) Configure the IWDG prescaler and counter reload value. This reload |
||||
value will be loaded in the IWDG counter each time the watchdog is |
||||
reloaded, then the IWDG will start counting down from this value. |
||||
(++) Wait for status flags to be reset. |
||||
|
||||
(#) Then the application program must refresh the IWDG counter at regular |
||||
intervals during normal operation to prevent an MCU reset, using |
||||
HAL_IWDG_Refresh() function. |
||||
|
||||
*** IWDG HAL driver macros list *** |
||||
==================================== |
||||
[..] |
||||
Below the list of most used macros in IWDG HAL driver: |
||||
(+) __HAL_IWDG_START: Enable the IWDG peripheral |
||||
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in |
||||
the reload register |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED |
||||
/** @addtogroup IWDG
|
||||
* @brief IWDG HAL module driver. |
||||
* @{ |
||||
*/ |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/** @defgroup IWDG_Private_Defines IWDG Private Defines
|
||||
* @{ |
||||
*/ |
||||
/* Status register needs up to 5 LSI clock periods divided by the clock
|
||||
prescaler to be updated. The number of LSI clock periods is upper-rounded to |
||||
6 for the timeout value calculation. |
||||
The timeout value is calculated using the highest prescaler (256) and |
||||
the LSI_VALUE constant. The value of this constant can be changed by the user |
||||
to take into account possible LSI clock period variations. |
||||
The timeout value is multiplied by 1000 to be converted in milliseconds. |
||||
LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT |
||||
converted in milliseconds. */ |
||||
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) |
||||
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup IWDG_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group1
|
||||
* @brief Initialization and Start functions. |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Initialization and Start functions ##### |
||||
=============================================================================== |
||||
[..] This section provides functions allowing to: |
||||
(+) Initialize the IWDG according to the specified parameters in the |
||||
IWDG_InitTypeDef of associated handle. |
||||
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog |
||||
is reloaded in order to exit function with correct time base. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Initialize the IWDG according to the specified parameters in the |
||||
* IWDG_InitTypeDef and start watchdog. Before exiting function, |
||||
* watchdog is refreshed in order to have correct time base. |
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains |
||||
* the configuration information for the specified IWDG module. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) |
||||
{ |
||||
uint32_t tickstart; |
||||
|
||||
/* Check the IWDG handle allocation */ |
||||
if (hiwdg == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); |
||||
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); |
||||
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); |
||||
|
||||
/* Enable IWDG. LSI is turned on automatically */ |
||||
__HAL_IWDG_START(hiwdg); |
||||
|
||||
/* Enable write access to IWDG_PR and IWDG_RLR registers by writing
|
||||
0x5555 in KR */ |
||||
IWDG_ENABLE_WRITE_ACCESS(hiwdg); |
||||
|
||||
/* Write to IWDG registers the Prescaler & Reload values to work with */ |
||||
hiwdg->Instance->PR = hiwdg->Init.Prescaler; |
||||
hiwdg->Instance->RLR = hiwdg->Init.Reload; |
||||
|
||||
/* Check pending flag, if previous update not done, return timeout */ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Wait for register to be updated */ |
||||
while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) |
||||
{ |
||||
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) |
||||
{ |
||||
if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* Reload IWDG counter with value defined in the reload register */ |
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg); |
||||
|
||||
/* Return function status */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group2
|
||||
* @brief IO operation functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### IO operation functions ##### |
||||
=============================================================================== |
||||
[..] This section provides functions allowing to: |
||||
(+) Refresh the IWDG. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Refresh the IWDG. |
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains |
||||
* the configuration information for the specified IWDG module. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) |
||||
{ |
||||
/* Reload IWDG counter with value defined in the reload register */ |
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg); |
||||
|
||||
/* Return function status */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,621 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_pwr.c |
||||
* @author MCD Application Team |
||||
* @brief PWR HAL module driver. |
||||
* |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities of the Power Controller (PWR) peripheral: |
||||
* + Initialization/de-initialization functions |
||||
* + Peripheral Control functions
|
||||
* |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @brief PWR HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup PWR_Private_Constants PWR Private Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
||||
* @{ |
||||
*/
|
||||
#define PVD_MODE_IT 0x00010000U |
||||
#define PVD_MODE_EVT 0x00020000U |
||||
#define PVD_RISING_EDGE 0x00000001U |
||||
#define PVD_FALLING_EDGE 0x00000002U |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup PWR_register_alias_address PWR Register alias address
|
||||
* @{ |
||||
*/
|
||||
/* ------------- PWR registers bit address in the alias region ---------------*/ |
||||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) |
||||
#define PWR_CR_OFFSET 0x00U |
||||
#define PWR_CSR_OFFSET 0x04U |
||||
#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) |
||||
#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_CR_register_alias PWR CR Register alias address
|
||||
* @{ |
||||
*/
|
||||
/* --- CR Register ---*/ |
||||
/* Alias word address of LPSDSR bit */ |
||||
#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos |
||||
#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) |
||||
|
||||
/* Alias word address of DBP bit */ |
||||
#define DBP_BIT_NUMBER PWR_CR_DBP_Pos |
||||
#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) |
||||
|
||||
/* Alias word address of PVDE bit */ |
||||
#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos |
||||
#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* --- CSR Register ---*/ |
||||
/* Alias word address of EWUP1 bit */ |
||||
#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/** @defgroup PWR_Private_Functions PWR Private Functions
|
||||
* brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) |
||||
* @{ |
||||
*/ |
||||
static void PWR_OverloadWfe(void); |
||||
|
||||
/* Private functions ---------------------------------------------------------*/ |
||||
__NOINLINE |
||||
static void PWR_OverloadWfe(void) |
||||
{ |
||||
__asm volatile( "wfe" ); |
||||
__asm volatile( "nop" ); |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Initialization and de-initialization functions ##### |
||||
=============================================================================== |
||||
[..] |
||||
After reset, the backup domain (RTC registers, RTC backup data |
||||
registers) is protected against possible unwanted |
||||
write accesses. |
||||
To enable access to the RTC Domain and RTC registers, proceed as follows: |
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the |
||||
__HAL_RCC_PWR_CLK_ENABLE() macro. |
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DeInit(void) |
||||
{ |
||||
__HAL_RCC_PWR_FORCE_RESET(); |
||||
__HAL_RCC_PWR_RELEASE_RESET(); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables access to the backup domain (RTC registers, RTC |
||||
* backup data registers ). |
||||
* @note If the HSE divided by 128 is used as the RTC clock, the |
||||
* Backup Domain Access should be kept enabled. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnableBkUpAccess(void) |
||||
{ |
||||
/* Enable access to RTC and backup registers */ |
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables access to the backup domain (RTC registers, RTC |
||||
* backup data registers). |
||||
* @note If the HSE divided by 128 is used as the RTC clock, the |
||||
* Backup Domain Access should be kept enabled. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DisableBkUpAccess(void) |
||||
{ |
||||
/* Disable access to RTC and backup registers */ |
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Low Power modes configuration functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Peripheral Control functions ##### |
||||
=============================================================================== |
||||
|
||||
*** PVD configuration *** |
||||
========================= |
||||
[..] |
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a |
||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). |
||||
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower |
||||
than the PVD threshold. This event is internally connected to the EXTI |
||||
line16 and can generate an interrupt if enabled. This is done through |
||||
__HAL_PVD_EXTI_ENABLE_IT() macro. |
||||
(+) The PVD is stopped in Standby mode. |
||||
|
||||
*** WakeUp pin configuration *** |
||||
================================ |
||||
[..] |
||||
(+) WakeUp pin is used to wake up the system from Standby mode. This pin is |
||||
forced in input pull-down configuration and is active on rising edges. |
||||
(+) There is one WakeUp pin: |
||||
WakeUp Pin 1 on PA.00. |
||||
|
||||
[..] |
||||
|
||||
*** Low Power modes configuration *** |
||||
===================================== |
||||
[..] |
||||
The device features 3 low-power modes: |
||||
(+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
|
||||
NVIC, SysTick, etc. are kept running |
||||
(+) Stop mode: All clocks are stopped |
||||
(+) Standby mode: 1.8V domain powered off |
||||
|
||||
|
||||
*** Sleep mode *** |
||||
================== |
||||
[..] |
||||
(+) Entry: |
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
||||
functions with |
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
||||
|
||||
(+) Exit: |
||||
(++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt |
||||
controller (NVIC) can wake up the device from Sleep mode. |
||||
(++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. |
||||
(+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend) |
||||
(+++) Any EXTI Line (Internal or External) configured in Event mode |
||||
|
||||
*** Stop mode *** |
||||
================= |
||||
[..] |
||||
The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral |
||||
clock gating. The voltage regulator can be configured either in normal or low-power mode. |
||||
In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
|
||||
oscillators are disabled. SRAM and register contents are preserved. |
||||
In Stop mode, all I/O pins keep the same state as in Run mode. |
||||
|
||||
(+) Entry: |
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx ) |
||||
function with: |
||||
(++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. |
||||
(++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. |
||||
(++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction |
||||
(++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction |
||||
(+) Exit: |
||||
(++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured |
||||
(++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. |
||||
|
||||
*** Standby mode *** |
||||
==================== |
||||
[..] |
||||
The Standby mode allows to achieve the lowest power consumption. It is based on the |
||||
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
|
||||
consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
|
||||
switched off. SRAM and register contents are lost except for registers in the Backup domain
|
||||
and Standby circuitry |
||||
|
||||
(+) Entry: |
||||
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. |
||||
(+) Exit: |
||||
(++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
|
||||
NRSTpin, IWDG Reset |
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode *** |
||||
============================================= |
||||
[..] |
||||
|
||||
(+) The MCU can be woken up from low-power mode by an RTC Alarm event,
|
||||
without depending on an external interrupt (Auto-wakeup mode). |
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop and Standby modes |
||||
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. |
||||
|
||||
*** PWR Workarounds linked to Silicon Limitation *** |
||||
==================================================== |
||||
[..] |
||||
Below the list of all silicon limitations known on STM32F1xx prouct. |
||||
|
||||
(#)Workarounds Implemented inside PWR HAL Driver |
||||
(##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
|
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). |
||||
* @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration |
||||
* information for the PVD. |
||||
* @note Refer to the electrical characteristics of your device datasheet for |
||||
* more details about the voltage threshold corresponding to each |
||||
* detection level. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); |
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); |
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */ |
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); |
||||
|
||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT(); |
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT(); |
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); |
||||
|
||||
/* Configure interrupt mode */ |
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) |
||||
{ |
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT(); |
||||
} |
||||
|
||||
/* Configure event mode */ |
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) |
||||
{ |
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT(); |
||||
} |
||||
|
||||
/* Configure the edge */ |
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) |
||||
{ |
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); |
||||
} |
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) |
||||
{ |
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD). |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnablePVD(void) |
||||
{ |
||||
/* Enable the power voltage detector */ |
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD). |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DisablePVD(void) |
||||
{ |
||||
/* Disable the power voltage detector */ |
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables the WakeUp PINx functionality. |
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_WAKEUP_PIN1 |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) |
||||
{ |
||||
/* Check the parameter */ |
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
||||
/* Enable the EWUPx pin */ |
||||
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables the WakeUp PINx functionality. |
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_WAKEUP_PIN1 |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) |
||||
{ |
||||
/* Check the parameter */ |
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
||||
/* Disable the EWUPx pin */ |
||||
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode. |
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode. |
||||
* @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software |
||||
* @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. |
||||
* When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||||
* the interrupt wake up source. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) |
||||
{ |
||||
/* Check the parameters */ |
||||
/* No check on Regulator because parameter not used in SLEEP mode */ |
||||
/* Prevent unused argument(s) compilation warning */ |
||||
UNUSED(Regulator); |
||||
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); |
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */ |
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/ |
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI) |
||||
{ |
||||
/* Request Wait For Interrupt */ |
||||
__WFI(); |
||||
} |
||||
else |
||||
{ |
||||
/* Request Wait For Event */ |
||||
__SEV(); |
||||
__WFE(); |
||||
__WFE(); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enters Stop mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode. |
||||
* @note When exiting Stop mode by using an interrupt or a wakeup event, |
||||
* HSI RC oscillator is selected as system clock. |
||||
* @note When the voltage regulator operates in low power mode, an additional |
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption |
||||
* is higher although the startup time is reduced.
|
||||
* @param Regulator: Specifies the regulator state in Stop mode. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON |
||||
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON |
||||
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction |
||||
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
|
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_PWR_REGULATOR(Regulator)); |
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
||||
|
||||
/* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
|
||||
CLEAR_BIT(PWR->CR, PWR_CR_PDDS); |
||||
|
||||
/* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ |
||||
MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); |
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */ |
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
||||
|
||||
/* Select Stop mode entry --------------------------------------------------*/ |
||||
if(STOPEntry == PWR_STOPENTRY_WFI) |
||||
{ |
||||
/* Request Wait For Interrupt */ |
||||
__WFI(); |
||||
} |
||||
else |
||||
{ |
||||
/* Request Wait For Event */ |
||||
__SEV(); |
||||
PWR_OverloadWfe(); /* WFE redefine locally */ |
||||
PWR_OverloadWfe(); /* WFE redefine locally */ |
||||
} |
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */ |
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enters Standby mode. |
||||
* @note In Standby mode, all I/O pins are high impedance except for: |
||||
* - Reset pad (still available)
|
||||
* - TAMPER pin if configured for tamper or calibration out. |
||||
* - WKUP pin (PA0) if enabled. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnterSTANDBYMode(void) |
||||
{ |
||||
/* Select Standby mode */ |
||||
SET_BIT(PWR->CR, PWR_CR_PDDS); |
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */ |
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
||||
|
||||
/* This option is used to ensure that store operations are completed */ |
||||
#if defined ( __CC_ARM) |
||||
__force_stores(); |
||||
#endif |
||||
/* Request Wait For Interrupt */ |
||||
__WFI(); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over. |
||||
* Setting this bit is useful when the processor is expected to run only on |
||||
* interruptions handling.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnableSleepOnExit(void) |
||||
{ |
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */ |
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DisableSleepOnExit(void) |
||||
{ |
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Enables CORTEX M3 SEVONPEND bit.
|
||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnableSEVOnPend(void) |
||||
{ |
||||
/* Set SEVONPEND bit of Cortex System Control Register */ |
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Disables CORTEX M3 SEVONPEND bit.
|
||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DisableSEVOnPend(void) |
||||
{ |
||||
/* Clear SEVONPEND bit of Cortex System Control Register */ |
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
||||
} |
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request. |
||||
* @note This API should be called under the PVD_IRQHandler(). |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_PVD_IRQHandler(void) |
||||
{ |
||||
/* Check PWR exti flag */ |
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) |
||||
{ |
||||
/* PWR PVD interrupt user callback */ |
||||
HAL_PWR_PVDCallback(); |
||||
|
||||
/* Clear PWR Exti pending bit */ |
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG(); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_PWR_PVDCallback(void) |
||||
{ |
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file |
||||
*/
|
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,863 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32f1xx_hal_rcc_ex.c |
||||
* @author MCD Application Team |
||||
* @brief Extended RCC HAL module driver. |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities RCC extension peripheral: |
||||
* + Extended Peripheral Control functions |
||||
* |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||||
* All rights reserved.</center></h2> |
||||
* |
||||
* This software component is licensed by ST under BSD 3-Clause license, |
||||
* the "License"; You may not use this file except in compliance with the |
||||
* License. You may obtain a copy of the License at: |
||||
* opensource.org/licenses/BSD-3-Clause |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32f1xx_hal.h" |
||||
|
||||
/** @addtogroup STM32F1xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED |
||||
|
||||
/** @defgroup RCCEx RCCEx
|
||||
* @brief RCC Extension HAL module driver. |
||||
* @{ |
||||
*/ |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* Private functions ---------------------------------------------------------*/ |
||||
|
||||
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Extended Peripheral Control functions ##### |
||||
=============================================================================== |
||||
[..] |
||||
This subsection provides a set of functions allowing to control the RCC Clocks |
||||
frequencies. |
||||
[..] |
||||
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
||||
select the RTC clock source; in this case the Backup domain will be reset in |
||||
order to modify the RTC Clock source, as consequence RTC registers (including |
||||
the backup registers) are set to their reset values. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the |
||||
* RCC_PeriphCLKInitTypeDef. |
||||
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that |
||||
* contains the configuration information for the Extended Peripherals clocks(RTC clock). |
||||
* |
||||
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select |
||||
* the RTC clock source; in this case the Backup domain will be reset in |
||||
* order to modify the RTC Clock source, as consequence RTC registers (including |
||||
* the backup registers) are set to their reset values. |
||||
* |
||||
* @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on |
||||
* one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to |
||||
* manually disable it. |
||||
* |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
||||
{ |
||||
uint32_t tickstart = 0U, temp_reg = 0U; |
||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
||||
uint32_t pllactive = 0U; |
||||
#endif /* STM32F105xC || STM32F107xC */ |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
||||
|
||||
/*------------------------------- RTC/LCD Configuration ------------------------*/ |
||||
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
||||
{ |
||||
FlagStatus pwrclkchanged = RESET; |
||||
|
||||
/* check for RTC Parameters used to output RTCCLK */ |
||||
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); |
||||
|
||||
/* As soon as function is called to change RTC clock source, activation of the
|
||||
power domain is done. */ |
||||
/* Requires to enable write access to Backup Domain of necessary */ |
||||
if (__HAL_RCC_PWR_IS_CLK_DISABLED()) |
||||
{ |
||||
__HAL_RCC_PWR_CLK_ENABLE(); |
||||
pwrclkchanged = SET; |
||||
} |
||||
|
||||
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) |
||||
{ |
||||
/* Enable write access to Backup domain */ |
||||
SET_BIT(PWR->CR, PWR_CR_DBP); |
||||
|
||||
/* Wait for Backup domain Write protection disable */ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) |
||||
{ |
||||
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ |
||||
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); |
||||
if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) |
||||
{ |
||||
/* Store the content of BDCR register before the reset of Backup Domain */ |
||||
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
||||
/* RTC Clock selection can be changed only if the Backup Domain is reset */ |
||||
__HAL_RCC_BACKUPRESET_FORCE(); |
||||
__HAL_RCC_BACKUPRESET_RELEASE(); |
||||
/* Restore the Content of BDCR register */ |
||||
RCC->BDCR = temp_reg; |
||||
|
||||
/* Wait for LSERDY if LSE was enabled */ |
||||
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) |
||||
{ |
||||
/* Get Start Tick */ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Wait till LSE is ready */ |
||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
||||
{ |
||||
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
||||
|
||||
/* Require to disable power clock if necessary */ |
||||
if (pwrclkchanged == SET) |
||||
{ |
||||
__HAL_RCC_PWR_CLK_DISABLE(); |
||||
} |
||||
} |
||||
|
||||
/*------------------------------ ADC clock Configuration ------------------*/ |
||||
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); |
||||
|
||||
/* Configure the ADC clock source */ |
||||
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); |
||||
} |
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
||||
/*------------------------------ I2S2 Configuration ------------------------*/ |
||||
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); |
||||
|
||||
/* Configure the I2S2 clock source */ |
||||
__HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); |
||||
} |
||||
|
||||
/*------------------------------ I2S3 Configuration ------------------------*/ |
||||
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection)); |
||||
|
||||
/* Configure the I2S3 clock source */ |
||||
__HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection); |
||||
} |
||||
|
||||
/*------------------------------ PLL I2S Configuration ----------------------*/ |
||||
/* Check that PLLI2S need to be enabled */ |
||||
if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) |
||||
{ |
||||
/* Update flag to indicate that PLL I2S should be active */ |
||||
pllactive = 1; |
||||
} |
||||
|
||||
/* Check if PLL I2S need to be enabled */ |
||||
if (pllactive == 1) |
||||
{ |
||||
/* Enable PLL I2S only if not active */ |
||||
if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON)) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL)); |
||||
assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value)); |
||||
|
||||
/* Prediv2 can be written only when the PLL2 is disabled. */ |
||||
/* Return an error only if new value is different from the programmed value */ |
||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \
|
||||
(__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value)) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Configure the HSE prediv2 factor --------------------------------*/ |
||||
__HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value); |
||||
|
||||
/* Configure the main PLLI2S multiplication factors. */ |
||||
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL); |
||||
|
||||
/* Enable the main PLLI2S. */ |
||||
__HAL_RCC_PLLI2S_ENABLE(); |
||||
|
||||
/* Get Start Tick*/ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Wait till PLLI2S is ready */ |
||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
||||
{ |
||||
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
else |
||||
{ |
||||
/* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */ |
||||
if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
} |
||||
} |
||||
#endif /* STM32F105xC || STM32F107xC */ |
||||
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC) |
||||
/*------------------------------ USB clock Configuration ------------------*/ |
||||
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); |
||||
|
||||
/* Configure the USB clock source */ |
||||
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); |
||||
} |
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Get the PeriphClkInit according to the internal |
||||
* RCC configuration registers. |
||||
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that |
||||
* returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks). |
||||
* @retval None |
||||
*/ |
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
||||
{ |
||||
uint32_t srcclk = 0U; |
||||
|
||||
/* Set all possible values for the extended clock type parameter------------*/ |
||||
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; |
||||
|
||||
/* Get the RTC configuration -----------------------------------------------*/ |
||||
srcclk = __HAL_RCC_GET_RTC_SOURCE(); |
||||
/* Source clock is LSE or LSI*/ |
||||
PeriphClkInit->RTCClockSelection = srcclk; |
||||
|
||||
/* Get the ADC clock configuration -----------------------------------------*/ |
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC; |
||||
PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); |
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
||||
/* Get the I2S2 clock configuration -----------------------------------------*/ |
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; |
||||
PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); |
||||
|
||||
/* Get the I2S3 clock configuration -----------------------------------------*/ |
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; |
||||
PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE(); |
||||
|
||||
#endif /* STM32F105xC || STM32F107xC */ |
||||
|
||||
#if defined(STM32F103xE) || defined(STM32F103xG) |
||||
/* Get the I2S2 clock configuration -----------------------------------------*/ |
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; |
||||
PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK; |
||||
|
||||
/* Get the I2S3 clock configuration -----------------------------------------*/ |
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3; |
||||
PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK; |
||||
|
||||
#endif /* STM32F103xE || STM32F103xG */ |
||||
|
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC) |
||||
/* Get the USB clock configuration -----------------------------------------*/ |
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; |
||||
PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); |
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns the peripheral clock frequency |
||||
* @note Returns 0 if peripheral clock is unknown |
||||
* @param PeriphClk Peripheral clock identifier |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock |
||||
@if STM32F103xE |
||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
@endif |
||||
@if STM32F103xG |
||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
||||
@endif |
||||
@if STM32F105xC |
||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock |
||||
@endif |
||||
@if STM32F107xC |
||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock |
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock |
||||
@endif |
||||
@if STM32F102xx |
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock |
||||
@endif |
||||
@if STM32F103xx |
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock |
||||
@endif |
||||
* @retval Frequency in Hz (0: means that no available frequency for the peripheral) |
||||
*/ |
||||
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) |
||||
{ |
||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
||||
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; |
||||
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; |
||||
|
||||
uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; |
||||
uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; |
||||
#endif /* STM32F105xC || STM32F107xC */ |
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \ |
||||
defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) |
||||
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; |
||||
const uint8_t aPredivFactorTable[2] = {1, 2}; |
||||
|
||||
uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; |
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ |
||||
uint32_t temp_reg = 0U, frequency = 0U; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); |
||||
|
||||
switch (PeriphClk) |
||||
{ |
||||
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ |
||||
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|
||||
|| defined(STM32F105xC) || defined(STM32F107xC) |
||||
case RCC_PERIPHCLK_USB: |
||||
{ |
||||
/* Get RCC configuration ------------------------------------------------------*/ |
||||
temp_reg = RCC->CFGR; |
||||
|
||||
/* Check if PLL is enabled */ |
||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLON)) |
||||
{ |
||||
pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; |
||||
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) |
||||
{ |
||||
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ |
||||
|| defined(STM32F100xE) |
||||
prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; |
||||
#else |
||||
prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; |
||||
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ |
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
||||
if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) |
||||
{ |
||||
/* PLL2 selected as Prediv1 source */ |
||||
/* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ |
||||
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; |
||||
pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; |
||||
pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); |
||||
} |
||||
else |
||||
{ |
||||
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ |
||||
pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); |
||||
} |
||||
|
||||
/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ |
||||
/* In this case need to divide pllclk by 2 */ |
||||
if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) |
||||
{ |
||||
pllclk = pllclk / 2; |
||||
} |
||||
#else |
||||
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) |
||||
{ |
||||
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ |
||||
pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul); |
||||
} |
||||
#endif /* STM32F105xC || STM32F107xC */ |
||||
} |
||||
else |
||||
{ |
||||
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ |
||||
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); |
||||
} |
||||
|
||||
/* Calcul of the USB frequency*/ |
||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
||||
/* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */ |
||||
if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2) |
||||
{ |
||||
/* Prescaler of 2 selected for USB */ |
||||
frequency = pllclk; |
||||
} |
||||
else |
||||
{ |
||||
/* Prescaler of 3 selected for USB */ |
||||
frequency = (2 * pllclk) / 3; |
||||
} |
||||
#else |
||||
/* USBCLK = PLLCLK / USB prescaler */ |
||||
if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL) |
||||
{ |
||||
/* No prescaler selected for USB */ |
||||
frequency = pllclk; |
||||
} |
||||
else |
||||
{ |
||||
/* Prescaler of 1.5 selected for USB */ |
||||
frequency = (pllclk * 2) / 3; |
||||
} |
||||
#endif |
||||
} |
||||
break; |
||||
} |
||||
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||||
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) |
||||
case RCC_PERIPHCLK_I2S2: |
||||
{ |
||||
#if defined(STM32F103xE) || defined(STM32F103xG) |
||||
/* SYSCLK used as source clock for I2S2 */ |
||||
frequency = HAL_RCC_GetSysClockFreq(); |
||||
#else |
||||
if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK) |
||||
{ |
||||
/* SYSCLK used as source clock for I2S2 */ |
||||
frequency = HAL_RCC_GetSysClockFreq(); |
||||
} |
||||
else |
||||
{ |
||||
/* Check if PLLI2S is enabled */ |
||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) |
||||
{ |
||||
/* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ |
||||
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; |
||||
pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; |
||||
frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); |
||||
} |
||||
} |
||||
#endif /* STM32F103xE || STM32F103xG */ |
||||
break; |
||||
} |
||||
case RCC_PERIPHCLK_I2S3: |
||||
{ |
||||
#if defined(STM32F103xE) || defined(STM32F103xG) |
||||
/* SYSCLK used as source clock for I2S3 */ |
||||
frequency = HAL_RCC_GetSysClockFreq(); |
||||
#else |
||||
if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK) |
||||
{ |
||||
/* SYSCLK used as source clock for I2S3 */ |
||||
frequency = HAL_RCC_GetSysClockFreq(); |
||||
} |
||||
else |
||||
{ |
||||
/* Check if PLLI2S is enabled */ |
||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) |
||||
{ |
||||
/* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ |
||||
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; |
||||
pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; |
||||
frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); |
||||
} |
||||
} |
||||
#endif /* STM32F103xE || STM32F103xG */ |
||||
break; |
||||
} |
||||
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ |
||||
case RCC_PERIPHCLK_RTC: |
||||
{ |
||||
/* Get RCC BDCR configuration ------------------------------------------------------*/ |
||||
temp_reg = RCC->BDCR; |
||||
|
||||
/* Check if LSE is ready if RTC clock selection is LSE */ |
||||
if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) |
||||
{ |
||||
frequency = LSE_VALUE; |
||||
} |
||||
/* Check if LSI is ready if RTC clock selection is LSI */ |
||||
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) |
||||
{ |
||||
frequency = LSI_VALUE; |
||||
} |
||||
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) |
||||
{ |
||||
frequency = HSE_VALUE / 128U; |
||||
} |
||||
/* Clock not enabled for RTC*/ |
||||
else |
||||
{ |
||||
/* nothing to do: frequency already initialized to 0U */ |
||||
} |
||||
break; |
||||
} |
||||
case RCC_PERIPHCLK_ADC: |
||||
{ |
||||
frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); |
||||
break; |
||||
} |
||||
default: |
||||
{ |
||||
break; |
||||
} |
||||
} |
||||
return (frequency); |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC) |
||||
/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
|
||||
* @brief PLLI2S Management functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Extended PLLI2S Management functions ##### |
||||
=============================================================================== |
||||
[..] |
||||
This subsection provides a set of functions allowing to control the PLLI2S |
||||
activation or deactivation |
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Enable PLLI2S |
||||
* @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that |
||||
* contains the configuration information for the PLLI2S |
||||
* @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) |
||||
{ |
||||
uint32_t tickstart = 0U; |
||||
|
||||
/* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/ |
||||
if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL)); |
||||
assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value)); |
||||
|
||||
/* Prediv2 can be written only when the PLL2 is disabled. */ |
||||
/* Return an error only if new value is different from the programmed value */ |
||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2ON) && \
|
||||
(__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value)) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Disable the main PLLI2S. */ |
||||
__HAL_RCC_PLLI2S_DISABLE(); |
||||
|
||||
/* Get Start Tick*/ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Wait till PLLI2S is ready */ |
||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
||||
{ |
||||
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
|
||||
/* Configure the HSE prediv2 factor --------------------------------*/ |
||||
__HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value); |
||||
|
||||
|
||||
/* Configure the main PLLI2S multiplication factors. */ |
||||
__HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL); |
||||
|
||||
/* Enable the main PLLI2S. */ |
||||
__HAL_RCC_PLLI2S_ENABLE(); |
||||
|
||||
/* Get Start Tick*/ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Wait till PLLI2S is ready */ |
||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) |
||||
{ |
||||
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
else |
||||
{ |
||||
/* PLLI2S cannot be modified as already used by I2S2 or I2S3 */ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable PLLI2S |
||||
* @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) |
||||
{ |
||||
uint32_t tickstart = 0U; |
||||
|
||||
/* Disable PLL I2S as not requested by I2S2 or I2S3*/ |
||||
if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) |
||||
{ |
||||
/* Disable the main PLLI2S. */ |
||||
__HAL_RCC_PLLI2S_DISABLE(); |
||||
|
||||
/* Get Start Tick*/ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Wait till PLLI2S is ready */ |
||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) |
||||
{ |
||||
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
else |
||||
{ |
||||
/* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
|
||||
* @brief PLL2 Management functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Extended PLL2 Management functions ##### |
||||
=============================================================================== |
||||
[..] |
||||
This subsection provides a set of functions allowing to control the PLL2 |
||||
activation or deactivation |
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Enable PLL2 |
||||
* @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that |
||||
* contains the configuration information for the PLL2 |
||||
* @note The PLL2 configuration not modified if used indirectly as system clock. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) |
||||
{ |
||||
uint32_t tickstart = 0U; |
||||
|
||||
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
|
||||
clock (i.e. it is used as PLL clock entry that is used as system clock). */ |
||||
if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
|
||||
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
|
||||
((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
else |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL)); |
||||
assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value)); |
||||
|
||||
/* Prediv2 can be written only when the PLLI2S is disabled. */ |
||||
/* Return an error only if new value is different from the programmed value */ |
||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON) && \
|
||||
(__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value)) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Disable the main PLL2. */ |
||||
__HAL_RCC_PLL2_DISABLE(); |
||||
|
||||
/* Get Start Tick*/ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Wait till PLL2 is disabled */ |
||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) |
||||
{ |
||||
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
|
||||
/* Configure the HSE prediv2 factor --------------------------------*/ |
||||
__HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value); |
||||
|
||||
/* Configure the main PLL2 multiplication factors. */ |
||||
__HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL); |
||||
|
||||
/* Enable the main PLL2. */ |
||||
__HAL_RCC_PLL2_ENABLE(); |
||||
|
||||
/* Get Start Tick*/ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Wait till PLL2 is ready */ |
||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET) |
||||
{ |
||||
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable PLL2 |
||||
* @note PLL2 is not disabled if used indirectly as system clock. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) |
||||
{ |
||||
uint32_t tickstart = 0U; |
||||
|
||||
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
|
||||
clock (i.e. it is used as PLL clock entry that is used as system clock). */ |
||||
if ((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
|
||||
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
|
||||
((READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2)) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
else |
||||
{ |
||||
/* Disable the main PLL2. */ |
||||
__HAL_RCC_PLL2_DISABLE(); |
||||
|
||||
/* Get Start Tick*/ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Wait till PLL2 is disabled */ |
||||
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET) |
||||
{ |
||||
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* STM32F105xC || STM32F107xC */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,4 @@ |
||||
*.o |
||||
ufb-test |
||||
.idea/ |
||||
|
||||
@ -0,0 +1,32 @@ |
||||
/**
|
||||
* Draw 7-seg digits to the framebuffer |
||||
*/ |
||||
|
||||
#ifndef FB_7SEG_H |
||||
#define FB_7SEG_H |
||||
|
||||
#include "framebuffer.h" |
||||
|
||||
/// Draw a 7-segment digit. Returns its width (without spacing)
|
||||
///
|
||||
/// \param x - pos X (left top)
|
||||
/// \param y - pos Y (left top)
|
||||
/// \param w - full digit width
|
||||
/// \param h - full digit height; will be adjusted down if needed
|
||||
/// \param th - thickness
|
||||
/// \param digit - digit 0-9
|
||||
/// \return width taken
|
||||
fbpos_t fb_7seg_dig(fbpos_t x, fbpos_t y, fbpos_t w, fbpos_t h, fbpos_t th, uint8_t digit, fbcolor_t color); |
||||
|
||||
/// Draw a 7-segment period. Returns its width (without spacing).
|
||||
/// Digit height is (w * 2 - th)
|
||||
///
|
||||
/// \param x - pos X (digit left top)
|
||||
/// \param y - pos Y (digit left top)
|
||||
/// \param w - full digit width
|
||||
/// \param h - full digit height; will be adjusted down if needed
|
||||
/// \param th - thickness
|
||||
/// \return width taken
|
||||
fbpos_t fb_7seg_period(fbpos_t x, fbpos_t y, fbpos_t w, fbpos_t h, fbpos_t th, fbcolor_t color); |
||||
|
||||
#endif //FB_7SEG_H
|
||||
@ -0,0 +1,29 @@ |
||||
/**
|
||||
* Draw text |
||||
*/ |
||||
|
||||
#ifndef UFB_FB_TEXT_H |
||||
#define UFB_FB_TEXT_H |
||||
|
||||
#include "framebuffer.h" |
||||
|
||||
/// Use tiny font 5x4, supports only digits and select symbols
|
||||
#define FONT_4X5 8 |
||||
#define FONT_3X5 16 |
||||
#define FONT_5X7 0 // default font
|
||||
/// Use bold variant (each character is printed twice, 1px offset)
|
||||
#define FONT_BOLD 1 |
||||
/// Print characters 2x wider
|
||||
#define FONT_DOUBLEW 2 |
||||
/// Print characters 2x taller
|
||||
#define FONT_DOUBLEH 4 |
||||
/// Print characters 2x wider and taller
|
||||
#define FONT_DOUBLE (FONT_DOUBLEW | FONT_DOUBLEH) |
||||
|
||||
/// Print text stored in flash
|
||||
void fb_text_P(fbpos_t x, fbpos_t y, const char *text, uint8_t flags, fbcolor_t color); |
||||
|
||||
/// Print text stored in RAM
|
||||
void fb_text(fbpos_t x, fbpos_t y, const char *text, uint8_t flags, fbcolor_t color); |
||||
|
||||
#endif //UFB_FB_TEXT_H
|
||||
@ -0,0 +1,35 @@ |
||||
/**
|
||||
* UTF-8 capable bitmap font |
||||
* |
||||
* Created on 2020/01/04. |
||||
*/ |
||||
|
||||
#ifndef GFX_FONT_H |
||||
#define GFX_FONT_H |
||||
|
||||
#include "font.h" |
||||
#include "utf8.h" |
||||
#include <stdint.h> |
||||
|
||||
typedef struct { |
||||
uint8_t data[5]; |
||||
} font5x_bitmap_t; |
||||
|
||||
typedef struct { |
||||
uint8_t data[4]; |
||||
} font4x_bitmap_t; |
||||
|
||||
typedef struct { |
||||
uint8_t data[3]; |
||||
} font3x_bitmap_t; |
||||
|
||||
/// Get font graphic for a character.
|
||||
///
|
||||
/// The returned pointer is PROGMEM!
|
||||
const font5x_bitmap_t *font57_getsym(const struct Utf8Char *ch); |
||||
|
||||
const font4x_bitmap_t *font45_getsym(const struct Utf8Char *ch); |
||||
|
||||
const font3x_bitmap_t *font35_getsym(const struct Utf8Char *ch); |
||||
|
||||
#endif //GFX_FONT_H
|
||||
@ -0,0 +1,108 @@ |
||||
//
|
||||
// Created by MightyPork on 2022/11/12.
|
||||
//
|
||||
|
||||
#ifndef FRAMEBUFFER_H |
||||
#define FRAMEBUFFER_H |
||||
|
||||
#include <stdbool.h> |
||||
#include <stdint.h> |
||||
|
||||
#include "framebuffer_config.h" |
||||
|
||||
#define FBSET 0xFF |
||||
#define FBCLEAR 0x00 |
||||
|
||||
/// Width/height type
|
||||
typedef uint16_t fbsize_t; |
||||
/// Position type (X/Y)
|
||||
typedef int16_t fbpos_t; |
||||
/// Color type
|
||||
typedef uint8_t fbcolor_t; |
||||
|
||||
/// Bitmap struct
|
||||
typedef struct { |
||||
const uint8_t *data; |
||||
fbsize_t width; |
||||
fbsize_t height; |
||||
} fb_bitmap_t; |
||||
|
||||
#define FB_LEN ((FBH / 8) * FBW) |
||||
|
||||
/// Framebuffer backing array.
|
||||
///
|
||||
/// The format is the native format for SSD1306: array of bytes representing pixels in 8 rows at once, LSB is the topmost row.
|
||||
///
|
||||
/// a0 b0 ... til the display width
|
||||
/// a1 b1
|
||||
/// a2 b2
|
||||
/// ... ...
|
||||
/// a7 b7
|
||||
///
|
||||
/// and more bytes continue rows 8-15 and so on
|
||||
extern uint8_t fb[ FB_LEN ]; |
||||
|
||||
/// Fill the entire screen with a byte pattern.
|
||||
/// Use 0xFF or 0x00 for a solid fill. Other patterns may be used to create horizontal stripes.
|
||||
void fb_fill(uint8_t pattern); |
||||
|
||||
/// Invert the entire screen
|
||||
void fb_invert(); |
||||
|
||||
/// Clear the display (fill with 0x00)
|
||||
static inline void fb_clear(void) |
||||
{ |
||||
fb_fill(0); |
||||
} |
||||
|
||||
/// Fill screen with a repeating pattern
|
||||
///
|
||||
/// \param pattern - bytes to repeat, PROGMEM
|
||||
/// \param pattern_len - len of the pattern
|
||||
void fb_fill_pattern(const uint8_t* pattern, uint8_t pattern_len, fbcolor_t color); |
||||
|
||||
/// Set a single pixel
|
||||
void fb_px(fbpos_t x, fbpos_t y, fbcolor_t color); |
||||
|
||||
/// Get pixel color
|
||||
uint8_t fb_getpx(fbpos_t x, fbpos_t y); |
||||
|
||||
/// Draw a horizontal line
|
||||
void fb_hline(fbpos_t x, fbpos_t y, fbpos_t w, fbcolor_t color); |
||||
|
||||
/// Draw a vertical line
|
||||
void fb_vline(fbpos_t x, fbpos_t y, fbpos_t h, fbcolor_t color); |
||||
|
||||
/// Draw a filled rect
|
||||
void fb_rect(fbpos_t x, fbpos_t y, fbpos_t w, fbpos_t h, fbcolor_t color); |
||||
|
||||
/// Draw a frame (unfilled rect)
|
||||
void fb_frame(fbpos_t x, fbpos_t y, fbpos_t w, fbpos_t h, fbpos_t thickness, fbcolor_t color); |
||||
|
||||
/// Draw a bitmap from progmem
|
||||
#if IS_AVR |
||||
void fb_bitmap_ex_P(fbpos_t x, fbpos_t y, fbpos_t w, fbpos_t h, const uint8_t *map, fbcolor_t color); |
||||
#else |
||||
void fb_bitmap_ex(fbpos_t x, fbpos_t y, fbpos_t w, fbpos_t h, const uint8_t *map, fbcolor_t color); |
||||
#endif |
||||
|
||||
/// Draw a bitmap using the bitmap struct
|
||||
#if IS_AVR |
||||
static inline void fb_bitmap_P(fbpos_t x, fbpos_t y, const fb_bitmap_t *bitmap, fbcolor_t color) { |
||||
fb_bitmap_ex_P(x, y, bitmap->width, bitmap->height, bitmap->data, color); |
||||
} |
||||
#else |
||||
static inline void fb_bitmap(fbpos_t x, fbpos_t y, const fb_bitmap_t *bitmap, fbcolor_t color) { |
||||
fb_bitmap_ex(x, y, bitmap->width, bitmap->height, bitmap->data, color); |
||||
} |
||||
#endif |
||||
|
||||
/// Draw a circle
|
||||
void fb_circle(fbpos_t x, fbpos_t y, fbpos_t r, uint8_t thickness, fbcolor_t color); |
||||
|
||||
/// Output the framebuffer array `fb` to the display device.
|
||||
///
|
||||
/// The user must implement this
|
||||
extern void fb_blit(void); |
||||
|
||||
#endif //FRAMEBUFFER_H
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue