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409 lines
14 KiB
409 lines
14 KiB
2 years ago
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/**
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******************************************************************************
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* @file system_stm32f1xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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* factors, AHB/APBx prescalers and Flash settings).
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* This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f1xx_xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* 2. After each device reset the HSI (8 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
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* the product used), refer to "HSE_VALUE".
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* When HSE is used as system clock source, directly or through PLL, and you
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* are using different crystal you have to adapt the HSE value to your own
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* configuration.
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f1xx_system
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* @{
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*/
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/** @addtogroup STM32F1xx_System_Private_Includes
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* @{
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*/
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#include "stm32f1xx.h"
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_Defines
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* @{
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
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This value can be provided and adapted by the user application. */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
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This value can be provided and adapted by the user application. */
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#endif /* HSI_VALUE */
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/*!< Uncomment the following line if you need to use external SRAM */
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#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
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/* #define DATA_IN_ExtSRAM */
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#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
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/* Note: Following vector table addresses must be defined in line with linker
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configuration. */
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/*!< Uncomment the following line if you need to relocate the vector table
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anywhere in Flash or Sram, else the vector table is kept at the automatic
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remap of boot address selected */
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/* #define USER_VECT_TAB_ADDRESS */
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#if defined(USER_VECT_TAB_ADDRESS)
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/*!< Uncomment the following line if you need to relocate your vector Table
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in Sram else user remap will be done in Flash. */
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/* #define VECT_TAB_SRAM */
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#if defined(VECT_TAB_SRAM)
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#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
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This value must be a multiple of 0x200. */
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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#else
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#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
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This value must be a multiple of 0x200. */
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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#endif /* VECT_TAB_SRAM */
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#endif /* USER_VECT_TAB_ADDRESS */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 16000000;
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const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
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* @{
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*/
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#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
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#ifdef DATA_IN_ExtSRAM
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM */
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#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
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/**
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* @}
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*/
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/** @addtogroup STM32F1xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemCoreClock variable.
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* @note This function should be used only after reset.
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* @param None
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* @retval None
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*/
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void SystemInit (void)
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{
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#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
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#ifdef DATA_IN_ExtSRAM
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM */
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#endif
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/* Configure the Vector Table location -------------------------------------*/
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#if defined(USER_VECT_TAB_ADDRESS)
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SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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#endif /* USER_VECT_TAB_ADDRESS */
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
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* 8 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
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* 8 MHz or 25 MHz, depending on the product used), user has to ensure
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* that HSE_VALUE is same as the real frequency of the crystal used.
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* Otherwise, this function may have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
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#if defined(STM32F105xC) || defined(STM32F107xC)
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uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
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#endif /* STM32F105xC */
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#if defined(STM32F100xB) || defined(STM32F100xE)
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uint32_t prediv1factor = 0U;
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#endif /* STM32F100xB or STM32F100xE */
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00U: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04U: /* HSE used as system clock */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08U: /* PLL used as system clock */
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/* Get PLL clock source and multiplication factor ----------------------*/
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pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
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pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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#if !defined(STM32F105xC) && !defined(STM32F107xC)
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pllmull = ( pllmull >> 18U) + 2U;
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if (pllsource == 0x00U)
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{
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/* HSI oscillator clock divided by 2 selected as PLL clock entry */
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SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
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}
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else
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{
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#if defined(STM32F100xB) || defined(STM32F100xE)
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prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
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/* HSE oscillator clock selected as PREDIV1 clock entry */
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SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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#else
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/* HSE selected as PLL clock entry */
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if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
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{/* HSE oscillator clock divided by 2 */
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SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
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}
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else
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{
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SystemCoreClock = HSE_VALUE * pllmull;
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}
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#endif
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}
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#else
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pllmull = pllmull >> 18U;
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if (pllmull != 0x0DU)
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{
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pllmull += 2U;
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}
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else
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{ /* PLL multiplication factor = PLL input clock * 6.5 */
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pllmull = 13U / 2U;
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}
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if (pllsource == 0x00U)
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{
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/* HSI oscillator clock divided by 2 selected as PLL clock entry */
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SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
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}
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else
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{/* PREDIV1 selected as PLL clock entry */
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/* Get PREDIV1 clock source and division factor */
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prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
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prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
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if (prediv1source == 0U)
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{
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/* HSE oscillator clock selected as PREDIV1 clock entry */
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SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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}
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else
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{/* PLL2 clock selected as PREDIV1 clock entry */
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/* Get PREDIV2 division factor and PLL2 multiplication factor */
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prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
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pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
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SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
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}
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}
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#endif /* STM32F105xC */
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK clock frequency ----------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
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/**
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* @brief Setup the external memory controller. Called in startup_stm32f1xx.s
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* before jump to __main
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* @param None
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* @retval None
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*/
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#ifdef DATA_IN_ExtSRAM
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/**
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* @brief Setup the external memory controller.
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* Called in startup_stm32f1xx_xx.s/.c before jump to main.
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* This function configures the external SRAM mounted on STM3210E-EVAL
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* board (STM32 High density devices). This SRAM will be used as program
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* data memory (including heap and stack).
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* @param None
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* @retval None
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*/
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void SystemInit_ExtMemCtl(void)
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{
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__IO uint32_t tmpreg;
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||
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/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
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required, then adjust the Register Addresses */
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/* Enable FSMC clock */
|
||
|
|
RCC->AHBENR = 0x00000114U;
|
||
|
|
|
||
|
|
/* Delay after an RCC peripheral clock enabling */
|
||
|
|
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
|
||
|
|
|
||
|
|
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
|
||
|
|
RCC->APB2ENR = 0x000001E0U;
|
||
|
|
|
||
|
|
/* Delay after an RCC peripheral clock enabling */
|
||
|
|
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
|
||
|
|
|
||
|
|
(void)(tmpreg);
|
||
|
|
|
||
|
|
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
|
||
|
|
/*---------------- SRAM Address lines configuration -------------------------*/
|
||
|
|
/*---------------- NOE and NWE configuration --------------------------------*/
|
||
|
|
/*---------------- NE3 configuration ----------------------------------------*/
|
||
|
|
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
|
||
|
|
|
||
|
|
GPIOD->CRL = 0x44BB44BBU;
|
||
|
|
GPIOD->CRH = 0xBBBBBBBBU;
|
||
|
|
|
||
|
|
GPIOE->CRL = 0xB44444BBU;
|
||
|
|
GPIOE->CRH = 0xBBBBBBBBU;
|
||
|
|
|
||
|
|
GPIOF->CRL = 0x44BBBBBBU;
|
||
|
|
GPIOF->CRH = 0xBBBB4444U;
|
||
|
|
|
||
|
|
GPIOG->CRL = 0x44BBBBBBU;
|
||
|
|
GPIOG->CRH = 0x444B4B44U;
|
||
|
|
|
||
|
|
/*---------------- FSMC Configuration ---------------------------------------*/
|
||
|
|
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
|
||
|
|
|
||
|
|
FSMC_Bank1->BTCR[4U] = 0x00001091U;
|
||
|
|
FSMC_Bank1->BTCR[5U] = 0x00110212U;
|
||
|
|
}
|
||
|
|
#endif /* DATA_IN_ExtSRAM */
|
||
|
|
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|