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48 lines
2.3 KiB
48 lines
2.3 KiB
;********************************************************************************
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; SOUBOR : INI_BITS_WWDG.S
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; AUTOR : Petr Dousa, Ondrej Hruska
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; DATUM : 10/2015
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; POPIS : Bitove masky ridicich registru pro WWDG
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;
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; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
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;********************************************************************************
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;****************************************************************************
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;
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; Window WATCHDOG (WWDG)
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;
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;****************************************************************************
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;****************** Bit definition for WWDG_CR register *******************
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WWDG_CR_T EQU 0x7F ; T[6:0] bits (7-Bit counter (MSB to LSB))
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WWDG_CR_T0 EQU 0x01 ; Bit 0
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WWDG_CR_T1 EQU 0x02 ; Bit 1
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WWDG_CR_T2 EQU 0x04 ; Bit 2
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WWDG_CR_T3 EQU 0x08 ; Bit 3
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WWDG_CR_T4 EQU 0x10 ; Bit 4
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WWDG_CR_T5 EQU 0x20 ; Bit 5
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WWDG_CR_T6 EQU 0x40 ; Bit 6
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WWDG_CR_WDGA EQU 0x80 ; Activation bit
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;****************** Bit definition for WWDG_CFR register ******************
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WWDG_CFR_W EQU 0x007F ; W[6:0] bits (7-bit window value)
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WWDG_CFR_W0 EQU 0x0001 ; Bit 0
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WWDG_CFR_W1 EQU 0x0002 ; Bit 1
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WWDG_CFR_W2 EQU 0x0004 ; Bit 2
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WWDG_CFR_W3 EQU 0x0008 ; Bit 3
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WWDG_CFR_W4 EQU 0x0010 ; Bit 4
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WWDG_CFR_W5 EQU 0x0020 ; Bit 5
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WWDG_CFR_W6 EQU 0x0040 ; Bit 6
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WWDG_CFR_WDGTB EQU 0x0180 ; WDGTB[1:0] bits (Timer Base)
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WWDG_CFR_WDGTB0 EQU 0x0080 ; Bit 0
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WWDG_CFR_WDGTB1 EQU 0x0100 ; Bit 1
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WWDG_CFR_EWI EQU 0x0200 ; Early Wakeup Interrupt
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;****************** Bit definition for WWDG_SR register *******************
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WWDG_SR_EWIF EQU 0x01 ; Early Wakeup Interrupt Flag
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END
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