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103 lines
4.4 KiB
103 lines
4.4 KiB
;********************************************************************************
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; SOUBOR : INI_BASE.S
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; AUTOR : Ondrej Hruska
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; DATUM : 10/2015
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; POPIS : Zakladni soubor knihovny. Musi byt includovat pred vsemi ostatnimi.
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; Soubor definuje rozdeleni adresniho prostoru a adresy periferii.
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;
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; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
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;********************************************************************************
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FLASH_BASE EQU 0x08000000 ; FLASH base address in the alias region
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SRAM_BASE EQU 0x20000000 ; SRAM base address in the alias region
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PERIPH_BASE EQU 0x40000000 ; Peripheral base address in the alias region
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SRAM_BB_BASE EQU (SRAM_BASE + 0x02000000) ; SRAM base address in the bit-band region
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PERIPH_BB_BASE EQU (PERIPH_BASE + 0x02000000) ; Peripheral base address in the bit-band region
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; ------------------------- System Config Blocks -----------------------------
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_SCS_BASE EQU 0xE000E000 ; System Control Space base
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_SCB EQU (_SCS_BASE + 0x0D00) ; System Control Block base
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_NVIC EQU (_SCS_BASE + 0x0100) ; Nested Interrupt Vector Controller base
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_OB EQU 0x1FF80000 ; FLASH Option Bytes base address
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_AES EQU 0x50060000 ; Encryption module
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_FSMC EQU 0xA0000000 ; External Memory Control base
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_DBGMCU EQU 0xE0042000 ; Debug MCU registers base address
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; ----------------------------- Peripherals ----------------------------------
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; *** Peripheral bus bases ***
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_APB1 EQU PERIPH_BASE ; Advanced Peripheral Bus 1 base
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_APB2 EQU (PERIPH_BASE + 0x10000) ; Advanced Peripheral Bus 2 base
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_AHB EQU (PERIPH_BASE + 0x20000) ; Advanced High-speed Bus base
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; *** Peripheral Bus 1 devices ***
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_TIM2 EQU (_APB1 + 0x0000) ; Timer bases
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_TIM3 EQU (_APB1 + 0x0400)
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_TIM4 EQU (_APB1 + 0x0800)
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_TIM5 EQU (_APB1 + 0x0C00)
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_TIM6 EQU (_APB1 + 0x1000)
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_TIM7 EQU (_APB1 + 0x1400)
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_LCD EQU (_APB1 + 0x2400) ; LCD controller base
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_RTC EQU (_APB1 + 0x2800) ; RTC base
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_WWDG EQU (_APB1 + 0x2C00) ; Window Watchdog base
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_IWDG EQU (_APB1 + 0x3000) ; Independent Watchdog base
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_SPI2 EQU (_APB1 + 0x3800) ; SPI base
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_SPI3 EQU (_APB1 + 0x3C00)
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_USART2 EQU (_APB1 + 0x4400) ; USART base
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_USART3 EQU (_APB1 + 0x4800)
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_UART4 EQU (_APB1 + 0x4C00) ; UART base (?)
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_UART5 EQU (_APB1 + 0x5000)
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_I2C1 EQU (_APB1 + 0x5400) ; I2C base
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_I2C2 EQU (_APB1 + 0x5800)
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_PWR EQU (_APB1 + 0x7000) ; Power Control block base
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_DAC EQU (_APB1 + 0x7400) ; D/A config base
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_COMP EQU (_APB1 + 0x7C00) ; Analog Comparator base
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_RI EQU (_APB1 + 0x7C04) ; Routing Interface base (analog pin connections)
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_OPAMP EQU (_APB1 + 0x7C5C) ; OpAmp config base
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; *** Peripheral Bus 2 devices ***
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_TIM9 EQU (_APB2 + 0x0800) ; Timer base
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_TIM10 EQU (_APB2 + 0x0C00)
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_TIM11 EQU (_APB2 + 0x1000)
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_SYSCFG EQU (_APB2 + 0x0000) ; System config block base
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_EXTI EQU (_APB2 + 0x0400) ; External interrupt settings base
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_ADC1 EQU (_APB2 + 0x2400) ; A/D 1
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_ADCC EQU (_APB2 + 0x2700) ; common A/D registers base
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_SDIO EQU (_APB2 + 0x2C00) ; SD host
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_SPI1 EQU (_APB2 + 0x3000) ; SPI
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_USART1 EQU (_APB2 + 0x3800)
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; *** High Speed Bus devices ***
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_GPIO EQU (_AHB + 0x0000) ; GPIO block base
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_CRC EQU (_AHB + 0x3000) ; CRC module base
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_RCC EQU (_AHB + 0x3800) ; Reset and Clock Config base
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_DMA1 EQU (_AHB + 0x6000) ; DMA control base
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_DMA2 EQU (_AHB + 0x6400)
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_FLASH EQU (_AHB + 0x3C00) ; FLASH control base
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END
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