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106 lines
6.5 KiB
106 lines
6.5 KiB
;********************************************************************************
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; SOUBOR : INI_BITS_I2C.S
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; AUTOR : Petr Dousa, Ondrej Hruska
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; DATUM : 10/2015
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; POPIS : Bitove masky ridicich registru pro I2C
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;
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; Toto je soucast knihovny pro STM32L100 vyvijene na Katedre mereni FEL CVUT.
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;********************************************************************************
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;****************************************************************************
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;
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; Inter-integrated Circuit Interface (I2C)
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;
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;****************************************************************************
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;****************** Bit definition for I2C_CR1 register *******************
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I2C_CR1_PE EQU 0x0001 ; Peripheral Enable
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I2C_CR1_SMBUS EQU 0x0002 ; SMBus Mode
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I2C_CR1_SMBTYPE EQU 0x0008 ; SMBus Type
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I2C_CR1_ENARP EQU 0x0010 ; ARP Enable
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I2C_CR1_ENPEC EQU 0x0020 ; PEC Enable
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I2C_CR1_ENGC EQU 0x0040 ; General Call Enable
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I2C_CR1_NOSTRETCH EQU 0x0080 ; Clock Stretching Disable (Slave mode)
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I2C_CR1_START EQU 0x0100 ; Start Generation
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I2C_CR1_STOP EQU 0x0200 ; Stop Generation
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I2C_CR1_ACK EQU 0x0400 ; Acknowledge Enable
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I2C_CR1_POS EQU 0x0800 ; Acknowledge/PEC Position (for data reception)
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I2C_CR1_PEC EQU 0x1000 ; Packet Error Checking
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I2C_CR1_ALERT EQU 0x2000 ; SMBus Alert
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I2C_CR1_SWRST EQU 0x8000 ; Software Reset
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;****************** Bit definition for I2C_CR2 register *******************
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I2C_CR2_FREQ EQU 0x003F ; FREQ[5:0] bits (Peripheral Clock Frequency)
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I2C_CR2_FREQ_0 EQU 0x0001 ; Bit 0
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I2C_CR2_FREQ_1 EQU 0x0002 ; Bit 1
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I2C_CR2_FREQ_2 EQU 0x0004 ; Bit 2
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I2C_CR2_FREQ_3 EQU 0x0008 ; Bit 3
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I2C_CR2_FREQ_4 EQU 0x0010 ; Bit 4
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I2C_CR2_FREQ_5 EQU 0x0020 ; Bit 5
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I2C_CR2_ITERREN EQU 0x0100 ; Error Interrupt Enable
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I2C_CR2_ITEVTEN EQU 0x0200 ; Event Interrupt Enable
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I2C_CR2_ITBUFEN EQU 0x0400 ; Buffer Interrupt Enable
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I2C_CR2_DMAEN EQU 0x0800 ; DMA Requests Enable
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I2C_CR2_LAST EQU 0x1000 ; DMA Last Transfer
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;****************** Bit definition for I2C_OAR1 register ******************
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I2C_OAR1_ADD1_7 EQU 0x00FE ; Interface Address
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I2C_OAR1_ADD8_9 EQU 0x0300 ; Interface Address
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I2C_OAR1_ADD0 EQU 0x0001 ; Bit 0
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I2C_OAR1_ADD1 EQU 0x0002 ; Bit 1
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I2C_OAR1_ADD2 EQU 0x0004 ; Bit 2
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I2C_OAR1_ADD3 EQU 0x0008 ; Bit 3
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I2C_OAR1_ADD4 EQU 0x0010 ; Bit 4
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I2C_OAR1_ADD5 EQU 0x0020 ; Bit 5
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I2C_OAR1_ADD6 EQU 0x0040 ; Bit 6
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I2C_OAR1_ADD7 EQU 0x0080 ; Bit 7
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I2C_OAR1_ADD8 EQU 0x0100 ; Bit 8
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I2C_OAR1_ADD9 EQU 0x0200 ; Bit 9
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I2C_OAR1_ADDMODE EQU 0x8000 ; Addressing Mode (Slave mode)
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;****************** Bit definition for I2C_OAR2 register ******************
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I2C_OAR2_ENDUAL EQU 0x01 ; Dual addressing mode enable
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I2C_OAR2_ADD2 EQU 0xFE ; Interface address
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;******************* Bit definition for I2C_DR register *******************
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I2C_DR_DR EQU 0xFF ; 8-bit Data Register
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;****************** Bit definition for I2C_SR1 register *******************
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I2C_SR1_SB EQU 0x0001 ; Start Bit (Master mode)
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I2C_SR1_ADDR EQU 0x0002 ; Address sent (master mode)/matched (slave mode)
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I2C_SR1_BTF EQU 0x0004 ; Byte Transfer Finished
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I2C_SR1_ADD10 EQU 0x0008 ; 10-bit header sent (Master mode)
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I2C_SR1_STOPF EQU 0x0010 ; Stop detection (Slave mode)
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I2C_SR1_RXNE EQU 0x0040 ; Data Register not Empty (receivers)
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I2C_SR1_TXE EQU 0x0080 ; Data Register Empty (transmitters)
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I2C_SR1_BERR EQU 0x0100 ; Bus Error
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I2C_SR1_ARLO EQU 0x0200 ; Arbitration Lost (master mode)
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I2C_SR1_AF EQU 0x0400 ; Acknowledge Failure
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I2C_SR1_OVR EQU 0x0800 ; Overrun/Underrun
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I2C_SR1_PECERR EQU 0x1000 ; PEC Error in reception
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I2C_SR1_TIMEOUT EQU 0x4000 ; Timeout or Tlow Error
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I2C_SR1_SMBALERT EQU 0x8000 ; SMBus Alert
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;****************** Bit definition for I2C_SR2 register *******************
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I2C_SR2_MSL EQU 0x0001 ; Master/Slave
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I2C_SR2_BUSY EQU 0x0002 ; Bus Busy
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I2C_SR2_TRA EQU 0x0004 ; Transmitter/Receiver
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I2C_SR2_GENCALL EQU 0x0010 ; General Call Address (Slave mode)
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I2C_SR2_SMBDEFAULT EQU 0x0020 ; SMBus Device Default Address (Slave mode)
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I2C_SR2_SMBHOST EQU 0x0040 ; SMBus Host Header (Slave mode)
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I2C_SR2_DUALF EQU 0x0080 ; Dual Flag (Slave mode)
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I2C_SR2_PEC EQU 0xFF00 ; Packet Error Checking Register
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;****************** Bit definition for I2C_CCR register *******************
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I2C_CCR_CCR EQU 0x0FFF ; Clock Control Register in Fast/Standard mode (Master mode)
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I2C_CCR_DUTY EQU 0x4000 ; Fast Mode Duty Cycle
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I2C_CCR_FS EQU 0x8000 ; I2C Master Mode Selection
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;***************** Bit definition for I2C_TRISE register ******************
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I2C_TRISE_TRISE EQU 0x3F ; Maximum Rise Time in Fast/Standard mode (Master mode)
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END
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