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@ -16,17 +16,20 @@ |
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;*
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;****************************************************************************
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; FSMC
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_FSMC_B1 EQU (_FSMC + 0x0000) ; FSMC Bank1 registers base address
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_FSMC_B1E EQU (_FSMC + 0x0104) ; FSMC Bank1E registers base address
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; Bank 1
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FSMC_B1_BTCR EQU (_FSMC_B1 + 0x00) ; NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR),
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; Bank 2
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FSMC_B1E_BWTR EQU (_FSMC_B1E + 0x104) ; NOR/PSRAM write timing registers,
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; TODO missing some registers
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FSMC_BCR1 EQU (_FSCM + 0x0000) ; SRAM/NOR-Flash chip-select control registers
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FSMC_BCR2 EQU (_FSCM + 0x0008) ;
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FSMC_BCR3 EQU (_FSCM + 0x0010) ;
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FSMC_BCR4 EQU (_FSCM + 0x0018) ;
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FSMC_BTR1 EQU (_FSCM + 0x0004) ; SRAM/NOR-Flash chip-select timing registers
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FSMC_BTR2 EQU (_FSCM + 0x000C) ;
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FSMC_BTR3 EQU (_FSCM + 0x0014) ;
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FSMC_BTR4 EQU (_FSCM + 0x001C) ;
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FSMC_BWTR1 EQU (_FSCM + 0x0104) ; SRAM/NOR-Flash write timing registers
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FSMC_BWTR2 EQU (_FSCM + 0x010C) ;
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FSMC_BWTR3 EQU (_FSCM + 0x0114) ;
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FSMC_BWTR4 EQU (_FSCM + 0x011C) ;
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;****************************************************************************
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