Added examples

master
Ondřej Hruška 8 years ago
parent 0f63307ecf
commit 0e0d9df84e
  1. 6
      .gitignore
  2. 18
      examples/Delay.asm
  3. 31
      examples/F303K8/Cfg_GPIO.asm
  4. 81
      examples/F303K8/Cfg_RCC.asm
  5. 121
      examples/F303K8/Makefile
  6. 80
      examples/F303K8/main.asm
  7. BIN
      examples/F303K8/main.bin
  8. 11031
      examples/F303K8/sfr_f303x.asm
  9. 363
      examples/F303K8/startup_stm32f303x8.s
  10. 31
      examples/F303RE-Nucleo/Cfg_GPIO.asm
  11. 84
      examples/F303RE-Nucleo/Cfg_RCC.asm
  12. 121
      examples/F303RE-Nucleo/Makefile
  13. 80
      examples/F303RE-Nucleo/main.asm
  14. BIN
      examples/F303RE-Nucleo/main.bin
  15. 11650
      examples/F303RE-Nucleo/sfr_f303xE.asm
  16. 418
      examples/F303RE-Nucleo/startup_stm32f303xe.s
  17. 34
      examples/L100-Discovery/Cfg_GPIO.asm
  18. 59
      examples/L100-Discovery/Cfg_RCC.asm
  19. 121
      examples/L100-Discovery/Makefile
  20. 88
      examples/L100-Discovery/main.asm
  21. BIN
      examples/L100-Discovery/main.bin
  22. 5823
      examples/L100-Discovery/sfr_l100.asm
  23. 358
      examples/L100-Discovery/startup_stm32l100xc.s
  24. 10
      examples/README.md
  25. 128
      examples/main_example.asm

6
.gitignore vendored

@ -3,6 +3,12 @@
*.ko
*.obj
*.elf
*.axf
*.lst
*.dis
*.disasm
# Precompiled Headers
*.gch

@ -0,0 +1,18 @@
;;;-------------------------------------------------
;; Delay function. Duration in R0
;;
Delay PROC
PUSH {R0, R2, LR}
DELAY1
LDR R2, =40000
DELAY2 SUBS R2, #1
BNE DELAY2
SUBS R0, R0, #1
BNE DELAY1
POP {R0, R2, PC}
ENDP
;;
;;;-------------------------------------------------
END

@ -0,0 +1,31 @@
;;;-------------------------------------------------
;; Configure GPIO - PA5 as output (LED)
;;
Cfg_GPIO PROC
PUSH {R0-R2, LR}
; Enable GPIO clocks
LDR R2, =RCC_AHBENR ; AHBENR address
LDR R1, [R2]
LDR R0, =RCC_AHBENR_IOPAEN ; strange bit names, only on F303
ORR R1, R0
STR R1, [R2]
; Configure MODER
LDR R2, =GPIOA_MODER
LDR R1, [R2]
BIC R1, #GPIO_MODER_MODER5
LDR R0, =(2_01 << GPIO_MODER_MODER5_ofs); 2_01 = output mode
ORR R1, R0
; Store modified value back to MODER
STR R1, [R2]
; TODO: can now also configure OType and other registers
POP {R0-R2, PC}
ENDP
;;
;;;-------------------------------------------------
END

@ -0,0 +1,81 @@
;;;-------------------------------------------------
;; Configure the system clock & flash timing
;;
;; Code for F303x8, clock set to 48 MHz from HSI
;;
;; Different speed can be achieved by changing the value
;; of PLL_MUL in RCC_CFGR.
;;
Cfg_RCC PROC
PUSH {R0, R1, R2, LR}
; --- Flash timing config ---
; Frefetch, Latency
LDR R2, =FLASH_ACR
LDR R1, =(FLASH_ACR_PRFTBE :OR: (1 << FLASH_ACR_LATENCY_ofs))
STR R1, [R2]
; --- Internal High-speed Oscillator ---
; Power on HSI (runs from MSI on start)
LDR R2, =RCC_CR
LDR R1, [R2]
ORR R1, #RCC_CR_HSION
STR R1, [R2]
; Wait for HSIRDY
LDR R0, =RCC_CR
HsyWait LDR R1, [R0]
TST R1, #RCC_CR_HSIRDY
BEQ HsyWait
; --- PLL to get higher frequency ---
; Set up PLL
LDR R2, =RCC_CFGR
LDR R1, =0
ORR R1, #(2_100 << RCC_CFGR_PPRE1_ofs) ; APB1 divided by 2 (AHB, APB2 not divided - 0b000 in register)
ORR R1, #(2_00 << RCC_CFGR_PLLSRC_ofs) ; PPLSRC = HSI - 0b00 = HSI/2
ORR R1, #(2_1010 << RCC_CFGR_PLLMUL_ofs) ; PLL_MUL -> (8MHz / 2) x12 = 48MHz -- built-in PREDIV2 in k8
STR R1, [R2]
; Power on PLL
LDR R2, =RCC_CR
LDR R1, [R2]
ORR R1, #RCC_CR_PLLON
STR R1, [R2]
; Wait for PLLRDY
LDR R0, =RCC_CR
PllWait LDR R1, [R0]
TST R1, #RCC_CR_PLLRDY
BEQ PllWait
; --- Select PLL as source ---
; write 0b10 to RCC_CFGR_SW
; Select PLL as the core clock source
LDR R2, =RCC_CFGR
LDR R1, [R2]
; clear field
LDR R0, =RCC_CFGR_SW
BIC R1, R0
; select PLL
LDR R0, =(2_10 << RCC_CFGR_SW_ofs)
ORR R1, R0
; save
STR R1, [R2]
; TODO: should now wait for the switch (SWS == SW)
POP {R0, R1, R2, PC}
ENDP
;;
;;;-------------------------------------------------
END

@ -0,0 +1,121 @@
#####################################################################################
# File config
#####################################################################################
BINARY = main
STARTUP = startup_stm32f303x8
OBJS = $(STARTUP).o $(BINARY).o
lib_dir = lib/
#####################################################################################
# ASSEMBLER CONFIG
#####################################################################################
ASOPTS = --cpu Cortex-M4 -g --apcs interwork
# Add library to include path
ASOPTS += -I$(lib_dir)
#####################################################################################
# LINKER CONFIG
#####################################################################################
LDOPTS = --cpu Cortex-M4 --strict
LDOPTS += --bestdebug
LDOPTS += --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000
LDOPTS += --entry Reset_Handler --first __Vectors
# Verbose flags (run make V=1)
ifeq ($(V), 1)
LDOPTS += --summary_stderr --map --xref --callgraph --symbols
LDOPTS += --info summarysizes,sizes,totals,unused,veneers
endif
#####################################################################################
# EXTERNAL PROGRAMS
#####################################################################################
# armlink, armasm, fromelf - exe files in Wine directory (with Keil installed)
# Disable Wine fixme warnings
ENVS = WINEDEBUG=fixme-all
# Stop DS-5 from trying to use it's internal unlicensed compiler (Attempt at DRM?)
ENVS += ARMCC5_ASMOPT='' ARMCC5_CCOPT='' ARMCC5_FROMELFOPT='' ARMCC5_LINKOPT='' ARMCOMPILER6_ASMOPT='' ARMCOMPILER6_CLANGOPT=''
ENVS += ARMCOMPILER6_FROMELFOPT='' ARMCOMPILER6_LINKOPT='' ARM_PRODUCT_PATH='' ARM_TOOL_VARIANT=''
# ARM_PRODUCT_PATH should be possible to use if you want to run linux version of those programs.
WINEPREFIX=$(ENVS) wine ~/.wine/drive_c/Keil_v5/ARM/ARMCC_505u2/bin
# ARM programs from Keil
LD = $(WINEPREFIX)/armlink.exe
AS = $(WINEPREFIX)/armasm.exe
FROMELF = $(WINEPREFIX)/fromelf.exe
# Native programs
OBJDUMP = arm-none-eabi-objdump
STFLASH = st-flash
RM = rm
# --- END OF CONFIG ---
.PHONY: all build clean flash hex dis
all: build
# Link object files to AXF file
$(BINARY).axf: $(OBJS)
@echo "== Linking object files to $@ =="
@$(LD) $(LDOPTS) --output $@ $(OBJS)
# Get BIN image file from AXF file
%.bin: %.axf
@echo "== Converting $< to $@ =="
@$(FROMELF) --bincombined --output $@ $<
# Get Intel Hex file from AXF file
%.hex: %.axf
@echo "== Converting $< to $@ =="
@$(FROMELF) --i32combined --output $@ $<
# Get Object file from Assembler source file
%.o: %.asm
@echo "== Compiling $< to $@ =="
@$(AS) $(ASOPTS) -o $@ $<
@#--list $(basename $<).lst --depend $(basename $<).d
%.o: %.s
@echo "== Compiling $< to $@ =="
@$(AS) $(ASOPTS) -o $@ $<
@# --list $(basename $<).lst --depend $(basename $<).d
# Get binary image (compile and link)
build: $(BINARY).bin
# Get hex image (compile and link)
hex: $(BINARY).hex
# Run through linker
link: $(BINARY).axf
# Flash using st-link
flash: $(BINARY).bin
@echo "== Writing image to device via ST-Link =="
@$(STFLASH) write "$(BINARY).bin" 0x8000000
@echo "== Write OK! =="
dis: $(BINARY).axf
@echo "== Disassembling $< to $(BINARY).disasm =="
@$(OBJDUMP) -S -D $< > $(BINARY).dis
# Remove temporary files
clean:
@echo "== Removing temporary files =="
$(RM) -f *.bak *.lnp *.iex *.hex *.elf *.axf *.htm *.lnp *.lst *.plg *.tra *.o *.map *.d *.dep *.dis *.disasm *.bin *.uvguix.*
$(RM) -rf ./RTE

@ -0,0 +1,80 @@
;***************************************************************************************************
;*
;* F303k8 example
;*
;* (c) Ondrej Hruska, 2016
;*
;***************************************************************************************************
AREA MAIN, CODE, READONLY
; this is required by the startup script (?)
__use_two_region_memory
EXPORT __use_two_region_memory
;;;--- Include library files -----------------------
;;
GET sfr_f303x.asm
GET Cfg_RCC.asm
GET Cfg_GPIO.asm
GET ../Delay.asm
;;
;;;-------------------------------------------------
;;;-------------------------------------------------
;; System config.
;;
;; Called by startup script before __main
;;
SystemInit PROC
EXPORT SystemInit ; Export to startup script
PUSH {LR}
BL Cfg_RCC
BL Cfg_GPIO
POP {PC}
ENDP
;;
;;;-------------------------------------------------
;;;-------------------------------------------------
;; Main function
;;
;; Called by startup script after SystemInit.
;; __main is called only once, and does not return!
;;
ALIGN
__main PROC
EXPORT __main ; Export to startup script
MAIN_LOOP ; Main loop
LDR R0, =10
BL Delay
; Toggle LED at PA5
LDR R2, =GPIOA_ODR
LDR R1, [R2]
EOR R1, #GPIO_ODR_ODR5
STR R1, [R2]
B MAIN_LOOP ; Jump to start of the main loop
ENDP
;;
;;;-------------------------------------------------
;; end of file, aligned to 4 bytes
ALIGN
END

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@ -0,0 +1,363 @@
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f303x8.s
;* Author : MCD Application Team
;* Version : $VERSION$
;* Date : 12-Sept-2014
;* Description : STM32F303x6/x8 devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN_TX_IRQHandler ; CAN TX
DCD CAN_RX0_IRQHandler ; CAN RX0
DCD CAN_RX1_IRQHandler ; CAN RX1
DCD CAN_SCE_IRQHandler ; CAN SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1 and EXTI Line 25
DCD USART2_IRQHandler ; USART2 and EXTI Line 26
DCD USART3_IRQHandler ; USART3 and EXTI Line 28
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP2_IRQHandler ; COMP2
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TSC_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN_TX_IRQHandler [WEAK]
EXPORT CAN_RX0_IRQHandler [WEAK]
EXPORT CAN_RX1_IRQHandler [WEAK]
EXPORT CAN_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM6_DAC1_IRQHandler [WEAK]
EXPORT TIM7_DAC2_IRQHandler [WEAK]
EXPORT COMP2_IRQHandler [WEAK]
EXPORT COMP4_6_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_TSC_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN_TX_IRQHandler
CAN_RX0_IRQHandler
CAN_RX1_IRQHandler
CAN_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM6_DAC1_IRQHandler
TIM7_DAC2_IRQHandler
COMP2_IRQHandler
COMP4_6_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

@ -0,0 +1,31 @@
;;;-------------------------------------------------
;; Configure GPIO - PA5 as output (LED)
;;
Cfg_GPIO PROC
PUSH {R0-R2, LR}
; Enable GPIO clocks
LDR R2, =RCC_AHBENR ; AHBENR address
LDR R1, [R2]
LDR R0, =RCC_AHBENR_IOPAEN ; strange bit names, only on F303
ORR R1, R0
STR R1, [R2]
; Configure MODER
LDR R2, =GPIOA_MODER
LDR R1, [R2]
BIC R1, #GPIO_MODER_MODER5
LDR R0, =(2_01 << GPIO_MODER_MODER5_ofs); 2_01 = output mode
ORR R1, R0
; Store modified value back to MODER
STR R1, [R2]
; TODO: can now also configure OType and other registers
POP {R0-R2, PC}
ENDP
;;
;;;-------------------------------------------------
END

@ -0,0 +1,84 @@
;;;-------------------------------------------------
;; Configure the system clock & flash timing
;;
;; Code for F303RE, clock set to 48 MHz from HSI
;;
;; Different speed (16 MHz, 72 MHz) can be achieved
;; by changing the value of PLL_MUL in RCC_CFGR.
;;
;; !!! if changing speed to 72 MHz, Flash latency must
;; be changed to 2 wait states - see reference manual.
;;
Cfg_RCC PROC
PUSH {R0, R1, R2, LR}
; --- Flash timing config ---
; Frefetch, Latency
LDR R2, =FLASH_ACR
LDR R1, =(FLASH_ACR_PRFTBE :OR: (1 << FLASH_ACR_LATENCY_ofs))
STR R1, [R2]
; --- Internal High-speed Oscillator ---
; Power on HSI (runs from MSI on start)
LDR R2, =RCC_CR
LDR R1, [R2]
ORR R1, #RCC_CR_HSION
STR R1, [R2]
; Wait for HSIRDY
LDR R0, =RCC_CR
HsyWait LDR R1, [R0]
TST R1, #RCC_CR_HSIRDY
BEQ HsyWait
; --- PLL to get higher frequency ---
; Set up PLL
LDR R2, =RCC_CFGR
LDR R1, =0
ORR R1, #(2_100 << RCC_CFGR_PPRE2_ofs) ; PPRE2 divided by 2 (AHB, APB1 not divided - zero)
ORR R1, #(1 << RCC_CFGR_PLLSRC_ofs) ; PPLSRC = HSI
ORR R1, #(2_0100 << RCC_CFGR_PLLMUL_ofs) ; PLL_MUL -> 8MHz x6 = 48MHz
STR R1, [R2]
; Power on PLL
LDR R2, =RCC_CR
LDR R1, [R2]
ORR R1, #RCC_CR_PLLON
STR R1, [R2]
; Wait for PLLRDY
LDR R0, =RCC_CR
PllWait LDR R1, [R0]
TST R1, #RCC_CR_PLLRDY
BEQ PllWait
; --- Select PLL as source ---
; write 0b10 to RCC_CFGR_SW
; Select PLL as the core clock source
LDR R2, =RCC_CFGR
LDR R1, [R2]
; clear field
LDR R0, =RCC_CFGR_SW
BIC R1, R0
; select PLL
LDR R0, =(2_10 << RCC_CFGR_SW_ofs)
ORR R1, R0
; save
STR R1, [R2]
; TODO: should now wait for the switch (SWS == SW)
POP {R0, R1, R2, PC}
ENDP
;;
;;;-------------------------------------------------
END

@ -0,0 +1,121 @@
#####################################################################################
# File config
#####################################################################################
BINARY = main
STARTUP = startup_stm32f303xe
OBJS = $(STARTUP).o $(BINARY).o
lib_dir = lib/
#####################################################################################
# ASSEMBLER CONFIG
#####################################################################################
ASOPTS = --cpu Cortex-M4 -g --apcs interwork
# Add library to include path
ASOPTS += -I$(lib_dir)
#####################################################################################
# LINKER CONFIG
#####################################################################################
LDOPTS = --cpu Cortex-M4 --strict
LDOPTS += --bestdebug
LDOPTS += --ro-base 0x08000000 --entry 0x08000000 --rw-base 0x20000000
LDOPTS += --entry Reset_Handler --first __Vectors
# Verbose flags (run make V=1)
ifeq ($(V), 1)
LDOPTS += --summary_stderr --map --xref --callgraph --symbols
LDOPTS += --info summarysizes,sizes,totals,unused,veneers
endif
#####################################################################################
# EXTERNAL PROGRAMS
#####################################################################################
# armlink, armasm, fromelf - exe files in Wine directory (with Keil installed)
# Disable Wine fixme warnings
ENVS = WINEDEBUG=fixme-all
# Stop DS-5 from trying to use it's internal unlicensed compiler (Attempt at DRM?)
ENVS += ARMCC5_ASMOPT='' ARMCC5_CCOPT='' ARMCC5_FROMELFOPT='' ARMCC5_LINKOPT='' ARMCOMPILER6_ASMOPT='' ARMCOMPILER6_CLANGOPT=''
ENVS += ARMCOMPILER6_FROMELFOPT='' ARMCOMPILER6_LINKOPT='' ARM_PRODUCT_PATH='' ARM_TOOL_VARIANT=''
# ARM_PRODUCT_PATH should be possible to use if you want to run linux version of those programs.
WINEPREFIX=$(ENVS) wine ~/.wine/drive_c/Keil_v5/ARM/ARMCC_505u2/bin
# ARM programs from Keil
LD = $(WINEPREFIX)/armlink.exe
AS = $(WINEPREFIX)/armasm.exe
FROMELF = $(WINEPREFIX)/fromelf.exe
# Native programs
OBJDUMP = arm-none-eabi-objdump
STFLASH = st-flash
RM = rm
# --- END OF CONFIG ---
.PHONY: all build clean flash hex dis
all: build
# Link object files to AXF file
$(BINARY).axf: $(OBJS)
@echo "== Linking object files to $@ =="
@$(LD) $(LDOPTS) --output $@ $(OBJS)
# Get BIN image file from AXF file
%.bin: %.axf
@echo "== Converting $< to $@ =="
@$(FROMELF) --bincombined --output $@ $<
# Get Intel Hex file from AXF file
%.hex: %.axf
@echo "== Converting $< to $@ =="
@$(FROMELF) --i32combined --output $@ $<
# Get Object file from Assembler source file
%.o: %.asm
@echo "== Compiling $< to $@ =="
@$(AS) $(ASOPTS) -o $@ $<
@#--list $(basename $<).lst --depend $(basename $<).d
%.o: %.s
@echo "== Compiling $< to $@ =="
@$(AS) $(ASOPTS) -o $@ $<
@# --list $(basename $<).lst --depend $(basename $<).d
# Get binary image (compile and link)
build: $(BINARY).bin
# Get hex image (compile and link)
hex: $(BINARY).hex
# Run through linker
link: $(BINARY).axf
# Flash using st-link
flash: $(BINARY).bin
@echo "== Writing image to device via ST-Link =="
@$(STFLASH) write "$(BINARY).bin" 0x8000000
@echo "== Write OK! =="
dis: $(BINARY).axf
@echo "== Disassembling $< to $(BINARY).disasm =="
@$(OBJDUMP) -S -D $< > $(BINARY).dis
# Remove temporary files
clean:
@echo "== Removing temporary files =="
$(RM) -f *.bak *.lnp *.iex *.hex *.elf *.axf *.htm *.lnp *.lst *.plg *.tra *.o *.map *.d *.dep *.dis *.disasm *.bin *.uvguix.*
$(RM) -rf ./RTE

@ -0,0 +1,80 @@
;***************************************************************************************************
;*
;* F303RE Nucleo "blinky" example
;*
;* (c) Ondrej Hruska, 2016
;*
;***************************************************************************************************
AREA MAIN, CODE, READONLY
; this is required by the startup script (?)
__use_two_region_memory
EXPORT __use_two_region_memory
;;;--- Include library files -----------------------
;;
GET sfr_f303xE.asm
GET Cfg_RCC.asm
GET Cfg_GPIO.asm
GET ../Delay.asm
;;
;;;-------------------------------------------------
;;;-------------------------------------------------
;; System config.
;;
;; Called by startup script before __main
;;
SystemInit PROC
EXPORT SystemInit ; Export to startup script
PUSH {LR}
BL Cfg_RCC
BL Cfg_GPIO
POP {PC}
ENDP
;;
;;;-------------------------------------------------
;;;-------------------------------------------------
;; Main function
;;
;; Called by startup script after SystemInit.
;; __main is called only once, and does not return!
;;
ALIGN
__main PROC
EXPORT __main ; Export to startup script
MAIN_LOOP ; Main loop
LDR R0, =100
BL Delay
; Toggle LED at PA5
LDR R2, =GPIOA_ODR
LDR R1, [R2]
EOR R1, #GPIO_ODR_ODR5
STR R1, [R2]
B MAIN_LOOP ; Jump to start of the main loop
ENDP
;;
;;;-------------------------------------------------
;; end of file, aligned to 4 bytes
ALIGN
END

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@ -0,0 +1,418 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f303xe.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F303xE devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD TIM20_BRK_IRQHandler ; TIM20 Break
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI4_IRQHandler ; SPI4
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TS_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]