added driver directories and bsp

master
Ondřej Hruška 7 years ago
parent 018b69cdc8
commit 11ccc7496e
  1. 1
      .gitignore
  2. 46
      .idea/workspace.xml
  3. 208
      Drivers/BSP/Components/sx1272/Release_Notes.html
  4. 1703
      Drivers/BSP/Components/sx1272/sx1272.c
  5. 523
      Drivers/BSP/Components/sx1272/sx1272.h
  6. 1134
      Drivers/BSP/Components/sx1272/sx1272Regs-Fsk.h
  7. 545
      Drivers/BSP/Components/sx1272/sx1272Regs-LoRa.h
  8. 269
      Drivers/BSP/sx1272mb2das/Release_Notes.html
  9. 262
      Drivers/BSP/sx1272mb2das/sx1272mb2das.c
  10. 98
      Drivers/BSP/sx1272mb2das/sx1272mb2das.h
  11. 147
      Middlewares/Third_Party/Lora/Conf/Commissioning_template.h
  12. 154
      Middlewares/Third_Party/Lora/Conf/Inc/hw_gpio_template.h
  13. 181
      Middlewares/Third_Party/Lora/Conf/Inc/hw_rtc_template.h
  14. 128
      Middlewares/Third_Party/Lora/Conf/Inc/hw_spi_template.h
  15. 87
      Middlewares/Third_Party/Lora/Conf/Inc/hw_template.h
  16. 192
      Middlewares/Third_Party/Lora/Conf/Src/hw_gpio_template.c
  17. 632
      Middlewares/Third_Party/Lora/Conf/Src/hw_rtc_template.c
  18. 224
      Middlewares/Third_Party/Lora/Conf/Src/hw_spi_template.c
  19. 773
      Middlewares/Third_Party/Lora/Core/lora.c
  20. 251
      Middlewares/Third_Party/Lora/Core/lora.h
  21. 88
      Middlewares/Third_Party/Lora/Core/lora_mac_version.h
  22. 936
      Middlewares/Third_Party/Lora/Crypto/aes.c
  23. 160
      Middlewares/Third_Party/Lora/Crypto/aes.h
  24. 153
      Middlewares/Third_Party/Lora/Crypto/cmac.c
  25. 63
      Middlewares/Third_Party/Lora/Crypto/cmac.h
  26. 25
      Middlewares/Third_Party/Lora/LICENSE.txt
  27. 3353
      Middlewares/Third_Party/Lora/Mac/LoRaMac.c
  28. 1961
      Middlewares/Third_Party/Lora/Mac/LoRaMac.h
  29. 202
      Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.c
  30. 111
      Middlewares/Third_Party/Lora/Mac/LoRaMacCrypto.h
  31. 81
      Middlewares/Third_Party/Lora/Mac/LoRaMacTest.h
  32. 1037
      Middlewares/Third_Party/Lora/Mac/region/Region.c
  33. 1492
      Middlewares/Third_Party/Lora/Mac/region/Region.h
  34. 1101
      Middlewares/Third_Party/Lora/Mac/region/RegionAS923.c
  35. 503
      Middlewares/Third_Party/Lora/Mac/region/RegionAS923.h
  36. 863
      Middlewares/Third_Party/Lora/Mac/region/RegionAU915.c
  37. 455
      Middlewares/Third_Party/Lora/Mac/region/RegionAU915.h
  38. 814
      Middlewares/Third_Party/Lora/Mac/region/RegionCN470.c
  39. 441
      Middlewares/Third_Party/Lora/Mac/region/RegionCN470.h
  40. 1051
      Middlewares/Third_Party/Lora/Mac/region/RegionCN779.c
  41. 465
      Middlewares/Third_Party/Lora/Mac/region/RegionCN779.h
  42. 362
      Middlewares/Third_Party/Lora/Mac/region/RegionCommon.c
  43. 367
      Middlewares/Third_Party/Lora/Mac/region/RegionCommon.h
  44. 1051
      Middlewares/Third_Party/Lora/Mac/region/RegionEU433.c
  45. 466
      Middlewares/Third_Party/Lora/Mac/region/RegionEU433.h
  46. 1082
      Middlewares/Third_Party/Lora/Mac/region/RegionEU868.c
  47. 487
      Middlewares/Third_Party/Lora/Mac/region/RegionEU868.h
  48. 1051
      Middlewares/Third_Party/Lora/Mac/region/RegionIN865.c
  49. 468
      Middlewares/Third_Party/Lora/Mac/region/RegionIN865.h
  50. 1052
      Middlewares/Third_Party/Lora/Mac/region/RegionKR920.c
  51. 478
      Middlewares/Third_Party/Lora/Mac/region/RegionKR920.h
  52. 964
      Middlewares/Third_Party/Lora/Mac/region/RegionUS915-Hybrid.c
  53. 448
      Middlewares/Third_Party/Lora/Mac/region/RegionUS915-Hybrid.h
  54. 871
      Middlewares/Third_Party/Lora/Mac/region/RegionUS915.c
  55. 448
      Middlewares/Third_Party/Lora/Mac/region/RegionUS915.h
  56. 86
      Middlewares/Third_Party/Lora/Mac/timer.h
  57. 350
      Middlewares/Third_Party/Lora/Phy/radio.h
  58. 77
      Middlewares/Third_Party/Lora/Utilities/delay.c
  59. 29
      Middlewares/Third_Party/Lora/Utilities/delay.h
  60. 149
      Middlewares/Third_Party/Lora/Utilities/low_power.c
  61. 98
      Middlewares/Third_Party/Lora/Utilities/low_power.h
  62. 406
      Middlewares/Third_Party/Lora/Utilities/timeServer.c
  63. 164
      Middlewares/Third_Party/Lora/Utilities/timeServer.h
  64. 85
      Middlewares/Third_Party/Lora/Utilities/utilities.c
  65. 175
      Middlewares/Third_Party/Lora/Utilities/utilities.h
  66. 750
      Middlewares/Third_Party/Lora/readme.md
  67. 182
      Middlewares/Third_Party/Lora/st_readme.txt

1
.gitignore vendored

@ -3,3 +3,4 @@ cmake-*
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<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
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<span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 08-September-2017</span>
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<span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
Redistribution and use in source and binary forms, with or without
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met:
</span>
<br>
</font>
<ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
in binary form must reproduce the above copyright notice, this list of
conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived
</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">from this software without specific prior written permission.</span><br>
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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: Generic SX1272 driver implementation
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
/*******************************************************************************
* @file sx1272.h
* @author MCD Application Team
* @version V1.0.1
* @date 08-September-2017
* @brief Header for driver sx1272.c
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __SX1272_H__
#define __SX1272_H__
#include "sx1272Regs-Fsk.h"
#include "sx1272Regs-LoRa.h"
/*!
* Radio wake-up time from sleep
*/
#define RADIO_WAKEUP_TIME 2 // [ms]
/*!
* Sync word for Private LoRa networks
*/
#define LORA_MAC_PRIVATE_SYNCWORD 0x12
/*!
* Sync word for Public LoRa networks
*/
#define LORA_MAC_PUBLIC_SYNCWORD 0x34
/*!
* Radio FSK modem parameters
*/
typedef struct
{
int8_t Power;
uint32_t Fdev;
uint32_t Bandwidth;
uint32_t BandwidthAfc;
uint32_t Datarate;
uint16_t PreambleLen;
bool FixLen;
uint8_t PayloadLen;
bool CrcOn;
bool IqInverted;
bool RxContinuous;
uint32_t TxTimeout;
uint32_t RxSingleTimeout;
}RadioFskSettings_t;
/*!
* Radio FSK packet handler state
*/
typedef struct
{
uint8_t PreambleDetected;
uint8_t SyncWordDetected;
int8_t RssiValue;
int32_t AfcValue;
uint8_t RxGain;
uint16_t Size;
uint16_t NbBytes;
uint8_t FifoThresh;
uint8_t ChunkSize;
}RadioFskPacketHandler_t;
/*!
* Radio LoRa modem parameters
*/
typedef struct
{
int8_t Power;
uint32_t Bandwidth;
uint32_t Datarate;
bool LowDatarateOptimize;
uint8_t Coderate;
uint16_t PreambleLen;
bool FixLen;
uint8_t PayloadLen;
bool CrcOn;
bool FreqHopOn;
uint8_t HopPeriod;
bool IqInverted;
bool RxContinuous;
uint32_t TxTimeout;
bool PublicNetwork;
}RadioLoRaSettings_t;
/*!
* Radio LoRa packet handler state
*/
typedef struct
{
int8_t SnrValue;
int16_t RssiValue;
uint8_t Size;
}RadioLoRaPacketHandler_t;
/*!
* Radio Settings
*/
typedef struct
{
RadioState_t State;
RadioModems_t Modem;
uint32_t Channel;
RadioFskSettings_t Fsk;
RadioFskPacketHandler_t FskPacketHandler;
RadioLoRaSettings_t LoRa;
RadioLoRaPacketHandler_t LoRaPacketHandler;
}RadioSettings_t;
/*!
* Radio hardware and global parameters
*/
typedef struct SX1272_s
{
uint8_t RxTx;
RadioSettings_t Settings;
}SX1272_t;
extern SX1272_t SX1272;
/*!
* Hardware IO IRQ callback function definition
*/
typedef void ( DioIrqHandler )( void );
/*!
* SX1272 definitions
*/
#define XTAL_FREQ 32000000
#define FREQ_STEP 61.03515625
#define FREQ_STEP_8 15625 /* FREQ_STEP<<8 */
/*!
* \brief Radio hardware registers initialization definition
*
* \remark Can be automatically generated by the SX1272 GUI (not yet implemented)
*/
#define RADIO_INIT_REGISTERS_VALUE \
{ \
{ MODEM_FSK , REG_LNA , 0x23 },\
{ MODEM_FSK , REG_RXCONFIG , 0x1E },\
{ MODEM_FSK , REG_RSSICONFIG , 0xD2 },\
{ MODEM_FSK , REG_AFCFEI , 0x01 },\
{ MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },\
{ MODEM_FSK , REG_OSC , 0x07 },\
{ MODEM_FSK , REG_SYNCCONFIG , 0x12 },\
{ MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },\
{ MODEM_FSK , REG_SYNCVALUE2 , 0x94 },\
{ MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },\
{ MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },\
{ MODEM_FSK , REG_FIFOTHRESH , 0x8F },\
{ MODEM_FSK , REG_IMAGECAL , 0x02 },\
{ MODEM_FSK , REG_DIOMAPPING1 , 0x00 },\
{ MODEM_FSK , REG_DIOMAPPING2 , 0x30 },\
{ MODEM_LORA, REG_LR_DETECTOPTIMIZE , 0x43 },\
{ MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\
} \
/* Freq = channel * FREQ_STEP */
#define SX_CHANNEL_TO_FREQ( channel, freq ) \
do \
{ \
uint32_t initialChanInt, initialChanFrac; \
initialChanInt = channel >> 8; \
initialChanFrac = channel - ( initialChanInt << 8 ); \
freq = initialChanInt * FREQ_STEP_8 + ( ( initialChanFrac * FREQ_STEP_8 + ( 128 ) ) >> 8 ); \
}while( 0 )
/* channel = Freq / FREQ_STEP */
#define SX_FREQ_TO_CHANNEL( channel, freq ) \
do \
{ \
uint32_t initialFreqInt, initialFreqFrac; \
initialFreqInt = freq / FREQ_STEP_8; \
initialFreqFrac = freq - ( initialFreqInt * FREQ_STEP_8 ); \
channel = ( initialFreqInt << 8 ) + ( ( ( initialFreqFrac << 8 ) + ( FREQ_STEP_8 / 2 ) ) / FREQ_STEP_8 ); \
}while( 0 )
#define RX_BUFFER_SIZE 256
typedef struct sBoardCallback
{
/*!
* \brief Set XO state on the board
*/
void ( *SX1272BoardSetXO )( uint8_t state );
/*!
* \brief Get Board Wake Up time
*/
uint32_t ( *SX1272BoardGetWakeTime )( void );
/*!
* \brief Initializes the radio I/Os Irq
*/
void ( *SX1272BoardIoIrqInit )( DioIrqHandler **irqHandlers );
/*!
* \brief Sets the radio output power.
*
* \param [IN] power Sets the RF output power
*/
void ( *SX1272BoardSetRfTxPower )( int8_t power );
/*!
* \brief Set the RF Switch I/Os pins in Low Power mode
*
* \param [IN] status enable or disable
*/
void ( *SX1272BoardSetAntSwLowPower )( bool status );
/*!
* \brief Controls the antena switch if necessary.
*
* \remark see errata note
*
* \param [IN] opMode Current radio operating mode
*/
void ( *SX1272BoardSetAntSw )( uint8_t opMode );
}LoRaBoardCallback_t;
/*!
* ============================================================================
* Public functions prototypes
* ============================================================================
*/
void SX1272BoardInit( LoRaBoardCallback_t *callbacks );
/*!
* \brief Initializes the radio
*
* \param [IN] events Structure containing the driver callback functions
* \param [OUT] returns the wake up time of the radio and associated board
*/
uint32_t SX1272Init( RadioEvents_t *events );
/*!
* Return current radio status
*
* \param status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING]
*/
RadioState_t SX1272GetStatus( void );
/*!
* \brief Configures the radio with the given modem
*
* \param [IN] modem Modem to be used [0: FSK, 1: LoRa]
*/
void SX1272SetModem( RadioModems_t modem );
/*!
* \brief Sets the channel configuration
*
* \param [IN] freq Channel RF frequency
*/
void SX1272SetChannel( uint32_t freq );
/*!
* \brief Checks if the channel is free for the given time
*
* \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
* \param [IN] freq Channel RF frequency
* \param [IN] rssiThresh RSSI threshold
* \param [IN] maxCarrierSenseTime Max time while the RSSI is measured
*
* \retval isFree [true: Channel is free, false: Channel is not free]
*/
bool SX1272IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime );
/*!
* \brief Generates a 32 bits random value based on the RSSI readings
*
* \remark This function sets the radio in LoRa modem mode and disables
* all interrupts.
* After calling this function either SX1272SetRxConfig or
* SX1272SetTxConfig functions must be called.
*
* \retval randomValue 32 bits random value
*/
uint32_t SX1272Random( void );
/*!
* \brief Sets the reception parameters
*
* \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
* \param [IN] bandwidth Sets the bandwidth
* FSK : >= 2600 and <= 250000 Hz
* LoRa: [0: 125 kHz, 1: 250 kHz,
* 2: 500 kHz, 3: Reserved]
* \param [IN] datarate Sets the Datarate
* FSK : 600..300000 bits/s
* LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
* 10: 1024, 11: 2048, 12: 4096 chips]
* \param [IN] coderate Sets the coding rate (LoRa only)
* FSK : N/A ( set to 0 )
* LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
* \param [IN] bandwidthAfc Sets the AFC Bandwidth (FSK only)
* FSK : >= 2600 and <= 250000 Hz
* LoRa: N/A ( set to 0 )
* \param [IN] preambleLen Sets the Preamble length
* FSK : Number of bytes
* LoRa: Length in symbols (the hardware adds 4 more symbols)
* \param [IN] symbTimeout Sets the RxSingle timeout value
* FSK : timeout number of bytes
* LoRa: timeout in symbols
* \param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
* \param [IN] payloadLen Sets payload length when fixed length is used
* \param [IN] crcOn Enables/Disables the CRC [0: OFF, 1: ON]
* \param [IN] freqHopOn Enables disables the intra-packet frequency hopping
* FSK : N/A ( set to 0 )
* LoRa: [0: OFF, 1: ON]
* \param [IN] hopPeriod Number of symbols between each hop
* FSK : N/A ( set to 0 )
* LoRa: Number of symbols
* \param [IN] iqInverted Inverts IQ signals (LoRa only)
* FSK : N/A ( set to 0 )
* LoRa: [0: not inverted, 1: inverted]
* \param [IN] rxContinuous Sets the reception in continuous mode
* [false: single mode, true: continuous mode]
*/
void SX1272SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
uint32_t datarate, uint8_t coderate,
uint32_t bandwidthAfc, uint16_t preambleLen,
uint16_t symbTimeout, bool fixLen,
uint8_t payloadLen,
bool crcOn, bool freqHopOn, uint8_t hopPeriod,
bool iqInverted, bool rxContinuous );
/*!
* \brief Sets the transmission parameters
*
* \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
* \param [IN] power Sets the output power [dBm]
* \param [IN] fdev Sets the frequency deviation (FSK only)
* FSK : [Hz]
* LoRa: 0
* \param [IN] bandwidth Sets the bandwidth (LoRa only)
* FSK : 0
* LoRa: [0: 125 kHz, 1: 250 kHz,
* 2: 500 kHz, 3: Reserved]
* \param [IN] datarate Sets the Datarate
* FSK : 600..300000 bits/s
* LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
* 10: 1024, 11: 2048, 12: 4096 chips]
* \param [IN] coderate Sets the coding rate (LoRa only)
* FSK : N/A ( set to 0 )
* LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
* \param [IN] preambleLen Sets the preamble length
* FSK : Number of bytes
* LoRa: Length in symbols (the hardware adds 4 more symbols)
* \param [IN] fixLen Fixed length packets [0: variable, 1: fixed]
* \param [IN] crcOn Enables disables the CRC [0: OFF, 1: ON]
* \param [IN] freqHopOn Enables disables the intra-packet frequency hopping
* FSK : N/A ( set to 0 )
* LoRa: [0: OFF, 1: ON]
* \param [IN] hopPeriod Number of symbols between each hop
* FSK : N/A ( set to 0 )
* LoRa: Number of symbols
* \param [IN] iqInverted Inverts IQ signals (LoRa only)
* FSK : N/A ( set to 0 )
* LoRa: [0: not inverted, 1: inverted]
* \param [IN] timeout Transmission timeout [ms]
*/
void SX1272SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
uint32_t bandwidth, uint32_t datarate,
uint8_t coderate, uint16_t preambleLen,
bool fixLen, bool crcOn, bool freqHopOn,
uint8_t hopPeriod, bool iqInverted, uint32_t timeout );
/*!
* \brief Computes the packet time on air in ms for the given payload
*
* \Remark Can only be called once SetRxConfig or SetTxConfig have been called
*
* \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
* \param [IN] pktLen Packet payload length
*
* \retval airTime Computed airTime (ms) for the given packet payload length
*/
uint32_t SX1272GetTimeOnAir( RadioModems_t modem, uint8_t pktLen );
/*!
* \brief Sends the buffer of size. Prepares the packet to be sent and sets
* the radio in transmission
*
* \param [IN]: buffer Buffer pointer
* \param [IN]: size Buffer size
*/
void SX1272Send( uint8_t *buffer, uint8_t size );
/*!
* \brief Sets the radio in sleep mode
*/
void SX1272SetSleep( void );
/*!
* \brief Sets the radio in standby mode
*/
void SX1272SetStby( void );
/*!
* \brief Sets the radio in reception mode for the given time
* \param [IN] timeout Reception timeout [ms] [0: continuous, others timeout]
*/
void SX1272SetRx( uint32_t timeout );
/*!
* \brief Start a Channel Activity Detection
*/
void SX1272StartCad( void );
/*!
* \brief Sets the radio in continuous wave transmission mode
*
* \param [IN]: freq Channel RF frequency
* \param [IN]: power Sets the output power [dBm]
* \param [IN]: time Transmission mode timeout [s]
*/
void SX1272SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time );
/*!
* \brief Reads the current RSSI value
*
* \retval rssiValue Current RSSI value in [dBm]
*/
int16_t SX1272ReadRssi( RadioModems_t modem );
/*!
* \brief Writes the radio register at the specified address
*
* \param [IN]: addr Register address
* \param [IN]: data New register value
*/
void SX1272Write( uint8_t addr, uint8_t data );
/*!
* \brief Reads the radio register at the specified address
*
* \param [IN]: addr Register address
* \retval data Register value
*/
uint8_t SX1272Read( uint8_t addr );
/*!
* \brief Writes multiple radio registers starting at address
*
* \param [IN] addr First Radio register address
* \param [IN] buffer Buffer containing the new register's values
* \param [IN] size Number of registers to be written
*/
void SX1272WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size );
/*!
* \brief Reads multiple radio registers starting at address
*
* \param [IN] addr First Radio register address
* \param [OUT] buffer Buffer where to copy the registers data
* \param [IN] size Number of registers to be read
*/
void SX1272ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size );
/*!
* \brief Sets the maximum payload length.
*
* \param [IN] modem Radio modem to be used [0: FSK, 1: LoRa]
* \param [IN] max Maximum payload length in bytes
*/
void SX1272SetMaxPayloadLength( RadioModems_t modem, uint8_t max );
/*!
* \brief Sets the network to public or private. Updates the sync byte.
*
* \remark Applies to LoRa modem only
*
* \param [IN] enable if true, it enables a public network
*/
void SX1272SetPublicNetwork( bool enable );
/*!
* \brief Service to get the radio wake-up time.
*
* \retval Value of the radio wake-up time.
*/
uint32_t SX1272GetRadioWakeUpTime( void );
#endif /* __SX1272_H__ */

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/*
/ _____) _ | |
( (____ _____ ____ _| |_ _____ ____| |__
\____ \| ___ | (_ _) ___ |/ ___) _ \
_____) ) ____| | | || |_| ____( (___| | | |
(______/|_____)_|_|_| \__)_____)\____)_| |_|
(C)2013 Semtech
Description: SX1272 LoRa modem registers and bits definitions
License: Revised BSD License, see LICENSE.TXT file include in the project
Maintainer: Miguel Luis and Gregory Cristian
*/
#ifndef __SX1272_REGS_LORA_H__
#define __SX1272_REGS_LORA_H__
/*!
* ============================================================================
* SX1272 Internal registers Address
* ============================================================================
*/
#define REG_LR_FIFO 0x00
// Common settings
#define REG_LR_OPMODE 0x01
#define REG_LR_FRFMSB 0x06
#define REG_LR_FRFMID 0x07
#define REG_LR_FRFLSB 0x08
// Tx settings
#define REG_LR_PACONFIG 0x09
#define REG_LR_PARAMP 0x0A
#define REG_LR_OCP 0x0B
// Rx settings
#define REG_LR_LNA 0x0C
// LoRa registers
#define REG_LR_FIFOADDRPTR 0x0D
#define REG_LR_FIFOTXBASEADDR 0x0E
#define REG_LR_FIFORXBASEADDR 0x0F
#define REG_LR_FIFORXCURRENTADDR 0x10
#define REG_LR_IRQFLAGSMASK 0x11
#define REG_LR_IRQFLAGS 0x12
#define REG_LR_RXNBBYTES 0x13
#define REG_LR_RXHEADERCNTVALUEMSB 0x14
#define REG_LR_RXHEADERCNTVALUELSB 0x15
#define REG_LR_RXPACKETCNTVALUEMSB 0x16
#define REG_LR_RXPACKETCNTVALUELSB 0x17
#define REG_LR_MODEMSTAT 0x18
#define REG_LR_PKTSNRVALUE 0x19
#define REG_LR_PKTRSSIVALUE 0x1A
#define REG_LR_RSSIVALUE 0x1B
#define REG_LR_HOPCHANNEL 0x1C
#define REG_LR_MODEMCONFIG1 0x1D
#define REG_LR_MODEMCONFIG2 0x1E
#define REG_LR_SYMBTIMEOUTLSB 0x1F
#define REG_LR_PREAMBLEMSB 0x20
#define REG_LR_PREAMBLELSB 0x21
#define REG_LR_PAYLOADLENGTH 0x22
#define REG_LR_PAYLOADMAXLENGTH 0x23
#define REG_LR_HOPPERIOD 0x24
#define REG_LR_FIFORXBYTEADDR 0x25
#define REG_LR_FEIMSB 0x28
#define REG_LR_FEIMID 0x29
#define REG_LR_FEILSB 0x2A
#define REG_LR_RSSIWIDEBAND 0x2C
#define REG_LR_DETECTOPTIMIZE 0x31
#define REG_LR_INVERTIQ 0x33
#define REG_LR_DETECTIONTHRESHOLD 0x37
#define REG_LR_SYNCWORD 0x39
#define REG_LR_INVERTIQ2 0x3B
// end of documented register in datasheet
// I/O settings
#define REG_LR_DIOMAPPING1 0x40
#define REG_LR_DIOMAPPING2 0x41
// Version
#define REG_LR_VERSION 0x42
// Additional settings
#define REG_LR_AGCREF 0x43
#define REG_LR_AGCTHRESH1 0x44
#define REG_LR_AGCTHRESH2 0x45
#define REG_LR_AGCTHRESH3 0x46
#define REG_LR_PLLHOP 0x4B
#define REG_LR_TCXO 0x58
#define REG_LR_PADAC 0x5A
#define REG_LR_PLL 0x5C
#define REG_LR_PLLLOWPN 0x5E
#define REG_LR_FORMERTEMP 0x6C
/*!
* ============================================================================
* SX1272 LoRa bits control definition
* ============================================================================
*/
/*!
* RegFifo
*/
/*!
* RegOpMode
*/
#define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F
#define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default
#define RFLR_OPMODE_LONGRANGEMODE_ON 0x80
#define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF
#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40
#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default
#define RFLR_OPMODE_MASK 0xF8
#define RFLR_OPMODE_SLEEP 0x00
#define RFLR_OPMODE_STANDBY 0x01 // Default
#define RFLR_OPMODE_SYNTHESIZER_TX 0x02
#define RFLR_OPMODE_TRANSMITTER 0x03
#define RFLR_OPMODE_SYNTHESIZER_RX 0x04
#define RFLR_OPMODE_RECEIVER 0x05
// LoRa specific modes
#define RFLR_OPMODE_RECEIVER_SINGLE 0x06
#define RFLR_OPMODE_CAD 0x07
/*!
* RegFrf (MHz)
*/
#define RFLR_FRFMSB_915_MHZ 0xE4 // Default
#define RFLR_FRFMID_915_MHZ 0xC0 // Default
#define RFLR_FRFLSB_915_MHZ 0x00 // Default
/*!
* RegPaConfig
*/
#define RFLR_PACONFIG_PASELECT_MASK 0x7F
#define RFLR_PACONFIG_PASELECT_PABOOST 0x80
#define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
#define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
/*!
* RegPaRamp
*/
#define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0
#define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default
#define RFLR_PARAMP_LOWPNTXPLL_ON 0x00
#define RFLR_PARAMP_MASK 0xF0
#define RFLR_PARAMP_3400_US 0x00
#define RFLR_PARAMP_2000_US 0x01
#define RFLR_PARAMP_1000_US 0x02
#define RFLR_PARAMP_0500_US 0x03
#define RFLR_PARAMP_0250_US 0x04
#define RFLR_PARAMP_0125_US 0x05
#define RFLR_PARAMP_0100_US 0x06
#define RFLR_PARAMP_0062_US 0x07
#define RFLR_PARAMP_0050_US 0x08
#define RFLR_PARAMP_0040_US 0x09 // Default
#define RFLR_PARAMP_0031_US 0x0A
#define RFLR_PARAMP_0025_US 0x0B
#define RFLR_PARAMP_0020_US 0x0C
#define RFLR_PARAMP_0015_US 0x0D
#define RFLR_PARAMP_0012_US 0x0E
#define RFLR_PARAMP_0010_US 0x0F
/*!
* RegOcp
*/
#define RFLR_OCP_MASK 0xDF
#define RFLR_OCP_ON 0x20 // Default
#define RFLR_OCP_OFF 0x00
#define RFLR_OCP_TRIM_MASK 0xE0
#define RFLR_OCP_TRIM_045_MA 0x00
#define RFLR_OCP_TRIM_050_MA 0x01
#define RFLR_OCP_TRIM_055_MA 0x02
#define RFLR_OCP_TRIM_060_MA 0x03
#define RFLR_OCP_TRIM_065_MA 0x04
#define RFLR_OCP_TRIM_070_MA 0x05
#define RFLR_OCP_TRIM_075_MA 0x06
#define RFLR_OCP_TRIM_080_MA 0x07
#define RFLR_OCP_TRIM_085_MA 0x08
#define RFLR_OCP_TRIM_090_MA 0x09
#define RFLR_OCP_TRIM_095_MA 0x0A
#define RFLR_OCP_TRIM_100_MA 0x0B // Default
#define RFLR_OCP_TRIM_105_MA 0x0C
#define RFLR_OCP_TRIM_110_MA 0x0D
#define RFLR_OCP_TRIM_115_MA 0x0E
#define RFLR_OCP_TRIM_120_MA 0x0F
#define RFLR_OCP_TRIM_130_MA 0x10
#define RFLR_OCP_TRIM_140_MA 0x11
#define RFLR_OCP_TRIM_150_MA 0x12
#define RFLR_OCP_TRIM_160_MA 0x13
#define RFLR_OCP_TRIM_170_MA 0x14
#define RFLR_OCP_TRIM_180_MA 0x15
#define RFLR_OCP_TRIM_190_MA 0x16
#define RFLR_OCP_TRIM_200_MA 0x17
#define RFLR_OCP_TRIM_210_MA 0x18
#define RFLR_OCP_TRIM_220_MA 0x19
#define RFLR_OCP_TRIM_230_MA 0x1A
#define RFLR_OCP_TRIM_240_MA 0x1B
/*!
* RegLna
*/
#define RFLR_LNA_GAIN_MASK 0x1F
#define RFLR_LNA_GAIN_G1 0x20 // Default
#define RFLR_LNA_GAIN_G2 0x40
#define RFLR_LNA_GAIN_G3 0x60
#define RFLR_LNA_GAIN_G4 0x80
#define RFLR_LNA_GAIN_G5 0xA0
#define RFLR_LNA_GAIN_G6 0xC0
#define RFLR_LNA_BOOST_MASK 0xFC
#define RFLR_LNA_BOOST_OFF 0x00 // Default
#define RFLR_LNA_BOOST_ON 0x03
/*!
* RegFifoAddrPtr
*/
#define RFLR_FIFOADDRPTR 0x00 // Default
/*!
* RegFifoTxBaseAddr
*/
#define RFLR_FIFOTXBASEADDR 0x80 // Default
/*!
* RegFifoTxBaseAddr
*/
#define RFLR_FIFORXBASEADDR 0x00 // Default
/*!
* RegFifoRxCurrentAddr (Read Only)
*/
/*!
* RegIrqFlagsMask
*/
#define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
#define RFLR_IRQFLAGS_RXDONE_MASK 0x40
#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
#define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
#define RFLR_IRQFLAGS_TXDONE_MASK 0x08
#define RFLR_IRQFLAGS_CADDONE_MASK 0x04
#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
#define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
/*!
* RegIrqFlags
*/
#define RFLR_IRQFLAGS_RXTIMEOUT 0x80
#define RFLR_IRQFLAGS_RXDONE 0x40
#define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
#define RFLR_IRQFLAGS_VALIDHEADER 0x10
#define RFLR_IRQFLAGS_TXDONE 0x08
#define RFLR_IRQFLAGS_CADDONE 0x04
#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
#define RFLR_IRQFLAGS_CADDETECTED 0x01
/*!
* RegFifoRxNbBytes (Read Only)
*/
/*!
* RegRxHeaderCntValueMsb (Read Only)
*/
/*!
* RegRxHeaderCntValueLsb (Read Only)
*/
/*!
* RegRxPacketCntValueMsb (Read Only)
*/
/*!
* RegRxPacketCntValueLsb (Read Only)
*/
/*!
* RegModemStat (Read Only)
*/
#define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
#define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
/*!
* RegPktSnrValue (Read Only)
*/
/*!
* RegPktRssiValue (Read Only)
*/
/*!
* RegRssiValue (Read Only)
*/
/*!
* RegHopChannel (Read Only)
*/
#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
#define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF
#define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40
#define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default
#define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
/*!
* RegModemConfig1
*/
#define RFLR_MODEMCONFIG1_BW_MASK 0x3F
#define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default
#define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40
#define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80
#define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7
#define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08
#define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default
#define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18
#define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04
#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default
#define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD
#define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02
#define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default
#define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE
#define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01
#define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
/*!
* RegModemConfig2
*/
#define RFLR_MODEMCONFIG2_SF_MASK 0x0F
#define RFLR_MODEMCONFIG2_SF_6 0x60
#define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
#define RFLR_MODEMCONFIG2_SF_8 0x80
#define RFLR_MODEMCONFIG2_SF_9 0x90
#define RFLR_MODEMCONFIG2_SF_10 0xA0
#define RFLR_MODEMCONFIG2_SF_11 0xB0
#define RFLR_MODEMCONFIG2_SF_12 0xC0
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
#define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB
#define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default
#define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
/*!
* RegSymbTimeoutLsb
*/
#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
/*!
* RegPreambleLengthMsb
*/
#define RFLR_PREAMBLELENGTHMSB 0x00 // Default
/*!
* RegPreambleLengthLsb
*/
#define RFLR_PREAMBLELENGTHLSB 0x08 // Default
/*!
* RegPayloadLength
*/
#define RFLR_PAYLOADLENGTH 0x0E // Default
/*!
* RegPayloadMaxLength
*/
#define RFLR_PAYLOADMAXLENGTH 0xFF // Default
/*!
* RegHopPeriod
*/
#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
/*!
* RegFifoRxByteAddr (Read Only)
*/
/*!
* RegFeiMsb (Read Only)
*/
/*!
* RegFeiMid (Read Only)
*/
/*!
* RegFeiLsb (Read Only)
*/
/*!
* RegRssiWideband (Read Only)
*/
/*!
* RegDetectOptimize
*/
#define RFLR_DETECTIONOPTIMIZE_MASK 0xF8
#define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default
#define RFLR_DETECTIONOPTIMIZE_SF6 0x05
/*!
* RegInvertIQ
*/
#define RFLR_INVERTIQ_RX_MASK 0xBF
#define RFLR_INVERTIQ_RX_OFF 0x00
#define RFLR_INVERTIQ_RX_ON 0x40
#define RFLR_INVERTIQ_TX_MASK 0xFE
#define RFLR_INVERTIQ_TX_OFF 0x01
#define RFLR_INVERTIQ_TX_ON 0x00
/*!
* RegDetectionThreshold
*/
#define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default
#define RFLR_DETECTIONTHRESH_SF6 0x0C
/*!
* RegInvertIQ2
*/
#define RFLR_INVERTIQ2_ON 0x19
#define RFLR_INVERTIQ2_OFF 0x1D
/*!
* RegDioMapping1
*/
#define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
#define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO0_01 0x40
#define RFLR_DIOMAPPING1_DIO0_10 0x80
#define RFLR_DIOMAPPING1_DIO0_11 0xC0
#define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
#define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO1_01 0x10
#define RFLR_DIOMAPPING1_DIO1_10 0x20
#define RFLR_DIOMAPPING1_DIO1_11 0x30
#define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
#define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
#define RFLR_DIOMAPPING1_DIO2_01 0x04
#define RFLR_DIOMAPPING1_DIO2_10 0x08
#define RFLR_DIOMAPPING1_DIO2_11 0x0C
#define RFLR_DIOMAPPING1_DIO3_MASK 0xFC