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@ -0,0 +1,14 @@ |
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[PreviousGenFiles] |
||||
HeaderPath=/home/ondra/spd/cubeproject/nortos/proj/Inc |
||||
HeaderFiles=gpio.h;i2c.h;rtc.h;spi.h;usart.h;stm32l0xx_it.h;stm32l0xx_hal_conf.h;main.h; |
||||
SourcePath=/home/ondra/spd/cubeproject/nortos/proj/Src |
||||
SourceFiles=gpio.c;i2c.c;rtc.c;spi.c;usart.c;stm32l0xx_it.c;stm32l0xx_hal_msp.c;main.c; |
||||
|
||||
[PreviousLibFiles] |
||||
LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/arm_common_tables.h; |
||||
|
||||
[PreviousUsedSW4STM32Files] |
||||
SourceFiles=../Src/main.c;../Src/gpio.c;../Src/i2c.c;../Src/rtc.c;../Src/spi.c;../Src/usart.c;../Src/stm32l0xx_it.c;../Src/stm32l0xx_hal_msp.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;../Src/system_stm32l0xx.c;../Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;../Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l073xx.s; |
||||
HeaderPath=../Drivers/STM32L0xx_HAL_Driver/Inc;../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32L0xx/Include;../Drivers/CMSIS/Include;../Inc; |
||||
CDefines=__weak:"__attribute__((weak))";__packed:"__attribute__((__packed__))"; |
||||
|
||||
@ -0,0 +1,30 @@ |
||||
<?xml version="1.0" encoding="UTF-8"?> |
||||
<projectDescription> |
||||
<name>proj</name> |
||||
<comment /> |
||||
<projects> |
||||
</projects> |
||||
<buildSpec> |
||||
<buildCommand> |
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> |
||||
<triggers>clean,full,incremental,</triggers> |
||||
<arguments> |
||||
</arguments> |
||||
</buildCommand> |
||||
<buildCommand> |
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> |
||||
<triggers>full,incremental,</triggers> |
||||
<arguments> |
||||
</arguments> |
||||
</buildCommand> |
||||
</buildSpec> |
||||
<natures> |
||||
<nature>org.eclipse.cdt.core.cnature</nature> |
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> |
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> |
||||
<nature>fr.ac6.mcu.ide.core.MCUProjectNature</nature> |
||||
</natures> |
||||
<linkedResources> |
||||
|
||||
</linkedResources> |
||||
</projectDescription> |
||||
@ -0,0 +1,27 @@ |
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?> |
||||
<project> |
||||
<configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1636346117" name="Debug"> |
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> |
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> |
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> |
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> |
||||
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/> |
||||
<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1176636128779449975" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> |
||||
<language-scope id="org.eclipse.cdt.core.gcc"/> |
||||
<language-scope id="org.eclipse.cdt.core.g++"/> |
||||
</provider> |
||||
</extension> |
||||
</configuration> |
||||
<configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.release.2060462303" name="Release"> |
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> |
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> |
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> |
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> |
||||
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/> |
||||
<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1176636128779449975" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> |
||||
<language-scope id="org.eclipse.cdt.core.gcc"/> |
||||
<language-scope id="org.eclipse.cdt.core.g++"/> |
||||
</provider> |
||||
</extension> |
||||
</configuration> |
||||
</project> |
||||
@ -0,0 +1,73 @@ |
||||
eclipse.preferences.version=1 |
||||
fr.ac6.mcu.ide.source.checker.libnano.problem=Error |
||||
fr.ac6.mcu.ide.source.checker.libnano.problem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Float formatting support\\")"} |
||||
org.eclipse.cdt.codan.checkers.errnoreturn=Warning |
||||
org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} |
||||
org.eclipse.cdt.codan.checkers.errreturnvalue=Error |
||||
org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} |
||||
org.eclipse.cdt.codan.checkers.nocommentinside=-Error |
||||
org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} |
||||
org.eclipse.cdt.codan.checkers.nolinecomment=-Error |
||||
org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} |
||||
org.eclipse.cdt.codan.checkers.noreturn=Error |
||||
org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} |
||||
org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error |
||||
org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false} |
||||
org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} |
||||
org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} |
||||
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error |
||||
org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info |
||||
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} |
||||
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning |
||||
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning |
||||
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()} |
||||
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false} |
||||
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false} |
||||
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} |
||||
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} |
||||
@ -0,0 +1,93 @@ |
||||
cmake_minimum_required(VERSION 3.9) |
||||
project(proj) |
||||
|
||||
set(CMAKE_CXX_STANDARD 11) |
||||
|
||||
set(SOURCE_FILES |
||||
Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h |
||||
Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h |
||||
Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h |
||||
Drivers/CMSIS/Include/arm_common_tables.h |
||||
Drivers/CMSIS/Include/arm_const_structs.h |
||||
Drivers/CMSIS/Include/arm_math.h |
||||
Drivers/CMSIS/Include/cmsis_armcc.h |
||||
Drivers/CMSIS/Include/cmsis_armcc_V6.h |
||||
Drivers/CMSIS/Include/cmsis_gcc.h |
||||
Drivers/CMSIS/Include/core_cm0.h |
||||
Drivers/CMSIS/Include/core_cm0plus.h |
||||
Drivers/CMSIS/Include/core_cm3.h |
||||
Drivers/CMSIS/Include/core_cm4.h |
||||
Drivers/CMSIS/Include/core_cm7.h |
||||
Drivers/CMSIS/Include/core_cmFunc.h |
||||
Drivers/CMSIS/Include/core_cmInstr.h |
||||
Drivers/CMSIS/Include/core_cmSimd.h |
||||
Drivers/CMSIS/Include/core_sc000.h |
||||
Drivers/CMSIS/Include/core_sc300.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c |
||||
Inc/gpio.h |
||||
Inc/i2c.h |
||||
Inc/main.h |
||||
Inc/rtc.h |
||||
Inc/spi.h |
||||
Inc/stm32l0xx_hal_conf.h |
||||
Inc/stm32l0xx_it.h |
||||
Inc/usart.h |
||||
Src/gpio.c |
||||
Src/i2c.c |
||||
Src/main.c |
||||
Src/rtc.c |
||||
Src/spi.c |
||||
Src/stm32l0xx_hal_msp.c |
||||
Src/stm32l0xx_it.c |
||||
Src/system_stm32l0xx.c |
||||
Src/usart.c) |
||||
|
||||
include_directories(Drivers/CMSIS/Device/ST/STM32L0xx/Include) |
||||
include_directories(Drivers/CMSIS/Include) |
||||
include_directories(Drivers/STM32L0xx_HAL_Driver/Inc) |
||||
include_directories(Drivers/STM32L0xx_HAL_Driver/Inc/Legacy) |
||||
include_directories(Inc) |
||||
|
||||
add_executable(proj ${SOURCE_FILES}) |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,241 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx.h |
||||
* @author MCD Application Team |
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for STM32L0xx devices.
|
||||
*
|
||||
* The file is the unique include file that the application programmer |
||||
* is using in the C source code, usually in main.c. This file contains: |
||||
* - Configuration section that allows to select: |
||||
* - The device used in the target application |
||||
* - To use or not the peripheral's drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral's registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER" |
||||
*
|
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup stm32l0xx
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifndef __STM32L0xx_H |
||||
#define __STM32L0xx_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif /* __cplusplus */ |
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief STM32 Family |
||||
*/ |
||||
#if !defined (STM32L0) |
||||
#define STM32L0 |
||||
#endif /* STM32L0 */ |
||||
|
||||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/ |
||||
|
||||
#if !defined (STM32L011xx) && !defined (STM32L021xx) && \ |
||||
!defined (STM32L031xx) && !defined (STM32L041xx) && \
|
||||
!defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
|
||||
!defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \
|
||||
!defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
|
||||
!defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \
|
||||
/* #define STM32L011xx */ |
||||
/* #define STM32L021xx */ |
||||
/* #define STM32L031xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */ |
||||
/* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */ |
||||
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */ |
||||
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */ |
||||
/* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */ |
||||
/* #define STM32L061xx */ /*!< */ |
||||
/* #define STM32L062xx */ /*!< STM32L062K8 */ |
||||
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
|
||||
/* #define STM32L071xx */ /*!< */ |
||||
/* #define STM32L072xx */ /*!< */ |
||||
/* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */ |
||||
/* #define STM32L081xx */ /*!< */ |
||||
/* #define STM32L082xx */ /*!< */ |
||||
/* #define STM32L083xx */ /*!< */
|
||||
#endif |
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor. |
||||
*/ |
||||
#if !defined (USE_HAL_DRIVER) |
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers. |
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/ |
||||
/*#define USE_HAL_DRIVER */ |
||||
#endif /* USE_HAL_DRIVER */ |
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.7.1 |
||||
*/ |
||||
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ |
||||
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ |
||||
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ |
||||
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ |
||||
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\ |
||||
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__STM32L0xx_CMSIS_VERSION_RC)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{ |
||||
*/ |
||||
#if defined(STM32L011xx) |
||||
#include "stm32l011xx.h" |
||||
#elif defined(STM32L021xx) |
||||
#include "stm32l021xx.h" |
||||
#elif defined(STM32L031xx) |
||||
#include "stm32l031xx.h" |
||||
#elif defined(STM32L041xx) |
||||
#include "stm32l041xx.h" |
||||
#elif defined(STM32L051xx) |
||||
#include "stm32l051xx.h" |
||||
#elif defined(STM32L052xx) |
||||
#include "stm32l052xx.h" |
||||
#elif defined(STM32L053xx) |
||||
#include "stm32l053xx.h" |
||||
#elif defined(STM32L062xx) |
||||
#include "stm32l062xx.h" |
||||
#elif defined(STM32L063xx) |
||||
#include "stm32l063xx.h" |
||||
#elif defined(STM32L061xx) |
||||
#include "stm32l061xx.h" |
||||
#elif defined(STM32L071xx) |
||||
#include "stm32l071xx.h" |
||||
#elif defined(STM32L072xx) |
||||
#include "stm32l072xx.h" |
||||
#elif defined(STM32L073xx) |
||||
#include "stm32l073xx.h" |
||||
#elif defined(STM32L082xx) |
||||
#include "stm32l082xx.h" |
||||
#elif defined(STM32L083xx) |
||||
#include "stm32l083xx.h" |
||||
#elif defined(STM32L081xx) |
||||
#include "stm32l081xx.h" |
||||
#else |
||||
#error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)" |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{ |
||||
*/
|
||||
typedef enum
|
||||
{ |
||||
RESET = 0,
|
||||
SET = !RESET |
||||
} FlagStatus, ITStatus; |
||||
|
||||
typedef enum
|
||||
{ |
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE |
||||
} FunctionalState; |
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
||||
|
||||
typedef enum
|
||||
{ |
||||
ERROR = 0,
|
||||
SUCCESS = !ERROR |
||||
} ErrorStatus; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{ |
||||
*/ |
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) |
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT)) |
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0)) |
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) |
||||
|
||||
#define READ_REG(REG) ((REG)) |
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined (USE_HAL_DRIVER) |
||||
#include "stm32l0xx_hal.h" |
||||
#endif /* USE_HAL_DRIVER */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif /* __cplusplus */ |
||||
|
||||
#endif /* __STM32L0xx_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,125 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file system_stm32l0xx.h |
||||
* @author MCD Application Team |
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup stm32l0xx_system
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion |
||||
*/ |
||||
#ifndef __SYSTEM_STM32L0XX_H |
||||
#define __SYSTEM_STM32L0XX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/** @addtogroup STM32L0xx_System_Includes
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @addtogroup STM32L0xx_System_Exported_types
|
||||
* @{ |
||||
*/ |
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate() |
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq() |
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there |
||||
is no need to call the 2 first functions listed above, since SystemCoreClock |
||||
variable is updated automatically. |
||||
*/ |
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ |
||||
/*
|
||||
*/ |
||||
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ |
||||
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ |
||||
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
extern void SystemInit(void); |
||||
extern void SystemCoreClockUpdate(void); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /*__SYSTEM_STM32L0XX_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,136 @@ |
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
||||
* |
||||
* $Date: 19. October 2015 |
||||
* $Revision: V.1.4.5 a |
||||
* |
||||
* Project: CMSIS DSP Library |
||||
* Title: arm_common_tables.h |
||||
* |
||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions |
||||
* |
||||
* Target Processor: Cortex-M4/Cortex-M3 |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without |
||||
* modification, are permitted provided that the following conditions |
||||
* are met: |
||||
* - Redistributions of source code must retain the above copyright |
||||
* notice, this list of conditions and the following disclaimer. |
||||
* - Redistributions in binary form must reproduce the above copyright |
||||
* notice, this list of conditions and the following disclaimer in |
||||
* the documentation and/or other materials provided with the |
||||
* distribution. |
||||
* - Neither the name of ARM LIMITED nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this |
||||
* software without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
* POSSIBILITY OF SUCH DAMAGE. |
||||
* -------------------------------------------------------------------- */ |
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H |
||||
#define _ARM_COMMON_TABLES_H |
||||
|
||||
#include "arm_math.h" |
||||
|
||||
extern const uint16_t armBitRevTable[1024]; |
||||
extern const q15_t armRecipTableQ15[64]; |
||||
extern const q31_t armRecipTableQ31[64]; |
||||
/* extern const q31_t realCoefAQ31[1024]; */ |
||||
/* extern const q31_t realCoefBQ31[1024]; */ |
||||
extern const float32_t twiddleCoef_16[32]; |
||||
extern const float32_t twiddleCoef_32[64]; |
||||
extern const float32_t twiddleCoef_64[128]; |
||||
extern const float32_t twiddleCoef_128[256]; |
||||
extern const float32_t twiddleCoef_256[512]; |
||||
extern const float32_t twiddleCoef_512[1024]; |
||||
extern const float32_t twiddleCoef_1024[2048]; |
||||
extern const float32_t twiddleCoef_2048[4096]; |
||||
extern const float32_t twiddleCoef_4096[8192]; |
||||
#define twiddleCoef twiddleCoef_4096 |
||||
extern const q31_t twiddleCoef_16_q31[24]; |
||||
extern const q31_t twiddleCoef_32_q31[48]; |
||||
extern const q31_t twiddleCoef_64_q31[96]; |
||||
extern const q31_t twiddleCoef_128_q31[192]; |
||||
extern const q31_t twiddleCoef_256_q31[384]; |
||||
extern const q31_t twiddleCoef_512_q31[768]; |
||||
extern const q31_t twiddleCoef_1024_q31[1536]; |
||||
extern const q31_t twiddleCoef_2048_q31[3072]; |
||||
extern const q31_t twiddleCoef_4096_q31[6144]; |
||||
extern const q15_t twiddleCoef_16_q15[24]; |
||||
extern const q15_t twiddleCoef_32_q15[48]; |
||||
extern const q15_t twiddleCoef_64_q15[96]; |
||||
extern const q15_t twiddleCoef_128_q15[192]; |
||||
extern const q15_t twiddleCoef_256_q15[384]; |
||||
extern const q15_t twiddleCoef_512_q15[768]; |
||||
extern const q15_t twiddleCoef_1024_q15[1536]; |
||||
extern const q15_t twiddleCoef_2048_q15[3072]; |
||||
extern const q15_t twiddleCoef_4096_q15[6144]; |
||||
extern const float32_t twiddleCoef_rfft_32[32]; |
||||
extern const float32_t twiddleCoef_rfft_64[64]; |
||||
extern const float32_t twiddleCoef_rfft_128[128]; |
||||
extern const float32_t twiddleCoef_rfft_256[256]; |
||||
extern const float32_t twiddleCoef_rfft_512[512]; |
||||
extern const float32_t twiddleCoef_rfft_1024[1024]; |
||||
extern const float32_t twiddleCoef_rfft_2048[2048]; |
||||
extern const float32_t twiddleCoef_rfft_4096[4096]; |
||||
|
||||
|
||||
/* floating-point bit reversal tables */ |
||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) |
||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) |
||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) |
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) |
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) |
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) |
||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) |
||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) |
||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) |
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; |
||||
|
||||
/* fixed-point bit reversal tables */ |
||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) |
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) |
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; |
||||
|
||||
/* Tables for Fast Math Sine and Cosine */ |
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; |
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; |
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; |
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */ |
||||
@ -0,0 +1,79 @@ |
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
||||
* |
||||
* $Date: 19. March 2015 |
||||
* $Revision: V.1.4.5 |
||||
* |
||||
* Project: CMSIS DSP Library |
||||
* Title: arm_const_structs.h |
||||
* |
||||
* Description: This file has constant structs that are initialized for |
||||
* user convenience. For example, some can be given as |
||||
* arguments to the arm_cfft_f32() function. |
||||
* |
||||
* Target Processor: Cortex-M4/Cortex-M3 |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without |
||||
* modification, are permitted provided that the following conditions |
||||
* are met: |
||||
* - Redistributions of source code must retain the above copyright |
||||
* notice, this list of conditions and the following disclaimer. |
||||
* - Redistributions in binary form must reproduce the above copyright |
||||
* notice, this list of conditions and the following disclaimer in |
||||
* the documentation and/or other materials provided with the |
||||
* distribution. |
||||
* - Neither the name of ARM LIMITED nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this |
||||
* software without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
* POSSIBILITY OF SUCH DAMAGE. |
||||
* -------------------------------------------------------------------- */ |
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H |
||||
#define _ARM_CONST_STRUCTS_H |
||||
|
||||
#include "arm_math.h" |
||||
#include "arm_common_tables.h" |
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; |
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; |
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; |
||||
|
||||
#endif |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,734 @@ |
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h |
||||
* @brief CMSIS Cortex-M Core Function/Instruction Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H |
||||
#define __CMSIS_ARMCC_H |
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) |
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
||||
#endif |
||||
|
||||
/* ########################### Core Function Access ########################### */ |
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
||||
@{ |
||||
*/ |
||||
|
||||
/* intrinsic void __enable_irq(); */ |
||||
/* intrinsic void __disable_irq(); */ |
||||
|
||||
/**
|
||||
\brief Get Control Register |
||||
\details Returns the content of the Control Register. |
||||
\return Control Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_CONTROL(void) |
||||
{ |
||||
register uint32_t __regControl __ASM("control"); |
||||
return(__regControl); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register |
||||
\details Writes the given value to the Control Register. |
||||
\param [in] control Control Register value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control) |
||||
{ |
||||
register uint32_t __regControl __ASM("control"); |
||||
__regControl = control; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register |
||||
\details Returns the content of the IPSR Register. |
||||
\return IPSR Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_IPSR(void) |
||||
{ |
||||
register uint32_t __regIPSR __ASM("ipsr"); |
||||
return(__regIPSR); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register |
||||
\details Returns the content of the APSR Register. |
||||
\return APSR Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_APSR(void) |
||||
{ |
||||
register uint32_t __regAPSR __ASM("apsr"); |
||||
return(__regAPSR); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register |
||||
\details Returns the content of the xPSR Register. |
||||
\return xPSR Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_xPSR(void) |
||||
{ |
||||
register uint32_t __regXPSR __ASM("xpsr"); |
||||
return(__regXPSR); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer |
||||
\details Returns the current value of the Process Stack Pointer (PSP). |
||||
\return PSP Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_PSP(void) |
||||
{ |
||||
register uint32_t __regProcessStackPointer __ASM("psp"); |
||||
return(__regProcessStackPointer); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer |
||||
\details Assigns the given value to the Process Stack Pointer (PSP). |
||||
\param [in] topOfProcStack Process Stack Pointer value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
||||
{ |
||||
register uint32_t __regProcessStackPointer __ASM("psp"); |
||||
__regProcessStackPointer = topOfProcStack; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer |
||||
\details Returns the current value of the Main Stack Pointer (MSP). |
||||
\return MSP Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_MSP(void) |
||||
{ |
||||
register uint32_t __regMainStackPointer __ASM("msp"); |
||||
return(__regMainStackPointer); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer |
||||
\details Assigns the given value to the Main Stack Pointer (MSP). |
||||
\param [in] topOfMainStack Main Stack Pointer value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
||||
{ |
||||
register uint32_t __regMainStackPointer __ASM("msp"); |
||||
__regMainStackPointer = topOfMainStack; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask |
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register. |
||||
\return Priority Mask value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void) |
||||
{ |
||||
register uint32_t __regPriMask __ASM("primask"); |
||||
return(__regPriMask); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask |
||||
\details Assigns the given value to the Priority Mask Register. |
||||
\param [in] priMask Priority Mask |
||||
*/ |
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
||||
{ |
||||
register uint32_t __regPriMask __ASM("primask"); |
||||
__regPriMask = (priMask); |
||||
} |
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) |
||||
|
||||
/**
|
||||
\brief Enable FIQ |
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR. |
||||
Can only be executed in Privileged modes. |
||||
*/ |
||||
#define __enable_fault_irq __enable_fiq |
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ |
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR. |
||||
Can only be executed in Privileged modes. |
||||
*/ |
||||
#define __disable_fault_irq __disable_fiq |
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority |
||||
\details Returns the current value of the Base Priority register. |
||||
\return Base Priority register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void) |
||||
{ |
||||
register uint32_t __regBasePri __ASM("basepri"); |
||||
return(__regBasePri); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority |
||||
\details Assigns the given value to the Base Priority register. |
||||
\param [in] basePri Base Priority value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) |
||||
{ |
||||
register uint32_t __regBasePri __ASM("basepri"); |
||||
__regBasePri = (basePri & 0xFFU); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition |
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, |
||||
or the new value increases the BASEPRI priority level. |
||||
\param [in] basePri Base Priority value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) |
||||
{ |
||||
register uint32_t __regBasePriMax __ASM("basepri_max"); |
||||
__regBasePriMax = (basePri & 0xFFU); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask |
||||
\details Returns the current value of the Fault Mask register. |
||||
\return Fault Mask register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void) |
||||
{ |
||||
register uint32_t __regFaultMask __ASM("faultmask"); |
||||
return(__regFaultMask); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask |
||||
\details Assigns the given value to the Fault Mask register. |
||||
\param [in] faultMask Fault Mask value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
||||
{ |
||||
register uint32_t __regFaultMask __ASM("faultmask"); |
||||
__regFaultMask = (faultMask & (uint32_t)1); |
||||
} |
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ |
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) |
||||
|
||||
/**
|
||||
\brief Get FPSCR |
||||
\details Returns the current value of the Floating Point Status/Control register. |
||||
\return Floating Point Status/Control register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_FPSCR(void) |
||||
{ |
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) |
||||
register uint32_t __regfpscr __ASM("fpscr"); |
||||
return(__regfpscr); |
||||
#else |
||||
return(0U); |
||||
#endif |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR |
||||
\details Assigns the given value to the Floating Point Status/Control register. |
||||
\param [in] fpscr Floating Point Status/Control value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
||||
{ |
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) |
||||
register uint32_t __regfpscr __ASM("fpscr"); |
||||
__regfpscr = (fpscr); |
||||
#endif |
||||
} |
||||
|
||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ |
||||
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */ |
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */ |
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief No Operation |
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes. |
||||
*/ |
||||
#define __NOP __nop |
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt |
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. |
||||
*/ |
||||
#define __WFI __wfi |
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event |
||||
\details Wait For Event is a hint instruction that permits the processor to enter |
||||
a low-power state until one of a number of events occurs. |
||||
*/ |
||||
#define __WFE __wfe |
||||
|
||||
|
||||
/**
|
||||
\brief Send Event |
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
||||
*/ |
||||
#define __SEV __sev |
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier |
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor, |
||||
so that all instructions following the ISB are fetched from cache or memory, |
||||
after the instruction has been completed. |
||||
*/ |
||||
#define __ISB() do {\ |
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U) |
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier |
||||
\details Acts as a special kind of Data Memory Barrier. |
||||
It completes when all explicit memory accesses before this instruction complete. |
||||
*/ |
||||
#define __DSB() do {\ |
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U) |
||||
|
||||
/**
|
||||
\brief Data Memory Barrier |
||||
\details Ensures the apparent order of the explicit memory operations before |
||||
and after the instruction, without ensuring their completion. |
||||
*/ |
||||
#define __DMB() do {\ |
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U) |
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit) |
||||
\details Reverses the byte order in integer value. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#define __REV __rev |
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit) |
||||
\details Reverses the byte order in two unsigned short values. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#ifndef __NO_EMBEDDED_ASM |
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) |
||||
{ |
||||
rev16 r0, r0 |
||||
bx lr |
||||
} |
||||
#endif |
||||
|
||||
/**
|
||||
\brief Reverse byte order in signed short value |
||||
\details Reverses the byte order in a signed short value with sign extension to integer. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#ifndef __NO_EMBEDDED_ASM |
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) |
||||
{ |
||||
revsh r0, r0 |
||||
bx lr |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit) |
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
||||
\param [in] value Value to rotate |
||||
\param [in] value Number of Bits to rotate |
||||
\return Rotated value |
||||
*/ |
||||
#define __ROR __ror |
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint |
||||
\details Causes the processor to enter Debug state. |
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached. |
||||
\param [in] value is ignored by the processor. |
||||
If required, a debugger can use it to store additional information about the breakpoint. |
||||
*/ |
||||
#define __BKPT(value) __breakpoint(value) |
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value |
||||
\details Reverses the bit order of the given value. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) |
||||
#define __RBIT __rbit |
||||
#else |
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) |
||||
{ |
||||
uint32_t result; |
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ |
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */ |
||||
for (value >>= 1U; value; value >>= 1U) |
||||
{ |
||||
result <<= 1U; |
||||
result |= value & 1U; |
||||
s--; |
||||
} |
||||
result <<= s; /* shift when v's highest bits are zero */ |
||||
return(result); |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros |
||||
\details Counts the number of leading zeros of a data value. |
||||
\param [in] value Value to count the leading zeros |
||||
\return number of leading zeros in value |
||||
*/ |
||||
#define __CLZ __clz |
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) |
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit) |
||||
\details Executes a exclusive LDR instruction for 8 bit value. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint8_t at (*ptr) |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) |
||||
#else |
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit) |
||||
\details Executes a exclusive LDR instruction for 16 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint16_t at (*ptr) |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) |
||||
#else |
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit) |
||||
\details Executes a exclusive LDR instruction for 32 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint32_t at (*ptr) |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) |
||||
#else |
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit) |
||||
\details Executes a exclusive STR instruction for 8 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
\return 0 Function succeeded |
||||
\return 1 Function failed |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __STREXB(value, ptr) __strex(value, ptr) |
||||
#else |
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit) |
||||
\details Executes a exclusive STR instruction for 16 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
\return 0 Function succeeded |
||||
\return 1 Function failed |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __STREXH(value, ptr) __strex(value, ptr) |
||||
#else |
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit) |
||||
\details Executes a exclusive STR instruction for 32 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
\return 0 Function succeeded |
||||
\return 1 Function failed |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __STREXW(value, ptr) __strex(value, ptr) |
||||
#else |
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock |
||||
\details Removes the exclusive lock which is created by LDREX. |
||||
*/ |
||||
#define __CLREX __clrex |
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate |
||||
\details Saturates a signed value. |
||||
\param [in] value Value to be saturated |
||||
\param [in] sat Bit position to saturate to (1..32) |
||||
\return Saturated value |
||||
*/ |
||||
#define __SSAT __ssat |
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate |
||||
\details Saturates an unsigned value. |
||||
\param [in] value Value to be saturated |
||||
\param [in] sat Bit position to saturate to (0..31) |
||||
\return Saturated value |
||||
*/ |
||||
#define __USAT __usat |
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit) |
||||
\details Moves each bit of a bitstring right by one bit. |
||||
The carry input is shifted in at the left end of the bitstring. |
||||
\param [in] value Value to rotate |
||||
\return Rotated value |
||||
*/ |
||||
#ifndef __NO_EMBEDDED_ASM |
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) |
||||
{ |
||||
rrx r0, r0 |
||||
bx lr |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit) |
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint8_t at (*ptr) |
||||
*/ |
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) |
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit) |
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint16_t at (*ptr) |
||||
*/ |
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) |
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit) |
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint32_t at (*ptr) |
||||
*/ |
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) |
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit) |
||||
\details Executes a Unprivileged STRT instruction for 8 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
*/ |
||||
#define __STRBT(value, ptr) __strt(value, ptr) |
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit) |
||||
\details Executes a Unprivileged STRT instruction for 16 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
*/ |
||||
#define __STRHT(value, ptr) __strt(value, ptr) |
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit) |
||||
\details Executes a Unprivileged STRT instruction for 32 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
*/ |
||||
#define __STRT(value, ptr) __strt(value, ptr) |
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ |
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */ |
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions |
||||
@{ |
||||
*/ |
||||
|
||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ |
||||
|
||||
#define __SADD8 __sadd8 |
||||
#define __QADD8 __qadd8 |
||||
#define __SHADD8 __shadd8 |
||||
#define __UADD8 __uadd8 |
||||
#define __UQADD8 __uqadd8 |
||||
#define __UHADD8 __uhadd8 |
||||
#define __SSUB8 __ssub8 |
||||
#define __QSUB8 __qsub8 |
||||
#define __SHSUB8 __shsub8 |
||||
#define __USUB8 __usub8 |
||||
#define __UQSUB8 __uqsub8 |
||||
#define __UHSUB8 __uhsub8 |
||||
#define __SADD16 __sadd16 |
||||
#define __QADD16 __qadd16 |
||||
#define __SHADD16 __shadd16 |
||||
#define __UADD16 __uadd16 |
||||
#define __UQADD16 __uqadd16 |
||||
#define __UHADD16 __uhadd16 |
||||
#define __SSUB16 __ssub16 |
||||
#define __QSUB16 __qsub16 |
||||
#define __SHSUB16 __shsub16 |
||||
#define __USUB16 __usub16 |
||||
#define __UQSUB16 __uqsub16 |
||||
#define __UHSUB16 __uhsub16 |
||||
#define __SASX __sasx |
||||
#define __QASX __qasx |
||||
#define __SHASX __shasx |
||||
#define __UASX __uasx |
||||
#define __UQASX __uqasx |
||||
#define __UHASX __uhasx |
||||
#define __SSAX __ssax |
||||
#define __QSAX __qsax |
||||
#define __SHSAX __shsax |
||||
#define __USAX __usax |
||||
#define __UQSAX __uqsax |
||||
#define __UHSAX __uhsax |
||||
#define __USAD8 __usad8 |
||||
#define __USADA8 __usada8 |
||||
#define __SSAT16 __ssat16 |
||||
#define __USAT16 __usat16 |
||||
#define __UXTB16 __uxtb16 |
||||
#define __UXTAB16 __uxtab16 |
||||
#define __SXTB16 __sxtb16 |
||||
#define __SXTAB16 __sxtab16 |
||||
#define __SMUAD __smuad |
||||
#define __SMUADX __smuadx |
||||
#define __SMLAD __smlad |
||||
#define __SMLADX __smladx |
||||
#define __SMLALD __smlald |
||||
#define __SMLALDX __smlaldx |
||||
#define __SMUSD __smusd |
||||
#define __SMUSDX __smusdx |
||||
#define __SMLSD __smlsd |
||||
#define __SMLSDX __smlsdx |
||||
#define __SMLSLD __smlsld |
||||
#define __SMLSLDX __smlsldx |
||||
#define __SEL __sel |
||||
#define __QADD __qadd |
||||
#define __QSUB __qsub |
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ |
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) |
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ |
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) |
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ |
||||
((int64_t)(ARG3) << 32U) ) >> 32U)) |
||||
|
||||
#endif /* (__CORTEX_M >= 0x04) */ |
||||
/*@} end of group CMSIS_SIMD_intrinsics */ |
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,798 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h |
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC |
||||
#define __CORE_CM0_H_GENERIC |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
||||
CMSIS violates the following MISRA-C:2004 rules: |
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br> |
||||
Function definitions in header files are used to allow 'inlining'. |
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
||||
Unions are used for effective representation of core registers. |
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br> |
||||
Function-like macros are used to allow more efficient code. |
||||
*/ |
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions |
||||
******************************************************************************/ |
||||
/**
|
||||
\ingroup Cortex_M0 |
||||
@{ |
||||
*/ |
||||
|
||||
/* CMSIS CM0 definitions */ |
||||
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ |
||||
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ |
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ |
||||
|
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#define __packed |
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#else |
||||
#error Unknown compiler |
||||
#endif |
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all |
||||
*/ |
||||
#define __FPU_USED 0U |
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#if defined __TARGET_FPU_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#if defined __ARM_PCS_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#if defined __ARMVFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#if defined __TI_VFP_SUPPORT__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#if defined __FPU_VFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#if ( __CSMC__ & 0x400U) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */ |
||||
#include "core_cmFunc.h" /* Core Function Access */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */ |
||||
|
||||
#ifndef __CMSIS_GENERIC |
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT |
||||
#define __CORE_CM0_H_DEPENDANT |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* check device defines and use defaults */ |
||||
#if defined __CHECK_DEVICE_DEFINES |
||||
#ifndef __CM0_REV |
||||
#define __CM0_REV 0x0000U |
||||
#warning "__CM0_REV not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __NVIC_PRIO_BITS |
||||
#define __NVIC_PRIO_BITS 2U |
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __Vendor_SysTickConfig |
||||
#define __Vendor_SysTickConfig 0U |
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
||||
#endif |
||||
#endif |
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */ |
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines |
||||
|
||||
<strong>IO Type Qualifiers</strong> are used |
||||
\li to specify the access to peripheral variables. |
||||
\li for automatic generation of peripheral register debug information. |
||||
*/ |
||||
#ifdef __cplusplus |
||||
#define __I volatile /*!< Defines 'read only' permissions */ |
||||
#else |
||||
#define __I volatile const /*!< Defines 'read only' permissions */ |
||||
#endif |
||||
#define __O volatile /*!< Defines 'write only' permissions */ |
||||
#define __IO volatile /*!< Defines 'read / write' permissions */ |
||||
|
||||
/* following defines should be used for structure members */ |
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */ |
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */ |
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
||||
|
||||
/*@} end of group Cortex_M0 */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction |
||||
Core Register contain: |
||||
- Core Register |
||||
- Core NVIC Register |
||||
- Core SCB Register |
||||
- Core SysTick Register |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions |
||||
\brief Type definitions and defines for Cortex-M processor based devices. |
||||
*/ |
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CORE Status and Control Registers |
||||
\brief Core Register type definitions. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} APSR_Type; |
||||
|
||||
/* APSR Register Definitions */ |
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */ |
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */ |
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */ |
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} IPSR_Type; |
||||
|
||||
/* IPSR Register Definitions */ |
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} xPSR_Type; |
||||
|
||||
/* xPSR Register Definitions */ |
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} CONTROL_Type; |
||||
|
||||
/* CONTROL Register Definitions */ |
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
||||
|
||||
/*@} end of group CMSIS_CORE */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
||||
\brief Type definitions for the NVIC Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
||||
uint32_t RESERVED0[31U]; |
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
||||
uint32_t RSERVED1[31U]; |
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
||||
uint32_t RESERVED2[31U]; |
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
||||
uint32_t RESERVED3[31U]; |
||||
uint32_t RESERVED4[64U]; |
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
||||
} NVIC_Type; |
||||
|
||||
/*@} end of group CMSIS_NVIC */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCB System Control Block (SCB) |
||||
\brief Type definitions for the System Control Block Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
||||
uint32_t RESERVED0; |
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
||||
uint32_t RESERVED1; |
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
||||
} SCB_Type; |
||||
|
||||
/* SCB CPUID Register Definitions */ |
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */ |
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||||
|
||||
/* SCB System Control Register Definitions */ |
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||||
|
||||
/* SCB Configuration Control Register Definitions */ |
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||||
|
||||
/* SCB System Handler Control and State Register Definitions */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||||
\brief Type definitions for the System Timer Registers. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||||
} SysTick_Type; |
||||
|
||||
/* SysTick Control / Status Register Definitions */ |
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||||
|
||||
/* SysTick Reload Register Definitions */ |
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||||
|
||||
/* SysTick Current Register Definitions */ |
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||||
|
||||
/* SysTick Calibration Register Definitions */ |
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||||
|
||||
/*@} end of group CMSIS_SysTick */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
||||
Therefore they are not covered by the Cortex-M0 header file. |
||||
@{ |
||||
*/ |
||||
/*@} end of group CMSIS_CoreDebug */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_bitfield Core register bit field macros |
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of the bit field. |
||||
\return Masked and shifted value. |
||||
*/ |
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) |
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of register. |
||||
\return Masked and shifted bit field value. |
||||
*/ |
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) |
||||
|
||||
/*@} end of group CMSIS_core_bitfield */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_base Core Definitions |
||||
\brief Definitions for base addresses, unions, and structures. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Memory mapping of Cortex-M0 Hardware */ |
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||||
|
||||
|
||||
/*@} */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer |
||||
Core Function Interface contains: |
||||
- Core NVIC Functions |
||||
- Core SysTick Functions |
||||
- Core Register Access Functions |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||||
*/ |
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||||
\brief Functions that manage interrupts and exceptions via the NVIC. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */ |
||||
/* The following MACROS handle generation of the register offset and byte masks */ |
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt |
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt |
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt |
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return 0 Interrupt status is not pending. |
||||
\return 1 Interrupt status is pending. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt |
||||
\details Sets the pending bit of an external interrupt. |
||||
\param [in] IRQn Interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt |
||||
\details Clears the pending bit of an external interrupt. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority |
||||
\details Sets the priority of an interrupt. |
||||
\note The priority cannot be set for every core interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\param [in] priority Priority to set. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||||
{ |
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
else |
||||
{ |
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority |
||||
\details Reads the priority of an interrupt. |
||||
The interrupt number can be positive to specify an external (device specific) interrupt, |
||||
or negative to specify an internal (core) interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Interrupt Priority. |
||||
Value is aligned automatically to the implemented priority bits of the microcontroller. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
||||
{ |
||||
|
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
else |
||||
{ |
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief System Reset |
||||
\details Initiates a system reset request to reset the MCU. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SystemReset(void) |
||||
{ |
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */ |
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||||
SCB_AIRCR_SYSRESETREQ_Msk); |
||||
__DSB(); /* Ensure completion of memory access */ |
||||
|
||||
for(;;) /* wait until reset */ |
||||
{ |
||||
__NOP(); |
||||
} |
||||
} |
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */ |
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||||
\brief Functions that configure the System. |
||||
@{ |
||||
*/ |
||||
|
||||
#if (__Vendor_SysTickConfig == 0U) |
||||
|
||||
/**
|
||||
\brief System Tick Configuration |
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
Counter is in free running mode to generate periodic interrupts. |
||||
\param [in] ticks Number of ticks between two interrupts. |
||||
\return 0 Function succeeded. |
||||
\return 1 Function failed. |
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||||
must contain a vendor-specific implementation of this function. |
||||
*/ |
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||||
{ |
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||||
{ |
||||
return (1UL); /* Reload value impossible */ |
||||
} |
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||||
SysTick_CTRL_TICKINT_Msk | |
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||||
return (0UL); /* Function successful */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */ |
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */ |
||||
|
||||
#endif /* __CMSIS_GENERIC */ |
||||
@ -0,0 +1,914 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cm0plus.h |
||||
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CM0PLUS_H_GENERIC |
||||
#define __CORE_CM0PLUS_H_GENERIC |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
||||
CMSIS violates the following MISRA-C:2004 rules: |
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br> |
||||
Function definitions in header files are used to allow 'inlining'. |
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
||||
Unions are used for effective representation of core registers. |
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br> |
||||
Function-like macros are used to allow more efficient code. |
||||
*/ |
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions |
||||
******************************************************************************/ |
||||
/**
|
||||
\ingroup Cortex-M0+ |
||||
@{ |
||||
*/ |
||||
|
||||
/* CMSIS CM0+ definitions */ |
||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ |
||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ |
||||
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ |
||||
|
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#define __packed |
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#else |
||||
#error Unknown compiler |
||||
#endif |
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all |
||||
*/ |
||||
#define __FPU_USED 0U |
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#if defined __TARGET_FPU_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#if defined __ARM_PCS_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#if defined __ARMVFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#if defined __TI_VFP_SUPPORT__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#if defined __FPU_VFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#if ( __CSMC__ & 0x400U) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */ |
||||
#include "core_cmFunc.h" /* Core Function Access */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM0PLUS_H_GENERIC */ |
||||
|
||||
#ifndef __CMSIS_GENERIC |
||||
|
||||
#ifndef __CORE_CM0PLUS_H_DEPENDANT |
||||
#define __CORE_CM0PLUS_H_DEPENDANT |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* check device defines and use defaults */ |
||||
#if defined __CHECK_DEVICE_DEFINES |
||||
#ifndef __CM0PLUS_REV |
||||
#define __CM0PLUS_REV 0x0000U |
||||
#warning "__CM0PLUS_REV not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __MPU_PRESENT |
||||
#define __MPU_PRESENT 0U |
||||
#warning "__MPU_PRESENT not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __VTOR_PRESENT |
||||
#define __VTOR_PRESENT 0U |
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __NVIC_PRIO_BITS |
||||
#define __NVIC_PRIO_BITS 2U |
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __Vendor_SysTickConfig |
||||
#define __Vendor_SysTickConfig 0U |
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
||||
#endif |
||||
#endif |
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */ |
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines |
||||
|
||||
<strong>IO Type Qualifiers</strong> are used |
||||
\li to specify the access to peripheral variables. |
||||
\li for automatic generation of peripheral register debug information. |
||||
*/ |
||||
#ifdef __cplusplus |
||||
#define __I volatile /*!< Defines 'read only' permissions */ |
||||
#else |
||||
#define __I volatile const /*!< Defines 'read only' permissions */ |
||||
#endif |
||||
#define __O volatile /*!< Defines 'write only' permissions */ |
||||
#define __IO volatile /*!< Defines 'read / write' permissions */ |
||||
|
||||
/* following defines should be used for structure members */ |
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */ |
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */ |
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
||||
|
||||
/*@} end of group Cortex-M0+ */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction |
||||
Core Register contain: |
||||
- Core Register |
||||
- Core NVIC Register |
||||
- Core SCB Register |
||||
- Core SysTick Register |
||||
- Core MPU Register |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions |
||||
\brief Type definitions and defines for Cortex-M processor based devices. |
||||
*/ |
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CORE Status and Control Registers |
||||
\brief Core Register type definitions. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} APSR_Type; |
||||
|
||||
/* APSR Register Definitions */ |
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */ |
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */ |
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */ |
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} IPSR_Type; |
||||
|
||||
/* IPSR Register Definitions */ |
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} xPSR_Type; |
||||
|
||||
/* xPSR Register Definitions */ |
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} CONTROL_Type; |
||||
|
||||
/* CONTROL Register Definitions */ |
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
||||
|
||||
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
||||
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
||||
|
||||
/*@} end of group CMSIS_CORE */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
||||
\brief Type definitions for the NVIC Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
||||
uint32_t RESERVED0[31U]; |
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
||||
uint32_t RSERVED1[31U]; |
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
||||
uint32_t RESERVED2[31U]; |
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
||||
uint32_t RESERVED3[31U]; |
||||
uint32_t RESERVED4[64U]; |
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
||||
} NVIC_Type; |
||||
|
||||
/*@} end of group CMSIS_NVIC */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCB System Control Block (SCB) |
||||
\brief Type definitions for the System Control Block Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
||||
#if (__VTOR_PRESENT == 1U) |
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
||||
#else |
||||
uint32_t RESERVED0; |
||||
#endif |
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
||||
uint32_t RESERVED1; |
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
||||
} SCB_Type; |
||||
|
||||
/* SCB CPUID Register Definitions */ |
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||||
|
||||
#if (__VTOR_PRESENT == 1U) |
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ |
||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
||||
#endif |
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */ |
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||||
|
||||
/* SCB System Control Register Definitions */ |
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||||
|
||||
/* SCB Configuration Control Register Definitions */ |
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||||
|
||||
/* SCB System Handler Control and State Register Definitions */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||||
\brief Type definitions for the System Timer Registers. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||||
} SysTick_Type; |
||||
|
||||
/* SysTick Control / Status Register Definitions */ |
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||||
|
||||
/* SysTick Reload Register Definitions */ |
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||||
|
||||
/* SysTick Current Register Definitions */ |
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||||
|
||||
/* SysTick Calibration Register Definitions */ |
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||||
|
||||
/*@} end of group CMSIS_SysTick */ |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU) |
||||
\brief Type definitions for the Memory Protection Unit (MPU) |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
||||
} MPU_Type; |
||||
|
||||
/* MPU Type Register Definitions */ |
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
||||
|
||||
/* MPU Control Register Definitions */ |
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
||||
|
||||
/* MPU Region Number Register Definitions */ |
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
||||
|
||||
/* MPU Region Base Address Register Definitions */ |
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ |
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */ |
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
||||
|
||||
/*@} end of group CMSIS_MPU */ |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||||
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
||||
Therefore they are not covered by the Cortex-M0+ header file. |
||||
@{ |
||||
*/ |
||||
/*@} end of group CMSIS_CoreDebug */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_bitfield Core register bit field macros |
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of the bit field. |
||||
\return Masked and shifted value. |
||||
*/ |
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) |
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of register. |
||||
\return Masked and shifted bit field value. |
||||
*/ |
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) |
||||
|
||||
/*@} end of group CMSIS_core_bitfield */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_base Core Definitions |
||||
\brief Definitions for base addresses, unions, and structures. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Memory mapping of Cortex-M0+ Hardware */ |
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
||||
#endif |
||||
|
||||
/*@} */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer |
||||
Core Function Interface contains: |
||||
- Core NVIC Functions |
||||
- Core SysTick Functions |
||||
- Core Register Access Functions |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||||
*/ |
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||||
\brief Functions that manage interrupts and exceptions via the NVIC. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */ |
||||
/* The following MACROS handle generation of the register offset and byte masks */ |
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt |
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt |
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt |
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return 0 Interrupt status is not pending. |
||||
\return 1 Interrupt status is pending. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt |
||||
\details Sets the pending bit of an external interrupt. |
||||
\param [in] IRQn Interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt |
||||
\details Clears the pending bit of an external interrupt. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority |
||||
\details Sets the priority of an interrupt. |
||||
\note The priority cannot be set for every core interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\param [in] priority Priority to set. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||||
{ |
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
else |
||||
{ |
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority |
||||
\details Reads the priority of an interrupt. |
||||
The interrupt number can be positive to specify an external (device specific) interrupt, |
||||
or negative to specify an internal (core) interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Interrupt Priority. |
||||
Value is aligned automatically to the implemented priority bits of the microcontroller. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
||||
{ |
||||
|
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
else |
||||
{ |
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief System Reset |
||||
\details Initiates a system reset request to reset the MCU. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SystemReset(void) |
||||
{ |
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */ |
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||||
SCB_AIRCR_SYSRESETREQ_Msk); |
||||
__DSB(); /* Ensure completion of memory access */ |
||||
|
||||
for(;;) /* wait until reset */ |
||||
{ |
||||
__NOP(); |
||||
} |
||||
} |
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */ |
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||||
\brief Functions that configure the System. |
||||
@{ |
||||
*/ |
||||
|
||||
#if (__Vendor_SysTickConfig == 0U) |
||||
|
||||
/**
|
||||
\brief System Tick Configuration |
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
Counter is in free running mode to generate periodic interrupts. |
||||
\param [in] ticks Number of ticks between two interrupts. |
||||
\return 0 Function succeeded. |
||||
\return 1 Function failed. |
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||||
must contain a vendor-specific implementation of this function. |
||||
*/ |
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||||
{ |
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||||
{ |
||||
return (1UL); /* Reload value impossible */ |
||||
} |
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||||
SysTick_CTRL_TICKINT_Msk | |
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||||
return (0UL); /* Function successful */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */ |
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM0PLUS_H_DEPENDANT */ |
||||
|
||||
#endif /* __CMSIS_GENERIC */ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,87 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h |
||||
* @brief CMSIS Cortex-M Core Function Access Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CMFUNC_H |
||||
#define __CORE_CMFUNC_H |
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */ |
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
||||
@{ |
||||
*/ |
||||
|
||||
/*------------------ RealView Compiler -----------------*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armcc_V6.h" |
||||
|
||||
/*------------------ GNU Compiler ----------------------*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
/*------------------ ICC Compiler ----------------------*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iar.h> |
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/ |
||||
#elif defined ( __TMS470__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
/*------------------ TASKING Compiler ------------------*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */ |
||||
|
||||
#endif /* __CORE_CMFUNC_H */ |
||||
@ -0,0 +1,87 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h |
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CMINSTR_H |
||||
#define __CORE_CMINSTR_H |
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */ |
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions |
||||
@{ |
||||
*/ |
||||
|
||||
/*------------------ RealView Compiler -----------------*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armcc_V6.h" |
||||
|
||||
/*------------------ GNU Compiler ----------------------*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
/*------------------ ICC Compiler ----------------------*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iar.h> |
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/ |
||||
#elif defined ( __TMS470__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
/*------------------ TASKING Compiler ------------------*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#endif |
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
||||
|
||||
#endif /* __CORE_CMINSTR_H */ |
||||
@ -0,0 +1,96 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h |
||||
* @brief CMSIS Cortex-M SIMD Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CMSIMD_H |
||||
#define __CORE_CMSIMD_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */ |
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions |
||||
@{ |
||||
*/ |
||||
|
||||
/*------------------ RealView Compiler -----------------*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armcc_V6.h" |
||||
|
||||
/*------------------ GNU Compiler ----------------------*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
/*------------------ ICC Compiler ----------------------*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iar.h> |
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/ |
||||
#elif defined ( __TMS470__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
/*------------------ TASKING Compiler ------------------*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#endif |
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */ |
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CMSIMD_H */ |
||||
@ -0,0 +1,926 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_sc000.h |
||||
* @brief CMSIS SC000 Core Peripheral Access Layer Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_SC000_H_GENERIC |
||||
#define __CORE_SC000_H_GENERIC |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
||||
CMSIS violates the following MISRA-C:2004 rules: |
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br> |
||||
Function definitions in header files are used to allow 'inlining'. |
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
||||
Unions are used for effective representation of core registers. |
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br> |
||||
Function-like macros are used to allow more efficient code. |
||||
*/ |
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions |
||||
******************************************************************************/ |
||||
/**
|
||||
\ingroup SC000 |
||||
@{ |
||||
*/ |
||||
|
||||
/* CMSIS SC000 definitions */ |
||||
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ |
||||
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ |
||||
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
||||
|
||||
#define __CORTEX_SC (000U) /*!< Cortex secure core */ |
||||
|
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#define __packed |
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#else |
||||
#error Unknown compiler |
||||
#endif |
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all |
||||
*/ |
||||
#define __FPU_USED 0U |
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#if defined __TARGET_FPU_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#if defined __ARM_PCS_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#if defined __ARMVFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#if defined __TI_VFP_SUPPORT__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#if defined __FPU_VFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#if ( __CSMC__ & 0x400U) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */ |
||||
#include "core_cmFunc.h" /* Core Function Access */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_SC000_H_GENERIC */ |
||||
|
||||
#ifndef __CMSIS_GENERIC |
||||
|
||||
#ifndef __CORE_SC000_H_DEPENDANT |
||||
#define __CORE_SC000_H_DEPENDANT |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* check device defines and use defaults */ |
||||
#if defined __CHECK_DEVICE_DEFINES |
||||
#ifndef __SC000_REV |
||||
#define __SC000_REV 0x0000U |
||||
#warning "__SC000_REV not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __MPU_PRESENT |
||||
#define __MPU_PRESENT 0U |
||||
#warning "__MPU_PRESENT not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __NVIC_PRIO_BITS |
||||
#define __NVIC_PRIO_BITS 2U |
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __Vendor_SysTickConfig |
||||
#define __Vendor_SysTickConfig 0U |
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
||||
#endif |
||||
#endif |
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */ |
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines |
||||
|
||||
<strong>IO Type Qualifiers</strong> are used |
||||
\li to specify the access to peripheral variables. |
||||
\li for automatic generation of peripheral register debug information. |
||||
*/ |
||||
#ifdef __cplusplus |
||||
#define __I volatile /*!< Defines 'read only' permissions */ |
||||
#else |
||||
#define __I volatile const /*!< Defines 'read only' permissions */ |
||||
#endif |
||||
#define __O volatile /*!< Defines 'write only' permissions */ |
||||
#define __IO volatile /*!< Defines 'read / write' permissions */ |
||||
|
||||
/* following defines should be used for structure members */ |
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */ |
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */ |
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
||||
|
||||
/*@} end of group SC000 */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction |
||||
Core Register contain: |
||||
- Core Register |
||||
- Core NVIC Register |
||||
- Core SCB Register |
||||
- Core SysTick Register |
||||
- Core MPU Register |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions |
||||
\brief Type definitions and defines for Cortex-M processor based devices. |
||||
*/ |
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CORE Status and Control Registers |
||||
\brief Core Register type definitions. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} APSR_Type; |
||||
|
||||
/* APSR Register Definitions */ |
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */ |
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */ |
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */ |
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} IPSR_Type; |
||||
|
||||
/* IPSR Register Definitions */ |
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} xPSR_Type; |
||||
|
||||
/* xPSR Register Definitions */ |
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} CONTROL_Type; |
||||
|
||||
/* CONTROL Register Definitions */ |
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
||||
|
||||
/*@} end of group CMSIS_CORE */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
||||
\brief Type definitions for the NVIC Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
||||
uint32_t RESERVED0[31U]; |
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
||||
uint32_t RSERVED1[31U]; |
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
||||
uint32_t RESERVED2[31U]; |
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
||||
uint32_t RESERVED3[31U]; |
||||
uint32_t RESERVED4[64U]; |
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
||||
} NVIC_Type; |
||||
|
||||
/*@} end of group CMSIS_NVIC */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCB System Control Block (SCB) |
||||
\brief Type definitions for the System Control Block Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
||||
uint32_t RESERVED0[1U]; |
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
||||
uint32_t RESERVED1[154U]; |
||||
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ |
||||
} SCB_Type; |
||||
|
||||
/* SCB CPUID Register Definitions */ |
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ |
||||
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */ |
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||||
|
||||
/* SCB System Control Register Definitions */ |
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||||
|
||||
/* SCB Configuration Control Register Definitions */ |
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||||
|
||||
/* SCB System Handler Control and State Register Definitions */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
||||
\brief Type definitions for the System Control and ID Register not in the SCB |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB. |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t RESERVED0[2U]; |
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
||||
} SCnSCB_Type; |
||||
|
||||
/* Auxiliary Control Register Definitions */ |
||||
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ |
||||
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||||
\brief Type definitions for the System Timer Registers. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||||
} SysTick_Type; |
||||
|
||||
/* SysTick Control / Status Register Definitions */ |
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||||
|
||||
/* SysTick Reload Register Definitions */ |
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||||
|
||||
/* SysTick Current Register Definitions */ |
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||||
|
||||
/* SysTick Calibration Register Definitions */ |
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||||
|
||||
/*@} end of group CMSIS_SysTick */ |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU) |
||||
\brief Type definitions for the Memory Protection Unit (MPU) |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
||||
} MPU_Type; |
||||
|
||||
/* MPU Type Register Definitions */ |
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
||||
|
||||
/* MPU Control Register Definitions */ |
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
||||
|
||||
/* MPU Region Number Register Definitions */ |
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
||||
|
||||
/* MPU Region Base Address Register Definitions */ |
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ |
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */ |
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
||||
|
||||
/*@} end of group CMSIS_MPU */ |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||||
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
||||
Therefore they are not covered by the SC000 header file. |
||||
@{ |
||||
*/ |
||||
/*@} end of group CMSIS_CoreDebug */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_bitfield Core register bit field macros |
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of the bit field. |
||||
\return Masked and shifted value. |
||||
*/ |
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) |
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of register. |
||||
\return Masked and shifted bit field value. |
||||
*/ |
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) |
||||
|
||||
/*@} end of group CMSIS_core_bitfield */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_base Core Definitions |
||||
\brief Definitions for base addresses, unions, and structures. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Memory mapping of SC000 Hardware */ |
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
||||
#endif |
||||
|
||||
/*@} */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer |
||||
Core Function Interface contains: |
||||
- Core NVIC Functions |
||||
- Core SysTick Functions |
||||
- Core Register Access Functions |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||||
*/ |
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||||
\brief Functions that manage interrupts and exceptions via the NVIC. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */ |
||||
/* The following MACROS handle generation of the register offset and byte masks */ |
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt |
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt |
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt |
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return 0 Interrupt status is not pending. |
||||
\return 1 Interrupt status is pending. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt |
||||
\details Sets the pending bit of an external interrupt. |
||||
\param [in] IRQn Interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt |
||||
\details Clears the pending bit of an external interrupt. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority |
||||
\details Sets the priority of an interrupt. |
||||
\note The priority cannot be set for every core interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\param [in] priority Priority to set. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||||
{ |
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
else |
||||
{ |
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority |
||||
\details Reads the priority of an interrupt. |
||||
The interrupt number can be positive to specify an external (device specific) interrupt, |
||||
or negative to specify an internal (core) interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Interrupt Priority. |
||||
Value is aligned automatically to the implemented priority bits of the microcontroller. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
||||
{ |
||||
|
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
else |
||||
{ |
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief System Reset |
||||
\details Initiates a system reset request to reset the MCU. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SystemReset(void) |
||||
{ |
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */ |
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||||
SCB_AIRCR_SYSRESETREQ_Msk); |
||||
__DSB(); /* Ensure completion of memory access */ |
||||
|
||||
for(;;) /* wait until reset */ |
||||
{ |
||||
__NOP(); |
||||
} |
||||
} |
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */ |
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||||
\brief Functions that configure the System. |
||||
@{ |
||||
*/ |
||||
|
||||
#if (__Vendor_SysTickConfig == 0U) |
||||
|
||||
/**
|
||||
\brief System Tick Configuration |
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
Counter is in free running mode to generate periodic interrupts. |
||||
\param [in] ticks Number of ticks between two interrupts. |
||||
\return 0 Function succeeded. |
||||
\return 1 Function failed. |
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||||
must contain a vendor-specific implementation of this function. |
||||
*/ |
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||||
{ |
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||||
{ |
||||
return (1UL); /* Reload value impossible */ |
||||
} |
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||||
SysTick_CTRL_TICKINT_Msk | |
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||||
return (0UL); /* Function successful */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */ |
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_SC000_H_DEPENDANT */ |
||||
|
||||
#endif /* __CMSIS_GENERIC */ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,444 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal.h |
||||
* @author MCD Application Team |
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_H |
||||
#define __STM32L0xx_HAL_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
|
||||
// added
|
||||
#include <stm32l073xx.h> |
||||
|
||||
#include "stm32l0xx_hal_conf.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup HAL HAL
|
||||
* @{ |
||||
*/
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_BootMode Boot Mode
|
||||
* @{ |
||||
*/ |
||||
#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000U) |
||||
#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0) |
||||
#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration
|
||||
* @{ |
||||
*/ |
||||
#define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP |
||||
#define DBGMCU_STOP DBGMCU_CR_DBG_STOP |
||||
#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY |
||||
#define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U)) |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined (LCD_BASE) /* STM32L0x3xx only */ |
||||
/** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors
|
||||
* @{ |
||||
*/ |
||||
#define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */ |
||||
#define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */ |
||||
#define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */ |
||||
#define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */ |
||||
#if defined (SYSCFG_CFGR2_CAPA_3) |
||||
#define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */ |
||||
#endif |
||||
#if defined (SYSCFG_CFGR2_CAPA_4) |
||||
#define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */ |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif |
||||
|
||||
/** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection
|
||||
* @{ |
||||
*/
|
||||
#define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000U) /* no pad connected */ |
||||
#define SYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */ |
||||
#define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */ |
||||
#define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */ |
||||
|
||||
#define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || \ |
||||
((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || \
|
||||
((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || \
|
||||
((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition
|
||||
* @{ |
||||
*/ |
||||
#define SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF |
||||
|
||||
#define IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO
|
||||
* @{ |
||||
*/
|
||||
/** @brief Fast mode Plus driving capability on a specific GPIO
|
||||
*/
|
||||
#if defined (SYSCFG_CFGR2_I2C_PB6_FMP) |
||||
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */ |
||||
#endif |
||||
#if defined (SYSCFG_CFGR2_I2C_PB7_FMP) |
||||
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */ |
||||
#endif |
||||
#if defined (SYSCFG_CFGR2_I2C_PB8_FMP) |
||||
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */ |
||||
#endif |
||||
#if defined (SYSCFG_CFGR2_I2C_PB9_FMP) |
||||
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */ |
||||
#endif |
||||
|
||||
#define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || \ |
||||
(((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || \
|
||||
(((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || \
|
||||
(((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) ) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/ |
||||
#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
||||
/**
|
||||
* @brief TIM2 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
||||
/**
|
||||
* @brief TIM3 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
||||
/**
|
||||
* @brief TIM6 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
||||
/**
|
||||
* @brief TIM7 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) |
||||
/**
|
||||
* @brief RTC Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
||||
/**
|
||||
* @brief WWDG Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
||||
/**
|
||||
* @brief IWDG Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP) |
||||
/**
|
||||
* @brief I2C1 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP) |
||||
/**
|
||||
* @brief I2C2 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP) |
||||
/**
|
||||
* @brief I2C3 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) |
||||
/**
|
||||
* @brief LPTIMER Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP) |
||||
/**
|
||||
* @brief TIM22 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP) |
||||
/**
|
||||
* @brief TIM21 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) |
||||
#endif |
||||
|
||||
/** @brief Main Flash memory mapped at 0x00000000
|
||||
*/ |
||||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) |
||||
|
||||
/** @brief System Flash memory mapped at 0x00000000
|
||||
*/ |
||||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) |
||||
|
||||
|
||||
/** @brief Embedded SRAM mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1) |
||||
|
||||
/** @brief Configuration of the DBG Low Power mode.
|
||||
* @param __DBGLPMODE__: bit field to indicate in wich Low Power mode DBG is still active. |
||||
* This parameter can be a value of |
||||
* - DBGMCU_SLEEP |
||||
* - DBGMCU_STOP |
||||
* - DBGMCU_STANDBY |
||||
*/ |
||||
#define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \ |
||||
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \
|
||||
} while (0)
|
||||
|
||||
#if defined (LCD_BASE) /* STM32L0x3xx only */ |
||||
|
||||
/** @brief Macro to configure the VLCD Decoupling capacitance connection.
|
||||
* |
||||
* @param __SYSCFG_VLCD_CAPA__: specifies the decoupling of LCD capacitance for rails connection on GPIO. |
||||
* This parameter can be a combination of following values (when available): |
||||
* @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2
|
||||
* @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 |
||||
* @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 |
||||
* @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 |
||||
* @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
|
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \ |
||||
MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__)) |
||||
|
||||
/**
|
||||
* @brief Returns the decoupling of LCD capacitance configured by user. |
||||
* @retval The LCD capacitance connection as configured by user. The returned can be a combination of : |
||||
* SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2
|
||||
* SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 |
||||
* SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 |
||||
* SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 |
||||
* SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
|
||||
*/ |
||||
#define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA) |
||||
|
||||
#endif |
||||
|
||||
/**
|
||||
* @brief Returns the boot mode as configured by user. |
||||
* @retval The boot mode as configured by user. The returned can be a value of : |
||||
* - SYSCFG_BOOT_MAINFLASH |
||||
* - SYSCFG_BOOT_SYSTEMFLASH |
||||
* - SYSCFG_BOOT_SRAM |
||||
*/ |
||||
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE) |
||||
|
||||
|
||||
/** @brief Check whether the specified SYSCFG flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check. |
||||
* The only parameter supported is SYSCFG_FLAG_VREFINT_READY |
||||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
||||
*/ |
||||
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__)) |
||||
|
||||
/** @brief Fast mode Plus driving capability enable macro
|
||||
* @param __FASTMODEPLUS__: This parameter can be a value of :
|
||||
* @arg SYSCFG_FASTMODEPLUS_PB6 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB7 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB8 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB9 |
||||
*/ |
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ |
||||
SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
|
||||
}while(0) |
||||
/** @brief Fast mode Plus driving capability disable macro
|
||||
* @param __FASTMODEPLUS__: This parameter can be a value of :
|
||||
* @arg SYSCFG_FASTMODEPLUS_PB6 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB7 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB8 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB9 |
||||
*/ |
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ |
||||
CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
|
||||
}while(0) |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{ |
||||
*/ |
||||
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions |
||||
* @{ |
||||
*/ |
||||
HAL_StatusTypeDef HAL_Init(void); |
||||
HAL_StatusTypeDef HAL_DeInit(void); |
||||
void HAL_MspInit(void); |
||||
void HAL_MspDeInit(void); |
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Peripheral Control functions |
||||
* @{ |
||||
*/ |
||||
void HAL_IncTick(void); |
||||
void HAL_Delay(__IO uint32_t Delay); |
||||
uint32_t HAL_GetTick(void); |
||||
void HAL_SuspendTick(void); |
||||
void HAL_ResumeTick(void); |
||||
uint32_t HAL_GetHalVersion(void); |
||||
uint32_t HAL_GetREVID(void); |
||||
uint32_t HAL_GetDEVID(void); |
||||
void HAL_DBGMCU_EnableDBGSleepMode(void); |
||||
void HAL_DBGMCU_DisableDBGSleepMode(void); |
||||
void HAL_DBGMCU_EnableDBGStopMode(void); |
||||
void HAL_DBGMCU_DisableDBGStopMode(void); |
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void); |
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void); |
||||
void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph); |
||||
void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph); |
||||
uint32_t HAL_SYSCFG_GetBootMode(void); |
||||
void HAL_SYSCFG_Enable_Lock_VREFINT(void); |
||||
void HAL_SYSCFG_Disable_Lock_VREFINT(void); |
||||
void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Define the private group ***********************************/ |
||||
/**************************************************************/ |
||||
/** @defgroup HAL_Private HAL Private
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**************************************************************/ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,416 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_cortex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of CORTEX HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_CORTEX_H |
||||
#define __STM32L0xx_HAL_CORTEX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @{ |
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
#if (__MPU_PRESENT == 1) |
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @{ |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
||||
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
||||
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
||||
uint8_t TypeExtField; /*!< This parameter is NOT used but is kept to keep API unified through all families*/ |
||||
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
||||
}MPU_Region_InitTypeDef; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4U) |
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0) |
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source
|
||||
* @{ |
||||
*/ |
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) |
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) |
||||
#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ |
||||
((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if (__MPU_PRESENT == 1) |
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
|
||||
* @{ |
||||
*/ |
||||
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) |
||||
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) |
||||
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) |
||||
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01U) |
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{ |
||||
*/ |
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) |
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) |
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) |
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) |
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) |
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) |
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) |
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) |
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) |
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) |
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) |
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) |
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) |
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) |
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) |
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) |
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) |
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) |
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) |
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) |
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) |
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) |
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) |
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) |
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) |
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) |
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) |
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) |
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) |
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) |
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) |
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) |
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) |
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) |
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) |
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) |
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) |
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) |
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) |
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) |
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) |
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) |
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) |
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions |
||||
* @{ |
||||
*/ |
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_SystemReset(void); |
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
||||
#if (__MPU_PRESENT == 1) |
||||
/**
|
||||
* @brief Disable the MPU. |
||||
* @retval None |
||||
*/ |
||||
__STATIC_INLINE void HAL_MPU_Disable(void) |
||||
{ |
||||
|
||||
/*Data Memory Barrier setup */ |
||||
__DMB(); |
||||
/* Disable the MPU */ |
||||
MPU->CTRL = 0; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable the MPU. |
||||
* @param MPU_Control: Specifies the control mode of the MPU during hard fault, |
||||
* NMI, FAULTMASK and privileged access to the default memory |
||||
* This parameter can be one of the following values: |
||||
* @arg MPU_HFNMI_PRIVDEF_NONE |
||||
* @arg MPU_HARDFAULT_NMI |
||||
* @arg MPU_PRIVILEGED_DEFAULT |
||||
* @arg MPU_HFNMI_PRIVDEF |
||||
* @retval None |
||||
*/ |
||||
|
||||
__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) |
||||
{ |
||||
/* Enable the MPU */ |
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
||||
/* Data Synchronization Barrier setup */ |
||||
__DSB(); |
||||
/* Instruction Synchronization Barrier setup */ |
||||
__ISB(); |
||||
|
||||
} |
||||
#endif /* __MPU_PRESENT */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions |
||||
* @{ |
||||
*/ |
||||
|
||||
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); |
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
||||
void HAL_SYSTICK_IRQHandler(void); |
||||
void HAL_SYSTICK_Callback(void); |
||||
#if (__MPU_PRESENT == 1) |
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
||||
#endif /* __MPU_PRESENT */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private types -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
#if (__MPU_PRESENT == 1) |
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
||||
((STATE) == MPU_REGION_DISABLE)) |
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO)) |
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7)) |
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ |
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB)) |
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_CORTEX_H */ |
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,208 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_def.h |
||||
* @author MCD Application Team |
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_DEF |
||||
#define __STM32L0xx_HAL_DEF |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx.h" |
||||
#include "Legacy/stm32_hal_legacy.h" |
||||
#include <stdio.h> |
||||
#include <stdint.h> |
||||
#include <stdbool.h> |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{ |
||||
HAL_OK = 0x00U, |
||||
HAL_ERROR = 0x01U, |
||||
HAL_BUSY = 0x02U, |
||||
HAL_TIMEOUT = 0x03U |
||||
} HAL_StatusTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/ |
||||
typedef enum
|
||||
{ |
||||
HAL_UNLOCKED = 0x00U, |
||||
HAL_LOCKED = 0x01U
|
||||
} HAL_LockTypeDef; |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
|
||||
#define UNUSED(x) ((void)(x)) |
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU |
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) |
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) |
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ |
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0) |
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle. |
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter |
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field. |
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed |
||||
* (i.e. HAL_PPP_MspInit() will not be executed). |
||||
* - When there is a need to reconfigure the low level hardware: instead of calling |
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). |
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function |
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) |
||||
|
||||
#if (USE_RTOS == 1) |
||||
|
||||
/* Reserved for future use */ |
||||
#error "USE_RTOS should be 0 in the current HAL release" |
||||
|
||||
#else |
||||
#define __HAL_LOCK(__HANDLE__) \ |
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0) |
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \ |
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0) |
||||
#endif /* USE_RTOS */ |
||||
|
||||
#if defined ( __GNUC__ ) |
||||
#ifndef __weak |
||||
#define __weak __attribute__((weak)) |
||||
#endif /* __weak */ |
||||
#ifndef __packed |
||||
#define __packed __attribute__((__packed__)) |
||||
#endif /* __packed */ |
||||
|
||||
#define __NOINLINE __attribute__ ( (noinline) ) |
||||
|
||||
#endif /* __GNUC__ */ |
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ |
||||
#if defined (__GNUC__) /* GNU Compiler */ |
||||
#ifndef __ALIGN_END |
||||
#define __ALIGN_END __attribute__ ((aligned (4))) |
||||
#endif /* __ALIGN_END */ |
||||
#ifndef __ALIGN_BEGIN |
||||
#define __ALIGN_BEGIN |
||||
#endif /* __ALIGN_BEGIN */ |
||||
#else |
||||
#ifndef __ALIGN_END |
||||
#define __ALIGN_END |
||||
#endif /* __ALIGN_END */ |
||||
#ifndef __ALIGN_BEGIN |
||||
#if defined (__CC_ARM) /* ARM Compiler */ |
||||
#define __ALIGN_BEGIN __align(4) |
||||
#elif defined (__ICCARM__) /* IAR Compiler */ |
||||
#define __ALIGN_BEGIN |
||||
#endif /* __CC_ARM */ |
||||
#endif /* __ALIGN_BEGIN */ |
||||
#endif /* __GNUC__ */ |
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition |
||||
*/
|
||||
#if defined ( __CC_ARM ) |
||||
/* ARM Compiler
|
||||
------------ |
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module. |
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM. |
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target' |
||||
dialog.
|
||||
*/ |
||||
#define __RAM_FUNC HAL_StatusTypeDef |
||||
|
||||
#define __NOINLINE __attribute__ ( (noinline) ) |
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
/* ICCARM Compiler
|
||||
--------------- |
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/ |
||||
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef |
||||
|
||||
#define __NOINLINE _Pragma("optimize = no_inline") |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
/* GNU Compiler
|
||||
------------ |
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))". |
||||
*/ |
||||
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) |
||||
|
||||
#endif |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* ___STM32L0xx_HAL_DEF */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,694 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_dma.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of DMA HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_DMA_H |
||||
#define __STM32L0xx_HAL_DMA_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMA DMA
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @{ |
||||
*/ |
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Request; /*!< Specifies the request selected for the specified channel.
|
||||
This parameter can be a value of @ref DMA_request */ |
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory. |
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */ |
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
When Memory to Memory transfer is used, this is the Source Increment mode |
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
When Memory to Memory transfer is used, this is the Destination Increment mode |
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
When Memory to Memory transfer is used, this is the Source Alignment format |
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
When Memory to Memory transfer is used, this is the Destination Alignment format |
||||
This parameter can be a value of @ref DMA_Memory_data_size */ |
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular).
|
||||
This parameter can be a value of @ref DMA_mode |
||||
@note The circular buffer mode cannot be used if the memory-to-memory |
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */ |
||||
} DMA_InitTypeDef; |
||||
|
||||
/**
|
||||
* @brief DMA Configuration enumeration values definition
|
||||
*/
|
||||
typedef enum
|
||||
{ |
||||
DMA_MODE = 0U, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ |
||||
DMA_PRIORITY = 1U, /*!< Control related priority level Parameter in DMA_InitTypeDef */ |
||||
|
||||
} DMA_ControlTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum |
||||
{ |
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA process success and ready for use */ |
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||
HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ |
||||
HAL_DMA_STATE_READY_HALF = 0x05U, /*!< DMA Half process success */ |
||||
}HAL_DMA_StateTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum |
||||
{ |
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
||||
HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ |
||||
|
||||
}HAL_DMA_LevelCompleteTypeDef; |
||||
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef |
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */ |
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
||||
|
||||
void *Parent; /*!< Parent object state */ |
||||
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
||||
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
||||
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
||||
|
||||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */ |
||||
|
||||
} DMA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Codes
|
||||
* @{ |
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
||||
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ |
||||
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< no ongoing transfer */ |
||||
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ |
||||
|
||||
#if defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
||||
((INSTANCE) == DMA1_Channel2) || \
|
||||
((INSTANCE) == DMA1_Channel3) || \
|
||||
((INSTANCE) == DMA1_Channel4) || \
|
||||
((INSTANCE) == DMA1_Channel5)) |
||||
#else |
||||
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
||||
((INSTANCE) == DMA1_Channel2) || \
|
||||
((INSTANCE) == DMA1_Channel3) || \
|
||||
((INSTANCE) == DMA1_Channel4) || \
|
||||
((INSTANCE) == DMA1_Channel5) || \
|
||||
((INSTANCE) == DMA1_Channel6) || \
|
||||
((INSTANCE) == DMA1_Channel7))
|
||||
|
||||
#endif |
||||
#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_request DMA request defintiions
|
||||
* @{ |
||||
*/
|
||||
|
||||
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
|
||||
#define DMA_REQUEST_0 ((uint32_t)0x00000000U) |
||||
#define DMA_REQUEST_1 ((uint32_t)0x00000001U) |
||||
#define DMA_REQUEST_2 ((uint32_t)0x00000002U) |
||||
#define DMA_REQUEST_3 ((uint32_t)0x00000003U) |
||||
#define DMA_REQUEST_4 ((uint32_t)0x00000004U) |
||||
#define DMA_REQUEST_5 ((uint32_t)0x00000005U) |
||||
#define DMA_REQUEST_6 ((uint32_t)0x00000006U) |
||||
#define DMA_REQUEST_7 ((uint32_t)0x00000007U) |
||||
#define DMA_REQUEST_8 ((uint32_t)0x00000008U) |
||||
#define DMA_REQUEST_9 ((uint32_t)0x00000009U) |
||||
#define DMA_REQUEST_10 ((uint32_t)0x0000000AU) |
||||
#define DMA_REQUEST_11 ((uint32_t)0x0000000BU) |
||||
#define DMA_REQUEST_12 ((uint32_t)0x0000000CU) |
||||
#define DMA_REQUEST_13 ((uint32_t)0x0000000DU) |
||||
#define DMA_REQUEST_14 ((uint32_t)0x0000000EU) |
||||
#define DMA_REQUEST_15 ((uint32_t)0x0000000FU) |
||||
|
||||
#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
||||
((REQUEST) == DMA_REQUEST_1) || \
|
||||
((REQUEST) == DMA_REQUEST_2) || \
|
||||
((REQUEST) == DMA_REQUEST_3) || \
|
||||
((REQUEST) == DMA_REQUEST_4) || \
|
||||
((REQUEST) == DMA_REQUEST_5) || \
|
||||
((REQUEST) == DMA_REQUEST_6) || \
|
||||
((REQUEST) == DMA_REQUEST_7) || \
|
||||
((REQUEST) == DMA_REQUEST_8) || \
|
||||
((REQUEST) == DMA_REQUEST_9) || \
|
||||
((REQUEST) == DMA_REQUEST_10) || \
|
||||
((REQUEST) == DMA_REQUEST_11) || \
|
||||
((REQUEST) == DMA_REQUEST_12) || \
|
||||
((REQUEST) == DMA_REQUEST_13) || \
|
||||
((REQUEST) == DMA_REQUEST_14) || \
|
||||
((REQUEST) == DMA_REQUEST_15)) |
||||
|
||||
#else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ |
||||
|
||||
#define DMA_REQUEST_0 ((uint32_t)0x00000000U) |
||||
#define DMA_REQUEST_1 ((uint32_t)0x00000001U) |
||||
#define DMA_REQUEST_2 ((uint32_t)0x00000002U) |
||||
#define DMA_REQUEST_3 ((uint32_t)0x00000003U) |
||||
#define DMA_REQUEST_4 ((uint32_t)0x00000004U) |
||||
#define DMA_REQUEST_5 ((uint32_t)0x00000005U) |
||||
#define DMA_REQUEST_6 ((uint32_t)0x00000006U) |
||||
#define DMA_REQUEST_7 ((uint32_t)0x00000007U) |
||||
#define DMA_REQUEST_8 ((uint32_t)0x00000008U) |
||||
#define DMA_REQUEST_9 ((uint32_t)0x00000009U) |
||||
#define DMA_REQUEST_11 ((uint32_t)0x0000000BU) |
||||
|
||||
#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
||||
((REQUEST) == DMA_REQUEST_1) || \
|
||||
((REQUEST) == DMA_REQUEST_2) || \
|
||||
((REQUEST) == DMA_REQUEST_3) || \
|
||||
((REQUEST) == DMA_REQUEST_4) || \
|
||||
((REQUEST) == DMA_REQUEST_5) || \
|
||||
((REQUEST) == DMA_REQUEST_6) || \
|
||||
((REQUEST) == DMA_REQUEST_7) || \
|
||||
((REQUEST) == DMA_REQUEST_8) || \
|
||||
((REQUEST) == DMA_REQUEST_9) || \
|
||||
((REQUEST) == DMA_REQUEST_11)) |
||||
#endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
|
||||
* @{ |
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ |
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ |
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Data_buffer_size DMA Data Buffer Size Check
|
||||
* @{ |
||||
*/
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral Incremented Mode
|
||||
* @{ |
||||
*/
|
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
||||
#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ |
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
||||
((STATE) == DMA_PINC_DISABLE)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory Incremented Mode
|
||||
* @{ |
||||
*/
|
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
||||
#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ |
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
||||
((STATE) == DMA_MINC_DISABLE)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment
|
||||
* @{ |
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ |
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment
|
||||
* @{
|
||||
*/ |
||||
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ |
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD )) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_mode DMA Mode
|
||||
* @{ |
||||
*/
|
||||
#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ |
||||
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ |
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
||||
((MODE) == DMA_CIRCULAR))
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority Level
|
||||
* @{ |
||||
*/ |
||||
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ |
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA Interrupt Definitions
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
||||
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
||||
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_flag_definitions DMA Flag Definitions
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define DMA_FLAG_GL1 ((uint32_t)0x00000001U) |
||||
#define DMA_FLAG_TC1 ((uint32_t)0x00000002U) |
||||
#define DMA_FLAG_HT1 ((uint32_t)0x00000004U) |
||||
#define DMA_FLAG_TE1 ((uint32_t)0x00000008U) |
||||
#define DMA_FLAG_GL2 ((uint32_t)0x00000010U) |
||||
#define DMA_FLAG_TC2 ((uint32_t)0x00000020U) |
||||
#define DMA_FLAG_HT2 ((uint32_t)0x00000040U) |
||||
#define DMA_FLAG_TE2 ((uint32_t)0x00000080U) |
||||
#define DMA_FLAG_GL3 ((uint32_t)0x00000100U) |
||||
#define DMA_FLAG_TC3 ((uint32_t)0x00000200U) |
||||
#define DMA_FLAG_HT3 ((uint32_t)0x00000400U) |
||||
#define DMA_FLAG_TE3 ((uint32_t)0x00000800U) |
||||
#define DMA_FLAG_GL4 ((uint32_t)0x00001000U) |
||||
#define DMA_FLAG_TC4 ((uint32_t)0x00002000U) |
||||
#define DMA_FLAG_HT4 ((uint32_t)0x00004000U) |
||||
#define DMA_FLAG_TE4 ((uint32_t)0x00008000U) |
||||
#define DMA_FLAG_GL5 ((uint32_t)0x00010000U) |
||||
#define DMA_FLAG_TC5 ((uint32_t)0x00020000U) |
||||
#define DMA_FLAG_HT5 ((uint32_t)0x00040000U) |
||||
#define DMA_FLAG_TE5 ((uint32_t)0x00080000U) |
||||
#define DMA_FLAG_GL6 ((uint32_t)0x00100000U) |
||||
#define DMA_FLAG_TC6 ((uint32_t)0x00200000U) |
||||
#define DMA_FLAG_HT6 ((uint32_t)0x00400000U) |
||||
#define DMA_FLAG_TE6 ((uint32_t)0x00800000U) |
||||
#define DMA_FLAG_GL7 ((uint32_t)0x01000000U) |
||||
#define DMA_FLAG_TC7 ((uint32_t)0x02000000U) |
||||
#define DMA_FLAG_HT7 ((uint32_t)0x04000000U) |
||||
#define DMA_FLAG_TE7 ((uint32_t)0x08000000U) |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @brief Reset DMA handle state
|
||||
* @param __HANDLE__: DMA handle |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) |
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) |
||||
|
||||
|
||||
/* Interrupt & Flag management */ |
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer complete flag index. |
||||
*/ |
||||
|
||||
#if defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5) |
||||
#else |
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7)
|
||||
#endif |
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified half transfer complete flag index. |
||||
*/ |
||||
#if defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5) |
||||
#else |
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7) |
||||
#endif |
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer error flag index. |
||||
*/ |
||||
#if defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5) |
||||
#else |
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7) |
||||
#endif |
||||
/**
|
||||
* @brief Returns the current DMA Channel Global interrupt flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer error flag index. |
||||
*/ |
||||
#if defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||||
DMA_ISR_GIF5) |
||||
#else |
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
|
||||
DMA_ISR_GIF7) |
||||
#endif |
||||
/**
|
||||
* @brief Get the DMA Channel pending flags. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __FLAG__: Get the specified flag. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag |
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag |
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag |
||||
* @arg DMA_ISR_GIFx: Global interrupt flag |
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET). |
||||
*/ |
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __FLAG__: specifies the flag to clear. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag |
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag |
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag |
||||
* @arg DMA_ISR_GIFx: Global interrupt flag |
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
||||
|
||||
/**
|
||||
* @brief Enables the specified DMA Channel interrupts. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Disables the specified DMA Channel interrupts. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMA Channel interrupt is enabled or not. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __INTERRUPT__: specifies the DMA interrupt source to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
||||
* @retval The state of DMA_IT (SET or RESET). |
||||
*/ |
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) |
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer. |
||||
* @param __HANDLE__: DMA handle |
||||
* |
||||
* @retval The number of remaining data units in the current DMA Channel transfer. |
||||
*/ |
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Initialization and de-initialization functions *****************************/ |
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* IO operation functions *****************************************************/ |
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Peripheral State and Error functions ***************************************/ |
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Define the private group ***********************************/ |
||||
/**************************************************************/ |
||||
/** @defgroup DMA_Private DMA Private
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**************************************************************/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_DMA_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,386 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_flash.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of Flash HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
******************************************************************************
|
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_FLASH_H |
||||
#define __STM32L0xx_HAL_FLASH_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Private_Constants
|
||||
* @{ |
||||
*/ |
||||
#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ |
||||
#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Private_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(_VALUE_) ((_VALUE_) == FLASH_TYPEPROGRAM_WORD) |
||||
|
||||
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ |
||||
((__LATENCY__) == FLASH_LATENCY_1)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition |
||||
*/ |
||||
typedef enum
|
||||
{ |
||||
FLASH_PROC_NONE = 0,
|
||||
FLASH_PROC_PAGEERASE = 1, |
||||
FLASH_PROC_PROGRAM = 2, |
||||
} FLASH_ProcedureTypeDef; |
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ |
||||
|
||||
__IO uint32_t NbPagesToErase; /*!< Internal variable to save the remaining sectors to erase in IT context*/ |
||||
|
||||
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ |
||||
|
||||
__IO uint32_t Page; /*!< Internal variable to define the current page which is erasing */ |
||||
|
||||
HAL_LockTypeDef Lock; /*!< FLASH locking object */ |
||||
|
||||
__IO uint32_t ErrorCode; /*!< FLASH error code
|
||||
This parameter can be a value of @ref FLASH_Error_Codes */ |
||||
} FLASH_ProcessTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error_Codes FLASH Error Codes
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ |
||||
#define HAL_FLASH_ERROR_PGA 0x01U /*!< Programming alignment error */ |
||||
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ |
||||
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ |
||||
#define HAL_FLASH_ERROR_SIZE 0x08U /*!< */ |
||||
#define HAL_FLASH_ERROR_RD 0x10U /*!< Read protected error */ |
||||
#define HAL_FLASH_ERROR_FWWERR 0x20U /*!< FLASH Write or Erase operation aborted */ |
||||
#define HAL_FLASH_ERROR_NOTZERO 0x40U /*!< FLASH Write operation is done in a not-erased region */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Page_Size FLASH size information
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFF) * 1024U) |
||||
#define FLASH_PAGE_SIZE ((uint32_t)128U) /*!< FLASH Page Size in bytes */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{ |
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{ |
||||
*/
|
||||
#define FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */ |
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Interrupts FLASH Interrupts
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */ |
||||
#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */ |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags FLASH Flags
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ |
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ |
||||
#define FLASH_FLAG_ENDHV FLASH_SR_HVOFF /*!< FLASH End of High Voltage flag */ |
||||
#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */ |
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ |
||||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ |
||||
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ |
||||
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */ |
||||
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protected error flag */ |
||||
#define FLASH_FLAG_FWWERR FLASH_SR_FWWERR /*!< FLASH Write or Errase operation aborted */ |
||||
#define FLASH_FLAG_NOTZEROERR FLASH_SR_NOTZEROERR /*!< FLASH Read protected error flag */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys FLASH Keys
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */ |
||||
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 |
||||
to unlock the RUN_PD bit in FLASH_ACR */ |
||||
|
||||
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEFU) /*!< Flash program erase key1 */ |
||||
#define FLASH_PEKEY2 ((uint32_t)0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2 |
||||
to unlock the write access to the FLASH_PECR register and |
||||
data EEPROM */ |
||||
|
||||
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBFU) /*!< Flash program memory key1 */ |
||||
#define FLASH_PRGKEY2 ((uint32_t)0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2 |
||||
to unlock the program memory */ |
||||
|
||||
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8U) /*!< Flash option key1 */ |
||||
#define FLASH_OPTKEY2 ((uint32_t)0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to |
||||
unlock the write access to the option byte block */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* CMSIS_Legacy */
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup FLASH_Interrupt FLASH Interrupts
|
||||
* @brief macros to handle FLASH interrupts |
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt. |
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt |
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->PECR), (__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt. |
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt |
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__ specifies the FLASH flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag |
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag |
||||
* @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode |
||||
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag |
||||
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag |
||||
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx) |
||||
* @arg @ref FLASH_FLAG_RDERR FLASH Read protected error flag |
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_FWWERR FLASH Fetch While Write Error flag |
||||
* @arg @ref FLASH_FLAG_NOTZEROERR Not Zero area error flag
|
||||
* @retval The new state of __FLAG__ (SET or RESET). |
||||
*/ |
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) |
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag. |
||||
* @param __FLAG__ specifies the FLASH flags to clear. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag |
||||
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag |
||||
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx) |
||||
* @arg @ref FLASH_FLAG_RDERR FLASH Read protected error flag |
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_FWWERR FLASH Fetch While Write Error flag |
||||
* @arg @ref FLASH_FLAG_NOTZEROERR Not Zero area error flag
|
||||
* @retval none |
||||
*/ |
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extended module */ |
||||
#include "stm32l0xx_hal_flash_ex.h" |
||||
#include "stm32l0xx_hal_flash_ramfunc.h" |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
/* IO operation functions *****************************************************/ |
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); |
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data); |
||||
|
||||
/* FLASH IRQ handler function */ |
||||
void HAL_FLASH_IRQHandler(void); |
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); |
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral Control functions ***********************************************/ |
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral State and Error functions ***************************************/ |
||||
uint32_t HAL_FLASH_GetError(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private function -------------------------------------------------*/ |
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{ |
||||
*/ |
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_FLASH_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,827 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_flash_ex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of Flash HAL Extended module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_FLASH_EX_H |
||||
#define __STM32L0xx_HAL_FLASH_EX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Constants
|
||||
* @{ |
||||
*/ |
||||
#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE |
||||
|
||||
#define FLASH_NBPAGES_MAX (FLASH_SIZE / FLASH_PAGE_SIZE) |
||||
|
||||
#define WRP_MASK_LOW (0x0000FFFFU) |
||||
#define WRP_MASK_HIGH (0xFFFF0000U) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES)) |
||||
|
||||
#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | \ |
||||
OPTIONBYTE_USER | OPTIONBYTE_BOR | OPTIONBYTE_BOOT_BIT1))) |
||||
|
||||
#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \ |
||||
((__VALUE__) == OB_WRPSTATE_ENABLE)) |
||||
|
||||
#define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U)) |
||||
|
||||
#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\ |
||||
((__LEVEL__) == OB_RDP_LEVEL_1) ||\
|
||||
((__LEVEL__) == OB_RDP_LEVEL_2)) |
||||
|
||||
#define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \ |
||||
((__LEVEL__) == OB_BOR_LEVEL1) || \
|
||||
((__LEVEL__) == OB_BOR_LEVEL2) || \
|
||||
((__LEVEL__) == OB_BOR_LEVEL3) || \
|
||||
((__LEVEL__) == OB_BOR_LEVEL4) || \
|
||||
((__LEVEL__) == OB_BOR_LEVEL5)) |
||||
|
||||
#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW)) |
||||
|
||||
#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST)) |
||||
|
||||
#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST)) |
||||
|
||||
#if defined(FLASH_OPTR_WPRMOD) && defined(FLASH_OPTR_BFB2) |
||||
|
||||
#define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)) |
||||
|
||||
#elif defined(FLASH_OPTR_WPRMOD) && !defined(FLASH_OPTR_BFB2) |
||||
|
||||
#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP) |
||||
|
||||
#elif !defined(FLASH_OPTR_WPRMOD) && defined(FLASH_OPTR_BFB2) |
||||
|
||||
#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG) |
||||
|
||||
#endif /* FLASH_OPTR_WPRMOD && FLASH_OPTR_BFB2 */ |
||||
|
||||
#if defined(FLASH_OPTR_WPRMOD) |
||||
|
||||
#define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \ |
||||
((__VALUE__) == OB_PCROP_STATE_ENABLE))
|
||||
|
||||
#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U)) |
||||
#endif /* FLASH_OPTR_WPRMOD */ |
||||
|
||||
#if defined(FLASH_OPTR_BFB2) |
||||
|
||||
#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1)) |
||||
|
||||
#endif /* FLASH_OPTR_BFB2 */ |
||||
|
||||
#define IS_OB_BOOT1(__BOOT_BIT1__) (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET)) |
||||
#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \ |
||||
((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
|
||||
((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD)) |
||||
|
||||
|
||||
/** @defgroup FLASHEx_Address FLASHEx Address
|
||||
* @{ |
||||
*/ |
||||
|
||||
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
|
||||
#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END)) |
||||
#define IS_FLASH_DATA_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK1_END)) |
||||
#define IS_FLASH_DATA_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BANK2_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END)) |
||||
#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE))) |
||||
#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + (FLASH_SIZE >> 1)))) |
||||
#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE))) |
||||
#else |
||||
#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_END)) |
||||
#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE))) |
||||
#endif |
||||
|
||||
#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t TypeErase; /*!< TypeErase: Page Erase only.
|
||||
This parameter can be a value of @ref FLASHEx_Type_Erase */ |
||||
|
||||
uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
|
||||
This parameter must be a value belonging to FLASH Programm address (depending on the devices) */ |
||||
|
||||
uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
|
||||
This parameter must be a value between 1 and (max number of pages - value of Initial page)*/ |
||||
|
||||
} FLASH_EraseInitTypeDef; |
||||
|
||||
/**
|
||||
* @brief FLASH Option Bytes PROGRAM structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Type */ |
||||
|
||||
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASHEx_WRP_State */ |
||||
|
||||
uint32_t WRPSector; /*!< WRPSector: This bitfield specifies the sector (s) which are write protected.
|
||||
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection */ |
||||
|
||||
#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) |
||||
uint32_t WRPSector2; /*!< WRPSector2 : This bitfield specifies the sector(s) upper Sector31 which are write protected.
|
||||
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ |
||||
#endif |
||||
|
||||
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ |
||||
|
||||
uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */ |
||||
|
||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
|
||||
This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog,
|
||||
@ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ |
||||
|
||||
uint8_t BOOTBit1Config; /*!< BOOT1Config: Together with input pad Boot0, this bit selects the boot source, flash, ram or system memory
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOTBit1 */ |
||||
} FLASH_OBProgramInitTypeDef; |
||||
|
||||
#if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2) |
||||
/**
|
||||
* @brief FLASH Advanced Option Bytes Program structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
|
||||
This parameter can be a value of @ref FLASHEx_OptionAdv_Type */ |
||||
|
||||
#if defined(FLASH_OPTR_WPRMOD) |
||||
uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
|
||||
This parameter can be a value of @ref FLASHEx_PCROP_State */ |
||||
|
||||
uint32_t PCROPSector; /*!< PCROPSector : This bitfield specifies the sector(s) which are read/write protected.
|
||||
This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ |
||||
|
||||
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
uint32_t PCROPSector2; /*!< PCROPSector : This bitfield specifies the sector(s) upper Sector31 which are read/write protected.
|
||||
This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */ |
||||
#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ |
||||
#endif /* FLASH_OPTR_WPRMOD */ |
||||
|
||||
#if defined(FLASH_OPTR_BFB2) |
||||
uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */ |
||||
#endif /* FLASH_OPTR_BFB2*/ |
||||
} FLASH_AdvOBProgramInitTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
|
||||
* @{ |
||||
*/ |
||||
#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!<Page erase only*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_Option_Type FLASHEx Option Type
|
||||
* @{ |
||||
*/ |
||||
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!<WRP option byte configuration*/ |
||||
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!<RDP option byte configuration*/ |
||||
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!<USER option byte configuration*/ |
||||
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!<BOR option byte configuration*/ |
||||
#define OPTIONBYTE_BOOT_BIT1 ((uint32_t)0x10U) /*!< BOOT PIN1 option byte configuration*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_WRP_State FLASHEx WRP State
|
||||
* @{ |
||||
*/ |
||||
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!<Disable the write protection of the desired sectors*/ |
||||
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!<Enable the write protection of the desired sectors*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) |
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
||||
* @{ |
||||
*/ |
||||
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */ |
||||
#define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */ |
||||
#define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */ |
||||
#define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */ |
||||
#define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */ |
||||
#define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */ |
||||
#define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */ |
||||
#define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */ |
||||
#define OB_WRP_AllPages ((uint32_t)0x000000FFU) /*!< Write protection of all Sectors */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) |
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
||||
* @{ |
||||
*/ |
||||
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */ |
||||
#define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */ |
||||
#define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */ |
||||
#define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */ |
||||
#define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */ |
||||
#define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */ |
||||
#define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */ |
||||
#define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */ |
||||
#define OB_WRP_Pages256to287 ((uint32_t)0x00000100U) /* Write protection of Sector8 */ |
||||
#define OB_WRP_Pages288to319 ((uint32_t)0x00000200U) /* Write protection of Sector9 */ |
||||
#define OB_WRP_Pages320to351 ((uint32_t)0x00000400U) /* Write protection of Sector10 */ |
||||
#define OB_WRP_Pages352to383 ((uint32_t)0x00000800U) /* Write protection of Sector11 */ |
||||
#define OB_WRP_Pages384to415 ((uint32_t)0x00001000U) /* Write protection of Sector12 */ |
||||
#define OB_WRP_Pages416to447 ((uint32_t)0x00002000U) /* Write protection of Sector13 */ |
||||
#define OB_WRP_Pages448to479 ((uint32_t)0x00004000U) /* Write protection of Sector14 */ |
||||
#define OB_WRP_Pages480to511 ((uint32_t)0x00008000U) /* Write protection of Sector15 */ |
||||
#define OB_WRP_AllPages ((uint32_t)0x0000FFFFU) /*!< Write protection of all Sectors */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#elif defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write ProtectionP
|
||||
* @{ |
||||
*/ |
||||
#define OB_WRP_Pages0to31 ((uint32_t)0x00000001U) /* Write protection of Sector0 */ |
||||
#define OB_WRP_Pages32to63 ((uint32_t)0x00000002U) /* Write protection of Sector1 */ |
||||
#define OB_WRP_Pages64to95 ((uint32_t)0x00000004U) /* Write protection of Sector2 */ |
||||
#define OB_WRP_Pages96to127 ((uint32_t)0x00000008U) /* Write protection of Sector3 */ |
||||
#define OB_WRP_Pages128to159 ((uint32_t)0x00000010U) /* Write protection of Sector4 */ |
||||
#define OB_WRP_Pages160to191 ((uint32_t)0x00000020U) /* Write protection of Sector5 */ |
||||
#define OB_WRP_Pages192to223 ((uint32_t)0x00000040U) /* Write protection of Sector6 */ |
||||
#define OB_WRP_Pages224to255 ((uint32_t)0x00000080U) /* Write protection of Sector7 */ |
||||
#define OB_WRP_Pages256to287 ((uint32_t)0x00000100U) /* Write protection of Sector8 */ |
||||
#define OB_WRP_Pages288to319 ((uint32_t)0x00000200U) /* Write protection of Sector9 */ |
||||
#define OB_WRP_Pages320to351 ((uint32_t)0x00000400U) /* Write protection of Sector10 */ |
||||
#define OB_WRP_Pages352to383 ((uint32_t)0x00000800U) /* Write protection of Sector11 */ |
||||
#define OB_WRP_Pages384to415 ((uint32_t)0x00001000U) /* Write protection of Sector12 */ |
||||
#define OB_WRP_Pages416to447 ((uint32_t)0x00002000U) /* Write protection of Sector13 */ |
||||
#define OB_WRP_Pages448to479 ((uint32_t)0x00004000U) /* Write protection of Sector14 */ |
||||
#define OB_WRP_Pages480to511 ((uint32_t)0x00008000U) /* Write protection of Sector15 */ |
||||
#define OB_WRP_Pages512to543 ((uint32_t)0x00010000U) /* Write protection of Sector16 */ |
||||
#define OB_WRP_Pages544to575 ((uint32_t)0x00020000U) /* Write protection of Sector17 */ |
||||
#define OB_WRP_Pages576to607 ((uint32_t)0x00040000U) /* Write protection of Sector18 */ |
||||
#define OB_WRP_Pages608to639 ((uint32_t)0x00080000U) /* Write protection of Sector19 */ |
||||
#define OB_WRP_Pages640to671 ((uint32_t)0x00100000U) /* Write protection of Sector20 */ |
||||
#define OB_WRP_Pages672to703 ((uint32_t)0x00200000U) /* Write protection of Sector21 */ |
||||
#define OB_WRP_Pages704to735 ((uint32_t)0x00400000U) /* Write protection of Sector22 */ |
||||
#define OB_WRP_Pages736to767 ((uint32_t)0x00800000U) /* Write protection of Sector23 */ |
||||
#define OB_WRP_Pages768to799 ((uint32_t)0x01000000U) /* Write protection of Sector24 */ |
||||
#define OB_WRP_Pages800to831 ((uint32_t)0x02000000U) /* Write protection of Sector25 */ |
||||
#define OB_WRP_Pages832to863 ((uint32_t)0x04000000U) /* Write protection of Sector26 */ |
||||
#define OB_WRP_Pages864to895 ((uint32_t)0x08000000U) /* Write protection of Sector27 */ |
||||
#define OB_WRP_Pages896to927 ((uint32_t)0x10000000U) /* Write protection of Sector28 */ |
||||
#define OB_WRP_Pages928to959 ((uint32_t)0x20000000U) /* Write protection of Sector29 */ |
||||
#define OB_WRP_Pages960to991 ((uint32_t)0x40000000U) /* Write protection of Sector30 */ |
||||
#define OB_WRP_Pages992to1023 ((uint32_t)0x80000000U) /* Write protection of Sector31 */ |
||||
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFFU) /*!<Write protection of all Sectors */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASH Option Bytes Write Protection
|
||||
* @{ |
||||
*/ |
||||
#define OB_WRP2_Pages1024to1055 ((uint32_t)0x00000001U) /* Write protection of Sector32 */ |
||||
#define OB_WRP2_Pages1056to1087 ((uint32_t)0x00000002U) /* Write protection of Sector33 */ |
||||
#define OB_WRP2_Pages1088to1119 ((uint32_t)0x00000004U) /* Write protection of Sector34 */ |
||||
#define OB_WRP2_Pages1120to1151 ((uint32_t)0x00000008U) /* Write protection of Sector35 */ |
||||
#define OB_WRP2_Pages1152to1183 ((uint32_t)0x00000010U) /* Write protection of Sector36 */ |
||||
#define OB_WRP2_Pages1184to1215 ((uint32_t)0x00000020U) /* Write protection of Sector37 */ |
||||
#define OB_WRP2_Pages1216to1247 ((uint32_t)0x00000040U) /* Write protection of Sector38 */ |
||||
#define OB_WRP2_Pages1248to1279 ((uint32_t)0x00000080U) /* Write protection of Sector39 */ |
||||
#define OB_WRP2_Pages1280to1311 ((uint32_t)0x00000100U) /* Write protection of Sector40 */ |
||||
#define OB_WRP2_Pages1312to1343 ((uint32_t)0x00000200U) /* Write protection of Sector41 */ |
||||
#define OB_WRP2_Pages1344to1375 ((uint32_t)0x00000400U) /* Write protection of Sector42 */ |
||||
#define OB_WRP2_Pages1376to1407 ((uint32_t)0x00000800U) /* Write protection of Sector43 */ |
||||
#define OB_WRP2_Pages1408to1439 ((uint32_t)0x00001000U) /* Write protection of Sector44 */ |
||||
#define OB_WRP2_Pages1440to1471 ((uint32_t)0x00002000U) /* Write protection of Sector45 */ |
||||
#define OB_WRP2_Pages1472to1503 ((uint32_t)0x00004000U) /* Write protection of Sector46 */ |
||||
#define OB_WRP2_Pages1504to1535 ((uint32_t)0x00008000U) /* Write protection of Sector47 */ |
||||
#define OB_WRP2_AllPages ((uint32_t)0x0000FFFFU) /*!< Write protection of all Sectors WRP2 */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* STM32L071xx || STM32L072xx || (STM32L073xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */ |
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
|
||||
* @{ |
||||
*/
|
||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) |
||||
#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU) |
||||
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2 |
||||
it is no more possible to go back to level 1 or 0 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD |
||||
power supply reaches the PDR(Power Down Reset) threshold (1.5V) */ |
||||
#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */ |
||||
#define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */ |
||||
#define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */ |
||||
#define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */ |
||||
#define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */ |
||||
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */ |
||||
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */ |
||||
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined(FLASH_OPTR_WPRMOD) |
||||
|
||||
/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!<PCROP option byte configuration*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* FLASH_OPTR_WPRMOD */ |
||||
|
||||
#if defined(FLASH_OPTR_BFB2) |
||||
|
||||
/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02U) /*!<BOOTConfig option byte configuration*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* FLASH_OPTR_BFB2 */ |
||||
|
||||
#if defined(FLASH_OPTR_WPRMOD) |
||||
|
||||
/** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State
|
||||
* @{ |
||||
*/ |
||||
#define OB_PCROP_STATE_DISABLE ((uint32_t)0x00U) /*!<Disable PCROP for selected sectors */ |
||||
#define OB_PCROP_STATE_ENABLE ((uint32_t)0x01U) /*!<Enable PCROP for selected sectors */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
|
||||
* @{ |
||||
*/ |
||||
#define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */ |
||||
#define OB_PCROP_SELECTED ((uint16_t)FLASH_OPTR_WPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* FLASH_OPTR_WPRMOD */ |
||||
|
||||
#if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) |
||||
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
|
||||
* @{ |
||||
*/ |
||||
#define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */ |
||||
#define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */ |
||||
#define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */ |
||||
#define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */ |
||||
#define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */ |
||||
#define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */ |
||||
#define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */ |
||||
#define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */ |
||||
#define OB_PCROP_AllPages ((uint32_t)0x000000FFU) /*!< PC Read/Write protection of all Sectors */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) |
||||
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASHEx Option Bytes PC Read/Write Protection
|
||||
* @{ |
||||
*/ |
||||
#define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */ |
||||
#define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */ |
||||
#define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */ |
||||
#define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */ |
||||
#define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */ |
||||
#define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */ |
||||
#define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */ |
||||
#define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */ |
||||
#define OB_PCROP_Pages256to287 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */ |
||||
#define OB_PCROP_Pages288to319 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */ |
||||
#define OB_PCROP_Pages320to351 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */ |
||||
#define OB_PCROP_Pages352to383 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */ |
||||
#define OB_PCROP_Pages384to415 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */ |
||||
#define OB_PCROP_Pages416to447 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */ |
||||
#define OB_PCROP_Pages448to479 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */ |
||||
#define OB_PCROP_Pages480to511 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */ |
||||
#define OB_PCROP_AllPages ((uint32_t)0x0000FFFFU) /*!< PC Read/Write protection of all Sectors */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif |
||||
|
||||
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC Read/Write Protection
|
||||
* @{ |
||||
*/ |
||||
#define OB_PCROP_Pages0to31 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */ |
||||
#define OB_PCROP_Pages32to63 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */ |
||||
#define OB_PCROP_Pages64to95 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */ |
||||
#define OB_PCROP_Pages96to127 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */ |
||||
#define OB_PCROP_Pages128to159 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */ |
||||
#define OB_PCROP_Pages160to191 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */ |
||||
#define OB_PCROP_Pages192to223 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */ |
||||
#define OB_PCROP_Pages224to255 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */ |
||||
#define OB_PCROP_Pages256to287 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */ |
||||
#define OB_PCROP_Pages288to319 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */ |
||||
#define OB_PCROP_Pages320to351 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */ |
||||
#define OB_PCROP_Pages352to383 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */ |
||||
#define OB_PCROP_Pages384to415 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */ |
||||
#define OB_PCROP_Pages416to447 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */ |
||||
#define OB_PCROP_Pages448to479 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */ |
||||
#define OB_PCROP_Pages480to511 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */ |
||||
#define OB_PCROP_Pages512to543 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector16 */ |
||||
#define OB_PCROP_Pages544to575 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector17 */ |
||||
#define OB_PCROP_Pages576to607 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector18 */ |
||||
#define OB_PCROP_Pages608to639 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector19 */ |
||||
#define OB_PCROP_Pages640to671 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector20 */ |
||||
#define OB_PCROP_Pages672to703 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector21 */ |
||||
#define OB_PCROP_Pages704to735 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector22 */ |
||||
#define OB_PCROP_Pages736to767 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector23 */ |
||||
#define OB_PCROP_Pages768to799 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector24 */ |
||||
#define OB_PCROP_Pages800to831 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector25 */ |
||||
#define OB_PCROP_Pages832to863 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector26 */ |
||||
#define OB_PCROP_Pages864to895 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector27 */ |
||||
#define OB_PCROP_Pages896to927 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector28 */ |
||||
#define OB_PCROP_Pages928to959 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector29 */ |
||||
#define OB_PCROP_Pages960to991 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector30 */ |
||||
#define OB_PCROP_Pages992to1023 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector31 */ |
||||
#define OB_PCROP_AllPages ((uint32_t)0xFFFFFFFFU) /*!<PC Read/Write protection of all Sectors */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASH Option Bytes PC Read/Write Protection (Sector 2)
|
||||
* @{ |
||||
*/ |
||||
#define OB_PCROP2_Pages1024to1055 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector32 */ |
||||
#define OB_PCROP2_Pages1056to1087 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector33 */ |
||||
#define OB_PCROP2_Pages1088to1119 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector34 */ |
||||
#define OB_PCROP2_Pages1120to1151 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector35 */ |
||||
#define OB_PCROP2_Pages1152to1183 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector36 */ |
||||
#define OB_PCROP2_Pages1184to1215 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector37 */ |
||||
#define OB_PCROP2_Pages1216to1247 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector38 */ |
||||
#define OB_PCROP2_Pages1248to1279 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector39 */ |
||||
#define OB_PCROP2_Pages1280to1311 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector40 */ |
||||
#define OB_PCROP2_Pages1312to1343 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector41 */ |
||||
#define OB_PCROP2_Pages1344to1375 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector42 */ |
||||
#define OB_PCROP2_Pages1376to1407 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector43 */ |
||||
#define OB_PCROP2_Pages1408to1439 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector44 */ |
||||
#define OB_PCROP2_Pages1440to1471 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector45 */ |
||||
#define OB_PCROP2_Pages1472to1503 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector46 */ |
||||
#define OB_PCROP2_Pages1504to1535 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector47 */ |
||||
#define OB_PCROP2_AllPages ((uint32_t)0x0000FFFFU) /*!< PC Read/Write protection of all Sectors PCROP2 */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ |
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_BOOTBit1 FLASH Option Bytes BOOT Bit1 Setup
|
||||
* @{ |
||||
*/ |
||||
#define OB_BOOT_BIT1_RESET (uint8_t)(0x00U) /*!< BOOT Bit 1 Reset */ |
||||
#define OB_BOOT_BIT1_SET (uint8_t)(0x01U) /*!< BOOT Bit 1 Set */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
|
||||
* @{ |
||||
*/ |
||||
#define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00U) /*!<Program byte (8-bit) at a specified address.*/ |
||||
#define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01U) /*!<Program a half-word (16-bit) at a specified address.*/ |
||||
#define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined(FLASH_OPTR_BFB2) |
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define OB_BOOT_BANK1 ((uint8_t)0x00U) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position |
||||
and this parameter is selected the device will boot from Bank 1 (Default)*/ |
||||
#define OB_BOOT_BANK2 ((uint8_t)(FLASH_OPTR_BFB2 >> 16)) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position |
||||
and this parameter is selected the device will boot from Bank 2 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* FLASH_OPTR_BFB2 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency. |
||||
* @param __LATENCY__ FLASH Latency |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle |
||||
* @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ |
||||
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) |
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency. |
||||
* @retval FLASH Latency
|
||||
* This parameter can be one of the following values: |
||||
* @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle |
||||
* @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle |
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) |
||||
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer. |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) |
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer. |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) |
||||
|
||||
/**
|
||||
* @brief Enable the FLASH Buffer cache. |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_BUFFER_CACHE_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF) |
||||
|
||||
/**
|
||||
* @brief Disable the FLASH Buffer cache. |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_BUFFER_CACHE_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF) |
||||
|
||||
/**
|
||||
* @brief Enable the FLASH preread buffer. |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_PREREAD_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRE_READ) |
||||
|
||||
/**
|
||||
* @brief Disable the FLASH preread buffer. |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_PREREAD_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRE_READ) |
||||
|
||||
/**
|
||||
* @brief Enable the FLASH power down during Sleep mode |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) |
||||
|
||||
/**
|
||||
* @brief Disable the FLASH power down during Sleep mode |
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) |
||||
|
||||
/**
|
||||
* @brief Enable the Flash Run power down mode. |
||||
* @note Writing this bit to 0 this bit, automatically the keys are |
||||
* loss and a new unlock sequence is necessary to re-write it to 1. |
||||
*/ |
||||
#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ |
||||
FLASH->PDKEYR = FLASH_PDKEY2; \
|
||||
SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
|
||||
} while (0) |
||||
|
||||
/**
|
||||
* @brief Disable the Flash Run power down mode. |
||||
* @note Writing this bit to 0 this bit, automatically the keys are |
||||
* loss and a new unlock sequence is necessary to re-write it to 1. |
||||
*/ |
||||
#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ |
||||
FLASH->PDKEYR = FLASH_PDKEY2; \
|
||||
CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
|
||||
} while (0) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); |
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); |
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); |
||||
|
||||
#if defined(FLASH_OPTR_WPRMOD) || defined(FLASH_OPTR_BFB2) |
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); |
||||
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); |
||||
|
||||
#endif /* FLASH_OPTR_WPRMOD || FLASH_OPTR_BFB2 */ |
||||
|
||||
#if defined(FLASH_OPTR_WPRMOD) |
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); |
||||
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); |
||||
|
||||
#endif /* FLASH_OPTR_WPRMOD */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group3
|
||||
* @{ |
||||
*/ |
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void); |
||||
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void); |
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address); |
||||
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); |
||||
void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void); |
||||
void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_FLASH_EX_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,124 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_flash_ramfunc.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of FLASH RAMFUNC driver. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_FLASH_RAMFUNC_H |
||||
#define __STM32L0xx_FLASH_RAMFUNC_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_RAMFUNC
|
||||
* @{ |
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup FLASH_RAMFUNC_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/*
|
||||
* @brief FLASH memory functions that should be executed from internal SRAM. |
||||
* These functions are defined inside the "stm32l0xx_hal_flash_ramfunc.c" |
||||
* file. |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
|
||||
__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void); |
||||
__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
|
||||
#if defined(FLASH_PECR_PARALLBANK) |
||||
|
||||
__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2); |
||||
__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2); |
||||
|
||||
#endif /* FLASH_PECR_PARALLBANK */ |
||||
|
||||
__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer); |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group3
|
||||
* @{ |
||||
*/ |
||||
__RAM_FUNC HAL_FLASHEx_GetError(uint32_t *Error); |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_FLASH_RAMFUNC_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,342 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_gpio.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of GPIO HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_GPIO_H |
||||
#define __STM32L0xx_HAL_GPIO_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @{ |
||||
*/
|
||||
/******************************************************************************/ |
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/******************************************************************************/ |
||||
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_Init_Configuration GPIO init configuration structure
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct |
||||
{ |
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be a combination of @ref GPIO_pins_define */ |
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode_define */ |
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull_define */ |
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed_define */ |
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ |
||||
}GPIO_InitTypeDef; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_SetReset_Definition GPIO set reset definition
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/ |
||||
typedef enum |
||||
{ |
||||
GPIO_PIN_RESET = 0U, |
||||
GPIO_PIN_SET |
||||
}GPIO_PinState; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
#define IS_GPIO_PIN_ACTION(__ACTION__) (((__ACTION__) == GPIO_PIN_RESET) || ((__ACTION__) == GPIO_PIN_SET)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/******************************************************************************/ |
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/******************************************************************************/ |
||||
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup GPIO_pins_define Pin definition
|
||||
* @{ |
||||
*/ |
||||
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ |
||||
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ |
||||
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ |
||||
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ |
||||
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ |
||||
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ |
||||
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ |
||||
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ |
||||
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ |
||||
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ |
||||
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ |
||||
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ |
||||
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ |
||||
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ |
||||
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ |
||||
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ |
||||
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */ |
||||
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ |
||||
(((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00)) |
||||
|
||||
/** @defgroup GPIO_mode_define Mode definition
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ |
||||
* - X : GPIO mode or EXTI Mode |
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event |
||||
* - Y : Output type (Push Pull or Open Drain) |
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog) |
||||
* @{ |
||||
*/
|
||||
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ |
||||
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ |
||||
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */ |
||||
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */ |
||||
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */ |
||||
|
||||
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */ |
||||
|
||||
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ |
||||
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ |
||||
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
||||
|
||||
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ |
||||
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ |
||||
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ |
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_ANALOG)) |
||||
|
||||
|
||||
/** @defgroup GPIO_speed_define Speed definition
|
||||
* @brief GPIO Output Maximum frequency |
||||
* @{ |
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< range up to 0.4 MHz, please refer to the product datasheet */ |
||||
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< range 0.4 MHz to 2 MHz, please refer to the product datasheet */ |
||||
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< range 2 MHz to 10 MHz, please refer to the product datasheet */ |
||||
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< range 10 MHz to 35 MHz, please refer to the product datasheet */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW ) || ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM ) || \ |
||||
((__SPEED__) == GPIO_SPEED_FREQ_HIGH ) || ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) |
||||
|
||||
|
||||
/** @defgroup GPIO_pull_define Pull definition
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation |
||||
* @{ |
||||
*/
|
||||
#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */ |
||||
#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */ |
||||
#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) || ((__PULL__) == GPIO_PULLUP) || \ |
||||
((__PULL__) == GPIO_PULLDOWN)) |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/******************************************************************************/ |
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/******************************************************************************/ |
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup GPIO_Exported_Macro GPIO Exported Macros
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not. |
||||
* @param __EXTI_LINE__: specifies the EXTI line flag to check. |
||||
* This parameter can be GPIO_PIN_x where x can be(0..15) |
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET). |
||||
*/ |
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) |
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags. |
||||
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear. |
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) |
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not. |
||||
* @param __EXTI_LINE__: specifies the EXTI line to check. |
||||
* This parameter can be GPIO_PIN_x where x can be(0..15) |
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET). |
||||
*/ |
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) |
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits. |
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear. |
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) |
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line. |
||||
* @param __EXTI_LINE__: specifies the EXTI line to check. |
||||
* This parameter can be GPIO_PIN_x where x can be(0..15) |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Include GPIO HAL Extension module */ |
||||
#include "stm32l0xx_hal_gpio_ex.h" |
||||
|
||||
/******************************************************************************/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/******************************************************************************/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Initialization and de-initialization functions *******************************/ |
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{ |
||||
*/ |
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); |
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* IO operation functions *******************************************************/ |
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @{ |
||||
*/ |
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); |
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); |
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); |
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Define the private group ***********************************/ |
||||
/**************************************************************/ |
||||
/** @defgroup GPIO_Private GPIO Private
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**************************************************************/ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_GPIO_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,708 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_i2c.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of I2C HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_I2C_H |
||||
#define __STM32L0xx_HAL_I2C_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup I2C
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition |
||||
* @{ |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization |
||||
section in Reference manual */ |
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */ |
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */ |
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ |
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */ |
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ |
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ |
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ |
||||
|
||||
} I2C_InitTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition |
||||
* @note HAL I2C State value coding follow below described bitmap :\n |
||||
* b7-b6 Error information\n |
||||
* 00 : No Error\n |
||||
* 01 : Abort (Abort user request on going)\n |
||||
* 10 : Timeout\n |
||||
* 11 : Error\n |
||||
* b5 IP initilisation status\n |
||||
* 0 : Reset (IP not initialized)\n |
||||
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n |
||||
* b4 (not used)\n |
||||
* x : Should be set to 0\n |
||||
* b3\n |
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n |
||||
* 1 : Listen (IP in Address Listen Mode)\n |
||||
* b2 Intrinsic process state\n |
||||
* 0 : Ready\n |
||||
* 1 : Busy (IP busy with some configuration or internal operations)\n |
||||
* b1 Rx state\n |
||||
* 0 : Ready (no Rx operation ongoing)\n |
||||
* 1 : Busy (Rx operation ongoing)\n |
||||
* b0 Tx state\n |
||||
* 0 : Ready (no Tx operation ongoing)\n |
||||
* 1 : Busy (Tx operation ongoing) |
||||
* @{ |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ |
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ |
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ |
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ |
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ |
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */ |
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */ |
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ |
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ |
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ |
||||
|
||||
} HAL_I2C_StateTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition |
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n |
||||
* b7 (not used)\n |
||||
* x : Should be set to 0\n |
||||
* b6\n |
||||
* 0 : None\n |
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n |
||||
* b5\n |
||||
* 0 : None\n |
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n |
||||
* b4\n |
||||
* 0 : None\n |
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n |
||||
* b3-b2-b1-b0 (not used)\n |
||||
* xxxx : Should be set to 0000 |
||||
* @{ |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ |
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ |
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ |
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ |
||||
|
||||
} HAL_I2C_ModeTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition |
||||
* @{ |
||||
*/ |
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ |
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ |
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ |
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ |
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ |
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ |
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ |
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition |
||||
* @{ |
||||
*/ |
||||
typedef struct __I2C_HandleTypeDef |
||||
{ |
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */ |
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */ |
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ |
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */ |
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */ |
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */ |
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */ |
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ |
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ |
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ |
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */ |
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ |
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ |
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */ |
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ |
||||
} I2C_HandleTypeDef; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{ |
||||
*/ |
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) |
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) |
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) |
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) |
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{ |
||||
*/ |
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) |
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{ |
||||
*/ |
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U) |
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{ |
||||
*/ |
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U) |
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U) |
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U) |
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U) |
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U) |
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U) |
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U) |
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{ |
||||
*/ |
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U) |
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{ |
||||
*/ |
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U) |
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{ |
||||
*/ |
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U) |
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{ |
||||
*/ |
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U) |
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{ |
||||
*/ |
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD |
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND |
||||
#define I2C_SOFTEND_MODE (0x00000000U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{ |
||||
*/ |
||||
#define I2C_NO_STARTSTOP (0x00000000U) |
||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) |
||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) |
||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition |
||||
* Elements values convention: 0xXXXXXXXX |
||||
* - XXXXXXXX : Interrupt control mask |
||||
* @{ |
||||
*/ |
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE |
||||
#define I2C_IT_TCI I2C_CR1_TCIE |
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE |
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE |
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE |
||||
#define I2C_IT_RXI I2C_CR1_RXIE |
||||
#define I2C_IT_TXI I2C_CR1_TXIE |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{ |
||||
*/ |
||||
#define I2C_FLAG_TXE I2C_ISR_TXE |
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS |
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE |
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR |
||||
#define I2C_FLAG_AF I2C_ISR_NACKF |
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF |
||||
#define I2C_FLAG_TC I2C_ISR_TC |
||||
#define I2C_FLAG_TCR I2C_ISR_TCR |
||||
#define I2C_FLAG_BERR I2C_ISR_BERR |
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO |
||||
#define I2C_FLAG_OVR I2C_ISR_OVR |
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR |
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT |
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT |
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY |
||||
#define I2C_FLAG_DIR I2C_ISR_DIR |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macros -----------------------------------------------------------*/ |
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) |
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle. |
||||
* @param __INTERRUPT__ specifies the interrupt source to enable. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable |
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable |
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable |
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable |
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable |
||||
* @arg @ref I2C_IT_RXI RX interrupt enable |
||||
* @arg @ref I2C_IT_TXI TX interrupt enable |
||||
* |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) |
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle. |
||||
* @param __INTERRUPT__ specifies the interrupt source to disable. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable |
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable |
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable |
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable |
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable |
||||
* @arg @ref I2C_IT_RXI RX interrupt enable |
||||
* @arg @ref I2C_IT_TXI TX interrupt enable |
||||
* |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) |
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle. |
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable |
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable |
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable |
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable |
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable |
||||
* @arg @ref I2C_IT_RXI RX interrupt enable |
||||
* @arg @ref I2C_IT_TXI TX interrupt enable |
||||
* |
||||
* @retval The new state of __INTERRUPT__ (SET or RESET). |
||||
*/ |
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle. |
||||
* @param __FLAG__ specifies the flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty |
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status |
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty |
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode) |
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag |
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag |
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode) |
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload |
||||
* @arg @ref I2C_FLAG_BERR Bus error |
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost |
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun |
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception |
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag |
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert |
||||
* @arg @ref I2C_FLAG_BUSY Bus busy |
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) |
||||
* |
||||
* @retval The new state of __FLAG__ (SET or RESET). |
||||
*/ |
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) |
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle. |
||||
* @param __FLAG__ specifies the flag to clear. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty |
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode) |
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag |
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag |
||||
* @arg @ref I2C_FLAG_BERR Bus error |
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost |
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun |
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception |
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag |
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert |
||||
* |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ |
||||
: ((__HANDLE__)->Instance->ICR = (__FLAG__))) |
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) |
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) |
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Include I2C HAL Extended module */ |
||||
#include "stm32l0xx_hal_i2c_ex.h" |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{ |
||||
*/ |
||||
/* Initialization and de-initialization functions******************************/ |
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); |
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{ |
||||
*/ |
||||
/* IO operation functions ****************************************************/ |
||||
/******* Blocking mode: Polling */ |
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
||||
|
||||
/******* Non-Blocking mode: Interrupt */ |
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
||||
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
||||
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
||||
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); |
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); |
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); |
||||
|
||||
/******* Non-Blocking mode: DMA */ |
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{ |
||||
*/ |
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ |
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); |
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral State, Mode and Error functions *********************************/ |
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); |
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); |
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ |
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT)) |
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ |
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE)) |
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ |
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07)) |
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ |
||||
((CALL) == I2C_GENERALCALL_ENABLE)) |
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ |
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE)) |
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ |
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT)) |
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ |
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE)) |
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ |
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP)) |
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ |
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME)) |
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) |
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) |
||||
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) |
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) |
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) |
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) |
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) |
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) |
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) |
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) |
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ |
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private Functions ---------------------------------------------------------*/ |
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{ |
||||
*/ |
||||
/* Private functions are defined in stm32l0xx_hal_i2c.c file */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
|
||||
#endif /* __STM32L0xx_HAL_I2C_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,179 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_i2c_ex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of I2C HAL Extended module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_I2C_EX_H |
||||
#define __STM32L0xx_HAL_I2C_EX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{ |
||||
*/ |
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U |
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{ |
||||
*/ |
||||
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ |
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ |
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ |
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ |
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ |
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR2_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ |
||||
#if defined(SYSCFG_CFGR2_I2C2_FMP) |
||||
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR2_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ |
||||
#else |
||||
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ |
||||
#endif |
||||
#if defined(SYSCFG_CFGR2_I2C3_FMP) |
||||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR2_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ |
||||
#else |
||||
#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ |
||||
#endif |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions |
||||
* @{ |
||||
*/ |
||||
|
||||
/* Peripheral Control functions ************************************************/ |
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); |
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); |
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); |
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); |
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); |
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); |
||||
|
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{ |
||||
*/ |
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ |
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE)) |
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
||||
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ |
||||
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private Functions ---------------------------------------------------------*/ |
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{ |
||||
*/ |
||||
/* Private functions are defined in stm32l0xx_hal_i2c_ex.c file */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_I2C_EX_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,463 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_pwr.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of PWR HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_PWR_H |
||||
#define __STM32L0xx_HAL_PWR_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
||||
This parameter can be a value of @ref PWR_PVD_detection_level */ |
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode */ |
||||
}PWR_PVDTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup PWR_Private
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define PWR_EXTI_LINE_PVD EXTI_FTSR_TR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWR_register_alias_address PWR Register alias address
|
||||
* @{ |
||||
*/ |
||||
#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 |
||||
#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 |
||||
#if defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L071xx) || \ |
||||
defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
#define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3 |
||||
#endif |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_PVD_detection_level PVD detection level
|
||||
* @{ |
||||
*/ |
||||
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 |
||||
#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 |
||||
#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 |
||||
#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 |
||||
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 |
||||
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 |
||||
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 |
||||
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage |
||||
(Compare internally to VREFINT) */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_PVD_Mode PWR PVD Mode
|
||||
* @{ |
||||
*/ |
||||
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ |
||||
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ |
||||
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ |
||||
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
||||
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ |
||||
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ |
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
|
||||
* @{ |
||||
*/ |
||||
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) |
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{ |
||||
*/ |
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) |
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{ |
||||
*/ |
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) |
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 |
||||
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 |
||||
#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS |
||||
|
||||
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
||||
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
|
||||
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Flag PWR Flag
|
||||
* @{ |
||||
*/ |
||||
#define PWR_FLAG_WU PWR_CSR_WUF |
||||
#define PWR_FLAG_SB PWR_CSR_SBF |
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO |
||||
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF |
||||
#define PWR_FLAG_VOS PWR_CSR_VOSF |
||||
#define PWR_FLAG_REGLP PWR_CSR_REGLPF |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Exported_Macro PWR Exported Macros
|
||||
* @{ |
||||
*/ |
||||
/** @brief macros configure the main internal regulator output voltage.
|
||||
* When exiting Low Power Run Mode or during dynamic voltage scaling configuration, |
||||
* the reference manual recommends to poll PWR_FLAG_REGLP bit to wait for the regulator
|
||||
* to reach main mode (resp. to get stabilized) for a transition from 0 to 1.
|
||||
* Only then the clock can be increased. |
||||
* |
||||
* @param __REGULATOR__: specifies the regulator output voltage to achieve |
||||
* a tradeoff between performance and power consumption when the device does |
||||
* not operate at the maximum frequency (refer to the datasheets for more details). |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, |
||||
* System frequency up to 32 MHz. |
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, |
||||
* System frequency up to 16 MHz. |
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, |
||||
* System frequency up to 4.2 MHz |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) |
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
||||
* was received from the WKUP pin or from the RTC alarm (Alarm B), |
||||
* RTC Tamper event, RTC TimeStamp event or RTC Wakeup. |
||||
* An additional wakeup event is detected if the WKUP pin is enabled |
||||
* (by setting the EWUP bit) when the WKUP pin level is already high. |
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
||||
* resumed from StandBy mode. |
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode. |
||||
* For this reason, this bit is equal to 0 after Standby or reset |
||||
* until the PVDE bit is set. |
||||
* @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. |
||||
* This bit indicates the state of the internal voltage reference, VREFINT. |
||||
* @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for |
||||
* the internal regulator to be ready after the voltage range is changed. |
||||
* The VOSF bit indicates that the regulator has reached the voltage level |
||||
* defined with bits VOS of PWR_CR register. |
||||
* @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run |
||||
* mode, this bit stays at 1 until the regulator is ready in main mode. |
||||
* A polling on this bit is recommended to wait for the regulator main mode. |
||||
* This bit is reset by hardware when the regulator is ready. |
||||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
||||
*/ |
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
||||
|
||||
/** @brief Clear the PWR pending flags.
|
||||
* @param __FLAG__: specifies the flag to clear. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_FLAG_WU: Wake Up flag |
||||
* @arg PWR_FLAG_SB: StandBy flag |
||||
*/ |
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2U) |
||||
|
||||
/**
|
||||
* @brief Enable interrupt on PVD Exti Line 16. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief Disable interrupt on PVD Exti Line 16.
|
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief Enable event on PVD Exti Line 16. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief Disable event on PVD Exti Line 16. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set falling edge trigger.
|
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising edge trigger. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger. |
||||
* This parameter can be: |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising & falling edge trigger. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0); |
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
||||
* This parameter can be: |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0); |
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
||||
* @retval EXTI PVD Line Status. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
||||
|
||||
/**
|
||||
* @brief Clear the PVD EXTI flag. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup PWR_Private
|
||||
* @{ |
||||
*/ |
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
||||
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_NORMAL))
|
||||
|
||||
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
||||
((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3)) |
||||
#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) |
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
||||
((PIN) == PWR_WAKEUP_PIN2)) |
||||
#elif defined (STM32L031xx) || defined (STM32L041xx) |
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
||||
((PIN) == PWR_WAKEUP_PIN2)) |
||||
#elif defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
||||
((PIN) == PWR_WAKEUP_PIN3)) |
||||
#endif |
||||
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
||||
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Include PWR HAL Extension module */ |
||||
#include "stm32l0xx_hal_pwr_ex.h" |
||||
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{ |
||||
*/ |
||||
void HAL_PWR_DeInit(void); |
||||
void HAL_PWR_EnableBkUpAccess(void); |
||||
void HAL_PWR_DisableBkUpAccess(void); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* PVD control functions ************************************************/ |
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
||||
void HAL_PWR_EnablePVD(void); |
||||
void HAL_PWR_DisablePVD(void); |
||||
void HAL_PWR_PVD_IRQHandler(void); |
||||
void HAL_PWR_PVDCallback(void); |
||||
|
||||
/* WakeUp pins configuration functions ****************************************/ |
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
||||
|
||||
/* Low Power modes configuration functions ************************************/ |
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
||||
void HAL_PWR_EnterSTANDBYMode(void); |
||||
|
||||
void HAL_PWR_EnableSleepOnExit(void); |
||||
void HAL_PWR_DisableSleepOnExit(void); |
||||
void HAL_PWR_EnableSEVOnPend(void); |
||||
void HAL_PWR_DisableSEVOnPend(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Define the private group ***********************************/ |
||||
/**************************************************************/ |
||||
/** @defgroup PWR_Private PWR Private
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**************************************************************/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
|
||||
#endif /* __STM32L0xx_HAL_PWR_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,115 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_pwr_ex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of PWR HAL Extension module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_PWR_EX_H |
||||
#define __STM32L0xx_HAL_PWR_EX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWREx PWREx
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWREx_Exported_Macros PWREx Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Macros to enable the Deep-sleep mode with Flash memory kept off.
|
||||
* @note When entering low power mode (stop or standby only), if DS_EE_KOFF and RUN_PD of |
||||
* FLASH_ACR register are both set , the Flash memory will not be woken up
|
||||
* when exiting from deep-sleep mode. |
||||
*/ |
||||
#define __HAL_PWR_FLASHWAKEUP_ENABLE() CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF) |
||||
|
||||
/** @brief Macros to disable the Deep-sleep mode with Flash memory kept off.
|
||||
* @note When entering low power mode (stop or standby only), if DS_EE_KOFF and RUN_PD of |
||||
* FLASH_ACR register are both set , the Flash memory will not be woken up
|
||||
* when exiting from deep-sleep mode. |
||||
*/ |
||||
#define __HAL_PWR_FLASHWAKEUP_DISABLE() SET_BIT(PWR->CR, PWR_CR_DSEEKOFF) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{ |
||||
*/ |
||||
uint32_t HAL_PWREx_GetVoltageRange(void); |
||||
void HAL_PWREx_EnableFastWakeUp(void); |
||||
void HAL_PWREx_DisableFastWakeUp(void); |
||||
void HAL_PWREx_EnableUltraLowPower(void); |
||||
void HAL_PWREx_DisableUltraLowPower(void); |
||||
void HAL_PWREx_EnableLowPowerRunMode(void); |
||||
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Define the private group ***********************************/ |
||||
/**************************************************************/ |
||||
/** @defgroup PWREx_Private PWREx Private
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**************************************************************/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_PWR_EX_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,904 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_rtc.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of RTC HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_RTC_H |
||||
#define __STM32L0xx_HAL_RTC_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup RTC RTC
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Types RTC Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ |
||||
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ |
||||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ |
||||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ |
||||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ |
||||
|
||||
}HAL_RTCStateTypeDef; |
||||
|
||||
/**
|
||||
* @brief RTC Configuration Structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */ |
||||
|
||||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ |
||||
|
||||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ |
||||
|
||||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
|
||||
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ |
||||
|
||||
uint32_t OutPutRemap; /*!< Specifies the remap for RTC output.
|
||||
This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */ |
||||
|
||||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
|
||||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ |
||||
|
||||
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
|
||||
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ |
||||
}RTC_InitTypeDef; |
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. |
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ |
||||
|
||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ |
||||
|
||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ |
||||
|
||||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */ |
||||
|
||||
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
|
||||
This parameter corresponds to a time unit range between [0-1] Second |
||||
with [1 Sec / SecondFraction +1] granularity */ |
||||
|
||||
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
|
||||
corresponding to Synchronous pre-scaler factor value (PREDIV_S) |
||||
This parameter corresponds to a time unit range between [0-1] Second |
||||
with [1 Sec / SecondFraction +1] granularity. |
||||
This field will be used only by HAL_RTC_GetTime function */ |
||||
|
||||
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
|
||||
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ |
||||
|
||||
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
|
||||
in CR register to store the operation. |
||||
This parameter can be a value of @ref RTC_StoreOperation_Definitions */ |
||||
}RTC_TimeTypeDef; |
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */ |
||||
|
||||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */ |
||||
|
||||
uint8_t Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ |
||||
|
||||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ |
||||
|
||||
}RTC_DateTypeDef; |
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ |
||||
|
||||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */ |
||||
|
||||
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
|
||||
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ |
||||
|
||||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ |
||||
|
||||
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. |
||||
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ |
||||
|
||||
uint32_t Alarm; /*!< Specifies the alarm .
|
||||
This parameter can be a value of @ref RTC_Alarms_Definitions */ |
||||
}RTC_AlarmTypeDef; |
||||
|
||||
/**
|
||||
* @brief RTC Handle Structure definition
|
||||
*/
|
||||
typedef struct |
||||
{ |
||||
RTC_TypeDef *Instance; /*!< Register base address */ |
||||
|
||||
RTC_InitTypeDef Init; /*!< RTC required parameters */ |
||||
|
||||
HAL_LockTypeDef Lock; /*!< RTC locking object */ |
||||
|
||||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */ |
||||
|
||||
}RTC_HandleTypeDef; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Hour_Formats RTC Hour Formats
|
||||
* @{ |
||||
*/ |
||||
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U) |
||||
#define RTC_HOURFORMAT_12 ((uint32_t)RTC_CR_FMT) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U) |
||||
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)RTC_CR_POL) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
|
||||
* @{ |
||||
*/ |
||||
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U) |
||||
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
|
||||
* @{ |
||||
*/ |
||||
#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000U) |
||||
#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U) |
||||
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)RTC_CR_SUB1H) |
||||
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)RTC_CR_ADD1H) |
||||
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U) |
||||
#define RTC_STOREOPERATION_SET ((uint32_t)RTC_CR_BCK) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_FORMAT_BIN ((uint32_t)0x000000000U) |
||||
#define RTC_FORMAT_BCD ((uint32_t)0x000000001U) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Coded in BCD format */ |
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01U) |
||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) |
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03U) |
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04U) |
||||
#define RTC_MONTH_MAY ((uint8_t)0x05U) |
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06U) |
||||
#define RTC_MONTH_JULY ((uint8_t)0x07U) |
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08U) |
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) |
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) |
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) |
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) |
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) |
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) |
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) |
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) |
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) |
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) |
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U) |
||||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 |
||||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 |
||||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 |
||||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 |
||||
#define RTC_ALARMMASK_ALL ((uint32_t) (RTC_ALARMMASK_NONE | \ |
||||
RTC_ALARMMASK_DATEWEEKDAY | \
|
||||
RTC_ALARMMASK_HOURS | \
|
||||
RTC_ALARMMASK_MINUTES | \
|
||||
RTC_ALARMMASK_SECONDS)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_ALARM_A RTC_CR_ALRAE |
||||
#define RTC_ALARM_B RTC_CR_ALRBE |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) /*!< All Alarm SS fields are masked. |
||||
There is no comparison on sub seconds |
||||
for Alarm */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are don't care in Alarm |
||||
comparison. Only SS[0] is compared. */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] are don't care in Alarm |
||||
comparison. Only SS[1:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)) /*!< SS[14:3] are don't care in Alarm |
||||
comparison. Only SS[2:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] are don't care in Alarm |
||||
comparison. Only SS[3:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)) /*!< SS[14:5] are don't care in Alarm |
||||
comparison. Only SS[4:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)) /*!< SS[14:6] are don't care in Alarm |
||||
comparison. Only SS[5:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)) /*!< SS[14:7] are don't care in Alarm |
||||
` comparison. Only SS[6:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] are don't care in Alarm |
||||
comparison. Only SS[7:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:9] are don't care in Alarm |
||||
comparison. Only SS[8:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:10] are don't care in Alarm |
||||
comparison. Only SS[9:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:11] are don't care in Alarm |
||||
comparison. Only SS[10:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t) (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:12] are don't care in Alarm |
||||
comparison.Only SS[11:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:13] are don't care in Alarm |
||||
comparison. Only SS[12:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14] is don't care in Alarm |
||||
comparison.Only SS[13:0] are compared */ |
||||
#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match |
||||
to activate alarm. */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) /*!< Enable Timestamp Interrupt */ |
||||
#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) /*!< Enable Wakeup timer Interrupt */ |
||||
#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) /*!< Enable Alarm A Interrupt */ |
||||
#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) /*!< Enable Alarm B Interrupt */ |
||||
#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */ |
||||
|
||||
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ |
||||
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
|
||||
defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
|
||||
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
|
||||
defined (STM32L031xx) || defined (STM32L041xx) |
||||
|
||||
#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */ |
||||
#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || |
||||
* (STM32L053xx) || (STM32L052xx) || (STM32L051xx) || |
||||
* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || |
||||
* (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || |
||||
* (STM32L031xx) || (STM32L041xx) |
||||
*/ |
||||
#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
||||
* @{ |
||||
*/ |
||||
#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF) |
||||
#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F) |
||||
|
||||
#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ |
||||
defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) ||\
|
||||
defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \
|
||||
defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) || \
|
||||
defined (STM32L031xx) || defined (STM32L041xx) |
||||
#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F) |
||||
#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || |
||||
* (STM32L053xx) || (STM32L052xx) || (STM32L051xx) || |
||||
* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || |
||||
* (STM32L073xx) || (STM32L072xx) || (STM32L071xx) || |
||||
* (STM32L031xx) || (STM32L041xx) |
||||
*/ |
||||
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF) |
||||
#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF) |
||||
#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF) |
||||
#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF) |
||||
#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF) |
||||
#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF) |
||||
#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF) |
||||
#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS) |
||||
#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF) |
||||
#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF) |
||||
#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF) |
||||
#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macros -----------------------------------------------------------*/ |
||||
/** @defgroup RTC_Exported_Macros RTC Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Reset RTC handle state
|
||||
* @param __HANDLE__: RTC handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) |
||||
|
||||
/**
|
||||
* @brief Disable the write protection for RTC registers. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ |
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xCAU; \
|
||||
(__HANDLE__)->Instance->WPR = 0x53U; \
|
||||
} while(0U) |
||||
|
||||
/**
|
||||
* @brief Enable the write protection for RTC registers. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ |
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xFFU; \
|
||||
} while(0U) |
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMA peripheral. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) |
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMA peripheral. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) |
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMB peripheral. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) |
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMB peripheral. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) |
||||
|
||||
/**
|
||||
* @brief Enable the RTC Alarm interrupt. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg RTC_IT_ALRA: Alarm A interrupt |
||||
* @arg RTC_IT_ALRB: Alarm B interrupt |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Disable the RTC Alarm interrupt. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg RTC_IT_ALRA: Alarm A interrupt |
||||
* @arg RTC_IT_ALRB: Alarm B interrupt |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. |
||||
* This parameter can be: |
||||
* @arg RTC_IT_ALRA: Alarm A interrupt |
||||
* @arg RTC_IT_ALRB: Alarm B interrupt |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) |
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. |
||||
* This parameter can be: |
||||
* @arg RTC_IT_ALRA: Alarm A interrupt |
||||
* @arg RTC_IT_ALRB: Alarm B interrupt |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) |
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarm's flag status. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @param __FLAG__: specifies the RTC Alarm Flag sources to check. |
||||
* This parameter can be: |
||||
* @arg RTC_FLAG_ALRAF |
||||
* @arg RTC_FLAG_ALRBF |
||||
* @arg RTC_FLAG_ALRAWF |
||||
* @arg RTC_FLAG_ALRBWF |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) |
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm's pending flags. |
||||
* @param __HANDLE__: specifies the RTC handle. |
||||
* @param __FLAG__: specifies the RTC Alarm Flag sources to clear. |
||||
* This parameter can be: |
||||
* @arg RTC_FLAG_ALRAF |
||||
* @arg RTC_FLAG_ALRBF |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) |
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Alarm associated Exti line. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) |
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Alarm associated Exti line. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) |
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Alarm associated Exti line. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) |
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Alarm associated Exti line. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) |
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) |
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) |
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) |
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) |
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ |
||||
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0U) |
||||
|
||||
/**
|
||||
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ |
||||
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0U) |
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. |
||||
* @retval Line Status. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) |
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm associated Exti line flag. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) |
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on RTC Alarm associated Exti line. |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Include RTC HAL Extended module */ |
||||
#include "stm32l0xx_hal_rtc_ex.h" |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @defgroup RTC_Exported_Functions RTC Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{ |
||||
*/ |
||||
/* Initialization and de-initialization functions ****************************/ |
||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); |
||||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); |
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); |
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
|
||||
* @{ |
||||
*/ |
||||
/* RTC Time and Date functions ************************************************/ |
||||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); |
||||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); |
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); |
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
|
||||
* @{ |
||||
*/ |
||||
/* RTC Alarm functions ********************************************************/ |
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); |
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); |
||||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); |
||||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); |
||||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); |
||||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); |
||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
|
||||
* @{ |
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/ |
||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
|
||||
* @{ |
||||
*/
|
||||
/* Peripheral State functions *************************************************/ |
||||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/** @defgroup RTC_Private_Constants RTC Private Constants
|
||||
* @{ |
||||
*/ |
||||
/* Masks Definition */ |
||||
#define RTC_TR_RESERVED_MASK ((uint32_t) (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \ |
||||
RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
|
||||
RTC_TR_SU)) |
||||
#define RTC_DR_RESERVED_MASK ((uint32_t) (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ |
||||
RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
|
||||
RTC_DR_DU)) |
||||
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU) |
||||
#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) |
||||
|
||||
#define RTC_TIMEOUT_VALUE 1000U |
||||
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup RTC_Private_Macros RTC Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ |
||||
((FORMAT) == RTC_HOURFORMAT_24)) |
||||
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ |
||||
((POL) == RTC_OUTPUT_POLARITY_LOW)) |
||||
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ |
||||
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) |
||||
|
||||
#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \ |
||||
((REMAP) == RTC_OUTPUT_REMAP_POS1)) |
||||
|
||||
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ |
||||
((PM) == RTC_HOURFORMAT12_PM)) |
||||
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ |
||||
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_NONE)) |
||||
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ |
||||
((OPERATION) == RTC_STOREOPERATION_SET)) |
||||
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) |
||||
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99U) |
||||
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U)) |
||||
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U)) |
||||
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ |
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) |
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t)0U) && ((DATE) <= (uint32_t)31U)) |
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ |
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) |
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ |
||||
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) |
||||
|
||||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == (uint32_t)RESET) |
||||
|
||||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) |
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) |
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ |
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) |
||||
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FU) |
||||
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFFU) |
||||
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U)) |
||||
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23U) |
||||
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59U) |
||||
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59U) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private functions -------------------------------------------------------------*/ |
||||
/** @defgroup RTC_Private_Functions RTC Private Functions
|
||||
* @{ |
||||
*/ |
||||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); |
||||
uint8_t RTC_ByteToBcd2(uint8_t Value); |
||||
uint8_t RTC_Bcd2ToByte(uint8_t Value); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_RTC_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,676 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_spi.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of SPI HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_SPI_H |
||||
#define __STM32L0xx_HAL_SPI_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup SPI SPI
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/** @defgroup SPI_Exported_Types SPI Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief SPI Configuration Structure definition
|
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_mode */ |
||||
|
||||
uint32_t Direction; /*!< Specifies the SPI Directional mode state.
|
||||
This parameter can be a value of @ref SPI_Direction_mode */ |
||||
|
||||
uint32_t DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */ |
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */ |
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */ |
||||
|
||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit. |
||||
This parameter can be a value of @ref SPI_Slave_Select_management */ |
||||
|
||||
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock. |
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler |
||||
@note The communication clock is derived from the master |
||||
clock. The slave clock does not need to be set */ |
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
||||
|
||||
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
|
||||
This parameter can be a value of @ref SPI_TI_mode */ |
||||
|
||||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
||||
This parameter can be a value of @ref SPI_CRC_Calculation */ |
||||
|
||||
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ |
||||
|
||||
}SPI_InitTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL SPI State structure definition |
||||
*/ |
||||
typedef enum |
||||
{ |
||||
HAL_SPI_STATE_RESET = 0x00U, /*!< SPI not yet initialized or disabled */ |
||||
HAL_SPI_STATE_READY = 0x01U, /*!< SPI initialized and ready for use */ |
||||
HAL_SPI_STATE_BUSY = 0x02U, /*!< SPI process is ongoing */ |
||||
HAL_SPI_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ |
||||
HAL_SPI_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
||||
HAL_SPI_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ |
||||
HAL_SPI_STATE_ERROR = 0x03U /*!< SPI error state */ |
||||
|
||||
}HAL_SPI_StateTypeDef; |
||||
|
||||
/**
|
||||
* @brief SPI handle Structure definition |
||||
*/ |
||||
typedef struct __SPI_HandleTypeDef |
||||
{ |
||||
SPI_TypeDef *Instance; /*!< SPI registers base address */ |
||||
|
||||
SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
||||
|
||||
uint16_t TxXferSize; /*!< SPI Tx transfer size */ |
||||
|
||||
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
||||
|
||||
uint16_t RxXferSize; /*!< SPI Rx transfer size */ |
||||
|
||||
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */ |
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */ |
||||
|
||||
void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */ |
||||
|
||||
void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */ |
||||
|
||||
HAL_LockTypeDef Lock; /*!< SPI locking object */ |
||||
|
||||
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
||||
|
||||
__IO uint32_t ErrorCode; /*!< SPI Error code */ |
||||
|
||||
}SPI_HandleTypeDef; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup SPI_Exported_Constants SPI Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @defgroup SPI_ErrorCode SPI Error Code |
||||
* @{ |
||||
*/ |
||||
#define HAL_SPI_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ |
||||
#define HAL_SPI_ERROR_MODF ((uint32_t)0x01U) /*!< MODF error */ |
||||
#define HAL_SPI_ERROR_CRC ((uint32_t)0x02U) /*!< CRC error */ |
||||
#define HAL_SPI_ERROR_OVR ((uint32_t)0x04U) /*!< OVR error */ |
||||
#define HAL_SPI_ERROR_FRE ((uint32_t)0x08U) /*!< FRE error */ |
||||
#define HAL_SPI_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */ |
||||
#define HAL_SPI_ERROR_FLAG ((uint32_t)0x20U) /*!< Flag: RXNE,TXE, BSY */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_mode SPI mode
|
||||
* @{ |
||||
*/ |
||||
#define SPI_MODE_SLAVE ((uint32_t)0x00000000U) |
||||
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Direction_mode SPI Direction mode
|
||||
* @{ |
||||
*/ |
||||
#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U) |
||||
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
||||
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_data_size SPI data size
|
||||
* @{ |
||||
*/ |
||||
#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000U) |
||||
#define SPI_DATASIZE_16BIT SPI_CR1_DFF |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
|
||||
* @{ |
||||
*/ |
||||
#define SPI_POLARITY_LOW ((uint32_t)0x00000000U) |
||||
#define SPI_POLARITY_HIGH SPI_CR1_CPOL |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Clock_Phase SPI Clock Phase
|
||||
* @{ |
||||
*/ |
||||
#define SPI_PHASE_1EDGE ((uint32_t)0x00000000U) |
||||
#define SPI_PHASE_2EDGE SPI_CR1_CPHA |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Slave_Select_management SPI Slave Select management
|
||||
* @{ |
||||
*/ |
||||
#define SPI_NSS_SOFT SPI_CR1_SSM |
||||
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) |
||||
#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16U)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
|
||||
* @{ |
||||
*/ |
||||
#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U) |
||||
#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) |
||||
#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) |
||||
#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) |
||||
#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) |
||||
#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) |
||||
#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) |
||||
#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
|
||||
* @{ |
||||
*/ |
||||
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U) |
||||
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_TI_mode SPI TI mode
|
||||
* @{ |
||||
*/ |
||||
#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U) |
||||
#define SPI_TIMODE_ENABLE SPI_CR2_FRF |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
|
||||
* @{ |
||||
*/ |
||||
#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) |
||||
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
|
||||
* @{ |
||||
*/ |
||||
#define SPI_IT_TXE SPI_CR2_TXEIE |
||||
#define SPI_IT_RXNE SPI_CR2_RXNEIE |
||||
#define SPI_IT_ERR SPI_CR2_ERRIE |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SPI_Flag_definition SPI Flag definition
|
||||
* @{ |
||||
*/ |
||||
#define SPI_FLAG_RXNE SPI_SR_RXNE |
||||
#define SPI_FLAG_TXE SPI_SR_TXE |
||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR |
||||
#define SPI_FLAG_MODF SPI_SR_MODF |
||||
#define SPI_FLAG_OVR SPI_SR_OVR |
||||
#define SPI_FLAG_BSY SPI_SR_BSY |
||||
#define SPI_FLAG_FRE SPI_SR_FRE |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/** @defgroup SPI_Exported_Macros SPI Exported Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Reset SPI handle state
|
||||
* @param __HANDLE__: specifies the SPI handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
||||
|
||||
/** @brief Enable the specified SPI interrupts.
|
||||
* @param __HANDLE__: specifies the SPI handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @param __INTERRUPT__: specifies the interrupt source to enable. |
||||
* This parameter can be one of the following values: |
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||||
* @arg SPI_IT_ERR: Error interrupt enable |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
||||
|
||||
/** @brief Disable the specified SPI interrupts.
|
||||
* @param __HANDLE__: specifies the SPI handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @param __INTERRUPT__: specifies the interrupt source to disable. |
||||
* This parameter can be one of the following values: |
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||||
* @arg SPI_IT_ERR: Error interrupt enable |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
||||
|
||||
/** @brief Check if the specified SPI interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the SPI handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @param __INTERRUPT__: specifies the SPI interrupt source to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||||
* @arg SPI_IT_ERR: Error interrupt enable |
||||
* @retval The new state of __IT__ (TRUE or FALSE). |
||||
*/ |
||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __HANDLE__: specifies the SPI handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @param __FLAG__: specifies the flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag |
||||
* @arg SPI_FLAG_CRCERR: CRC error flag |
||||
* @arg SPI_FLAG_MODF: Mode fault flag |
||||
* @arg SPI_FLAG_OVR: Overrun flag |
||||
* @arg SPI_FLAG_BSY: Busy flag |
||||
* @arg SPI_FLAG_FRE: Frame format error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
||||
*/ |
||||
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
||||
|
||||
/** @brief Clear the SPI CRCERR pending flag.
|
||||
* @param __HANDLE__: specifies the SPI handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) |
||||
|
||||
/** @brief Clear the SPI MODF pending flag.
|
||||
* @param __HANDLE__: specifies the SPI handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
|
||||
* @retval None |
||||
*/
|
||||
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
||||
do{ \
|
||||
__IO uint32_t tmpreg_modf; \
|
||||
tmpreg_modf = (__HANDLE__)->Instance->SR; \
|
||||
(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
|
||||
UNUSED(tmpreg_modf); \
|
||||
} while(0) |
||||
|
||||
/** @brief Clear the SPI OVR pending flag.
|
||||
* @param __HANDLE__: specifies the SPI handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
|
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
||||
do{ \
|
||||
__IO uint32_t tmpreg_ovr; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
} while(0) |
||||
|
||||
/** @brief Clear the SPI FRE pending flag.
|
||||
* @param __HANDLE__: specifies the SPI handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
||||
do{ \
|
||||
__IO uint32_t tmpreg_fre; \
|
||||
tmpreg_fre = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_fre); \
|
||||
} while(0) |
||||
|
||||
/** @brief Enables the SPI.
|
||||
* @param __HANDLE__: specifies the SPI Handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @retval None |
||||
*/
|
||||
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
||||
|
||||
/** @brief Disables the SPI.
|
||||
* @param __HANDLE__: specifies the SPI Handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @retval None |
||||
*/
|
||||
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Private macros -----------------------------------------------------------*/ |
||||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
||||
* @param __MODE__: specifies the SPI Mode. |
||||
* This parameter can be a value of @ref SPI_mode |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER)) |
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
||||
* @param __MODE__: specifies the SPI Direction Mode. |
||||
* This parameter can be a value of @ref SPI_Direction_mode |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
||||
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
|
||||
((__MODE__) == SPI_DIRECTION_1LINE)) |
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
|
||||
* @param __MODE__: specifies the SPI Direction Mode. |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
||||
((__MODE__) == SPI_DIRECTION_1LINE)) |
||||
|
||||
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
|
||||
* @param __MODE__: specifies the SPI Direction Mode. |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) |
||||
|
||||
/** @brief Checks if SPI Data Size parameter is in allowed range.
|
||||
* @param __DATASIZE__: specifies the SPI Data Size. |
||||
* This parameter can be a value of @ref SPI_data_size |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ |
||||
((__DATASIZE__) == SPI_DATASIZE_8BIT)) |
||||
|
||||
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
|
||||
* @param __CPOL__: specifies the SPI serial clock steady state. |
||||
* This parameter can be a value of @ref SPI_Clock_Polarity |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ |
||||
((__CPOL__) == SPI_POLARITY_HIGH)) |
||||
|
||||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
||||
* @param __CPHA__: specifies the SPI Clock Phase. |
||||
* This parameter can be a value of @ref SPI_Clock_Phase |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ |
||||
((__CPHA__) == SPI_PHASE_2EDGE)) |
||||
|
||||
/** @brief Checks if SPI Slave select parameter is in allowed range.
|
||||
* @param __NSS__: specifies the SPI Slave Slelect management parameter. |
||||
* This parameter can be a value of @ref SPI_Slave_Select_management |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ |
||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
||||
((__NSS__) == SPI_NSS_HARD_OUTPUT)) |
||||
|
||||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
||||
* @param __PRESCALER__: specifies the SPI Baudrate prescaler. |
||||
* This parameter can be a value of @ref SPI_BaudRate_Prescaler |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ |
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
|
||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) |
||||
|
||||
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
|
||||
* @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). |
||||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ |
||||
((__BIT__) == SPI_FIRSTBIT_LSB)) |
||||
|
||||
/** @brief Checks if SPI TI mode parameter is in allowed range.
|
||||
* @param __MODE__: specifies the SPI TI mode. |
||||
* This parameter can be a value of @ref SPI_TI_mode |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ |
||||
((__MODE__) == SPI_TIMODE_ENABLE)) |
||||
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
|
||||
* @param __CALCULATION__: specifies the SPI CRC calculation enable state. |
||||
* This parameter can be a value of @ref SPI_CRC_Calculation |
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ |
||||
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) |
||||
|
||||
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
|
||||
* @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation. |
||||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
|
||||
* @retval None |
||||
*/ |
||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU)) |
||||
/** @brief Sets the SPI transmit-only mode.
|
||||
* @param __HANDLE__: specifies the SPI Handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
||||
|
||||
/** @brief Sets the SPI receive-only mode.
|
||||
* @param __HANDLE__: specifies the SPI Handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @retval None |
||||
*/
|
||||
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
||||
|
||||
/** @brief Resets the CRC calculation of the SPI.
|
||||
* @param __HANDLE__: specifies the SPI Handle. |
||||
* This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. |
||||
* @retval None |
||||
*/ |
||||
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @defgroup SPI_Exported_Functions SPI Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Initialization/de-initialization functions **********************************/ |
||||
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{ |
||||
*/ |
||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
||||
HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* I/O operation functions *****************************************************/ |
||||
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
|
||||
* @{ |
||||
*/ |
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); |
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
||||
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
||||
|
||||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
||||
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Peripheral State and Control functions **************************************/ |
||||
/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @{ |
||||
*/ |
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
||||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private group definition ------------------------------------------------------*/ |
||||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Define the private group ***********************************/ |
||||
/**************************************************************/ |
||||
/** @defgroup SPI_Private SPI Private
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**************************************************************/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_SPI_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,285 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_tim_ex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of TIM HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_TIM_EX_H |
||||
#define __STM32L0xx_HAL_TIM_EX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup TIMEx TIMEx
|
||||
* @{ |
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/** @defgroup TIM_Exported_Types TIM Exported Types
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @brief TIM Master configuration Structure definition
|
||||
*/
|
||||
typedef struct { |
||||
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
|
||||
This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
||||
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
|
||||
This parameter can be a value of @ref TIM_Master_Slave_Mode */ |
||||
}TIM_MasterConfigTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup TIMEx_Trigger_Selection Trigger selection
|
||||
* @{ |
||||
*/
|
||||
#define TIM_TRGO_RESET ((uint32_t)0x0000U) |
||||
#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
||||
#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
||||
#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
||||
#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
||||
#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
||||
#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
||||
#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
||||
|
||||
#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ |
||||
((__SOURCE__) == TIM_TRGO_ENABLE) || \
|
||||
((__SOURCE__) == TIM_TRGO_UPDATE) || \
|
||||
((__SOURCE__) == TIM_TRGO_OC1) || \
|
||||
((__SOURCE__) == TIM_TRGO_OC1REF) || \
|
||||
((__SOURCE__) == TIM_TRGO_OC2REF) || \
|
||||
((__SOURCE__) == TIM_TRGO_OC3REF) || \
|
||||
((__SOURCE__) == TIM_TRGO_OC4REF)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Remap Remaping
|
||||
* @{ |
||||
*/ |
||||
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ |
||||
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
|
||||
#define TIM2_ETR_GPIO ((uint32_t)0x0U) |
||||
#define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2 |
||||
#define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0) |
||||
#define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) |
||||
#define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) |
||||
#define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP |
||||
|
||||
#elif defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx) |
||||
|
||||
#define TIM2_ETR_GPIO ((uint32_t)0x0U) |
||||
#define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0) |
||||
#define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) |
||||
#define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) |
||||
#define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP |
||||
|
||||
#else |
||||
|
||||
#define TIM2_ETR_GPIO ((uint32_t)0x0U) |
||||
#define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2 |
||||
#define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) |
||||
#define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) |
||||
#define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP |
||||
|
||||
#endif |
||||
|
||||
|
||||
|
||||
#define TIM2_TI4_GPIO ((uint32_t)0x0U) |
||||
#define TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0 |
||||
#define TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1 |
||||
|
||||
#define TIM21_ETR_GPIO ((uint32_t)0x0U) |
||||
#define TIM21_ETR_COMP2_OUT TIM21_OR_ETR_RMP_0 |
||||
#define TIM21_ETR_COMP1_OUT TIM21_OR_ETR_RMP_1 |
||||
#define TIM21_ETR_LSE TIM21_OR_ETR_RMP |
||||
#define TIM21_TI1_GPIO ((uint32_t)0x0U) |
||||
#define TIM21_TI1_MCO TIM21_OR_TI1_RMP |
||||
#define TIM21_TI1_RTC_WKUT_IT TIM21_OR_TI1_RMP_0 |
||||
#define TIM21_TI1_HSE_RTC TIM21_OR_TI1_RMP_1 |
||||
#define TIM21_TI1_MSI (TIM21_OR_TI1_RMP_0 | TIM21_OR_TI1_RMP_1) |
||||
#define TIM21_TI1_LSE TIM21_OR_TI1_RMP_2 |
||||
#define TIM21_TI1_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0) |
||||
#define TIM21_TI1_COMP1_OUT (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1) |
||||
#define TIM21_TI2_GPIO ((uint32_t)0x0U) |
||||
#define TIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMP |
||||
|
||||
#if !defined(STM32L011xx) && !defined(STM32L021xx) |
||||
#define TIM22_ETR_GPIO ((uint32_t)0x0U) |
||||
#define TIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0 |
||||
#define TIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1 |
||||
#define TIM22_ETR_LSE TIM22_OR_ETR_RMP |
||||
#define TIM22_TI1_GPIO1 ((uint32_t)0x0U) |
||||
#define TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0 |
||||
#define TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1 |
||||
#define TIM22_TI1_GPIO2 TIM22_OR_TI1_RMP |
||||
#endif |
||||
|
||||
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ |
||||
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
|
||||
#define TIM3_TI4_GPIO_DEF ((uint32_t)0x0U) |
||||
#define TIM3_TI4_GPIOC9_AF2 TIM3_OR_TI4_RMP |
||||
#define TIM3_TI2_GPIO_DEF ((uint32_t)0x0U) |
||||
#define TIM3_TI2_GPIOB5_AF4 TIM3_OR_TI2_RMP |
||||
#define TIM3_TI1_USB_SOF ((uint32_t)0x0U) |
||||
#define TIM3_TI1_GPIO TIM3_OR_TI1_RMP |
||||
#define TIM3_ETR_GPIO ((uint32_t)0x0U) |
||||
#define TIM3_ETR_HSI TIM3_OR_ETR_RMP_1 |
||||
|
||||
#endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */ |
||||
|
||||
|
||||
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ |
||||
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
|
||||
|
||||
#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ |
||||
((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \
|
||||
(((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \
|
||||
(((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))) || \
|
||||
(((__INSTANCE__) == TIM3) && ((__TIM_REMAP__) <= (TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP)))) |
||||
|
||||
#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ |
||||
((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_4))) || \
|
||||
(((__INSTANCE__) == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_4))) || \
|
||||
(((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2))) || \
|
||||
(((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2)))) |
||||
|
||||
#elif defined (STM32L011xx) || defined (STM32L021xx) |
||||
|
||||
#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ |
||||
((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \
|
||||
(((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP)))) |
||||
|
||||
#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ |
||||
((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_4))) || \
|
||||
(((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2)))) |
||||
|
||||
#else |
||||
|
||||
#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ |
||||
((((__INSTANCE__) == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \
|
||||
(((__INSTANCE__) == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \
|
||||
(((__INSTANCE__) == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP)))) |
||||
|
||||
#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ |
||||
((((__INSTANCE__) == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_4))) || \
|
||||
(((__INSTANCE__) == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2))) || \
|
||||
(((__INSTANCE__) == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2)))) |
||||
|
||||
#endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/* Control functions ***********************************************************/ |
||||
|
||||
/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup TIMEx_Exported_Functions_Group1 TIMEx Peripheral Control functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); |
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_TIM_EX_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,437 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_uart_ex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of UART HAL Extended module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_UART_EX_H |
||||
#define __STM32L0xx_HAL_UART_EX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup UARTEx
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief UART wake up from stop mode parameters |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
|
||||
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. |
||||
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must |
||||
be filled up. */ |
||||
|
||||
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
|
||||
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ |
||||
|
||||
uint8_t Address; /*!< UART/USART node address (7-bit long max). */ |
||||
} UART_WakeUpTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup UARTEx_Word_Length UART Word Length
|
||||
* @{ |
||||
*/ |
||||
#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */ |
||||
#define UART_WORDLENGTH_8B ((uint32_t)0x00000000U) /*!< 8-bit long UART frame */ |
||||
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UARTEx_WakeUp_Address_Length UART Extended WakeUp Address Length
|
||||
* @{ |
||||
*/ |
||||
#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U) /*!< 4-bit long wake-up address */ |
||||
#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported macros -----------------------------------------------------------*/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup UARTEx_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Initialization and de-initialization functions ****************************/ |
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* IO operation functions *****************************************************/ |
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group3
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Peripheral Control functions **********************************************/ |
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); |
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); |
||||
HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); |
||||
HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); |
||||
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @brief Report the UART clock source.
|
||||
* @param __HANDLE__: specifies the UART Handle. |
||||
* @param __CLOCKSOURCE__: output variable. |
||||
* @retval UART clocking source, written in __CLOCKSOURCE__. |
||||
*/ |
||||
#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == LPUART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_LPUART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0) |
||||
|
||||
#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) |
||||
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == LPUART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_LPUART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0) |
||||
|
||||
#else |
||||
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ |
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == LPUART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_LPUART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_LPUART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0) |
||||
#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || defined (STM32L021xx) */ |
||||
|
||||
/** @brief Report the UART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation. |
||||
* @note If PCE = 1, the parity bit is not included in the data extracted |
||||
* by the reception API(). |
||||
* This masking operation is not carried out in the case of |
||||
* DMA transfers. |
||||
* @param __HANDLE__: specifies the UART Handle. |
||||
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. |
||||
*/ |
||||
#define UART_MASK_COMPUTATION(__HANDLE__) \ |
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003F ; \
|
||||
} \
|
||||
} \
|
||||
} while(0) |
||||
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART frame length is valid. |
||||
* @param __LENGTH__: UART frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) |
||||
*/ |
||||
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ |
||||
((__LENGTH__) == UART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_9B)) |
||||
|
||||
/**
|
||||
* @brief Ensure that UART wake-up address length is valid. |
||||
* @param __ADDRESS__: UART wake-up address length.
|
||||
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) |
||||
*/ |
||||
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ |
||||
((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private functions ---------------------------------------------------------*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_UART_EX_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,560 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal.c |
||||
* @author MCD Application Team |
||||
* @brief HAL module driver. |
||||
* This is the common part of the HAL initialization |
||||
* |
||||
@verbatim |
||||
============================================================================== |
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..] |
||||
The common HAL driver contains a set of generic and common APIs that can be |
||||
used by the PPP peripheral drivers and the user to start using the HAL.
|
||||
[..] |
||||
The HAL contains two APIs categories:
|
||||
(+) Common HAL APIs |
||||
(+) Services HAL APIs |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_MODULE_ENABLED |
||||
|
||||
/** @addtogroup HAL
|
||||
* @brief HAL module driver. |
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup HAL_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup SysTick System Tick
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @brief uwTick_variable uwTick variable |
||||
*/ |
||||
__IO uint32_t uwTick; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup HAL_Version HAL Version
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief STM32L0xx HAL Driver version number |
||||
*/ |
||||
#define __STM32L0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ |
||||
#define __STM32L0xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ |
||||
#define __STM32L0xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ |
||||
#define __STM32L0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ |
||||
#define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24U)\ |
||||
|(__STM32L0xx_HAL_VERSION_SUB1 << 16U)\
|
||||
|(__STM32L0xx_HAL_VERSION_SUB2 << 8U )\
|
||||
|(__STM32L0xx_HAL_VERSION_RC)) |
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFFU) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/** @defgroup HAL_Private HAL Private
|
||||
* @{ |
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @brief Initialization and de-initialization functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Initialization and de-initialization functions ##### |
||||
=============================================================================== |
||||
[..] This section provides functions allowing to: |
||||
(+) Initializes the Flash interface, the NVIC allocation and initial clock
|
||||
configuration. It initializes the source of time base also when timeout
|
||||
is needed and the backup domain when enabled. |
||||
(+) de-Initializes common part of the HAL. |
||||
(+) Configure The time base source to have 1ms time base with a dedicated
|
||||
Tick interrupt priority.
|
||||
(++) Systick timer is used by default as source of time base, but user
|
||||
can eventually implement his proper time base source (a general purpose
|
||||
timer for example or other time source), keeping in mind that Time base
|
||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
|
||||
handled in milliseconds basis. |
||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically
|
||||
at the beginning of the program after reset by HAL_Init() or at any time
|
||||
when clock is configured, by HAL_RCC_ClockConfig().
|
||||
(++) Source of time base is configured to generate interrupts at regular
|
||||
time intervals. Care must be taken if HAL_Delay() is called from a
|
||||
peripheral ISR process, the Tick interrupt line must have higher priority
|
||||
(numerically lower) than the peripheral interrupt. Otherwise the caller
|
||||
ISR process will be blocked.
|
||||
(++) functions affecting time base configurations are declared as __weak
|
||||
to make override possible in case of other implementations in user file. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief This function configures the Flash prefetch, Flash preread and Buffer cache, |
||||
* Configures time base source, NVIC and Low level hardware |
||||
* @note This function is called at the beginning of program after reset and before
|
||||
* the clock configuration |
||||
* @note The time base configuration is based on MSI clock when exiting from Reset. |
||||
* Once done, time base tick start incrementing. |
||||
* In the default implementation,Systick is used as source of time base. |
||||
* the tick variable is incremented each 1ms in its ISR. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_Init(void) |
||||
{ |
||||
/* Configure Buffer cache, Flash prefetch, Flash preread */
|
||||
#if (BUFFER_CACHE_DISABLE != 0) |
||||
__HAL_FLASH_BUFFER_CACHE_DISABLE(); |
||||
#endif /* BUFFER_CACHE_DISABLE */ |
||||
|
||||
#if (PREREAD_ENABLE != 0) |
||||
__HAL_FLASH_PREREAD_BUFFER_ENABLE(); |
||||
#endif /* PREREAD_ENABLE */ |
||||
|
||||
#if (PREFETCH_ENABLE != 0) |
||||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE(); |
||||
#endif /* PREFETCH_ENABLE */ |
||||
|
||||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ |
||||
|
||||
HAL_InitTick(TICK_INT_PRIORITY); |
||||
|
||||
/* Init the low level hardware */ |
||||
HAL_MspInit(); |
||||
|
||||
/* Return function status */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function de-Initializes common part of the HAL and stops the source |
||||
* of time base. |
||||
* @note This function is optional. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DeInit(void) |
||||
{ |
||||
/* Reset of all peripherals */ |
||||
__HAL_RCC_APB1_FORCE_RESET(); |
||||
__HAL_RCC_APB1_RELEASE_RESET(); |
||||
|
||||
__HAL_RCC_APB2_FORCE_RESET(); |
||||
__HAL_RCC_APB2_RELEASE_RESET(); |
||||
|
||||
__HAL_RCC_AHB_FORCE_RESET(); |
||||
__HAL_RCC_AHB_RELEASE_RESET(); |
||||
|
||||
__HAL_RCC_IOP_FORCE_RESET(); |
||||
__HAL_RCC_IOP_RELEASE_RESET(); |
||||
|
||||
/* De-Init the low level hardware */ |
||||
HAL_MspDeInit(); |
||||
|
||||
/* Return function status */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Initializes the MSP. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_MspInit(void) |
||||
{ |
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_MspInit could be implemented in the user file |
||||
*/ |
||||
} |
||||
|
||||
/**
|
||||
* @brief DeInitializes the MSP. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_MspDeInit(void) |
||||
{ |
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_MspDeInit could be implemented in the user file |
||||
*/ |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief This function configures the source of the time base.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority. |
||||
* @note This function is called automatically at the beginning of program after |
||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
|
||||
* @note In the default implementation, SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals.
|
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
|
||||
* The the SysTick interrupt must have higher priority (numerically lower)
|
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked. |
||||
* The function is declared as __Weak to be overwritten in case of other |
||||
* implementation in user file. |
||||
* @param TickPriority: Tick interrupt priority. |
||||
* @retval HAL status |
||||
*/ |
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) |
||||
{ |
||||
/*Configure the SysTick to have interrupt in 1ms time basis*/ |
||||
HAL_SYSTICK_Config(SystemCoreClock/1000U); |
||||
|
||||
/*Configure the SysTick IRQ priority */ |
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); |
||||
|
||||
/* Return function status */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @brief Peripheral Control functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### HAL Control functions ##### |
||||
=============================================================================== |
||||
[..] This section provides functions allowing to: |
||||
(+) Provide a tick value in millisecond |
||||
(+) Provide a blocking delay in millisecond |
||||
(+) Suspend the time base source interrupt |
||||
(+) Resume the time base source interrupt |
||||
(+) Get the HAL API driver version |
||||
(+) Get the device identifier |
||||
(+) Get the device revision identifier |
||||
(+) Configure low power mode behavior when the MCU is in Debug mode |
||||
(+) Manage the VEREFINT feature (activation, lock, output selection) |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief This function is called to increment a global variable "uwTick" |
||||
* used as application time base. |
||||
* @note In the default implementation, this variable is incremented each 1ms |
||||
* in Systick ISR. |
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_IncTick(void) |
||||
{ |
||||
uwTick++; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Provides a tick value in millisecond. |
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file. |
||||
* @retval tick value |
||||
*/ |
||||
__weak uint32_t HAL_GetTick(void) |
||||
{ |
||||
return uwTick; |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in ms) based on a variable incremented. |
||||
* @note In the default implementation , SysTick timer is the source of time base. |
||||
* It is used to generate interrupts at regular time intervals where uwTick |
||||
* is incremented. |
||||
* @note ThiS function is declared as __weak to be overwritten in case of other |
||||
* implementations in user file. |
||||
* @param Delay: specifies the delay time length, in milliseconds. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_Delay(__IO uint32_t Delay) |
||||
{ |
||||
uint32_t tickstart = 0U; |
||||
tickstart = HAL_GetTick(); |
||||
while((HAL_GetTick() - tickstart) < Delay) |
||||
{ |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Suspends the Tick increment. |
||||
* @note In the default implementation , SysTick timer is the source of time base. It is |
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick() |
||||
* is called, the the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended. |
||||
* @note This function is declared as __weak to be overwritten in case of other |
||||
* implementations in user file. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_SuspendTick(void) |
||||
{ |
||||
/* Disable SysTick Interrupt */ |
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Resumes the Tick increment. |
||||
* @note In the default implementation , SysTick timer is the source of time base. It is |
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick() |
||||
* is called, the the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed. |
||||
* @note This function is declared as __weak to be overwritten in case of other |
||||
* implementations in user file. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_ResumeTick(void) |
||||
{ |
||||
/* Enable SysTick Interrupt */ |
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns the HAL revision |
||||
* @retval version: 0xXYZR (8bits for each decimal, R for RC) |
||||
*/ |
||||
uint32_t HAL_GetHalVersion(void) |
||||
{ |
||||
return __STM32L0xx_HAL_VERSION; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier. |
||||
* @retval Device revision identifier |
||||
*/ |
||||
uint32_t HAL_GetREVID(void) |
||||
{ |
||||
return((DBGMCU->IDCODE) >> 16U); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns the device identifier. |
||||
* @retval Device identifier |
||||
*/ |
||||
uint32_t HAL_GetDEVID(void) |
||||
{ |
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables the Debug Module during SLEEP mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_EnableDBGSleepMode(void) |
||||
{ |
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables the Debug Module during SLEEP mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_DisableDBGSleepMode(void) |
||||
{ |
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables the Debug Module during STOP mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_EnableDBGStopMode(void) |
||||
{ |
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables the Debug Module during STOP mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_DisableDBGStopMode(void) |
||||
{ |
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables the Debug Module during STANDBY mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void) |
||||
{ |
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables the Debug Module during STANDBY mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void) |
||||
{ |
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable low power mode behavior when the MCU is in Debug mode. |
||||
* @param Periph: specifies the low power mode. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode |
||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode |
||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_DBGMCU_PERIPH(Periph)); |
||||
|
||||
DBGMCU->CR |= Periph; |
||||
|
||||
} |
||||
/**
|
||||
* @brief Disable low power mode behavior when the MCU is in Debug mode. |
||||
* @param Periph: specifies the low power mode. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode |
||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode |
||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_DBGMCU_PERIPH(Periph)); |
||||
{ |
||||
DBGMCU->CR &= ~Periph; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Returns the boot mode as configured by user. |
||||
* @retval The boot mode as configured by user. The returned value can be one
|
||||
* of the following values: |
||||
* - 0x00000000 : Boot is configured in Main Flash memory
|
||||
* - 0x00000100 : Boot is configured in System Flash memory
|
||||
* - 0x00000300 : Boot is configured in Embedded SRAM memory
|
||||
*/ |
||||
uint32_t HAL_SYSCFG_GetBootMode(void) |
||||
{ |
||||
return (SYSCFG->CFGR1 & SYSCFG_CFGR1_BOOT_MODE); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Selects the output of internal reference voltage (VREFINT). |
||||
* The VREFINT output can be routed to(PB0) or |
||||
* (PB1) or both. |
||||
* @param SYSCFG_Vrefint_OUTPUT: new state of the Vrefint output. |
||||
* This parameter can be one of the following values: |
||||
* @arg SYSCFG_VREFINT_OUT_NONE |
||||
* @arg SYSCFG_VREFINT_OUT_PB0 |
||||
* @arg SYSCFG_VREFINT_OUT_PB1 |
||||
* @arg SYSCFG_VREFINT_OUT_PB0_PB1 |
||||
* @retval None |
||||
*/ |
||||
void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_SYSCFG_VREFINT_OUT_SELECT(SYSCFG_Vrefint_OUTPUT)); |
||||
|
||||
/* Set the output Vrefint pin */ |
||||
SYSCFG->CFGR3 &= ~(SYSCFG_CFGR3_VREF_OUT); |
||||
SYSCFG->CFGR3 |= (uint32_t)(SYSCFG_Vrefint_OUTPUT); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Lock the SYSCFG VREF register values |
||||
* @retval None |
||||
*/ |
||||
void HAL_SYSCFG_Enable_Lock_VREFINT(void) |
||||
{ |
||||
/* Enable the LOCK by setting REF_LOCK bit in the CFGR3 register */ |
||||
SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Unlock the overall SYSCFG VREF register values |
||||
* @retval None |
||||
*/ |
||||
void HAL_SYSCFG_Disable_Lock_VREFINT(void) |
||||
{ |
||||
/* Disable the LOCK by setting REF_LOCK bit in the CFGR3 register */ |
||||
CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK); |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* HAL_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,396 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_cortex.c |
||||
* @author MCD Application Team |
||||
* @brief CORTEX HAL module driver. |
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX: |
||||
* + Initialization and de-initialization functions |
||||
* + Peripheral Control functions
|
||||
* |
||||
@verbatim
|
||||
============================================================================== |
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using CORTEX HAL driver *** |
||||
=========================================================== |
||||
[..]
|
||||
This section provide functions allowing to configure the NVIC interrupts (IRQ). |
||||
The Cortex-M0+ exceptions are managed by CMSIS functions. |
||||
(#) Enable and Configure the priority of the selected IRQ Channels.
|
||||
The priority can be 0..3.
|
||||
|
||||
-@- Lower priority values gives higher priority. |
||||
-@- Priority Order: |
||||
(#@) Lowest priority. |
||||
(#@) Lowest hardware priority (IRQn position).
|
||||
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using CORTEX HAL driver *** |
||||
======================================================== |
||||
[..] |
||||
Setup SysTick Timer for time base
|
||||
|
||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which |
||||
is a CMSIS function that: |
||||
(++) Configures the SysTick Reload register with value passed as function parameter. |
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x03). |
||||
(++) Resets the SysTick Counter register. |
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). |
||||
(++) Enables the SysTick Interrupt. |
||||
(++) Starts the SysTick Counter. |
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function |
||||
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the |
||||
HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() function is defined |
||||
inside the stm32l0xx_hal_cortex.c file. |
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the |
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. |
||||
|
||||
(+) To adjust the SysTick time base, use the following formula: |
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) |
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function |
||||
(++) Reload Value should not exceed 0xFFFFFF |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
******************************************************************************
|
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED |
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @brief CORTEX HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
/* Private types -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/* Private functions ---------------------------------------------------------*/ |
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* |
||||
@verbatim
|
||||
============================================================================== |
||||
##### Initialization and de-initialization functions ##### |
||||
============================================================================== |
||||
[..] |
||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts |
||||
Systick functionalities
|
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt. |
||||
* @param IRQn: External interrupt number . |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file) |
||||
* @param PreemptPriority: The pre-emption priority for the IRQn channel. |
||||
* This parameter can be a value between 0 and 3. |
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority: The subpriority level for the IRQ channel. |
||||
* with stm32l0xx devices, this parameter is a dummy value and it is ignored, because
|
||||
* no subpriority supported in Cortex M0+ based products.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) |
||||
{
|
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); |
||||
NVIC_SetPriority(IRQn,PreemptPriority); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller. |
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() |
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number . |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||||
|
||||
/* Enable interrupt */ |
||||
NVIC_EnableIRQ(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller. |
||||
* @param IRQn External interrupt number . |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); |
||||
|
||||
/* Disable interrupt */ |
||||
NVIC_DisableIRQ(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU. |
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_SystemReset(void) |
||||
{ |
||||
/* System Reset */ |
||||
NVIC_SystemReset(); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
* Counter is in free running mode to generate periodic interrupts. |
||||
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. |
||||
* @retval status: - 0 Function succeeded. |
||||
* - 1 Function failed. |
||||
*/ |
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) |
||||
{ |
||||
return SysTick_Config(TicksNumb); |
||||
} |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
* |
||||
@verbatim
|
||||
============================================================================== |
||||
##### Peripheral Control functions ##### |
||||
==============================================================================
|
||||
[..] |
||||
This subsection provides a set of functions allowing to control the CORTEX |
||||
(NVIC, SYSTICK) functionalities.
|
||||
|
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt. |
||||
* @param IRQn: External interrupt number. |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l0xxxx.h)) |
||||
* @retval None |
||||
*/ |
||||
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) |
||||
{ |
||||
/* Get priority for Cortex-M system or device specific interrupts */ |
||||
return NVIC_GetPriority(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt. |
||||
* @param IRQn: External interrupt number |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{
|
||||
/* Set interrupt pending */ |
||||
NVIC_SetPendingIRQ(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt). |
||||
* @param IRQn: External interrupt number . |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @retval status: - 0 Interrupt status is not pending. |
||||
* - 1 Interrupt status is pending. |
||||
*/ |
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{
|
||||
/* Return 1 if pending else 0 */ |
||||
return NVIC_GetPendingIRQ(IRQn); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt. |
||||
* @param IRQn: External interrupt number . |
||||
* This parameter can be an enumerator of IRQn_Type enumeration |
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
|
||||
* @retval None |
||||
*/ |
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{
|
||||
/* Clear pending interrupt */ |
||||
NVIC_ClearPendingIRQ(IRQn); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source. |
||||
* @param CLKSource: specifies the SysTick clock source. |
||||
* This parameter can be one of the following values: |
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. |
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. |
||||
* @retval None |
||||
*/ |
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); |
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK) |
||||
{ |
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; |
||||
} |
||||
else |
||||
{ |
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request. |
||||
* @retval None |
||||
*/ |
||||
void HAL_SYSTICK_IRQHandler(void) |
||||
{ |
||||
HAL_SYSTICK_Callback(); |
||||
} |
||||
|
||||
/**
|
||||
* @brief SYSTICK callback. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_SYSTICK_Callback(void) |
||||
{ |
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file |
||||
*/ |
||||
} |
||||
|
||||
#if (__MPU_PRESENT == 1) |
||||
/**
|
||||
* @brief Initialize and configure the Region and the memory to be protected. |
||||
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains |
||||
* the initialization and configuration information. |
||||
* @retval None |
||||
*/ |
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); |
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); |
||||
|
||||
/* Set the Region number */ |
||||
MPU->RNR = MPU_Init->Number; |
||||
|
||||
if ((MPU_Init->Enable) == MPU_REGION_ENABLE) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); |
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); |
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); |
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); |
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); |
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); |
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); |
||||
|
||||
/* Set the base adsress and set the 4 LSB to 0 */ |
||||
MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U; |
||||
|
||||
/* Fill the field RASR */ |
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | |
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | |
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | |
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | |
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | |
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | |
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | |
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); |
||||
} |
||||
else |
||||
{ |
||||
MPU->RBAR = 0x00U; |
||||
MPU->RASR = 0x00U; |
||||
} |
||||
} |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,813 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_dma.c |
||||
* @author MCD Application Team |
||||
* @brief DMA HAL module driver. |
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access (DMA) peripheral: |
||||
* + Initialization/de-initialization functions |
||||
* + I/O operation functions |
||||
* + Peripheral State functions |
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver ##### |
||||
==============================================================================
|
||||
[..] |
||||
(#) Enable and configure the peripheral to be connected to the DMA Channel |
||||
(except for internal SRAM / FLASH memories: no initialization is
|
||||
necessary).
|
||||
|
||||
(#) For a given Channel, program the required configuration through the following parameters:
|
||||
Channel request, Transfer Direction, Source and Destination data formats,
|
||||
Circular, Normal or peripheral flow control mode, Channel Priority level,
|
||||
Source and Destination Increment mode using HAL_DMA_Init() function. |
||||
|
||||
*** Polling mode IO operation *** |
||||
=================================
|
||||
[..]
|
||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
|
||||
address and destination address and the Length of data to be transferred |
||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
|
||||
case a fixed Timeout can be configured by User depending from his application. |
||||
|
||||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() |
||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
|
||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
|
||||
Source address and destination address and the Length of data to be transferred. In this
|
||||
case the DMA interrupt is configured
|
||||
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine |
||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
|
||||
add his own function by customization of function pointer XferCpltCallback and
|
||||
XferErrorCallback (i.e a member of DMA handle structure).
|
||||
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection. |
||||
|
||||
(#) Use HAL_DMA_Abort() function to abort the current transfer
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
|
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
#ifdef HAL_DMA_MODULE_ENABLED |
||||
|
||||
/** @addtogroup DMA DMA
|
||||
* @brief DMA HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/** @addtogroup DMA_Private
|
||||
* |
||||
* @{ |
||||
*/ |
||||
#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000U) /* 1s */ |
||||
|
||||
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group1
|
||||
* @brief Initialization/de-initialization functions
|
||||
* |
||||
@verbatim
|
||||
=============================================================================== |
||||
##### Initialization and de-initialization functions ##### |
||||
===============================================================================
|
||||
[..] This section provides functions allowing to: |
||||
(+) Initialize and configure the DMA |
||||
(+) De-Initialize the DMA
|
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Initializes the DMA according to the specified |
||||
* parameters in the DMA_InitTypeDef and create the associated handle. |
||||
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) |
||||
{
|
||||
uint32_t tmp = 0U; |
||||
|
||||
/* Check the DMA peripheral state */ |
||||
if(hdma == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); |
||||
assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); |
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); |
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); |
||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); |
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
||||
|
||||
if(hdma->State == HAL_DMA_STATE_RESET) |
||||
{ |
||||
/* Allocate lock resource and initialize it */ |
||||
hdma->Lock = HAL_UNLOCKED; |
||||
} |
||||
|
||||
/* Change DMA peripheral state */ |
||||
hdma->State = HAL_DMA_STATE_BUSY; |
||||
|
||||
/* Get the CR register value */ |
||||
tmp = hdma->Instance->CCR; |
||||
|
||||
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ |
||||
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
||||
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
|
||||
DMA_CCR_DIR)); |
||||
|
||||
/* Prepare the DMA Channel configuration */ |
||||
tmp |= hdma->Init.Direction | |
||||
hdma->Init.PeriphInc | hdma->Init.MemInc | |
||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | |
||||
hdma->Init.Mode | hdma->Init.Priority; |
||||
|
||||
/* Write to DMA Channel CR register */ |
||||
hdma->Instance->CCR = tmp;
|
||||
|
||||
/* Write to DMA channel selection register */ |
||||
if (hdma->Instance == DMA1_Channel1) |
||||
{ |
||||
/*Reset request selection for DMA1 Channel1*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S; |
||||
|
||||
/* Configure request selection for DMA1 Channel1 */ |
||||
DMA1_CSELR->CSELR |= hdma->Init.Request; |
||||
} |
||||
else if (hdma->Instance == DMA1_Channel2) |
||||
{ |
||||
/*Reset request selection for DMA1 Channel2*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S; |
||||
|
||||
/* Configure request selection for DMA1 Channel2 */ |
||||
DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4U); |
||||
} |
||||
else if (hdma->Instance == DMA1_Channel3) |
||||
{ |
||||
/*Reset request selection for DMA1 Channel3*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S; |
||||
|
||||
/* Configure request selection for DMA1 Channel3 */ |
||||
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8U); |
||||
} |
||||
else if (hdma->Instance == DMA1_Channel4) |
||||
{ |
||||
/*Reset request selection for DMA1 Channel4*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S; |
||||
|
||||
/* Configure request selection for DMA1 Channel4 */ |
||||
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12U); |
||||
} |
||||
else if (hdma->Instance == DMA1_Channel5) |
||||
{ |
||||
/*Reset request selection for DMA1 Channel5*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S; |
||||
|
||||
/* Configure request selection for DMA1 Channel5 */ |
||||
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16U); |
||||
} |
||||
#if !defined (STM32L011xx) && !defined (STM32L021xx) |
||||
else if (hdma->Instance == DMA1_Channel6) |
||||
{ |
||||
/*Reset request selection for DMA1 Channel6*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S; |
||||
|
||||
/* Configure request selection for DMA1 Channel6 */ |
||||
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20U); |
||||
} |
||||
else if (hdma->Instance == DMA1_Channel7) |
||||
{ |
||||
/*Reset request selection for DMA1 Channel7*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S; |
||||
|
||||
/* Configure request selection for DMA1 Channel7 */ |
||||
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24U); |
||||
} |
||||
#endif |
||||
/* Initialize the DMA state*/ |
||||
hdma->State = HAL_DMA_STATE_READY; |
||||
|
||||
return HAL_OK; |
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the DMA peripheral
|
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) |
||||
{ |
||||
/* Check the DMA peripheral state */ |
||||
if(hdma == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the DMA peripheral state */ |
||||
if(hdma->State == HAL_DMA_STATE_BUSY) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Disable the selected DMA Channelx */ |
||||
__HAL_DMA_DISABLE(hdma); |
||||
|
||||
/* Reset DMA Channel control register */ |
||||
hdma->Instance->CCR = 0U; |
||||
|
||||
/* Reset DMA Channel Number of Data to Transfer register */ |
||||
hdma->Instance->CNDTR = 0U; |
||||
|
||||
/* Reset DMA Channel peripheral address register */ |
||||
hdma->Instance->CPAR = 0U; |
||||
|
||||
/* Reset DMA Channel memory address register */ |
||||
hdma->Instance->CMAR = 0U; |
||||
|
||||
/* Clear all flags */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
||||
|
||||
/* Reset DMA channel selection register */ |
||||
if (hdma->Instance == DMA1_Channel1) |
||||
{ |
||||
/*Reset DMA request*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S; |
||||
} |
||||
else if (hdma->Instance == DMA1_Channel2) |
||||
{ |
||||
/*Reset DMA request*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S; |
||||
} |
||||
else if (hdma->Instance == DMA1_Channel3) |
||||
{ |
||||
/*Reset DMA request*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S; |
||||
} |
||||
else if (hdma->Instance == DMA1_Channel4) |
||||
{ |
||||
/*Reset DMA request*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S; |
||||
} |
||||
else if (hdma->Instance == DMA1_Channel5) |
||||
{ |
||||
/*Reset DMA request*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S; |
||||
} |
||||
#if !defined (STM32L011xx) && !defined (STM32L021xx) |
||||
else if (hdma->Instance == DMA1_Channel6) |
||||
{ |
||||
/*Reset DMA request*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S; |
||||
} |
||||
else if (hdma->Instance == DMA1_Channel7) |
||||
{ |
||||
/*Reset DMA request*/ |
||||
DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S; |
||||
} |
||||
#endif |
||||
/* Initialise the error code */ |
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE; |
||||
|
||||
/* Initialize the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_RESET; |
||||
|
||||
/* Release Lock */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group2
|
||||
* @brief I/O operation functions
|
||||
* |
||||
@verbatim
|
||||
=============================================================================== |
||||
##### IO operation functions ##### |
||||
===============================================================================
|
||||
[..] This section provides functions allowing to: |
||||
(+) Configure the source, destination address and data length and Start DMA transfer |
||||
(+) Configure the source, destination address and data length and
|
||||
Start DMA transfer with interrupt |
||||
(+) Abort DMA transfer |
||||
(+) Poll for transfer complete |
||||
(+) Handle DMA interrupt request
|
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Starts the DMA Transfer. |
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress: The source memory Buffer address |
||||
* @param DstAddress: The destination memory Buffer address |
||||
* @param DataLength: The length of data to be transferred from source to destination |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
||||
{
|
||||
/* Process locked */ |
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
||||
|
||||
/* Disable the peripheral */ |
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length */ |
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
||||
|
||||
/* Enable the Peripheral */ |
||||
__HAL_DMA_ENABLE(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer with interrupt enabled. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress: The source memory Buffer address |
||||
* @param DstAddress: The destination memory Buffer address |
||||
* @param DataLength: The length of data to be transferred from source to destination |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
||||
{ |
||||
/* Process locked */ |
||||
__HAL_LOCK(hdma); |
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
||||
|
||||
/* Disable the peripheral */ |
||||
__HAL_DMA_DISABLE(hdma); |
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); |
||||
|
||||
/* Enable the transfer complete interrupt */ |
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); |
||||
|
||||
/* Enable the Half transfer complete interrupt */ |
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
|
||||
|
||||
/* Enable the transfer Error interrupt */ |
||||
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); |
||||
|
||||
/* Enable the Peripheral */ |
||||
__HAL_DMA_ENABLE(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Aborts the DMA Transfer. |
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
||||
{ |
||||
uint32_t tickstart = 0U; |
||||
|
||||
/* Disable the channel */ |
||||
__HAL_DMA_DISABLE(hdma); |
||||
|
||||
/* Get timeout */ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Check if the DMA Channel is effectively disabled */ |
||||
while((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
|
||||
{ |
||||
/* Check for the Timeout */ |
||||
if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) |
||||
{ |
||||
/* Update error code */ |
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_TIMEOUT; |
||||
|
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
/* Change the DMA state*/ |
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Aborts the DMA Transfer in Interrupt mode. |
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Stream. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) |
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State) |
||||
{ |
||||
/* no transfer ongoing */ |
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
||||
|
||||
status = HAL_ERROR; |
||||
} |
||||
else |
||||
{
|
||||
/* Disable DMA IT */ |
||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
||||
|
||||
/* Disable the channel */ |
||||
__HAL_DMA_DISABLE(hdma); |
||||
|
||||
/* Clear all flags */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); |
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
/* Call User Abort callback */
|
||||
if(hdma->XferAbortCallback != NULL) |
||||
{ |
||||
hdma->XferAbortCallback(hdma); |
||||
}
|
||||
} |
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Polling for transfer complete. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @param CompleteLevel: Specifies the DMA level complete.
|
||||
* @param Timeout: Timeout duration. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) |
||||
{ |
||||
uint32_t temp; |
||||
uint32_t tickstart = 0U; |
||||
|
||||
/* Get the level transfer complete flag */ |
||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
||||
{ |
||||
/* Transfer Complete flag */ |
||||
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); |
||||
} |
||||
else |
||||
{ |
||||
/* Half Transfer Complete flag */ |
||||
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); |
||||
} |
||||
|
||||
/* Get timeout */ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) |
||||
{ |
||||
if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) |
||||
{
|
||||
/* Clear the transfer error flags */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
||||
|
||||
/* Update error code */ |
||||
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); |
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State= HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check for the Timeout */ |
||||
if(Timeout != HAL_MAX_DELAY) |
||||
{ |
||||
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
||||
{ |
||||
/* Update error code */ |
||||
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); |
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State= HAL_DMA_STATE_TIMEOUT; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
|
||||
if(CompleteLevel == HAL_DMA_FULL_TRANSFER) |
||||
{ |
||||
/* Clear the transfer complete flag */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
||||
|
||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||||
all transfers are complete) */ |
||||
hdma->State = HAL_DMA_STATE_READY; |
||||
|
||||
/* Process unlocked */ |
||||
__HAL_UNLOCK(hdma);
|
||||
} |
||||
else |
||||
{
|
||||
/* Clear the half transfer complete flag */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
||||
|
||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||||
all transfers are complete) */ |
||||
hdma->State = HAL_DMA_STATE_READY_HALF; |
||||
|
||||
/* Process unlocked */ |
||||
__HAL_UNLOCK(hdma);
|
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
/**
|
||||
* @brief Handles DMA interrupt request. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) |
||||
{
|
||||
/* Transfer Error Interrupt management ***************************************/ |
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) |
||||
{ |
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) |
||||
{ |
||||
/* Disable the transfer error interrupt */ |
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); |
||||
|
||||
/* Clear the transfer error flag */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); |
||||
|
||||
/* Update error code */ |
||||
hdma->ErrorCode |= HAL_DMA_ERROR_TE; |
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_ERROR;
|
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if (hdma->XferErrorCallback != NULL) |
||||
{ |
||||
/* Transfer error callback */ |
||||
hdma->XferErrorCallback(hdma); |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* Half Transfer Complete Interrupt management ******************************/ |
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) |
||||
{ |
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) |
||||
{
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ |
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
||||
{ |
||||
/* Disable the half transfer interrupt */ |
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); |
||||
} |
||||
/* Clear the half transfer complete flag */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); |
||||
|
||||
/* Change DMA peripheral state */ |
||||
hdma->State = HAL_DMA_STATE_READY_HALF; |
||||
|
||||
if(hdma->XferHalfCpltCallback != NULL) |
||||
{ |
||||
/* Half transfer callback */ |
||||
hdma->XferHalfCpltCallback(hdma); |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* Transfer Complete Interrupt management ***********************************/ |
||||
if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) |
||||
{ |
||||
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) |
||||
{ |
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) |
||||
{ |
||||
/* Disable the transfer complete interrupt */ |
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); |
||||
} |
||||
/* Clear the transfer complete flag */ |
||||
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); |
||||
|
||||
/* Update error code */ |
||||
hdma->ErrorCode |= HAL_DMA_ERROR_NONE; |
||||
|
||||
/* Change the DMA state */ |
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hdma); |
||||
|
||||
if(hdma->XferCpltCallback != NULL) |
||||
{
|
||||
/* Transfer complete callback */ |
||||
hdma->XferCpltCallback(hdma); |
||||
} |
||||
} |
||||
} |
||||
}
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group3
|
||||
* @brief Peripheral State functions
|
||||
* |
||||
@verbatim
|
||||
=============================================================================== |
||||
##### Peripheral State functions ##### |
||||
===============================================================================
|
||||
[..] |
||||
This subsection provides functions allowing to |
||||
(+) Check the DMA state |
||||
(+) Get error code |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the DMA state. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL state |
||||
*/ |
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) |
||||
{ |
||||
return hdma->State; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Return the DMA error code |
||||
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel. |
||||
* @retval DMA Error Code |
||||
*/ |
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) |
||||
{ |
||||
return hdma->ErrorCode; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @addtogroup DMA_Private
|
||||
* @{ |
||||
*/ |
||||
|
||||
/*
|
||||
* @brief Sets the DMA Transfer parameter. |
||||
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress: The source memory Buffer address |
||||
* @param DstAddress: The destination memory Buffer address |
||||
* @param DataLength: The length of data to be transferred from source to destination |
||||
* @retval HAL status |
||||
*/ |
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
||||
{
|
||||
/* Configure DMA Channel data length */ |
||||
hdma->Instance->CNDTR = DataLength; |
||||
|
||||
/* Peripheral to Memory */ |
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) |
||||
{
|
||||
/* Configure DMA Channel destination address */ |
||||
hdma->Instance->CPAR = DstAddress; |
||||
|
||||
/* Configure DMA Channel source address */ |
||||
hdma->Instance->CMAR = SrcAddress; |
||||
} |
||||
/* Memory to Peripheral */ |
||||
else |
||||
{ |
||||
/* Configure DMA Channel source address */ |
||||
hdma->Instance->CPAR = SrcAddress; |
||||
|
||||
/* Configure DMA Channel destination address */ |
||||
hdma->Instance->CMAR = DstAddress; |
||||
} |
||||
} |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,751 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_flash.c |
||||
* @author MCD Application Team |
||||
* @brief FLASH HAL module driver. |
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory: |
||||
* + Program operations functions |
||||
* + Memory Control functions
|
||||
* + Peripheral State functions |
||||
*
|
||||
@verbatim |
||||
============================================================================== |
||||
##### FLASH peripheral features ##### |
||||
============================================================================== |
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms. |
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction |
||||
prefetch.
|
||||
|
||||
[..] The FLASH main features are: |
||||
(+) Flash memory read operations |
||||
(+) Flash memory program/erase operations |
||||
(+) Read / write protections |
||||
(+) Prefetch on I-Code |
||||
(+) Option Bytes programming |
||||
|
||||
|
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32L0xx devices. |
||||
|
||||
(#) FLASH Memory I/O Programming functions: this group includes all needed |
||||
functions to erase and program the main memory: |
||||
(++) Lock and Unlock the FLASH interface |
||||
(++) Erase function: Erase page |
||||
(++) Program functions: Fast Word and Half Page(should be
|
||||
executed from internal SRAM). |
||||
|
||||
(#) DATA EEPROM Programming functions: this group includes all
|
||||
needed functions to erase and program the DATA EEPROM memory: |
||||
(++) Lock and Unlock the DATA EEPROM interface. |
||||
(++) Erase function: Erase Byte, erase HalfWord, erase Word, erase
|
||||
Double Word (should be executed from internal SRAM). |
||||
(++) Program functions: Fast Program Byte, Fast Program Half-Word,
|
||||
FastProgramWord, Program Byte, Program Half-Word,
|
||||
Program Word and Program Double-Word (should be executed
|
||||
from internal SRAM). |
||||
|
||||
(#) FLASH Option Bytes Programming functions: this group includes all needed |
||||
functions to manage the Option Bytes: |
||||
(++) Lock and Unlock the Option Bytes |
||||
(++) Set/Reset the write protection |
||||
(++) Set the Read protection Level |
||||
(++) Program the user Option Bytes |
||||
(++) Launch the Option Bytes loader |
||||
(++) Set/Get the Read protection Level. |
||||
(++) Set/Get the BOR level. |
||||
(++) Get the Write protection. |
||||
(++) Get the user option bytes. |
||||
|
||||
(#) Interrupts and flags management functions : this group
|
||||
includes all needed functions to: |
||||
(++) Handle FLASH interrupts |
||||
(++) Wait for last FLASH operation according to its status |
||||
(++) Get error flag status |
||||
|
||||
(#) FLASH Interface configuration functions: this group includes
|
||||
the management of following features: |
||||
(++) Enable/Disable the RUN PowerDown mode. |
||||
(++) Enable/Disable the SLEEP PowerDown mode.
|
||||
|
||||
(#) FLASH Peripheral State methods: this group includes
|
||||
the management of following features: |
||||
(++) Wait for the FLASH operation |
||||
(++) Get the specific FLASH error flag |
||||
|
||||
[..] In addition to these function, this driver includes a set of macros allowing |
||||
to handle the following operations: |
||||
|
||||
(+) Set/Get the latency |
||||
(+) Enable/Disable the prefetch buffer |
||||
(+) Enable/Disable the preread buffer |
||||
(+) Enable/Disable the Flash power-down |
||||
(+) Enable/Disable the FLASH interrupts |
||||
(+) Monitor the FLASH flags status |
||||
|
||||
##### Programming operation functions ##### |
||||
===============================================================================
|
||||
[..] |
||||
This subsection provides a set of functions allowing to manage the FLASH
|
||||
program operations. |
||||
|
||||
[..] The FLASH Memory Programming functions, includes the following functions: |
||||
(+) HAL_FLASH_Unlock(void); |
||||
(+) HAL_FLASH_Lock(void); |
||||
(+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) |
||||
(+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) |
||||
|
||||
[..] Any operation of erase or program should follow these steps: |
||||
(#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
|
||||
program memory access. |
||||
(#) Call the desired function to erase page or program data. |
||||
(#) Call the HAL_FLASH_Lock() to disable the flash program memory access
|
||||
(recommended to protect the FLASH memory against possible unwanted operation). |
||||
|
||||
##### Option Bytes Programming functions ##### |
||||
==============================================================================
|
||||
|
||||
[..] The FLASH_Option Bytes Programming_functions, includes the following functions: |
||||
(+) HAL_FLASH_OB_Unlock(void); |
||||
(+) HAL_FLASH_OB_Lock(void); |
||||
(+) HAL_FLASH_OB_Launch(void); |
||||
(+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); |
||||
(+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); |
||||
|
||||
[..] Any operation of erase or program should follow these steps: |
||||
(#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control
|
||||
register access. |
||||
(#) Call the following functions to program the desired option bytes. |
||||
(++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
(#) Once all needed option bytes to be programmed are correctly written, call the |
||||
HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. |
||||
(#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended |
||||
to protect the option Bytes against possible unwanted operations). |
||||
|
||||
[..] Proprietary code Read Out Protection (PcROP):
|
||||
(#) The PcROP sector is selected by using the same option bytes as the Write |
||||
protection. As a result, these 2 options are exclusive each other. |
||||
(#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below: |
||||
(++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE. |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
******************************************************************************
|
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED |
||||
|
||||
/** @defgroup FLASH FLASH
|
||||
* @brief FLASH HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private macro ---------------------------- ---------------------------------*/ |
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{ |
||||
*/ |
||||
/* Variables used for Erase pages under interruption*/ |
||||
FLASH_ProcessTypeDef pFlash; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{ |
||||
*/ |
||||
static void FLASH_SetErrorCode(void); |
||||
extern void FLASH_PageErase(uint32_t PageAddress); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions ---------------------------------------------------------*/ |
||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
* |
||||
@verbatim
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Program word at a specified address |
||||
* @note To correctly run this function, the HAL_FLASH_Unlock() function |
||||
* must be called before. |
||||
* Call the HAL_FLASH_Lock() to disable the flash memory access |
||||
* (recommended to protect the FLASH memory against possible unwanted operation). |
||||
* |
||||
* @param TypeProgram Indicate the way to program at a specified address. |
||||
* This parameter can be a value of @ref FLASH_Type_Program |
||||
* @param Address Specifie the address to be programmed. |
||||
* @param Data Specifie the data to be programmed |
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_ERROR; |
||||
|
||||
/* Process Locked */ |
||||
__HAL_LOCK(&pFlash); |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); |
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); |
||||
|
||||
/* Wait for last operation to be completed */ |
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
|
||||
if(status == HAL_OK) |
||||
{ |
||||
/* Clean the error context */ |
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; |
||||
|
||||
/*Program word (32-bit) at a specified address.*/ |
||||
*(__IO uint32_t *)Address = Data; |
||||
|
||||
/* Wait for last operation to be completed */ |
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
} |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(&pFlash); |
||||
|
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Program word at a specified address with interrupt enabled. |
||||
* |
||||
* @param TypeProgram Indicate the way to program at a specified address. |
||||
* This parameter can be a value of @ref FLASH_Type_Program |
||||
* @param Address Specifie the address to be programmed. |
||||
* @param Data Specifie the data to be programmed |
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
/* Process Locked */ |
||||
__HAL_LOCK(&pFlash); |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); |
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); |
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */ |
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); |
||||
|
||||
pFlash.Address = Address; |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; |
||||
/* Clean the error context */ |
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; |
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_WORD) |
||||
{ |
||||
/* Program word (32-bit) at a specified address. */ |
||||
*(__IO uint32_t *)Address = Data; |
||||
} |
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request. |
||||
* @retval None |
||||
*/ |
||||
void HAL_FLASH_IRQHandler(void) |
||||
{ |
||||
uint32_t addresstmp = 0; |
||||
|
||||
/* Check FLASH operation error flags */ |
||||
|
||||
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
|
||||
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving |
||||
* as expected. If the user run an application using the first |
||||
* cut of the STM32L031xx device or the first cut of the STM32L041xx |
||||
* device, the check on the FLASH_FLAG_OPTVERR bit should be ignored. |
||||
* |
||||
* Note :The revId of the device can be retrieved via the HAL_GetREVID() |
||||
* function. |
||||
* |
||||
*/ |
||||
|
||||
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) |
||||
{ |
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) |
||||
{ |
||||
/* Return the faulty sector */ |
||||
addresstmp = pFlash.Page; |
||||
pFlash.Page = 0xFFFFFFFFU; |
||||
} |
||||
else |
||||
{ |
||||
/* Return the faulty address */ |
||||
addresstmp = pFlash.Address; |
||||
} |
||||
/* Save the Error code */ |
||||
FLASH_SetErrorCode(); |
||||
|
||||
/* FLASH error interrupt user callback */ |
||||
HAL_FLASH_OperationErrorCallback(addresstmp); |
||||
|
||||
/* Stop the procedure ongoing */ |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
||||
} |
||||
|
||||
/* Check FLASH End of Operation flag */ |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) |
||||
{ |
||||
/* Clear FLASH End of Operation pending bit */ |
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); |
||||
|
||||
/* Process can continue only if no error detected */ |
||||
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) |
||||
{ |
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) |
||||
{ |
||||
/* Nb of pages to erased can be decreased */ |
||||
pFlash.NbPagesToErase--; |
||||
|
||||
/* Check if there are still pages to erase */ |
||||
if(pFlash.NbPagesToErase != 0U) |
||||
{ |
||||
addresstmp = pFlash.Page; |
||||
/*Indicate user which sector has been erased */ |
||||
HAL_FLASH_EndOfOperationCallback(addresstmp); |
||||
|
||||
/*Increment sector number*/ |
||||
addresstmp = pFlash.Page + FLASH_PAGE_SIZE; |
||||
pFlash.Page = addresstmp; |
||||
|
||||
/* If the erase operation is completed, disable the ERASE Bit */ |
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); |
||||
|
||||
FLASH_PageErase(addresstmp); |
||||
} |
||||
else |
||||
{ |
||||
/* No more pages to Erase, user callback can be called. */ |
||||
/* Reset Sector and stop Erase pages procedure */ |
||||
pFlash.Page = addresstmp = 0xFFFFFFFFU; |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
||||
/* FLASH EOP interrupt user callback */ |
||||
HAL_FLASH_EndOfOperationCallback(addresstmp); |
||||
} |
||||
} |
||||
else |
||||
{ |
||||
/* If the program operation is completed, disable the PROG Bit */ |
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); |
||||
|
||||
/* Program ended. Return the selected address */ |
||||
/* FLASH EOP interrupt user callback */ |
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address); |
||||
|
||||
/* Reset Address and stop Program procedure */ |
||||
pFlash.Address = 0xFFFFFFFFU; |
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; |
||||
} |
||||
} |
||||
} |
||||
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) |
||||
{ |
||||
/* Operation is completed, disable the PROG and ERASE */ |
||||
CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG)); |
||||
|
||||
/* Disable End of FLASH Operation and Error source interrupts */ |
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(&pFlash); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback |
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure |
||||
* - Pages Erase: Address of the page which has been erased
|
||||
* (if 0xFFFFFFFF, it means that all the selected pages have been erased) |
||||
* - Program: Address which was selected for data program |
||||
* @retval none |
||||
*/ |
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) |
||||
{ |
||||
/* Prevent unused argument(s) compilation warning */ |
||||
UNUSED(ReturnValue); |
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file |
||||
*/
|
||||
} |
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback |
||||
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure |
||||
* - Pages Erase: Address of the page which returned an error |
||||
* - Program: Address which was selected for data program |
||||
* @retval none |
||||
*/ |
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) |
||||
{ |
||||
/* Prevent unused argument(s) compilation warning */ |
||||
UNUSED(ReturnValue); |
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file |
||||
*/
|
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions
|
||||
* |
||||
@verbatim
|
||||
=============================================================================== |
||||
##### Peripheral Control functions ##### |
||||
===============================================================================
|
||||
[..] |
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access |
||||
* @retval HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void) |
||||
{ |
||||
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK)) |
||||
{ |
||||
/* Unlocking FLASH_PECR register access*/ |
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) |
||||
{
|
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); |
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); |
||||
} |
||||
|
||||
/* Unlocking the program memory access */ |
||||
WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1); |
||||
WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2);
|
||||
} |
||||
else |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access |
||||
* @retval HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void) |
||||
{ |
||||
/* Set the PRGLOCK Bit to lock the FLASH Registers access */ |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK); |
||||
|
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access. |
||||
* @retval HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) |
||||
{ |
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK)) |
||||
{ |
||||
/* Unlocking FLASH_PECR register access*/ |
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) |
||||
{
|
||||
/* Unlocking FLASH_PECR register access*/ |
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); |
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); |
||||
} |
||||
|
||||
/* Unlocking the option bytes block access */ |
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); |
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); |
||||
} |
||||
else |
||||
{ |
||||
return HAL_ERROR; |
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access. |
||||
* @retval HAL Status
|
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) |
||||
{ |
||||
/* Set the OPTLOCK Bit to lock the option bytes block access */ |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK); |
||||
|
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading. |
||||
* @note This function will reset automatically the MCU. |
||||
* @retval HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) |
||||
{ |
||||
/* Set the OBL_Launch bit to launch the option byte loading */ |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH); |
||||
|
||||
/* Wait for last operation to be completed */ |
||||
return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
|
||||
* @brief Peripheral errors functions
|
||||
* |
||||
@verbatim
|
||||
=============================================================================== |
||||
##### Peripheral Errors functions ##### |
||||
===============================================================================
|
||||
[..] |
||||
This subsection permit to get in run-time errors of the FLASH peripheral. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag. |
||||
* @retval FLASH_ErrorCode The returned value can be: |
||||
* @ref FLASH_Error_Codes |
||||
*/ |
||||
uint32_t HAL_FLASH_GetError(void) |
||||
{ |
||||
return pFlash.ErrorCode; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete. |
||||
* @param Timeout maximum flash operation timeout |
||||
* @retval HAL Status |
||||
*/ |
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) |
||||
{ |
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error |
||||
flag will be set */ |
||||
|
||||
uint32_t tickstart = HAL_GetTick(); |
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY) |
||||
{ |
||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* Check FLASH End of Operation flag */ |
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) |
||||
{ |
||||
/* Clear FLASH End of Operation pending bit */ |
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); |
||||
} |
||||
|
||||
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) |
||||
{ |
||||
/*Save the error code*/ |
||||
|
||||
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
|
||||
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving |
||||
* as expected. If the user run an application using the first |
||||
* cut of the STM32L031xx device or the first cut of the STM32L041xx |
||||
* device, this error should be ignored. The revId of the device |
||||
* can be retrieved via the HAL_GetREVID() function. |
||||
* |
||||
*/ |
||||
FLASH_SetErrorCode(); |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* There is no error flag set */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag. |
||||
* @retval None |
||||
*/ |
||||
static void FLASH_SetErrorCode(void) |
||||
{ |
||||
uint32_t flags = 0; |
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) |
||||
{ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; |
||||
flags |= FLASH_FLAG_WRPERR; |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) |
||||
{ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; |
||||
flags |= FLASH_FLAG_PGAERR; |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) |
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE; |
||||
flags |= FLASH_FLAG_SIZERR; |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) |
||||
{ |
||||
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
|
||||
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving |
||||
* as expected. If the user run an application using the first |
||||
* cut of the STM32L031xx device or the first cut of the STM32L041xx |
||||
* device, this error should be ignored. The revId of the device |
||||
* can be retrieved via the HAL_GetREVID() function. |
||||
* |
||||
*/ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; |
||||
flags |= FLASH_FLAG_OPTVERR; |
||||
} |
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) |
||||
{ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; |
||||
flags |= FLASH_FLAG_RDERR; |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR)) |
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR; |
||||
flags |= HAL_FLASH_ERROR_FWWERR; |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR)) |
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO; |
||||
flags |= FLASH_FLAG_NOTZEROERR; |
||||
} |
||||
|
||||
/* Clear FLASH error pending bits */ |
||||
__HAL_FLASH_CLEAR_FLAG(flags); |
||||
}
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,537 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_flash_ramfunc.c |
||||
* @author MCD Application Team |
||||
* @brief FLASH RAMFUNC driver. |
||||
* This file provides a Flash firmware functions which should be
|
||||
* executed from internal SRAM |
||||
* |
||||
* @verbatim |
||||
|
||||
*** ARM Compiler *** |
||||
-------------------- |
||||
[..] RAM functions are defined using the toolchain options.
|
||||
Functions that are be executed in RAM should reside in a separate |
||||
source module. Using the 'Options for File' dialog you can simply change |
||||
the 'Code / Const' area of a module to a memory space in physical RAM. |
||||
Available memory areas are declared in the 'Target' tab of the
|
||||
Options for Target' dialog. |
||||
|
||||
*** ICCARM Compiler *** |
||||
----------------------- |
||||
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc". |
||||
|
||||
*** GNU Compiler *** |
||||
-------------------- |
||||
[..] RAM functions are defined using a specific toolchain attribute |
||||
"__attribute__((section(".RamFunc")))". |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED |
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{ |
||||
*/ |
||||
/** @addtogroup FLASH_Private_Variables
|
||||
* @{ |
||||
*/ |
||||
extern FLASH_ProcessTypeDef pFlash; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
|
||||
* @brief FLASH functions executed from RAM |
||||
* @{ |
||||
*/
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout); |
||||
static __RAM_FUNC FLASHRAM_SetErrorCode(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private functions ---------------------------------------------------------*/ |
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions
|
||||
* |
||||
@verbatim
|
||||
=============================================================================== |
||||
##### ramfunc functions ##### |
||||
===============================================================================
|
||||
[..] |
||||
This subsection provides a set of functions that should be executed from RAM
|
||||
transfers. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the power down mode during RUN mode. |
||||
* @note This function can be used only when the user code is running from Internal SRAM. |
||||
* @retval HAL status |
||||
*/ |
||||
__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void) |
||||
{ |
||||
/* Enable the Power Down in Run mode*/ |
||||
__HAL_FLASH_POWER_DOWN_ENABLE(); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable the power down mode during RUN mode. |
||||
* @note This function can be used only when the user code is running from Internal SRAM. |
||||
* @retval HAL status |
||||
*/ |
||||
__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) |
||||
{ |
||||
/* Disable the Power Down in Run mode*/ |
||||
__HAL_FLASH_POWER_DOWN_DISABLE(); |
||||
|
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions
|
||||
* |
||||
@verbatim
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
#if defined(FLASH_PECR_PARALLBANK) |
||||
/**
|
||||
* @brief Erases a specified 2 pages in program memory in parallel. |
||||
* @note This function can be used only for STM32L07xxx/STM32L08xxx devices. |
||||
* To correctly run this function, the @ref HAL_FLASH_Unlock() function |
||||
* must be called before. |
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation). |
||||
* @param Page_Address1: The page address in program memory to be erased in
|
||||
* the first Bank (BANK1). This parameter should be between FLASH_BASE |
||||
* and FLASH_BANK1_END. |
||||
* @param Page_Address2: The page address in program memory to be erased in
|
||||
* the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE |
||||
* and FLASH_BANK2_END. |
||||
* @note A Page is erased in the Program memory only if the address to load
|
||||
* is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes). |
||||
* @retval HAL status |
||||
*/ |
||||
__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
/* Wait for last operation to be completed */ |
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
|
||||
if(status == HAL_OK) |
||||
{ |
||||
/* Proceed to erase the page */ |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PROG); |
||||
|
||||
/* Write 00000000h to the first word of the first program page to erase */ |
||||
*(__IO uint32_t *)Page_Address1 = 0x00000000U; |
||||
/* Write 00000000h to the first word of the second program page to erase */
|
||||
*(__IO uint32_t *)Page_Address2 = 0x00000000U; |
||||
|
||||
/* Wait for last operation to be completed */ |
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
|
||||
/* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */ |
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); |
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); |
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); |
||||
}
|
||||
/* Return the Erase Status */ |
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Program 2 half pages in program memory in parallel (half page size is 16 Words). |
||||
* @note This function can be used only for STM32L07xxx/STM32L08xxx devices. |
||||
* @param Address1: specifies the first address to be written in the first bank
|
||||
* (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE). |
||||
* @param pBuffer1: pointer to the buffer containing the data to be written
|
||||
* to the first half page in the first bank. |
||||
* @param Address2: specifies the second address to be written in the second bank |
||||
* (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE). |
||||
* @param pBuffer2: pointer to the buffer containing the data to be written
|
||||
* to the second half page in the second bank. |
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function |
||||
* must be called before. |
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation). |
||||
* @note Half page write is possible only from SRAM. |
||||
* @note A half page is written to the program memory only if the first
|
||||
* address to load is the start address of a half page (multiple of 64
|
||||
* bytes) and the 15 remaining words to load are in the same half page. |
||||
* @note During the Program memory half page write all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.). |
||||
* @note If a PGAERR is set during a Program memory half page write, the
|
||||
* complete write operation is aborted. Software should then reset the
|
||||
* FPRG and PROG/DATA bits and restart the write operation from the
|
||||
* beginning. |
||||
* @retval HAL status |
||||
*/ |
||||
__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2) |
||||
{ |
||||
uint32_t count = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
/* Wait for last operation to be completed */ |
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
|
||||
if(status == HAL_OK) |
||||
{ |
||||
/* Proceed to program the new half page */ |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PROG); |
||||
|
||||
/* Wait for last operation to be completed */ |
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
if(status == HAL_OK) |
||||
{ |
||||
/* Disable all IRQs */ |
||||
__disable_irq(); |
||||
|
||||
/* Write the first half page directly with 16 different words */ |
||||
while(count < 16U) |
||||
{ |
||||
/* Address1 doesn't need to be increased */
|
||||
*(__IO uint32_t*) Address1 = *pBuffer1; |
||||
pBuffer1++; |
||||
count ++;
|
||||
} |
||||
|
||||
/* Write the second half page directly with 16 different words */ |
||||
count = 0U; |
||||
while(count < 16U) |
||||
{ |
||||
/* Address2 doesn't need to be increased */
|
||||
*(__IO uint32_t*) Address2 = *pBuffer2; |
||||
pBuffer2++; |
||||
count ++;
|
||||
} |
||||
|
||||
/* Enable IRQs */ |
||||
__enable_irq(); |
||||
|
||||
/* Wait for last operation to be completed */ |
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
} |
||||
|
||||
/* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */ |
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); |
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); |
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); |
||||
} |
||||
|
||||
/* Return the Write Status */ |
||||
return status; |
||||
} |
||||
#endif /* FLASH_PECR_PARALLBANK */ |
||||
|
||||
/**
|
||||
* @brief Program a half page in program memory. |
||||
* @param Address: specifies the address to be written. |
||||
* @param pBuffer: pointer to the buffer containing the data to be written to
|
||||
* the half page. |
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function |
||||
* must be called before. |
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation) |
||||
* @note Half page write is possible only from SRAM. |
||||
* @note A half page is written to the program memory only if the first
|
||||
* address to load is the start address of a half page (multiple of 64
|
||||
* bytes) and the 15 remaining words to load are in the same half page. |
||||
* @note During the Program memory half page write all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.). |
||||
* @note If a PGAERR is set during a Program memory half page write, the
|
||||
* complete write operation is aborted. Software should then reset the
|
||||
* FPRG and PROG/DATA bits and restart the write operation from the
|
||||
* beginning. |
||||
* @retval HAL status |
||||
*/ |
||||
__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer) |
||||
{ |
||||
uint32_t count = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
|
||||
/* Wait for last operation to be completed */ |
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
|
||||
if(status == HAL_OK) |
||||
{ |
||||
/* Proceed to program the new half page */ |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); |
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PROG); |
||||
|
||||
/* Disable all IRQs */ |
||||
__disable_irq(); |
||||
|
||||
/* Write one half page directly with 16 different words */ |
||||
while(count < 16U) |
||||
{ |
||||
/* Address doesn't need to be increased */
|
||||
*(__IO uint32_t*) Address = *pBuffer; |
||||
pBuffer++; |
||||
count ++;
|
||||
} |
||||
|
||||
/* Enable IRQs */ |
||||
__enable_irq(); |
||||
|
||||
/* Wait for last operation to be completed */ |
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
||||
|
||||
/* If the write operation is completed, disable the PROG and FPRG bits */ |
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); |
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); |
||||
} |
||||
|
||||
/* Return the Write Status */ |
||||
return status; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions
|
||||
* @brief Peripheral errors functions
|
||||
* |
||||
@verbatim
|
||||
=============================================================================== |
||||
##### Peripheral errors functions ##### |
||||
===============================================================================
|
||||
[..] |
||||
This subsection permit to get in run-time errors of the FLASH peripheral. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH errors flag. |
||||
* @param Error pointer is the error value. It can be a mixed of: |
||||
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) |
||||
* @arg @ref HAL_FLASH_ERROR_SIZE FLASH Programming Parallelism error flag
|
||||
* @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag |
||||
* @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag |
||||
* @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag
|
||||
* @arg @ref HAL_FLASH_ERROR_FWWERR FLASH Write or Erase operation aborted |
||||
* @arg @ref HAL_FLASH_ERROR_NOTZERO FLASH Write operation is done in a not-erased region |
||||
* @retval HAL Status |
||||
*/ |
||||
__RAM_FUNC HAL_FLASHEx_GetError(uint32_t * Error) |
||||
{
|
||||
*Error = pFlash.ErrorCode; |
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_RAMFUNC_Private_Functions
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag. |
||||
* @retval HAL Status |
||||
*/ |
||||
static __RAM_FUNC FLASHRAM_SetErrorCode(void) |
||||
{ |
||||
uint32_t flags = 0; |
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) |
||||
{ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; |
||||
flags |= FLASH_FLAG_WRPERR; |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) |
||||
{ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; |
||||
flags |= FLASH_FLAG_PGAERR; |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) |
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE; |
||||
flags |= FLASH_FLAG_SIZERR; |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) |
||||
{ |
||||
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
|
||||
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving |
||||
* as expected. If the user run an application using the first |
||||
* cut of the STM32L031xx device or the first cut of the STM32L041xx |
||||
* device, this error should be ignored. The revId of the device |
||||
* can be retrieved via the HAL_GetREVID() function. |
||||
* |
||||
*/ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; |
||||
flags |= FLASH_FLAG_OPTVERR; |
||||
} |
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) |
||||
{ |
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; |
||||
flags |= FLASH_FLAG_RDERR; |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR)) |
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR; |
||||
flags |= HAL_FLASH_ERROR_FWWERR; |
||||
} |
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR)) |
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO; |
||||
flags |= FLASH_FLAG_NOTZEROERR; |
||||
} |
||||
|
||||
/* Clear FLASH error pending bits */ |
||||
__HAL_FLASH_CLEAR_FLAG(flags); |
||||
|
||||
return HAL_OK; |
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete. |
||||
* @param Timeout: maximum flash operationtimeout |
||||
* @retval HAL status |
||||
*/ |
||||
static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout) |
||||
{
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error |
||||
flag will be set */ |
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U))
|
||||
{
|
||||
Timeout--; |
||||
} |
||||
|
||||
if(Timeout == 0x00U) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
|
||||
/* Check FLASH End of Operation flag */ |
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) |
||||
{ |
||||
/* Clear FLASH End of Operation pending bit */ |
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); |
||||
} |
||||
|
||||
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) |
||||
{ |
||||
/*Save the error code*/ |
||||
|
||||
/* WARNING : On the first cut of STM32L031xx and STM32L041xx devices,
|
||||
* (RefID = 0x1000) the FLASH_FLAG_OPTVERR bit was not behaving |
||||
* as expected. If the user run an application using the first |
||||
* cut of the STM32L031xx device or the first cut of the STM32L041xx |
||||
* device, this error should be ignored. The revId of the device |
||||
* can be retrieved via the HAL_GetREVID() function. |
||||
* |
||||
*/ |
||||
FLASHRAM_SetErrorCode(); |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* There is no error flag set */ |
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,545 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_gpio.c |
||||
* @author MCD Application Team |
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral: |
||||
* + Initialization and de-initialization functions |
||||
* + IO operation functions |
||||
*
|
||||
@verbatim |
||||
============================================================================== |
||||
##### GPIO Peripheral features ##### |
||||
============================================================================== |
||||
[..]
|
||||
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
configured by software in several modes: |
||||
(++) Input mode
|
||||
(++) Analog mode |
||||
(++) Output mode |
||||
(++) Alternate function mode |
||||
(++) External interrupt/event lines |
||||
|
||||
(+) During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode. |
||||
|
||||
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not. |
||||
|
||||
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull |
||||
type and the IO speed can be selected depending on the VDD value. |
||||
|
||||
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
|
||||
multiplexer that allows only one peripheral alternate function (AF) connected
|
||||
to an IO pin at a time. In this way, there can be no conflict between peripherals
|
||||
sharing the same IO pin.
|
||||
|
||||
(+) All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. |
||||
|
||||
(+) The external interrupt/event controller consists of up to 28 edge detectors |
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver ##### |
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO IOPORT clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init(). |
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure |
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure. |
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure. |
||||
(++) In alternate mode is selection, the alternate function connected to the IO |
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure. |
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output. |
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both). |
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using |
||||
HAL_NVIC_EnableIRQ(). |
||||
|
||||
(#) HAL_GPIO_DeInit allows to set register values to their reset value. This function |
||||
is also to be used when unconfiguring pin which was used as an external interrupt |
||||
or in event mode. That is the only way to reset the corresponding bit in |
||||
EXTI & SYSCFG registers. |
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). |
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). |
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). |
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG |
||||
pins). |
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function. |
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function. |
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED |
||||
|
||||
/** @addtogroup GPIO
|
||||
* @brief GPIO HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup GPIO_Private
|
||||
* @{ |
||||
*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
|
||||
|
||||
#define GPIO_MODE ((uint32_t)0x00000003U) |
||||
#define EXTI_MODE ((uint32_t)0x10000000U) |
||||
#define GPIO_MODE_IT ((uint32_t)0x00010000U) |
||||
#define GPIO_MODE_EVT ((uint32_t)0x00020000U) |
||||
#define RISING_EDGE ((uint32_t)0x00100000U) |
||||
#define FALLING_EDGE ((uint32_t)0x00200000U) |
||||
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U) |
||||
|
||||
#define GPIO_NUMBER ((uint32_t)16U) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
||||
* @brief Initialization and de-initialization functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Initialization and de-initialization functions ##### |
||||
=============================================================================== |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. |
||||
* @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices. |
||||
* Note that GPIOE is not available on all devices. |
||||
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains |
||||
* the configuration information for the specified GPIO peripheral. |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) |
||||
{ |
||||
uint32_t position = 0x00U; |
||||
uint32_t iocurrent = 0x00U; |
||||
uint32_t temp = 0x00U; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); |
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); |
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,(GPIO_Init->Pin))); |
||||
|
||||
/* Configure the port pins */ |
||||
while (((GPIO_Init->Pin) >> position) != 0) |
||||
{ |
||||
/* Get the IO position */ |
||||
iocurrent = (GPIO_Init->Pin) & (1U << position); |
||||
|
||||
if(iocurrent) |
||||
{ |
||||
/*--------------------- GPIO Mode Configuration ------------------------*/ |
||||
/* In case of Alternate function mode selection */ |
||||
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{ |
||||
/* Check if the Alternate function is compliant with the GPIO in use */ |
||||
assert_param(IS_GPIO_AF_AVAILABLE(GPIOx,(GPIO_Init->Alternate))); |
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3U]; |
||||
temp &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ; |
||||
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U)) ; |
||||
GPIOx->AFR[position >> 3U] = temp; |
||||
}
|
||||
|
||||
/* In case of Output or Alternate function mode selection */ |
||||
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || |
||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) |
||||
{ |
||||
/* Check the Speed parameter */ |
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); |
||||
/* Configure the IO Speed */ |
||||
temp = GPIOx->OSPEEDR; |
||||
temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U)); |
||||
temp |= (GPIO_Init->Speed << (position * 2U)); |
||||
GPIOx->OSPEEDR = temp; |
||||
|
||||
/* Configure the IO Output Type */ |
||||
temp= GPIOx->OTYPER; |
||||
temp &= ~(GPIO_OTYPER_OT_0 << position) ; |
||||
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); |
||||
GPIOx->OTYPER = temp; |
||||
} |
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */ |
||||
temp = GPIOx->MODER; |
||||
temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); |
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); |
||||
GPIOx->MODER = temp; |
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */ |
||||
temp = GPIOx->PUPDR; |
||||
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); |
||||
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
||||
GPIOx->PUPDR = temp; |
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/ |
||||
/* Configure the External Interrupt or event for the current IO */ |
||||
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||
{ |
||||
/* Enable SYSCFG Clock */ |
||||
__HAL_RCC_SYSCFG_CLK_ENABLE(); |
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2U]; |
||||
CLEAR_BIT(temp, ((uint32_t)0x0FU) << (4U * (position & 0x03U))); |
||||
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U))); |
||||
SYSCFG->EXTICR[position >> 2U] = temp; |
||||
|
||||
/* Clear EXTI line configuration */ |
||||
temp = EXTI->IMR; |
||||
temp &= ~((uint32_t)iocurrent); |
||||
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) |
||||
{ |
||||
temp |= iocurrent; |
||||
} |
||||
EXTI->IMR = temp; |
||||
|
||||
temp = EXTI->EMR; |
||||
temp &= ~((uint32_t)iocurrent); |
||||
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) |
||||
{ |
||||
temp |= iocurrent; |
||||
} |
||||
EXTI->EMR = temp; |
||||
|
||||
/* Clear Rising Falling edge configuration */ |
||||
temp = EXTI->RTSR; |
||||
temp &= ~((uint32_t)iocurrent); |
||||
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) |
||||
{ |
||||
temp |= iocurrent; |
||||
} |
||||
EXTI->RTSR = temp; |
||||
|
||||
temp = EXTI->FTSR; |
||||
temp &= ~((uint32_t)iocurrent); |
||||
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) |
||||
{ |
||||
temp |= iocurrent; |
||||
} |
||||
EXTI->FTSR = temp; |
||||
} |
||||
} |
||||
position++; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values. |
||||
* @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices. |
||||
* Note that GPIOE is not available on all devices. |
||||
* @param GPIO_Pin: specifies the port bit to be written. |
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15). |
||||
* All port bits are not necessarily available on all GPIOs. |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) |
||||
{
|
||||
uint32_t position = 0x00U; |
||||
uint32_t iocurrent = 0x00U; |
||||
uint32_t tmp = 0x00U; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); |
||||
|
||||
/* Configure the port pins */ |
||||
while ((GPIO_Pin >> position) != 0) |
||||
{ |
||||
/* Get the IO position */ |
||||
iocurrent = (GPIO_Pin) & (1U << position); |
||||
|
||||
if(iocurrent) |
||||
{ |
||||
/*------------------------- GPIO Mode Configuration --------------------*/ |
||||
/* Configure IO Direction in Input Floting Mode */ |
||||
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); |
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3U] &= ~((uint32_t)0xFU << ((uint32_t)(position & (uint32_t)0x07U) * 4U)) ; |
||||
|
||||
/* Configure the default value for IO Speed */ |
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U)); |
||||
|
||||
/* Configure the default value IO Output Type */ |
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; |
||||
|
||||
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */ |
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); |
||||
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/ |
||||
/* Clear the External Interrupt or Event for the current IO */ |
||||
|
||||
tmp = SYSCFG->EXTICR[position >> 2U]; |
||||
tmp &= (((uint32_t)0x0FU) << (4U * (position & 0x03U))); |
||||
if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) |
||||
{ |
||||
tmp = ((uint32_t)0x0FU) << (4U * (position & 0x03U)); |
||||
SYSCFG->EXTICR[position >> 2U] &= ~tmp; |
||||
|
||||
/* Clear EXTI line configuration */ |
||||
EXTI->IMR &= ~((uint32_t)iocurrent); |
||||
EXTI->EMR &= ~((uint32_t)iocurrent); |
||||
|
||||
/* Clear Rising Falling edge configuration */ |
||||
EXTI->RTSR &= ~((uint32_t)iocurrent); |
||||
EXTI->FTSR &= ~((uint32_t)iocurrent); |
||||
} |
||||
} |
||||
position++; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
||||
* @brief GPIO Read and Write |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### IO operation functions ##### |
||||
=============================================================================== |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin. |
||||
* @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices. |
||||
* Note that GPIOE is not available on all devices. |
||||
* @param GPIO_Pin: specifies the port bit to read. |
||||
* This parameter can be GPIO_PIN_x where x can be (0..15). |
||||
* All port bits are not necessarily available on all GPIOs. |
||||
* @retval The input port pin value. |
||||
*/ |
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
||||
{ |
||||
GPIO_PinState bitstatus; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); |
||||
|
||||
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) |
||||
{ |
||||
bitstatus = GPIO_PIN_SET; |
||||
} |
||||
else |
||||
{ |
||||
bitstatus = GPIO_PIN_RESET; |
||||
} |
||||
return bitstatus; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit. |
||||
*
|
||||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between |
||||
* the read and the modify access. |
||||
*
|
||||
* @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices. |
||||
* Note that GPIOE is not available on all devices. |
||||
* @param GPIO_Pin: specifies the port bit to be written. |
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15). |
||||
* All port bits are not necessarily available on all GPIOs. |
||||
* @param PinState: specifies the value to be written to the selected bit. |
||||
* This parameter can be one of the GPIO_PinState enum values: |
||||
* GPIO_PIN_RESET: to clear the port pin |
||||
* GPIO_PIN_SET: to set the port pin |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); |
||||
assert_param(IS_GPIO_PIN_ACTION(PinState)); |
||||
|
||||
if(PinState != GPIO_PIN_RESET) |
||||
{ |
||||
GPIOx->BSRR = GPIO_Pin; |
||||
} |
||||
else |
||||
{ |
||||
GPIOx->BRR = GPIO_Pin ; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins. |
||||
* @param GPIOx: Where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices. |
||||
* Note that GPIOE is not available on all devices. |
||||
* All port bits are not necessarily available on all GPIOs. |
||||
* @param GPIO_Pin: Specifies the pins to be toggled. |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); |
||||
|
||||
GPIOx->ODR ^= GPIO_Pin; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers. |
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, |
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. |
||||
* @note The configuration of the locked GPIO pins can no longer be modified |
||||
* until the next reset. |
||||
* @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family. |
||||
* Note that GPIOE is not available on all devices. |
||||
* @param GPIO_Pin: specifies the port bit to be locked. |
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). |
||||
* All port bits are not necessarily available on all GPIOs. |
||||
* @retval None |
||||
*/ |
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
||||
{ |
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); |
||||
|
||||
/* Apply lock key write sequence */ |
||||
tmp |= GPIO_Pin; |
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
||||
GPIOx->LCKR = tmp; |
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ |
||||
GPIOx->LCKR = GPIO_Pin; |
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ |
||||
GPIOx->LCKR = tmp; |
||||
/* Read LCKK bit*/ |
||||
tmp = GPIOx->LCKR; |
||||
|
||||
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) |
||||
{ |
||||
return HAL_OK; |
||||
} |
||||
else |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
} |
||||
/**
|
||||
* @brief This function handles EXTI interrupt request. |
||||
* @param GPIO_Pin: Specifies the pins connected to the EXTI line. |
||||
* @retval None |
||||
*/ |
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) |
||||
{ |
||||
/* EXTI line interrupt detected */ |
||||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); |
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief EXTI line detection callbacks. |
||||
* @param GPIO_Pin: Specifies the pins connected to the EXTI line. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) |
||||
{ |
||||
/* Prevent unused argument(s) compilation warning */ |
||||
UNUSED(GPIO_Pin); |
||||
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file |
||||
*/
|
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,351 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_i2c_ex.c |
||||
* @author MCD Application Team |
||||
* @brief I2C Extended HAL module driver. |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities of I2C Extended peripheral: |
||||
* + Extended features functions |
||||
* |
||||
@verbatim |
||||
============================================================================== |
||||
##### I2C peripheral Extended features ##### |
||||
============================================================================== |
||||
|
||||
[..] Comparing to other previous devices, the I2C interface for STM32L0xx |
||||
devices contains the following additional features |
||||
|
||||
(+) Possibility to disable or enable Analog Noise Filter |
||||
(+) Use of a configured Digital Noise Filter |
||||
(+) Disable or enable wakeup from Stop mode(s) |
||||
(+) Disable or enable Fast Mode Plus |
||||
|
||||
##### How to use this driver ##### |
||||
============================================================================== |
||||
[..] This driver provides functions to configure Noise Filter and Wake Up Feature |
||||
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() |
||||
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() |
||||
(#) Configure the enable or disable of I2C Wake Up Mode using the functions : |
||||
(++) HAL_I2CEx_EnableWakeUp() |
||||
(++) HAL_I2CEx_DisableWakeUp() |
||||
(#) Configure the enable or disable of fast mode plus driving capability using the functions : |
||||
(++) HAL_I2CEx_EnableFastModePlus() |
||||
(++) HAL_I2CEx_DisableFastModePlus() |
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup I2CEx I2CEx
|
||||
* @brief I2C Extended HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/* Private macro -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/* Private functions ---------------------------------------------------------*/ |
||||
|
||||
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Extended features functions ##### |
||||
=============================================================================== |
||||
[..] This section provides functions allowing to: |
||||
(+) Configure Noise Filters |
||||
(+) Configure Wake Up Feature |
||||
(+) Configure Fast Mode Plus |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Configure I2C Analog noise filter. |
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||||
* the configuration information for the specified I2Cx peripheral. |
||||
* @param AnalogFilter New state of the Analog filter. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
||||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); |
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY) |
||||
{ |
||||
/* Process Locked */ |
||||
__HAL_LOCK(hi2c); |
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY; |
||||
|
||||
/* Disable the selected I2C peripheral */ |
||||
__HAL_I2C_DISABLE(hi2c); |
||||
|
||||
/* Reset I2Cx ANOFF bit */ |
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); |
||||
|
||||
/* Set analog filter bit*/ |
||||
hi2c->Instance->CR1 |= AnalogFilter; |
||||
|
||||
__HAL_I2C_ENABLE(hi2c); |
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hi2c); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
else |
||||
{ |
||||
return HAL_BUSY; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Configure I2C Digital noise filter. |
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||||
* the configuration information for the specified I2Cx peripheral. |
||||
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) |
||||
{ |
||||
uint32_t tmpreg = 0U; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
||||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); |
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY) |
||||
{ |
||||
/* Process Locked */ |
||||
__HAL_LOCK(hi2c); |
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY; |
||||
|
||||
/* Disable the selected I2C peripheral */ |
||||
__HAL_I2C_DISABLE(hi2c); |
||||
|
||||
/* Get the old register value */ |
||||
tmpreg = hi2c->Instance->CR1; |
||||
|
||||
/* Reset I2Cx DNF bits [11:8] */ |
||||
tmpreg &= ~(I2C_CR1_DNF); |
||||
|
||||
/* Set I2Cx DNF coefficient */ |
||||
tmpreg |= DigitalFilter << 8U; |
||||
|
||||
/* Store the new register value */ |
||||
hi2c->Instance->CR1 = tmpreg; |
||||
|
||||
__HAL_I2C_ENABLE(hi2c); |
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hi2c); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
else |
||||
{ |
||||
return HAL_BUSY; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable I2C wakeup from Stop mode(s). |
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||||
* the configuration information for the specified I2Cx peripheral. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); |
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY) |
||||
{ |
||||
/* Process Locked */ |
||||
__HAL_LOCK(hi2c); |
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY; |
||||
|
||||
/* Disable the selected I2C peripheral */ |
||||
__HAL_I2C_DISABLE(hi2c); |
||||
|
||||
/* Enable wakeup from stop mode */ |
||||
hi2c->Instance->CR1 |= I2C_CR1_WUPEN; |
||||
|
||||
__HAL_I2C_ENABLE(hi2c); |
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hi2c); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
else |
||||
{ |
||||
return HAL_BUSY; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable I2C wakeup from Stop mode(s). |
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
||||
* the configuration information for the specified I2Cx peripheral. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); |
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY) |
||||
{ |
||||
/* Process Locked */ |
||||
__HAL_LOCK(hi2c); |
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY; |
||||
|
||||
/* Disable the selected I2C peripheral */ |
||||
__HAL_I2C_DISABLE(hi2c); |
||||
|
||||
/* Enable wakeup from stop mode */ |
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); |
||||
|
||||
__HAL_I2C_ENABLE(hi2c); |
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(hi2c); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
else |
||||
{ |
||||
return HAL_BUSY; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable the I2C fast mode plus driving capability. |
||||
* @param ConfigFastModePlus Selects the pin. |
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values |
||||
* @note For I2C1, fast mode plus driving capability can be enabled on all selected |
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently |
||||
* on each one of the following pins PB6, PB7, PB8 and PB9. |
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability |
||||
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. |
||||
* @note For all I2C2 pins fast mode plus driving capability can be enabled |
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter. |
||||
* @note For all I2C3 pins fast mode plus driving capability can be enabled |
||||
* only by using I2C_FASTMODEPLUS_I2C3 parameter. |
||||
* @retval None |
||||
*/ |
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) |
||||
{ |
||||
/* Check the parameter */ |
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); |
||||
|
||||
/* Enable SYSCFG clock */ |
||||
__HAL_RCC_SYSCFG_CLK_ENABLE(); |
||||
|
||||
/* Enable fast mode plus driving capability for selected pin */ |
||||
SET_BIT(SYSCFG->CFGR2, (uint32_t)ConfigFastModePlus); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable the I2C fast mode plus driving capability. |
||||
* @param ConfigFastModePlus Selects the pin. |
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values |
||||
* @note For I2C1, fast mode plus driving capability can be disabled on all selected |
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently |
||||
* on each one of the following pins PB6, PB7, PB8 and PB9. |
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability |
||||
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. |
||||
* @note For all I2C2 pins fast mode plus driving capability can be disabled |
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter. |
||||
* @note For all I2C3 pins fast mode plus driving capability can be disabled |
||||
* only by using I2C_FASTMODEPLUS_I2C3 parameter. |
||||
* @retval None |
||||
*/ |
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) |
||||
{ |
||||
/* Check the parameter */ |
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); |
||||
|
||||
/* Enable SYSCFG clock */ |
||||
__HAL_RCC_SYSCFG_CLK_ENABLE(); |
||||
|
||||
/* Disable fast mode plus driving capability for selected pin */ |
||||
CLEAR_BIT(SYSCFG->CFGR2, (uint32_t)ConfigFastModePlus); |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,708 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_pwr.c |
||||
* @author MCD Application Team |
||||
* @brief PWR HAL module driver. |
||||
* |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities of the Power Controller (PWR) peripheral: |
||||
* + Initialization/de-initialization functions |
||||
* + Peripheral Control functions
|
||||
* |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED |
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup PWR
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup PWR_Private
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
||||
* @{ |
||||
*/
|
||||
#define PVD_MODE_IT ((uint32_t)0x00010000U) |
||||
#define PVD_MODE_EVT ((uint32_t)0x00020000U) |
||||
#define PVD_RISING_EDGE ((uint32_t)0x00000001U) |
||||
#define PVD_FALLING_EDGE ((uint32_t)0x00000002U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1
|
||||
* @brief Initialization and de-initialization functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Initialization and de-initialization functions ##### |
||||
=============================================================================== |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Deinitializes the HAL PWR peripheral registers to their default reset values. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DeInit(void) |
||||
{ |
||||
__HAL_RCC_PWR_FORCE_RESET(); |
||||
__HAL_RCC_PWR_RELEASE_RESET(); |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2
|
||||
* @brief Low Power modes configuration functions |
||||
* |
||||
@verbatim |
||||
|
||||
=============================================================================== |
||||
##### Peripheral Control functions ##### |
||||
=============================================================================== |
||||
|
||||
*** Backup domain *** |
||||
========================= |
||||
[..] |
||||
After reset, the backup domain (RTC registers, RTC backup data |
||||
registers) is protected against possible unwanted |
||||
write accesses. |
||||
To enable access to the RTC Domain and RTC registers, proceed as follows: |
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the |
||||
__HAL_RCC_PWR_CLK_ENABLE() macro. |
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
||||
|
||||
*** PVD configuration *** |
||||
========================= |
||||
[..] |
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a |
||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). |
||||
(+) The PVD can use an external input analog voltage (PVD_IN) which is compared
|
||||
internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
|
||||
when PWR_PVDLevel_7 is selected (PLS[2:0] = 111). |
||||
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower |
||||
than the PVD threshold. This event is internally connected to the EXTI |
||||
line16 and can generate an interrupt if enabled. This is done through |
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT() macro. |
||||
(+) The PVD is stopped in Standby mode. |
||||
|
||||
*** WakeUp pin configuration *** |
||||
================================ |
||||
[..] |
||||
(+) WakeUp pin is used to wake up the system from Standby mode. This pin is |
||||
forced in input pull-down configuration and is active on rising edges. |
||||
(+) There are two WakeUp pins: |
||||
WakeUp Pin 1 on PA.00. |
||||
WakeUp Pin 2 on PC.13. |
||||
WakeUp Pin 3 on PE.06 . |
||||
|
||||
|
||||
[..] |
||||
*** Main and Backup Regulators configuration *** |
||||
================================================ |
||||
|
||||
(+) The main internal regulator can be configured to have a tradeoff between |
||||
performance and power consumption when the device does not operate at |
||||
the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG() |
||||
macro which configures the two VOS bits in PWR_CR register: |
||||
(++) PWR_REGULATOR_VOLTAGE_SCALE1 (VOS bits = 01), the regulator voltage output Scale 1 mode selected and |
||||
the System frequency can go up to 32 MHz. |
||||
(++) PWR_REGULATOR_VOLTAGE_SCALE2 (VOS bits = 10), the regulator voltage output Scale 2 mode selected and |
||||
the System frequency can go up to 16 MHz. |
||||
(++) PWR_REGULATOR_VOLTAGE_SCALE3 (VOS bits = 11), the regulator voltage output Scale 3 mode selected and |
||||
the System frequency can go up to 4.2 MHz. |
||||
|
||||
Refer to the datasheets for more details. |
||||
|
||||
*** Low Power modes configuration *** |
||||
===================================== |
||||
[..] |
||||
The device features 5 low-power modes: |
||||
(+) Low power run mode: regulator in low power mode, limited clock frequency,
|
||||
limited number of peripherals running. |
||||
(+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running. |
||||
(+) Low power sleep mode: Cortex-M0+ core stopped, limited clock frequency,
|
||||
limited number of peripherals running, regulator in low power mode. |
||||
(+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode. |
||||
(+) Standby mode: VCORE domain powered off |
||||
|
||||
*** Low power run mode *** |
||||
========================= |
||||
[..] |
||||
To further reduce the consumption when the system is in Run mode, the regulator can be |
||||
configured in low power mode. In this mode, the system frequency should not exceed |
||||
MSI frequency range1. |
||||
In Low power run mode, all I/O pins keep the same state as in Run mode. |
||||
|
||||
(+) Entry: |
||||
(++) VCORE in range2 |
||||
(++) Decrease the system frequency not to exceed the frequency of MSI frequency range1. |
||||
(++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode() |
||||
function. |
||||
(+) Exit: |
||||
(++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode() |
||||
function. |
||||
(++) Increase the system frequency if needed. |
||||
|
||||
*** Sleep mode *** |
||||
================== |
||||
[..] |
||||
(+) Entry: |
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
||||
functions with |
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
||||
|
||||
(+) Exit: |
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt |
||||
controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction was used to enter sleep mode, |
||||
the MCU exits Sleep mode as soon as an event occurs.
|
||||
|
||||
*** Low power sleep mode *** |
||||
============================ |
||||
[..] |
||||
(+) Entry: |
||||
The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
||||
functions with |
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
||||
(+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register.
|
||||
This reduces power consumption but increases the wake-up time. |
||||
|
||||
(+) Exit: |
||||
(++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt |
||||
acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device |
||||
from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode, |
||||
the MCU exits Sleep mode as soon as an event occurs.
|
||||
|
||||
*** Stop mode *** |
||||
================= |
||||
[..] |
||||
The Stop mode is based on the Cortex-M0+ deepsleep mode combined with peripheral |
||||
clock gating. The voltage regulator can be configured either in normal or low-power mode. |
||||
In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and |
||||
the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. |
||||
To get the lowest consumption in Stop mode, the internal Flash memory also enters low |
||||
power mode. When the Flash memory is in power-down mode, an additional startup delay is |
||||
incurred when waking up from Stop mode. |
||||
To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature |
||||
sensor can be switched off before entering Stop mode. They can be switched on again by |
||||
software after exiting Stop mode using the ULP bit in the PWR_CR register. |
||||
In Stop mode, all I/O pins keep the same state as in Run mode. |
||||
|
||||
(+) Entry: |
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode |
||||
function with: |
||||
(++) Main regulator ON. |
||||
(++) Low Power regulator ON. |
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
||||
(+) Exit: |
||||
(++) By issuing an interrupt or a wakeup event, the MSI or HSI16 RC |
||||
oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR |
||||
register |
||||
|
||||
*** Standby mode *** |
||||
==================== |
||||
[..] |
||||
The Standby mode allows to achieve the lowest power consumption. It is based on the |
||||
Cortex-M0+ deepsleep mode, with the voltage regulator disabled. The VCORE domain is |
||||
consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are |
||||
also switched off. SRAM and register contents are lost except for the RTC registers, RTC |
||||
backup registers and Standby circuitry. |
||||
|
||||
To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature |
||||
sensor can be switched off before entering the Standby mode. They can be switched
|
||||
on again by software after exiting the Standby mode. |
||||
function. |
||||
|
||||
(+) Entry: |
||||
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. |
||||
(+) Exit: |
||||
(++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, |
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset. |
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode *** |
||||
============================================= |
||||
[..] |
||||
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||||
without depending on an external interrupt (Auto-wakeup mode). |
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop mode |
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: |
||||
(+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function. |
||||
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function |
||||
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
||||
and RTC_AlarmCmd() functions. |
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to: |
||||
(+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function. |
||||
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
||||
function. |
||||
(+++) Configure the RTC to detect the tamper or time stamp event using the |
||||
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() |
||||
functions. |
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: |
||||
(+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function. |
||||
(+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function. |
||||
(+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
|
||||
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. |
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Standby mode |
||||
(++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: |
||||
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function. |
||||
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
||||
and RTC_AlarmCmd() functions. |
||||
(++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to: |
||||
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
||||
function. |
||||
(+++) Configure the RTC to detect the tamper or time stamp event using the |
||||
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() |
||||
functions. |
||||
(++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: |
||||
(+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function |
||||
(+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
|
||||
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. |
||||
|
||||
(+) Comparator auto-wakeup (AWU) from the Stop mode |
||||
(++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup |
||||
event, it is necessary to: |
||||
(+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
|
||||
to be sensitive to to the selected edges (falling, rising or falling
|
||||
and rising) (Interrupt or Event modes) using the EXTI_Init() function. |
||||
(+++) Configure the comparator to generate the event.
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Enables access to the backup domain (RTC registers, RTC |
||||
* backup data registers ). |
||||
* @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the |
||||
* Backup Domain Access should be kept enabled. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnableBkUpAccess(void) |
||||
{ |
||||
/* Enable access to RTC and backup registers */ |
||||
SET_BIT(PWR->CR, PWR_CR_DBP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables access to the backup domain
|
||||
* @note Applies to RTC registers, RTC backup data registers. |
||||
* @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the |
||||
* Backup Domain Access should be kept enabled. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DisableBkUpAccess(void) |
||||
{ |
||||
/* Disable access to RTC and backup registers */ |
||||
CLEAR_BIT(PWR->CR, PWR_CR_DBP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). |
||||
* @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration |
||||
* information for the PVD. |
||||
* @note Refer to the electrical characteristics of your device datasheet for |
||||
* more details about the voltage threshold corresponding to each |
||||
* detection level. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); |
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); |
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */ |
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); |
||||
|
||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */ |
||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT(); |
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT(); |
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); |
||||
|
||||
/* Configure interrupt mode */ |
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) |
||||
{ |
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT(); |
||||
} |
||||
|
||||
/* Configure event mode */ |
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) |
||||
{ |
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT(); |
||||
} |
||||
|
||||
/* Configure the edge */ |
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) |
||||
{ |
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); |
||||
} |
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) |
||||
{ |
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD). |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnablePVD(void) |
||||
{ |
||||
/* Enable the power voltage detector */ |
||||
SET_BIT(PWR->CR, PWR_CR_PVDE); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD). |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DisablePVD(void) |
||||
{ |
||||
/* Disable the power voltage detector */ |
||||
CLEAR_BIT(PWR->CR, PWR_CR_PVDE); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables the WakeUp PINx functionality. |
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_WAKEUP_PIN1 |
||||
* @arg PWR_WAKEUP_PIN2 |
||||
* @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) |
||||
{ |
||||
/* Check the parameter */ |
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
||||
/* Enable the EWUPx pin */ |
||||
SET_BIT(PWR->CSR, WakeUpPinx); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables the WakeUp PINx functionality. |
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_WAKEUP_PIN1 |
||||
* @arg PWR_WAKEUP_PIN2
|
||||
* @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) |
||||
{ |
||||
/* Check the parameter */ |
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
||||
/* Disable the EWUPx pin */ |
||||
CLEAR_BIT(PWR->CSR, WakeUpPinx); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode. |
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode. |
||||
* @param Regulator: Specifies the regulator state in SLEEP mode. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON |
||||
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON |
||||
* @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. |
||||
* When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||||
* the interrupt wake up source. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) |
||||
{ |
||||
uint32_t tmpreg = 0U; |
||||
/* Check the parameters */ |
||||
assert_param(IS_PWR_REGULATOR(Regulator)); |
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); |
||||
|
||||
/* Select the regulator state in Sleep mode ---------------------------------*/ |
||||
tmpreg = PWR->CR; |
||||
|
||||
/* Clear PDDS and LPDS bits */ |
||||
CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR)); |
||||
|
||||
/* Set LPSDSR bit according to PWR_Regulator value */ |
||||
SET_BIT(tmpreg, Regulator); |
||||
|
||||
/* Store the new value */ |
||||
PWR->CR = tmpreg; |
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */ |
||||
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); |
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/ |
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI) |
||||
{ |
||||
/* Request Wait For Interrupt */ |
||||
__WFI(); |
||||
} |
||||
else |
||||
{ |
||||
/* Request Wait For Event */ |
||||
__SEV(); |
||||
__WFE(); |
||||
__WFE(); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enters Stop mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode. |
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event, |
||||
* MSI or HSI16 RCoscillator is selected as system clock depending
|
||||
* the bit STOPWUCK in the RCC_CFGR register. |
||||
* @note When the voltage regulator operates in low power mode, an additional |
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption |
||||
* is higher although the startup time is reduced. |
||||
* @note Before entering in this function, it is important to ensure that the WUF |
||||
* wakeup flag is cleared. To perform this action, it is possible to call the |
||||
* following macro : __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU) |
||||
* |
||||
* @param Regulator: Specifies the regulator state in Stop mode. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON |
||||
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON |
||||
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. |
||||
* This parameter can be one of the following values: |
||||
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction |
||||
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
|
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
||||
{ |
||||
uint32_t tmpreg = 0U; |
||||
|
||||
/* Check the parameters */ |
||||
assert_param(IS_PWR_REGULATOR(Regulator)); |
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
||||
|
||||
/* Select the regulator state in Stop mode ---------------------------------*/ |
||||
tmpreg = PWR->CR; |
||||
|
||||
/* Clear PDDS and LPDS bits */ |
||||
CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR)); |
||||
|
||||
/* Set LPSDSR bit according to PWR_Regulator value */ |
||||
SET_BIT(tmpreg, Regulator); |
||||
|
||||
/* Store the new value */ |
||||
PWR->CR = tmpreg; |
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */ |
||||
SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); |
||||
|
||||
/* Select Stop mode entry --------------------------------------------------*/ |
||||
if(STOPEntry == PWR_STOPENTRY_WFI) |
||||
{ |
||||
/* Request Wait For Interrupt */ |
||||
__WFI(); |
||||
} |
||||
else |
||||
{ |
||||
/* Request Wait For Event */ |
||||
__SEV(); |
||||
__WFE(); |
||||
__WFE(); |
||||
} |
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */ |
||||
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); |
||||
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Enters Standby mode. |
||||
* @note In Standby mode, all I/O pins are high impedance except for: |
||||
* - Reset pad (still available)
|
||||
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC |
||||
* Alarm out, or RTC clock calibration out. |
||||
* - RTC_AF2 pin (PC13) if configured for tamper. |
||||
* - WKUP pin 1 (PA00) if enabled. |
||||
* - WKUP pin 2 (PC13) if enabled. |
||||
* - WKUP pin 3 (PE06) if enabled, for stm32l07xxx and stm32l08xxx devices only. |
||||
* - WKUP pin 3 (PA02) if enabled, for stm32l031xx devices only. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnterSTANDBYMode(void) |
||||
{ |
||||
/* Select Standby mode */ |
||||
SET_BIT(PWR->CR, PWR_CR_PDDS); |
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */ |
||||
SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); |
||||
|
||||
/* This option is used to ensure that store operations are completed */ |
||||
#if defined ( __CC_ARM) |
||||
__force_stores(); |
||||
#endif |
||||
/* Request Wait For Interrupt */ |
||||
__WFI(); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over. |
||||
* Setting this bit is useful when the processor is expected to run only on |
||||
* interruptions handling.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnableSleepOnExit(void) |
||||
{ |
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */ |
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DisableSleepOnExit(void) |
||||
{ |
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Enables CORTEX M0+ SEVONPEND bit.
|
||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_EnableSEVOnPend(void) |
||||
{ |
||||
/* Set SEVONPEND bit of Cortex System Control Register */ |
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Disables CORTEX M0+ SEVONPEND bit.
|
||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_DisableSEVOnPend(void) |
||||
{ |
||||
/* Clear SEVONPEND bit of Cortex System Control Register */ |
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request. |
||||
* @note This API should be called under the PVD_IRQHandler(). |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWR_PVD_IRQHandler(void) |
||||
{ |
||||
/* Check PWR exti flag */ |
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) |
||||
{ |
||||
/* PWR PVD interrupt user callback */ |
||||
HAL_PWR_PVDCallback(); |
||||
|
||||
/* Clear PWR Exti pending bit */ |
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG(); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_PWR_PVDCallback(void) |
||||
{ |
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file |
||||
*/
|
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,200 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_pwr_ex.c |
||||
* @author MCD Application Team |
||||
* @brief Extended PWR HAL module driver. |
||||
* This file provides firmware functions to manage the following |
||||
* functionalities of the Power Controller (PWR) peripheral: |
||||
* + Extended Initialization and de-initialization functions |
||||
* + Extended Peripheral Control functions |
||||
*
|
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED |
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup PWREx
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup PWREx_Private
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup PWR_Extended_TimeOut_Value PWREx Flag Setting Time Out Value
|
||||
* @{ |
||||
*/
|
||||
#define PWR_FLAG_SETTING_DELAY_US 50U |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions
|
||||
* @brief Low Power modes configuration functions
|
||||
* |
||||
@verbatim |
||||
|
||||
=============================================================================== |
||||
##### Peripheral extended features functions ##### |
||||
=============================================================================== |
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Return Voltage Scaling Range.
|
||||
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3) |
||||
*/
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void) |
||||
{ |
||||
return (PWR->CR & PWR_CR_VOS); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Enables the Fast WakeUp from Ultra Low Power mode. |
||||
* @note This bit works in conjunction with ULP bit.
|
||||
* Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when
|
||||
* exiting from low power mode. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWREx_EnableFastWakeUp(void) |
||||
{ |
||||
/* Enable the fast wake up */ |
||||
SET_BIT(PWR->CR, PWR_CR_FWU); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables the Fast WakeUp from Ultra Low Power mode. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWREx_DisableFastWakeUp(void) |
||||
{ |
||||
/* Disable the fast wake up */ |
||||
CLEAR_BIT(PWR->CR, PWR_CR_FWU); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enables the Ultra Low Power mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWREx_EnableUltraLowPower(void) |
||||
{ |
||||
/* Enable the Ultra Low Power mode */ |
||||
SET_BIT(PWR->CR, PWR_CR_ULP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disables the Ultra Low Power mode |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWREx_DisableUltraLowPower(void) |
||||
{ |
||||
/* Disable the Ultra Low Power mode */ |
||||
CLEAR_BIT(PWR->CR, PWR_CR_ULP); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable the Low Power Run mode. |
||||
* @note Low power run mode can only be entered when VCORE is in range 2. |
||||
* In addition, the dynamic voltage scaling must not be used when Low |
||||
* power run mode is selected. Only Stop and Sleep modes with regulator |
||||
* configured in Low power mode is allowed when Low power run mode is
|
||||
* selected. |
||||
* @note The frequency of the system clock must be decreased to not exceed the |
||||
* frequency of RCC_MSIRANGE_1. |
||||
* @note In Low power run mode, all I/O pins keep the same state as in Run mode. |
||||
* @retval None |
||||
*/ |
||||
void HAL_PWREx_EnableLowPowerRunMode(void) |
||||
{ |
||||
/* Enters the Low Power Run mode */ |
||||
SET_BIT(PWR->CR, PWR_CR_LPSDSR); |
||||
SET_BIT(PWR->CR, PWR_CR_LPRUN); |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable the Low Power Run mode. |
||||
* @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
|
||||
* REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
|
||||
* returns HAL_TIMEOUT status). The system clock frequency can then be |
||||
* increased above 2 MHz.
|
||||
* @retval HAL_StatusTypeDef |
||||
*/ |
||||
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) |
||||
{ |
||||
uint32_t wait_loop_index = 0U; |
||||
|
||||
/* Exit the Low Power Run mode */ |
||||
CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); |
||||
CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); |
||||
|
||||
/* Wait until REGLPF is reset */ |
||||
wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U)); |
||||
|
||||
while ((wait_loop_index != 0U) && (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF))) |
||||
{ |
||||
wait_loop_index--; |
||||
} |
||||
|
||||
if (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF)) |
||||
{ |
||||
return HAL_TIMEOUT; |
||||
} |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* HAL_PWR_MODULE_ENABLED */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,464 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_tim_ex.c |
||||
* @author MCD Application Team |
||||
* @brief TIM HAL module driver. |
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Timer (TIM) peripheral: |
||||
* + Time Hall Sensor Interface Initialization |
||||
* + Time Hall Sensor Interface Start |
||||
* + Time Master and Slave synchronization configuration |
||||
@verbatim
|
||||
================================================================================ |
||||
##### TIM specific features integration ##### |
||||
================================================================================ |
||||
|
||||
[..] The Timer features include:
|
||||
(#) 16-bit up, down, up/down auto-reload counter. |
||||
(#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock |
||||
frequency either by any factor between 1 and 65536. |
||||
(#) Up to 4 independent channels for: |
||||
Input Capture |
||||
Output Compare |
||||
PWM generation (Edge and Center-aligned Mode) |
||||
One-pulse mode output |
||||
(#) Synchronization circuit to control the timer with external signals and to interconnect |
||||
several timers together. |
||||
(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning |
||||
purposes
|
||||
|
||||
##### How to use this driver ##### |
||||
================================================================================ |
||||
[..] |
||||
(#) Enable the TIM interface clock using
|
||||
__HAL_RCC_TIMx_CLK_ENABLE();
|
||||
|
||||
(#) TIM pins configuration |
||||
(++) Enable the clock for the TIM GPIOs using the following function: |
||||
__HAL_RCC_GPIOx_CLK_ENABLE();
|
||||
(++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
|
||||
|
||||
(#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx),
|
||||
using the following function: |
||||
HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. |
||||
|
||||
(#) Configure the TIM in the desired operating mode using one of the
|
||||
configuration function of this driver: |
||||
(++) HAL_TIMEx_MasterConfigSynchronization() to configure the peripheral in master mode. |
||||
|
||||
(#) Remap the Timer I/O using HAL_TIMEx_RemapConfig() API. |
||||
|
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup TIMEx
|
||||
* @brief TIMEx HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED |
||||
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group1
|
||||
* @brief Peripheral Control functions |
||||
* |
||||
@verbatim
|
||||
=============================================================================== |
||||
##### Peripheral Control functions ##### |
||||
===============================================================================
|
||||
[..] This section provides functions allowing to: |
||||
(+) Configure Master and the Slave synchronization. |
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Configures the TIM in master mode. |
||||
* @param htim: TIM handle.
|
||||
* @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that |
||||
* contains the selected trigger output (TRGO) and the Master/Slave
|
||||
* mode.
|
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig) |
||||
{ |
||||
/* Check the parameters */ |
||||
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); |
||||
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); |
||||
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); |
||||
|
||||
__HAL_LOCK(htim); |
||||
|
||||
/* Change the handler state */ |
||||
htim->State = HAL_TIM_STATE_BUSY; |
||||
|
||||
/* Reset the MMS Bits */ |
||||
htim->Instance->CR2 &= ~TIM_CR2_MMS; |
||||
/* Select the TRGO source */ |
||||
htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; |
||||
|
||||
/* Reset the MSM Bit */ |
||||
htim->Instance->SMCR &= ~TIM_SMCR_MSM; |
||||
/* Set or Reset the MSM Bit */ |
||||
htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; |
||||
|
||||
htim->State = HAL_TIM_STATE_READY; |
||||
|
||||
__HAL_UNLOCK(htim); |
||||
|
||||
return HAL_OK; |
||||
}
|
||||
|
||||
|
||||
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ |
||||
|| defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
|
||||
/**
|
||||
* @brief Configures the remapping of the TIM2, TIM3, TIM21 and TIM22 inputs. |
||||
* The channel inputs (T1..T4) and the Trigger input (ETR) of the |
||||
* timers can be remaped thanks to this function. When an input is |
||||
* mapped, on a GPIO, refer yourself to the GPIO alternate functions |
||||
* for more details. |
||||
* @note It is not possible to connect TIM2 and TIM21 on |
||||
* GPIOB5_AF4 at the same time. |
||||
* When selecting TIM3_TI2_GPIOB5_AF4, Channel2 of TIM3 will be |
||||
* connected to GPIOB5_AF4 and Channel2 of TIM22 will be connected to |
||||
* some other GPIOs. (refer to alternate functions for more details) |
||||
* When selecting TIM3_TI2_GPIO_DEF, Channel2 of Timer 3 will be |
||||
* connected an GPIO (other than GPIOB5_AF4) and Channel2 of TIM22 |
||||
* will be connected to GPIOB5_AF4. |
||||
* |
||||
* @param htim: pointer to a TIM_HandleTypeDef structure that contains |
||||
* the configuration information for TIM module. |
||||
* @param Remap: specifies the TIM input remapping source. |
||||
* This parameter is a combination of the following values |
||||
* depending on TIM instance: |
||||
* |
||||
* For TIM2, the parameter can have the following values: |
||||
* @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): |
||||
* GPIOA(0)_AF5 or GPIOA(5)_AF2 or |
||||
* GPIOA(15)_AF2 or GPIOE(9)_AF2 |
||||
* @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48 |
||||
* @arg TIM2_ETR_HSI16: TIM2 ETR connected to HSI16 |
||||
* @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE |
||||
* @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output |
||||
* @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output |
||||
* @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO1(default): |
||||
* GPIOA(3)_AF2 or GPIOB(11)_AF2 or |
||||
* GPIOE(12)_AF0 |
||||
* @arg TIM2_TI4_COMP1: TIM2 TI4 connected to COMP1 |
||||
* @arg TIM2_TI4_COMP2: TIM2 TI4 connected to COMP2 |
||||
* |
||||
* For TIM3, the parameter can have the following values: |
||||
* @arg TIM3_ETR_GPIO: TIM3 ETR connected to GPIO (default): |
||||
* GPIOE(2)_AF2 or GPIOD(2)_AF2 or |
||||
* GPIOE(2)AF2 |
||||
* @arg TIM3_ETR_HSI: TIM3 ETR connected to HSI |
||||
* @arg TIM3_TI1_USB_SOF: TIM3 TI1 connected to USB_SOF (default) |
||||
* @arg TIM3_TI1_GPIO: TIM3 TI1 connected to GPIO : |
||||
* GPIOE(3)_AF2 or GPIOA(6)_AF2 or |
||||
* GPIOC(6)_AF2 or GPIOB(4)_AF2 |
||||
* @arg TIM3_TI2_GPIOB5_AF4:TIM3 TI3 connected to GPIOB(5)_AF4 |
||||
* (refer to note) |
||||
* @arg TIM3_TI2_GPIO_DEF: TIM3 TI3 connected to GPIO (default): |
||||
* GPIO_A(7)_AF2 or GPIO_B(5)_AF4 or |
||||
* GPIOC(7)_AF2 or GPIOE(7)_AF2 |
||||
* @arg TIM3_TI4_GPIO_DEF: TIM3 TI4 connected to GPIO: |
||||
* GPIO_B(1)_AF2 or GPIO_E(6)_AF2 |
||||
* @arg TIM3_TI4_GPIOC9_AF2:TIM3 TI4 connected to GPIOC(9)_AF2 |
||||
* |
||||
* For TIM21, the parameter can have the following values: |
||||
* @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : |
||||
* APB2_PC(9)_AF0 or APB2_PA(1)_AF5 |
||||
* @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output |
||||
* @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output |
||||
* @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE |
||||
* @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO |
||||
* @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt |
||||
* @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC |
||||
* @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock |
||||
* @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE |
||||
* @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI |
||||
* @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT |
||||
* @arg TIM21_TI1_GPIO: TIM21 TI1 connected to GPIO(default): |
||||
* GPIOA(2)_AF0 or GPIOB(13)_AF6 or |
||||
* GPIOE(5)_AF0 or GPIOD(0)_AF0 |
||||
* @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): |
||||
* GPIOA(3)_AF0 or GPIOB(14)_AF6 or |
||||
* GPIOE(6)_AF0 or GPIOD(7)_AF1 |
||||
* @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output |
||||
* |
||||
* For TIM22, the parameter can have the following values: |
||||
* @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE |
||||
* @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output |
||||
* @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output |
||||
* @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default): |
||||
* GPIOC(8)_AF0 or GPIOA(4)_AF5 |
||||
* @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default): |
||||
* GPIOC(6)_AF0 or GPIOA(6)_AF5 or |
||||
* GPIOB(4)_AF4 or GPIOE(0)_AF3 |
||||
* @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output |
||||
* @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output |
||||
* @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO: |
||||
* GPIOC(6)_AF0 or GPIOA(6)_AF5 or |
||||
* GPIOB(4)_AF4 or GPIOE(3)_AF0 |
||||
* |
||||
* @retval HAL status |
||||
*/ |
||||
#elif defined (STM32L031xx) || defined (STM32L041xx) |
||||
/**
|
||||
* @brief Configures the remapping of the TIM2, TIM21 and TIM22 inputs. |
||||
* The channel inputs (T1..T4) and the Trigger input (ETR) of the |
||||
* timers can be remaped thanks to this function. When an input is |
||||
* mapped, on a GPIO, refer yourself to the GPIO alternate functions |
||||
* for more details. |
||||
* |
||||
* @param htim: pointer to a TIM_HandleTypeDef structure that contains |
||||
* the configuration information for TIM module. |
||||
* @param Remap: specifies the TIM input remapping source. |
||||
* This parameter is a combination of the following values |
||||
* depending on TIM instance: |
||||
* |
||||
* For TIM2, the parameter can have the following values: |
||||
* @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): |
||||
* GPIOA(0)_AF5 or GPIOA(5)_AF2 or |
||||
* GPIOA(15)_AF2 |
||||
* @arg TIM2_ETR_HSI16: TIM2 ETR connected to HS16 (HSIOUT) |
||||
* @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE |
||||
* @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output |
||||
* @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output |
||||
* @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO (default): |
||||
* GPIOA(3)_AF2 or GPIOB(11)_AF2 or |
||||
* GPIOB(1)_AF5 |
||||
* @arg TIM2_TI4_COMP1_OUT: TIM2 TI4 connected to COMP1 output |
||||
* @arg TIM2_TI4_COMP2_OUT: TIM2 TI4 connected to COMP2 output |
||||
* |
||||
* For TIM21, the parameter can have the following values: |
||||
* @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : |
||||
* APB2_PA(1)_AF5 |
||||
* @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output |
||||
* @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output |
||||
* @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE |
||||
* @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO |
||||
* @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt |
||||
* @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC |
||||
* @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock |
||||
* @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE |
||||
* @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI |
||||
* @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT |
||||
* @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): |
||||
* GPIOA(3)_AF0 or GPIOB(14)_AF6 |
||||
* @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output |
||||
* |
||||
* For TIM22, the parameter can have the following values: |
||||
* @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE |
||||
* @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output |
||||
* @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output |
||||
* @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default): |
||||
* GPIOA(4)_AF5 |
||||
* @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default): |
||||
* GPIOC(0)_AF6 or GPIOA(5)_AF6 or |
||||
* GPIOB(4)_AF4 |
||||
* @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output |
||||
* @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output |
||||
* @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO: |
||||
* GPIOA(6)_AF5 or GPIOB(4)_AF4 |
||||
* |
||||
* @retval HAL status |
||||
*/
|
||||
#elif defined (STM32L011xx) || defined (STM32L021xx) |
||||
/**
|
||||
* @brief Configures the remapping of the TIM2 and TIM21 inputs. |
||||
* The channel inputs (T1..T4) and the Trigger input (ETR) of the |
||||
* timers can be remaped thanks to this function. When an input is |
||||
* mapped, on a GPIO, refer yourself to the GPIO alternate functions |
||||
* for more details. |
||||
* |
||||
* @param htim: pointer to a TIM_HandleTypeDef structure that contains |
||||
* the configuration information for TIM module. |
||||
* @param Remap: specifies the TIM input remapping source. |
||||
* This parameter is a combination of the following values |
||||
* depending on TIM instance: |
||||
* |
||||
* For TIM2, the parameter can have the following values: |
||||
* @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): |
||||
* GPIOA(0)_AF5 or GPIOA(5)_AF2 or |
||||
* GPIOA(15)_AF2 |
||||
* @arg TIM2_ETR_HSI16: TIM2 ETR connected to HS16 (HSIOUT) |
||||
* @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE |
||||
* @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output |
||||
* @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output |
||||
* @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO (default): |
||||
* GPIOA(3)_AF2 or GPIOB(11)_AF2 or |
||||
* GPIOB(1)_AF5 |
||||
* @arg TIM2_TI4_COMP1_OUT: TIM2 TI4 connected to COMP1 output |
||||
* @arg TIM2_TI4_COMP2_OUT: TIM2 TI4 connected to COMP2 output |
||||
* |
||||
* For TIM21, the parameter can have the following values: |
||||
* @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : |
||||
* APB2_PA(1)_AF5 |
||||
* @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output |
||||
* @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output |
||||
* @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE |
||||
* @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO |
||||
* @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt |
||||
* @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC |
||||
* @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock |
||||
* @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE |
||||
* @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI |
||||
* @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT |
||||
* @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): |
||||
* GPIOA(3)_AF0 or GPIOB(14)_AF6 |
||||
* @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output |
||||
* |
||||
* @retval HAL status |
||||
*/
|
||||
#else |
||||
/**
|
||||
* @brief Configures the remapping of the TIM2, TIM21 and TIM22 inputs. |
||||
* The channel inputs (T1..T4) and the Trigger input (ETR) of the |
||||
* timers can be remaped thanks to this function. When an input is |
||||
* mapped, on a GPIO, refer yourself to the GPIO alternate functions |
||||
* for more details. |
||||
* |
||||
* @param htim: pointer to a TIM_HandleTypeDef structure that contains |
||||
* the configuration information for TIM module. |
||||
* @param Remap: specifies the TIM input remapping source. |
||||
* This parameter is a combination of the following values |
||||
* depending on TIM instance: |
||||
* |
||||
* For TIM2, the parameter can have the following values: |
||||
* @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): |
||||
* GPIOA(0)_AF5 or GPIOA(5)_AF2 or |
||||
* GPIOA(15)_AF2 or GPIOE(9)_AF2 |
||||
* @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48 |
||||
* @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE |
||||
* @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output |
||||
* @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output |
||||
* @arg TIM2_TI4_GPIO: TIM2 TI4 connected to GPIO1(default): |
||||
* GPIOA(3)_AF2 or GPIOB(11)_AF2 or |
||||
* GPIOE(12)_AF0 |
||||
* @arg TIM2_TI4_COMP1: TIM2 TI4 connected to COMP1 |
||||
* @arg TIM2_TI4_COMP2: TIM2 TI4 connected to COMP2 |
||||
* @arg TIM2_TI4_GPIO2: TIM2 TI4 connected to GPIO2 : |
||||
* GPIOA(3)_AF2 or GPIOB(11)_AF2 or |
||||
* GPIOE(12)_AF0 |
||||
* |
||||
* For TIM21, the parameter can have the following values: |
||||
* @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : |
||||
* APB2_PC(9)_AF0 or APB2_PA(1)_AF5 |
||||
* @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output |
||||
* @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output |
||||
* @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE |
||||
* @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO |
||||
* @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt |
||||
* @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC |
||||
* @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock |
||||
* @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE |
||||
* @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI |
||||
* @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT |
||||
* @arg TIM21_TI1_GPIO: TIM21 TI1 connected to GPIO(default): |
||||
* GPIOA(2)_AF0 or GPIOB(13)_AF6 or |
||||
* GPIOE(5)_AF0 or GPIOD(0)_AF0 |
||||
* @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): |
||||
* GPIOA(3)_AF0 or GPIOB(14)_AF6 or |
||||
* GPIOE(6)_AF0 or GPIOD(7)_AF1 |
||||
* @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output |
||||
* |
||||
* For TIM22, the parameter can have the following values: |
||||
* @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE |
||||
* @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output |
||||
* @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output |
||||
* @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default): |
||||
* GPIOC(8)_AF0 or GPIOA(4)_AF5 |
||||
* @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default): |
||||
* GPIOC(6)_AF0 or GPIOA(6)_AF5 or |
||||
* GPIOB(4)_AF4 or GPIOE(0)_AF3 |
||||
* @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output |
||||
* @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output |
||||
* @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO: |
||||
* GPIOC(6)_AF0 or GPIOA(6)_AF5 or |
||||
* GPIOB(4)_AF4 or GPIOE(3)_AF0 |
||||
* |
||||
* @retval HAL status |
||||
*/ |
||||
|
||||
#endif /* STM32L07xxx or STM32L08xxx */ |
||||
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) |
||||
{ |
||||
|
||||
__HAL_LOCK(htim); |
||||
|
||||
/* Check parameters */ |
||||
assert_param(IS_TIM_REMAP(htim->Instance,Remap)); |
||||
|
||||
/* Set the Timer remapping configuration */ |
||||
htim->Instance->OR = Remap; |
||||
|
||||
htim->State = HAL_TIM_STATE_READY; |
||||
|
||||
__HAL_UNLOCK(htim); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */ |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,520 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_uart_ex.c |
||||
* @author MCD Application Team |
||||
* @brief Extended UART HAL module driver. |
||||
* This file provides firmware functions to manage the following extended |
||||
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). |
||||
* + Initialization and de-initialization functions |
||||
* + Peripheral Control functions |
||||
* |
||||
* |
||||
@verbatim |
||||
============================================================================== |
||||
##### UART peripheral extended features ##### |
||||
============================================================================== |
||||
|
||||
(#) Declare a UART_HandleTypeDef handle structure. |
||||
|
||||
(#) For the UART RS485 Driver Enable mode, initialize the UART registers |
||||
by calling the HAL_RS485Ex_Init() API. |
||||
|
||||
|
||||
@endverbatim |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup UARTEx UARTEx
|
||||
* @brief UART Extended HAL module driver |
||||
* @{ |
||||
*/ |
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED |
||||
|
||||
/* Private typedef -----------------------------------------------------------*/ |
||||
/* Private define ------------------------------------------------------------*/ |
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
|
||||
* @{ |
||||
*/ |
||||
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Extended Initialization and Configuration Functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Initialization and Configuration functions ##### |
||||
=============================================================================== |
||||
[..] |
||||
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy |
||||
in asynchronous mode. |
||||
(+) For the asynchronous mode the parameters below can be configured: |
||||
(++) Baud Rate |
||||
(++) Word Length |
||||
(++) Stop Bit |
||||
(++) Parity: If the parity is enabled, then the MSB bit of the data written |
||||
in the data register is transmitted but is changed by the parity bit. |
||||
(++) Hardware flow control |
||||
(++) Receiver/transmitter modes |
||||
(++) Over Sampling Method |
||||
(++) One-Bit Sampling Method |
||||
(+) For the asynchronous mode, the following advanced features can be configured as well: |
||||
(++) TX and/or RX pin level inversion |
||||
(++) data logical level inversion |
||||
(++) RX and TX pins swap |
||||
(++) RX overrun detection disabling |
||||
(++) DMA disabling on RX error |
||||
(++) MSB first on communication line |
||||
(++) auto Baud rate detection |
||||
[..] |
||||
The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration |
||||
procedures (details for the procedures are available in reference manual). |
||||
|
||||
@endverbatim |
||||
|
||||
Depending on the frame length defined by the M1 and M0 bits (7-bit,
|
||||
8-bit or 9-bit), the possible UART formats are listed in the
|
||||
following table. |
||||
|
||||
Table 1. UART frame format. |
||||
+-----------------------------------------------------------------------+ |
||||
| M1 bit | M0 bit | PCE bit | UART frame | |
||||
|---------|---------|-----------|---------------------------------------| |
||||
| 0 | 0 | 0 | | SB | 8 bit data | STB | | |
||||
|---------|---------|-----------|---------------------------------------| |
||||
| 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | |
||||
|---------|---------|-----------|---------------------------------------| |
||||
| 0 | 1 | 0 | | SB | 9 bit data | STB | | |
||||
|---------|---------|-----------|---------------------------------------| |
||||
| 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | |
||||
|---------|---------|-----------|---------------------------------------| |
||||
| 1 | 0 | 0 | | SB | 7 bit data | STB | | |
||||
|---------|---------|-----------|---------------------------------------| |
||||
| 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | |
||||
+-----------------------------------------------------------------------+ |
||||
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Initialize the RS485 Driver enable feature according to the specified |
||||
* parameters in the UART_InitTypeDef and creates the associated handle. |
||||
* @param huart: UART handle. |
||||
* @param Polarity: select the driver enable polarity. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref UART_DE_POLARITY_HIGH DE signal is active high |
||||
* @arg @ref UART_DE_POLARITY_LOW DE signal is active low |
||||
* @param AssertionTime: Driver Enable assertion time: |
||||
* 5-bit value defining the time between the activation of the DE (Driver Enable) |
||||
* signal and the beginning of the start bit. It is expressed in sample time |
||||
* units (1/8 or 1/16 bit time, depending on the oversampling rate) |
||||
* @param DeassertionTime: Driver Enable deassertion time: |
||||
* 5-bit value defining the time between the end of the last stop bit, in a |
||||
* transmitted message, and the de-activation of the DE (Driver Enable) signal. |
||||
* It is expressed in sample time units (1/8 or 1/16 bit time, depending on the |
||||
* oversampling rate). |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) |
||||
{ |
||||
uint32_t temp = 0x0U; |
||||
|
||||
/* Check the UART handle allocation */ |
||||
if(huart == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the Driver Enable polarity */ |
||||
assert_param(IS_UART_DE_POLARITY(Polarity)); |
||||
|
||||
/* Check the Driver Enable assertion time */ |
||||
assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); |
||||
|
||||
/* Check the Driver Enable deassertion time */ |
||||
assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); |
||||
|
||||
if(huart->gState == HAL_UART_STATE_RESET) |
||||
{ |
||||
/* Allocate lock resource and initialize it */ |
||||
huart->Lock = HAL_UNLOCKED; |
||||
|
||||
/* Init the low level hardware : GPIO, CLOCK, CORTEX */ |
||||
HAL_UART_MspInit(huart); |
||||
} |
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY; |
||||
|
||||
/* Disable the Peripheral */ |
||||
__HAL_UART_DISABLE(huart); |
||||
|
||||
/* Set the UART Communication parameters */ |
||||
if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) |
||||
{ |
||||
UART_AdvFeatureConfig(huart); |
||||
} |
||||
|
||||
if (UART_SetConfig(huart) == HAL_ERROR) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ |
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DEM); |
||||
|
||||
/* Set the Driver Enable polarity */ |
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); |
||||
|
||||
/* Set the Driver Enable assertion and deassertion times */ |
||||
temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); |
||||
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); |
||||
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); |
||||
|
||||
/* Enable the Peripheral */ |
||||
__HAL_UART_ENABLE(huart); |
||||
|
||||
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ |
||||
return (UART_CheckIdleState(huart)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions |
||||
* |
||||
@verbatim |
||||
=============================================================================== |
||||
##### Peripheral Control functions ##### |
||||
=============================================================================== |
||||
[..] This section provides the following functions: |
||||
(+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode |
||||
(+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality |
||||
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address |
||||
detection length to more than 4 bits for multiprocessor address mark wake up. |
||||
(+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode |
||||
trigger: address match, Start Bit detection or RXNE bit status. |
||||
(+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode |
||||
(+) HAL_UARTEx_DisableStopMode() API disables the above functionality |
||||
(+) HAL_UARTEx_EnableClockStopMode() API enables the UART HSI clock during stop mode
|
||||
(+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
|
||||
(+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt |
||||
|
||||
|
||||
@endverbatim |
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief By default in multiprocessor mode, when the wake up method is set |
||||
* to address mark, the UART handles only 4-bit long addresses detection; |
||||
* this API allows to enable longer addresses detection (6-, 7- or 8-bit |
||||
* long). |
||||
* @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
|
||||
* 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. |
||||
* @param huart: UART handle. |
||||
* @param AddressLength: this parameter can be one of the following values: |
||||
* @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address |
||||
* @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) |
||||
{ |
||||
/* Check the UART handle allocation */ |
||||
if(huart == NULL) |
||||
{ |
||||
return HAL_ERROR; |
||||
} |
||||
|
||||
/* Check the address length parameter */ |
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); |
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY; |
||||
|
||||
/* Disable the Peripheral */ |
||||
__HAL_UART_DISABLE(huart); |
||||
|
||||
/* Set the address length */ |
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); |
||||
|
||||
/* Enable the Peripheral */ |
||||
__HAL_UART_ENABLE(huart); |
||||
|
||||
/* TEACK and/or REACK to check before moving huart->gState and/or huart->RxState to Ready */ |
||||
return (UART_CheckIdleState(huart)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Set Wakeup from Stop mode interrupt flag selection. |
||||
* @param huart: UART handle. |
||||
* @param WakeUpSelection: address match, Start Bit detection or RXNE bit status. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref UART_WAKEUP_ON_ADDRESS |
||||
* @arg @ref UART_WAKEUP_ON_STARTBIT |
||||
* @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) |
||||
{ |
||||
HAL_StatusTypeDef status = HAL_OK; |
||||
uint32_t tickstart = 0; |
||||
|
||||
/* check the wake-up from stop mode UART instance */ |
||||
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); |
||||
/* check the wake-up selection parameter */ |
||||
assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); |
||||
|
||||
/* Process Locked */ |
||||
__HAL_LOCK(huart); |
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY; |
||||
|
||||
/* Disable the Peripheral */ |
||||
__HAL_UART_DISABLE(huart); |
||||
|
||||
/* Set the wake-up selection scheme */ |
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); |
||||
|
||||
if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) |
||||
{ |
||||
UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); |
||||
} |
||||
|
||||
/* Enable the Peripheral */ |
||||
__HAL_UART_ENABLE(huart); |
||||
|
||||
/* Init tickstart for timeout managment*/ |
||||
tickstart = HAL_GetTick(); |
||||
|
||||
/* Wait until REACK flag is set */ |
||||
if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) |
||||
{ |
||||
status = HAL_TIMEOUT; |
||||
} |
||||
else |
||||
{ |
||||
/* Initialize the UART State */ |
||||
huart->gState = HAL_UART_STATE_READY; |
||||
} |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(huart); |
||||
|
||||
return status; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
* @brief Enable UART Stop Mode. |
||||
* @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. |
||||
* @param huart: UART handle. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) |
||||
{ |
||||
/* Process Locked */ |
||||
__HAL_LOCK(huart); |
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY; |
||||
|
||||
/* Set UESM bit */ |
||||
SET_BIT(huart->Instance->CR1, USART_CR1_UESM); |
||||
|
||||
huart->gState = HAL_UART_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(huart); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable UART Stop Mode. |
||||
* @param huart: UART handle. |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) |
||||
{ |
||||
/* Process Locked */ |
||||
__HAL_LOCK(huart); |
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY; |
||||
|
||||
/* Clear UESM bit */ |
||||
CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); |
||||
|
||||
huart->gState = HAL_UART_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(huart); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable UART Clock in Stop Mode |
||||
* The UART keeps the Clock ON during Stop mode |
||||
* @param huart: uart handle |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) |
||||
{ |
||||
/* Process Locked */ |
||||
__HAL_LOCK(huart); |
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY; |
||||
|
||||
/* Set UCESM bit */ |
||||
SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); |
||||
|
||||
huart->gState = HAL_UART_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(huart); |
||||
|
||||
return HAL_OK;
|
||||
} |
||||
|
||||
/**
|
||||
* @brief Disable UART Clock in Stop Mode
|
||||
* @param huart: uart handle |
||||
* @retval HAL status |
||||
*/ |
||||
HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) |
||||
{ |
||||
/* Process Locked */ |
||||
__HAL_LOCK(huart); |
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY; |
||||
|
||||
/* Clear UCESM bit */ |
||||
CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); |
||||
|
||||
huart->gState = HAL_UART_STATE_READY; |
||||
|
||||
/* Process Unlocked */ |
||||
__HAL_UNLOCK(huart); |
||||
|
||||
return HAL_OK; |
||||
} |
||||
|
||||
/**
|
||||
* @brief UART wakeup from Stop mode callback. |
||||
* @param huart: UART handle. |
||||
* @retval None |
||||
*/ |
||||
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) |
||||
{ |
||||
/* Prevent unused argument(s) compilation warning */ |
||||
UNUSED(huart); |
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_UARTEx_WakeupCallback can be implemented in the user file. |
||||
*/ |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup UARTEx_Private_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. |
||||
* @param huart: UART handle. |
||||
* @param WakeUpSelection: UART wake up from stop mode parameters. |
||||
* @retval None |
||||
*/ |
||||
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) |
||||
{ |
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); |
||||
if(WakeUpSelection.AddressLength == UART_ADDRESS_DETECT_4B) |
||||
{ |
||||
assert_param(IS_UART_4B_ADDRESS(WakeUpSelection.Address)); |
||||
} |
||||
else |
||||
{ |
||||
assert_param(IS_UART_7B_ADDRESS(WakeUpSelection.Address)); |
||||
} |
||||
|
||||
/* Set the USART address length */ |
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); |
||||
|
||||
/* Set the USART address node */ |
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); |
||||
} |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#endif /* HAL_UART_MODULE_ENABLED */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,78 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : gpio.h |
||||
* Description : This file contains all the functions prototypes for
|
||||
* the gpio
|
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __gpio_H |
||||
#define __gpio_H |
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
void MX_GPIO_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
#endif /*__ pinoutConfig_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,81 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : I2C.h |
||||
* Description : This file provides code for the configuration |
||||
* of the I2C instances. |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __i2c_H |
||||
#define __i2c_H |
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
extern I2C_HandleTypeDef hi2c1; |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
extern void _Error_Handler(char *, int); |
||||
|
||||
void MX_I2C1_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
#endif /*__ i2c_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,94 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : main.hpp |
||||
* Description : This file contains the common defines of the application |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __MAIN_H |
||||
#define __MAIN_H |
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Private define ------------------------------------------------------------*/ |
||||
|
||||
#define B1_Pin GPIO_PIN_13 |
||||
#define B1_GPIO_Port GPIOC |
||||
#define MCO_Pin GPIO_PIN_0 |
||||
#define MCO_GPIO_Port GPIOH |
||||
#define USART_TX_Pin GPIO_PIN_2 |
||||
#define USART_TX_GPIO_Port GPIOA |
||||
#define USART_RX_Pin GPIO_PIN_3 |
||||
#define USART_RX_GPIO_Port GPIOA |
||||
#define TMS_Pin GPIO_PIN_13 |
||||
#define TMS_GPIO_Port GPIOA |
||||
#define TCK_Pin GPIO_PIN_14 |
||||
#define TCK_GPIO_Port GPIOA |
||||
|
||||
/* ########################## Assert Selection ############################## */ |
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code |
||||
*/ |
||||
/* #define USE_FULL_ASSERT 1U */ |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
void _Error_Handler(char *, int); |
||||
|
||||
#define Error_Handler() _Error_Handler(__FILE__, __LINE__) |
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
#endif /* __MAIN_H */ |
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,81 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : RTC.h |
||||
* Description : This file provides code for the configuration |
||||
* of the RTC instances. |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __rtc_H |
||||
#define __rtc_H |
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
extern RTC_HandleTypeDef hrtc; |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
extern void _Error_Handler(char *, int); |
||||
|
||||
void MX_RTC_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
#endif /*__ rtc_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,81 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : SPI.h |
||||
* Description : This file provides code for the configuration |
||||
* of the SPI instances. |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __spi_H |
||||
#define __spi_H |
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
extern SPI_HandleTypeDef hspi1; |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
extern void _Error_Handler(char *, int); |
||||
|
||||
void MX_SPI1_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
#endif /*__ spi_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,311 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_conf.h |
||||
* @brief HAL configuration file.
|
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_CONF_H |
||||
#define __STM32L0xx_HAL_CONF_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
#include "main.h" |
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/* ########################## Module Selection ############################## */ |
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/ |
||||
|
||||
#define HAL_MODULE_ENABLED |
||||
/*#define HAL_ADC_MODULE_ENABLED */ |
||||
/*#define HAL_CRYP_MODULE_ENABLED */ |
||||
/*#define HAL_COMP_MODULE_ENABLED */ |
||||
/*#define HAL_CRC_MODULE_ENABLED */ |
||||
/*#define HAL_CRYP_MODULE_ENABLED */ |
||||
/*#define HAL_DAC_MODULE_ENABLED */ |
||||
/*#define HAL_FIREWALL_MODULE_ENABLED */ |
||||
/*#define HAL_I2S_MODULE_ENABLED */ |
||||
/*#define HAL_IWDG_MODULE_ENABLED */ |
||||
/*#define HAL_LCD_MODULE_ENABLED */ |
||||
/*#define HAL_LPTIM_MODULE_ENABLED */ |
||||
/*#define HAL_RNG_MODULE_ENABLED */ |
||||
#define HAL_RTC_MODULE_ENABLED |
||||
#define HAL_SPI_MODULE_ENABLED |
||||
/*#define HAL_TIM_MODULE_ENABLED */ |
||||
/*#define HAL_TSC_MODULE_ENABLED */ |
||||
#define HAL_UART_MODULE_ENABLED |
||||
/*#define HAL_USART_MODULE_ENABLED */ |
||||
/*#define HAL_IRDA_MODULE_ENABLED */ |
||||
/*#define HAL_SMARTCARD_MODULE_ENABLED */ |
||||
/*#define HAL_SMBUS_MODULE_ENABLED */ |
||||
/*#define HAL_WWDG_MODULE_ENABLED */ |
||||
/*#define HAL_PCD_MODULE_ENABLED */ |
||||
#define HAL_GPIO_MODULE_ENABLED |
||||
#define HAL_DMA_MODULE_ENABLED |
||||
#define HAL_I2C_MODULE_ENABLED |
||||
#define HAL_RCC_MODULE_ENABLED |
||||
#define HAL_FLASH_MODULE_ENABLED |
||||
#define HAL_PWR_MODULE_ENABLED |
||||
#define HAL_CORTEX_MODULE_ENABLED |
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/ |
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application. |
||||
* This value is used by the RCC HAL module to compute the system frequency |
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/ |
||||
#if !defined (HSE_VALUE) |
||||
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ |
||||
#endif /* HSE_VALUE */ |
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT) |
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ |
||||
#endif /* HSE_STARTUP_TIMEOUT */ |
||||
|
||||
/**
|
||||
* @brief Internal Multiple Speed oscillator (MSI) default value. |
||||
* This value is the default MSI range value after Reset. |
||||
*/ |
||||
#if !defined (MSI_VALUE) |
||||
#define MSI_VALUE ((uint32_t)2097000U) /*!< Value of the Internal oscillator in Hz*/ |
||||
#endif /* MSI_VALUE */ |
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value. |
||||
* This value is used by the RCC HAL module to compute the system frequency |
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/ |
||||
#if !defined (HSI_VALUE) |
||||
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ |
||||
#endif /* HSI_VALUE */ |
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator for USB (HSI48) value. |
||||
*/ |
||||
#if !defined (HSI48_VALUE) |
||||
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz. |
||||
The real value may vary depending on the variations |
||||
in voltage and temperature. */ |
||||
#endif /* HSI48_VALUE */ |
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value. |
||||
*/ |
||||
#if !defined (LSI_VALUE) |
||||
#define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/ |
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz |
||||
The real value may vary depending on the variations |
||||
in voltage and temperature.*/
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value. |
||||
* This value is used by the UART, RTC HAL module to compute the system frequency |
||||
*/ |
||||
#if !defined (LSE_VALUE) |
||||
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ |
||||
#endif /* LSE_VALUE */ |
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT) |
||||
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ |
||||
#endif /* LSE_STARTUP_TIMEOUT */ |
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */ |
||||
|
||||
/* ########################### System Configuration ######################### */ |
||||
/**
|
||||
* @brief This is the HAL system configuration section |
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ |
||||
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ |
||||
#define USE_RTOS 0U |
||||
#define PREFETCH_ENABLE 0U |
||||
#define PREREAD_ENABLE 1U |
||||
#define BUFFER_CACHE_DISABLE 0U |
||||
|
||||
/* ########################## Assert Selection ############################## */ |
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code |
||||
*/ |
||||
/* #define USE_FULL_ASSERT 1U */ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/ |
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_rcc.h" |
||||
#endif /* HAL_RCC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_gpio.h" |
||||
#endif /* HAL_GPIO_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_dma.h" |
||||
#endif /* HAL_DMA_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_cortex.h" |
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_adc.h" |
||||
#endif /* HAL_ADC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_comp.h" |
||||
#endif /* HAL_COMP_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_crc.h" |
||||
#endif /* HAL_CRC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_cryp.h" |
||||
#endif /* HAL_CRYP_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_dac.h" |
||||
#endif /* HAL_DAC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_FIREWALL_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_firewall.h" |
||||
#endif /* HAL_FIREWALL_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_flash.h" |
||||
#endif /* HAL_FLASH_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_i2c.h" |
||||
#endif /* HAL_I2C_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_i2s.h" |
||||
#endif /* HAL_I2S_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_iwdg.h" |
||||
#endif /* HAL_IWDG_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_LCD_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_lcd.h" |
||||
#endif /* HAL_LCD_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_lptim.h" |
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_pwr.h" |
||||
#endif /* HAL_PWR_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_rng.h" |
||||
#endif /* HAL_RNG_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_rtc.h" |
||||
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_spi.h" |
||||
#endif /* HAL_SPI_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_tim.h" |
||||
#endif /* HAL_TIM_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_TSC_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_tsc.h" |
||||
#endif /* HAL_TSC_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_uart.h" |
||||
#endif /* HAL_UART_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_usart.h" |
||||
#endif /* HAL_USART_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_irda.h" |
||||
#endif /* HAL_IRDA_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_smartcard.h" |
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_smbus.h" |
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_wwdg.h" |
||||
#endif /* HAL_WWDG_MODULE_ENABLED */ |
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED |
||||
#include "stm32l0xx_hal_pcd.h" |
||||
#endif /* HAL_PCD_MODULE_ENABLED */ |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
#ifdef USE_FULL_ASSERT |
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check. |
||||
* @param expr: If expr is false, it calls assert_failed function |
||||
* which reports the name of the source file and the source |
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value. |
||||
* @retval None |
||||
*/ |
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) |
||||
/* Exported functions ------------------------------------------------------- */ |
||||
void assert_failed(uint8_t* file, uint32_t line); |
||||
#else |
||||
#define assert_param(expr) ((void)0U) |
||||
#endif /* USE_FULL_ASSERT */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_CONF_H */ |
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,60 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_it.h |
||||
* @brief This file contains the headers of the interrupt handlers. |
||||
****************************************************************************** |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_IT_H |
||||
#define __STM32L0xx_IT_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
#include "main.h" |
||||
/* Exported types ------------------------------------------------------------*/ |
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
/* Exported functions ------------------------------------------------------- */ |
||||
|
||||
void SVC_Handler(void); |
||||
void PendSV_Handler(void); |
||||
void SysTick_Handler(void); |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_IT_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,83 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : USART.h |
||||
* Description : This file provides code for the configuration |
||||
* of the USART instances. |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __usart_H |
||||
#define __usart_H |
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
#include "main.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
extern UART_HandleTypeDef huart1; |
||||
extern UART_HandleTypeDef huart2; |
||||
|
||||
/* USER CODE BEGIN Private defines */ |
||||
|
||||
/* USER CODE END Private defines */ |
||||
|
||||
extern void _Error_Handler(char *, int); |
||||
|
||||
void MX_USART1_UART_Init(void); |
||||
void MX_USART2_UART_Init(void); |
||||
|
||||
/* USER CODE BEGIN Prototypes */ |
||||
|
||||
/* USER CODE END Prototypes */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
#endif /*__ usart_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,19 @@ |
||||
<?xml version="1.0" encoding="UTF-8"?> |
||||
<!DOCTYPE targetDefinitions [ |
||||
<!ELEMENT targetDefinitions (board)> |
||||
<!ELEMENT board (name, dbgIF+, dbgDEV, mcuId)> |
||||
<!ELEMENT name (#PCDATA)> |
||||
<!ELEMENT dbgIF (#PCDATA)> |
||||
<!ELEMENT dbgDEV (#PCDATA)> |
||||
<!ELEMENT mcuId (#PCDATA)> |
||||
<!ATTLIST board id CDATA #REQUIRED> |
||||
]> |
||||
|
||||
<targetDefinitions> |
||||
<board id="nucleo-l073rz"> |
||||
<name>NUCLEO-L073RZ</name> |
||||
<dbgIF>SWD</dbgIF> |
||||
<dbgDEV>ST-Link</dbgDEV> |
||||
<mcuId>stm32l073rztx</mcuId> |
||||
</board> |
||||
</targetDefinitions> |
||||
@ -0,0 +1,169 @@ |
||||
/* |
||||
***************************************************************************** |
||||
** |
||||
|
||||
** File : LinkerScript.ld |
||||
** |
||||
** Abstract : Linker script for STM32L073RZTx Device with |
||||
** 192KByte FLASH, 20KByte RAM |
||||
** |
||||
** Set heap size, stack size and stack location according |
||||
** to application requirements. |
||||
** |
||||
** Set memory bank area and size if external memory is used. |
||||
** |
||||
** Target : STMicroelectronics STM32 |
||||
** |
||||
** |
||||
** Distribution: The file is distributed as is, without any warranty |
||||
** of any kind. |
||||
** |
||||
** (c)Copyright Ac6. |
||||
** You may use this file as-is or modify it according to the needs of your |
||||
** project. Distribution of this file (unmodified or modified) is not |
||||
** permitted. Ac6 permit registered System Workbench for MCU users the |
||||
** rights to distribute the assembled, compiled & linked contents of this |
||||
** file as part of an application binary file, provided that it is built |
||||
** using the System Workbench for MCU toolchain. |
||||
** |
||||
***************************************************************************** |
||||
*/ |
||||
|
||||
/* Entry Point */ |
||||
ENTRY(Reset_Handler) |
||||
|
||||
/* Highest address of the user mode stack */ |
||||
_estack = 0x20005000; /* end of RAM */ |
||||
/* Generate a link error if heap and stack don't fit into RAM */ |
||||
_Min_Heap_Size = 0x200; /* required amount of heap */ |
||||
_Min_Stack_Size = 0x400; /* required amount of stack */ |
||||
|
||||
/* Specify the memory areas */ |
||||
MEMORY |
||||
{ |
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K |
||||
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 192K |
||||
} |
||||
|
||||
/* Define output sections */ |
||||
SECTIONS |
||||
{ |
||||
/* The startup code goes first into FLASH */ |
||||
.isr_vector : |
||||
{ |
||||
. = ALIGN(4); |
||||
KEEP(*(.isr_vector)) /* Startup code */ |
||||
. = ALIGN(4); |
||||
} >FLASH |
||||
|
||||
/* The program code and other data goes into FLASH */ |
||||
.text : |
||||
{ |
||||
. = ALIGN(4); |
||||
*(.text) /* .text sections (code) */ |
||||
*(.text*) /* .text* sections (code) */ |
||||
*(.glue_7) /* glue arm to thumb code */ |
||||
*(.glue_7t) /* glue thumb to arm code */ |
||||
*(.eh_frame) |
||||
|
||||
KEEP (*(.init)) |
||||
KEEP (*(.fini)) |
||||
|
||||
. = ALIGN(4); |
||||
_etext = .; /* define a global symbols at end of code */ |
||||
} >FLASH |
||||
|
||||
/* Constant data goes into FLASH */ |
||||
.rodata : |
||||
{ |
||||
. = ALIGN(4); |
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */ |
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */ |
||||
. = ALIGN(4); |
||||
} >FLASH |
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH |
||||
.ARM : { |
||||
__exidx_start = .; |
||||
*(.ARM.exidx*) |
||||
__exidx_end = .; |
||||
} >FLASH |
||||
|
||||
.preinit_array : |
||||
{ |
||||
PROVIDE_HIDDEN (__preinit_array_start = .); |
||||
KEEP (*(.preinit_array*)) |
||||
PROVIDE_HIDDEN (__preinit_array_end = .); |
||||
} >FLASH |
||||
.init_array : |
||||
{ |
||||
PROVIDE_HIDDEN (__init_array_start = .); |
||||
KEEP (*(SORT(.init_array.*))) |
||||
KEEP (*(.init_array*)) |
||||
PROVIDE_HIDDEN (__init_array_end = .); |
||||
} >FLASH |
||||
.fini_array : |
||||
{ |
||||
PROVIDE_HIDDEN (__fini_array_start = .); |
||||
KEEP (*(SORT(.fini_array.*))) |
||||
KEEP (*(.fini_array*)) |
||||
PROVIDE_HIDDEN (__fini_array_end = .); |
||||
} >FLASH |
||||
|
||||
/* used by the startup to initialize data */ |
||||
_sidata = LOADADDR(.data); |
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */ |
||||
.data : |
||||
{ |
||||
. = ALIGN(4); |
||||
_sdata = .; /* create a global symbol at data start */ |
||||
*(.data) /* .data sections */ |
||||
*(.data*) /* .data* sections */ |
||||
|
||||
. = ALIGN(4); |
||||
_edata = .; /* define a global symbol at data end */ |
||||
} >RAM AT> FLASH |
||||
|
||||
|
||||
/* Uninitialized data section */ |
||||
. = ALIGN(4); |
||||
.bss : |
||||
{ |
||||
/* This is used by the startup in order to initialize the .bss secion */ |
||||
_sbss = .; /* define a global symbol at bss start */ |
||||
__bss_start__ = _sbss; |
||||
*(.bss) |
||||
*(.bss*) |
||||
*(COMMON) |
||||
|
||||
. = ALIGN(4); |
||||
_ebss = .; /* define a global symbol at bss end */ |
||||
__bss_end__ = _ebss; |
||||
} >RAM |
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */ |
||||
._user_heap_stack : |
||||
{ |
||||
. = ALIGN(8); |
||||
PROVIDE ( end = . ); |
||||
PROVIDE ( _end = . ); |
||||
. = . + _Min_Heap_Size; |
||||
. = . + _Min_Stack_Size; |
||||
. = ALIGN(8); |
||||
} >RAM |
||||
|
||||
|
||||
|
||||
/* Remove information from the standard libraries */ |
||||
/DISCARD/ : |
||||
{ |
||||
libc.a ( * ) |
||||
libm.a ( * ) |
||||
libgcc.a ( * ) |
||||
} |
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) } |
||||
} |
||||
|
||||
|
||||
@ -0,0 +1,138 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : gpio.c |
||||
* Description : This file provides code for the configuration |
||||
* of all used GPIO pins. |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "gpio.h" |
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
/*----------------------------------------------------------------------------*/ |
||||
/* Configure GPIO */ |
||||
/*----------------------------------------------------------------------------*/ |
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
|
||||
/** Configure pins as
|
||||
* Analog
|
||||
* Input
|
||||
* Output |
||||
* EVENT_OUT |
||||
* EXTI |
||||
* Free pins are configured automatically as Analog (this feature is enabled through
|
||||
* the Code Generation settings) |
||||
*/ |
||||
void MX_GPIO_Init(void) |
||||
{ |
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct; |
||||
|
||||
/* GPIO Ports Clock Enable */ |
||||
__HAL_RCC_GPIOC_CLK_ENABLE(); |
||||
__HAL_RCC_GPIOH_CLK_ENABLE(); |
||||
__HAL_RCC_GPIOA_CLK_ENABLE(); |
||||
__HAL_RCC_GPIOB_CLK_ENABLE(); |
||||
__HAL_RCC_GPIOD_CLK_ENABLE(); |
||||
|
||||
/*Configure GPIO pin : PtPin */ |
||||
GPIO_InitStruct.Pin = B1_Pin; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); |
||||
|
||||
/*Configure GPIO pin : PH1 */ |
||||
GPIO_InitStruct.Pin = GPIO_PIN_1; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); |
||||
|
||||
/*Configure GPIO pins : PC0 PC1 PC2 PC3
|
||||
PC4 PC5 PC6 PC7
|
||||
PC8 PC9 PC10 PC11
|
||||
PC12 */ |
||||
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|
||||
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7
|
||||
|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|
||||
|GPIO_PIN_12; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); |
||||
|
||||
/*Configure GPIO pins : PA0 PA1 PA8 PA11
|
||||
PA12 PA15 */ |
||||
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_8|GPIO_PIN_11
|
||||
|GPIO_PIN_12|GPIO_PIN_15; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); |
||||
|
||||
/*Configure GPIO pins : PB0 PB1 PB2 PB10
|
||||
PB11 PB12 PB13 PB14
|
||||
PB15 PB3 PB4 PB5
|
||||
PB6 PB7 */ |
||||
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10
|
||||
|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
|
||||
|GPIO_PIN_15|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5
|
||||
|GPIO_PIN_6|GPIO_PIN_7; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); |
||||
|
||||
/*Configure GPIO pin : PD2 */ |
||||
GPIO_InitStruct.Pin = GPIO_PIN_2; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); |
||||
|
||||
} |
||||
|
||||
/* USER CODE BEGIN 2 */ |
||||
|
||||
/* USER CODE END 2 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,149 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : I2C.c |
||||
* Description : This file provides code for the configuration |
||||
* of the I2C instances. |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "i2c.h" |
||||
|
||||
#include "gpio.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
I2C_HandleTypeDef hi2c1; |
||||
|
||||
/* I2C1 init function */ |
||||
void MX_I2C1_Init(void) |
||||
{ |
||||
|
||||
hi2c1.Instance = I2C1; |
||||
hi2c1.Init.Timing = 0x00506682; |
||||
hi2c1.Init.OwnAddress1 = 0; |
||||
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; |
||||
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; |
||||
hi2c1.Init.OwnAddress2 = 0; |
||||
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; |
||||
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; |
||||
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; |
||||
if (HAL_I2C_Init(&hi2c1) != HAL_OK) |
||||
{ |
||||
_Error_Handler(__FILE__, __LINE__); |
||||
} |
||||
|
||||
/**Configure Analogue filter
|
||||
*/ |
||||
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) |
||||
{ |
||||
_Error_Handler(__FILE__, __LINE__); |
||||
} |
||||
|
||||
/**Configure Digital filter
|
||||
*/ |
||||
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) |
||||
{ |
||||
_Error_Handler(__FILE__, __LINE__); |
||||
} |
||||
|
||||
} |
||||
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) |
||||
{ |
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct; |
||||
if(i2cHandle->Instance==I2C1) |
||||
{ |
||||
/* USER CODE BEGIN I2C1_MspInit 0 */ |
||||
|
||||
/* USER CODE END I2C1_MspInit 0 */ |
||||
|
||||
/**I2C1 GPIO Configuration
|
||||
PB8 ------> I2C1_SCL |
||||
PB9 ------> I2C1_SDA
|
||||
*/ |
||||
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; |
||||
GPIO_InitStruct.Pull = GPIO_PULLUP; |
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
||||
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; |
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); |
||||
|
||||
/* I2C1 clock enable */ |
||||
__HAL_RCC_I2C1_CLK_ENABLE(); |
||||
/* USER CODE BEGIN I2C1_MspInit 1 */ |
||||
|
||||
/* USER CODE END I2C1_MspInit 1 */ |
||||
} |
||||
} |
||||
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) |
||||
{ |
||||
|
||||
if(i2cHandle->Instance==I2C1) |
||||
{ |
||||
/* USER CODE BEGIN I2C1_MspDeInit 0 */ |
||||
|
||||
/* USER CODE END I2C1_MspDeInit 0 */ |
||||
/* Peripheral clock disable */ |
||||
__HAL_RCC_I2C1_CLK_DISABLE(); |
||||
|
||||
/**I2C1 GPIO Configuration
|
||||
PB8 ------> I2C1_SCL |
||||
PB9 ------> I2C1_SDA
|
||||
*/ |
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9); |
||||
|
||||
/* USER CODE BEGIN I2C1_MspDeInit 1 */ |
||||
|
||||
/* USER CODE END I2C1_MspDeInit 1 */ |
||||
} |
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,30 @@ |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether |
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
@ -0,0 +1,231 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : main.c |
||||
* Description : Main program body |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "main.h" |
||||
#include "stm32l0xx_hal.h" |
||||
#include "i2c.h" |
||||
#include "rtc.h" |
||||
#include "spi.h" |
||||
#include "usart.h" |
||||
#include "gpio.h" |
||||
|
||||
/* USER CODE BEGIN Includes */ |
||||
|
||||
/* USER CODE END Includes */ |
||||
|
||||
/* Private variables ---------------------------------------------------------*/ |
||||
|
||||
/* USER CODE BEGIN PV */ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
|
||||
/* USER CODE END PV */ |
||||
|
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
void SystemClock_Config(void); |
||||
|
||||
/* USER CODE BEGIN PFP */ |
||||
/* Private function prototypes -----------------------------------------------*/ |
||||
|
||||
/* USER CODE END PFP */ |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
int main(void) |
||||
{ |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
|
||||
/* MCU Configuration----------------------------------------------------------*/ |
||||
|
||||
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */ |
||||
HAL_Init(); |
||||
|
||||
/* USER CODE BEGIN Init */ |
||||
|
||||
/* USER CODE END Init */ |
||||
|
||||
/* Configure the system clock */ |
||||
SystemClock_Config(); |
||||
|
||||
/* USER CODE BEGIN SysInit */ |
||||
|
||||
/* USER CODE END SysInit */ |
||||
|
||||
/* Initialize all configured peripherals */ |
||||
MX_GPIO_Init(); |
||||
MX_I2C1_Init(); |
||||
MX_SPI1_Init(); |
||||
MX_USART1_UART_Init(); |
||||
MX_USART2_UART_Init(); |
||||
MX_RTC_Init(); |
||||
|
||||
/* USER CODE BEGIN 2 */ |
||||
|
||||
/* USER CODE END 2 */ |
||||
|
||||
/* Infinite loop */ |
||||
/* USER CODE BEGIN WHILE */ |
||||
while (1) |
||||
{ |
||||
/* USER CODE END WHILE */ |
||||
|
||||
/* USER CODE BEGIN 3 */ |
||||
|
||||
} |
||||
/* USER CODE END 3 */ |
||||
|
||||
} |
||||
|
||||
/** System Clock Configuration
|
||||
*/ |
||||
void SystemClock_Config(void) |
||||
{ |
||||
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct; |
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct; |
||||
RCC_PeriphCLKInitTypeDef PeriphClkInit; |
||||
|
||||
/**Configure the main internal regulator output voltage
|
||||
*/ |
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
||||
|
||||
/**Initializes the CPU, AHB and APB busses clocks
|
||||
*/ |
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI; |
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
||||
RCC_OscInitStruct.HSICalibrationValue = 16; |
||||
RCC_OscInitStruct.LSIState = RCC_LSI_ON; |
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
||||
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_3; |
||||
RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; |
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
||||
{ |
||||
_Error_Handler(__FILE__, __LINE__); |
||||
} |
||||
|
||||
/**Initializes the CPU, AHB and APB busses clocks
|
||||
*/ |
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |
||||
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; |
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; |
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; |
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
||||
{ |
||||
_Error_Handler(__FILE__, __LINE__); |
||||
} |
||||
|
||||
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2 |
||||
|RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_RTC; |
||||
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; |
||||
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; |
||||
PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; |
||||
PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; |
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) |
||||
{ |
||||
_Error_Handler(__FILE__, __LINE__); |
||||
} |
||||
|
||||
/**Configure the Systick interrupt time
|
||||
*/ |
||||
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); |
||||
|
||||
/**Configure the Systick
|
||||
*/ |
||||
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); |
||||
|
||||
/* SysTick_IRQn interrupt configuration */ |
||||
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); |
||||
} |
||||
|
||||
/* USER CODE BEGIN 4 */ |
||||
|
||||
/* USER CODE END 4 */ |
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence. |
||||
* @param None |
||||
* @retval None |
||||
*/ |
||||
void _Error_Handler(char * file, int line) |
||||
{ |
||||
/* USER CODE BEGIN Error_Handler_Debug */ |
||||
/* User can add his own implementation to report the HAL error return state */ |
||||
while(1)
|
||||
{ |
||||
} |
||||
/* USER CODE END Error_Handler_Debug */
|
||||
} |
||||
|
||||
#ifdef USE_FULL_ASSERT |
||||
|
||||
/**
|
||||
* @brief Reports the name of the source file and the source line number |
||||
* where the assert_param error has occurred. |
||||
* @param file: pointer to the source file name |
||||
* @param line: assert_param error line source number |
||||
* @retval None |
||||
*/ |
||||
void assert_failed(uint8_t* file, uint32_t line) |
||||
{ |
||||
/* USER CODE BEGIN 6 */ |
||||
/* User can add his own implementation to report the file name and line number,
|
||||
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ |
||||
/* USER CODE END 6 */ |
||||
|
||||
} |
||||
|
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,114 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : RTC.c |
||||
* Description : This file provides code for the configuration |
||||
* of the RTC instances. |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "rtc.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
RTC_HandleTypeDef hrtc; |
||||
|
||||
/* RTC init function */ |
||||
void MX_RTC_Init(void) |
||||
{ |
||||
|
||||
/**Initialize RTC Only
|
||||
*/ |
||||
hrtc.Instance = RTC; |
||||
hrtc.Init.HourFormat = RTC_HOURFORMAT_24; |
||||
hrtc.Init.AsynchPrediv = 127; |
||||
hrtc.Init.SynchPrediv = 255; |
||||
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; |
||||
hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; |
||||
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; |
||||
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; |
||||
if (HAL_RTC_Init(&hrtc) != HAL_OK) |
||||
{ |
||||
_Error_Handler(__FILE__, __LINE__); |
||||
} |
||||
|
||||
} |
||||
|
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) |
||||
{ |
||||
|
||||
if(rtcHandle->Instance==RTC) |
||||
{ |
||||
/* USER CODE BEGIN RTC_MspInit 0 */ |
||||
|
||||
/* USER CODE END RTC_MspInit 0 */ |
||||
/* RTC clock enable */ |
||||
__HAL_RCC_RTC_ENABLE(); |
||||
/* USER CODE BEGIN RTC_MspInit 1 */ |
||||
|
||||
/* USER CODE END RTC_MspInit 1 */ |
||||
} |
||||
} |
||||
|
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef* rtcHandle) |
||||
{ |
||||
|
||||
if(rtcHandle->Instance==RTC) |
||||
{ |
||||
/* USER CODE BEGIN RTC_MspDeInit 0 */ |
||||
|
||||
/* USER CODE END RTC_MspDeInit 0 */ |
||||
/* Peripheral clock disable */ |
||||
__HAL_RCC_RTC_DISABLE(); |
||||
/* USER CODE BEGIN RTC_MspDeInit 1 */ |
||||
|
||||
/* USER CODE END RTC_MspDeInit 1 */ |
||||
} |
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,142 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : SPI.c |
||||
* Description : This file provides code for the configuration |
||||
* of the SPI instances. |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "spi.h" |
||||
|
||||
#include "gpio.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
SPI_HandleTypeDef hspi1; |
||||
|
||||
/* SPI1 init function */ |
||||
void MX_SPI1_Init(void) |
||||
{ |
||||
|
||||
hspi1.Instance = SPI1; |
||||
hspi1.Init.Mode = SPI_MODE_MASTER; |
||||
hspi1.Init.Direction = SPI_DIRECTION_2LINES; |
||||
hspi1.Init.DataSize = SPI_DATASIZE_8BIT; |
||||
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; |
||||
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; |
||||
hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT; |
||||
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; |
||||
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; |
||||
hspi1.Init.TIMode = SPI_TIMODE_DISABLE; |
||||
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; |
||||
hspi1.Init.CRCPolynomial = 7; |
||||
if (HAL_SPI_Init(&hspi1) != HAL_OK) |
||||
{ |
||||
_Error_Handler(__FILE__, __LINE__); |
||||
} |
||||
|
||||
} |
||||
|
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) |
||||
{ |
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct; |
||||
if(spiHandle->Instance==SPI1) |
||||
{ |
||||
/* USER CODE BEGIN SPI1_MspInit 0 */ |
||||
|
||||
/* USER CODE END SPI1_MspInit 0 */ |
||||
/* SPI1 clock enable */ |
||||
__HAL_RCC_SPI1_CLK_ENABLE(); |
||||
|
||||
/**SPI1 GPIO Configuration
|
||||
PA4 ------> SPI1_NSS |
||||
PA5 ------> SPI1_SCK |
||||
PA6 ------> SPI1_MISO |
||||
PA7 ------> SPI1_MOSI
|
||||
*/ |
||||
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
||||
GPIO_InitStruct.Pull = GPIO_NOPULL; |
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
||||
GPIO_InitStruct.Alternate = GPIO_AF0_SPI1; |
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); |
||||
|
||||
/* USER CODE BEGIN SPI1_MspInit 1 */ |
||||
|
||||
/* USER CODE END SPI1_MspInit 1 */ |
||||
} |
||||
} |
||||
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) |
||||
{ |
||||
|
||||
if(spiHandle->Instance==SPI1) |
||||
{ |
||||
/* USER CODE BEGIN SPI1_MspDeInit 0 */ |
||||
|
||||
/* USER CODE END SPI1_MspDeInit 0 */ |
||||
/* Peripheral clock disable */ |
||||
__HAL_RCC_SPI1_CLK_DISABLE(); |
||||
|
||||
/**SPI1 GPIO Configuration
|
||||
PA4 ------> SPI1_NSS |
||||
PA5 ------> SPI1_SCK |
||||
PA6 ------> SPI1_MISO |
||||
PA7 ------> SPI1_MOSI
|
||||
*/ |
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); |
||||
|
||||
/* USER CODE BEGIN SPI1_MspDeInit 1 */ |
||||
|
||||
/* USER CODE END SPI1_MspDeInit 1 */ |
||||
} |
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,83 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : stm32l0xx_hal_msp.c |
||||
* Description : This file provides code for the MSP Initialization
|
||||
* and de-Initialization codes. |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
|
||||
extern void _Error_Handler(char *, int); |
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
/**
|
||||
* Initializes the Global MSP. |
||||
*/ |
||||
void HAL_MspInit(void) |
||||
{ |
||||
/* USER CODE BEGIN MspInit 0 */ |
||||
|
||||
/* USER CODE END MspInit 0 */ |
||||
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE(); |
||||
__HAL_RCC_PWR_CLK_ENABLE(); |
||||
|
||||
/* System interrupt init*/ |
||||
/* SVC_IRQn interrupt configuration */ |
||||
HAL_NVIC_SetPriority(SVC_IRQn, 0, 0); |
||||
/* PendSV_IRQn interrupt configuration */ |
||||
HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); |
||||
/* SysTick_IRQn interrupt configuration */ |
||||
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); |
||||
|
||||
/* USER CODE BEGIN MspInit 1 */ |
||||
|
||||
/* USER CODE END MspInit 1 */ |
||||
} |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,99 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_it.c |
||||
* @brief Interrupt Service Routines. |
||||
****************************************************************************** |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal.h" |
||||
#include "stm32l0xx.h" |
||||
#include "stm32l0xx_it.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
/* External variables --------------------------------------------------------*/ |
||||
|
||||
/******************************************************************************/ |
||||
/* Cortex-M0+ Processor Interruption and Exception Handlers */
|
||||
/******************************************************************************/ |
||||
|
||||
/**
|
||||
* @brief This function handles System service call via SWI instruction. |
||||
*/ |
||||
void SVC_Handler(void) |
||||
{ |
||||
/* USER CODE BEGIN SVC_IRQn 0 */ |
||||
|
||||
/* USER CODE END SVC_IRQn 0 */ |
||||
/* USER CODE BEGIN SVC_IRQn 1 */ |
||||
|
||||
/* USER CODE END SVC_IRQn 1 */ |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles Pendable request for system service. |
||||
*/ |
||||
void PendSV_Handler(void) |
||||
{ |
||||
/* USER CODE BEGIN PendSV_IRQn 0 */ |
||||
|
||||
/* USER CODE END PendSV_IRQn 0 */ |
||||
/* USER CODE BEGIN PendSV_IRQn 1 */ |
||||
|
||||
/* USER CODE END PendSV_IRQn 1 */ |
||||
} |
||||
|
||||
/**
|
||||
* @brief This function handles System tick timer. |
||||
*/ |
||||
void SysTick_Handler(void) |
||||
{ |
||||
/* USER CODE BEGIN SysTick_IRQn 0 */ |
||||
|
||||
/* USER CODE END SysTick_IRQn 0 */ |
||||
HAL_IncTick(); |
||||
HAL_SYSTICK_IRQHandler(); |
||||
/* USER CODE BEGIN SysTick_IRQn 1 */ |
||||
|
||||
/* USER CODE END SysTick_IRQn 1 */ |
||||
} |
||||
|
||||
/******************************************************************************/ |
||||
/* STM32L0xx Peripheral Interrupt Handlers */ |
||||
/* Add here the Interrupt Handlers for the used peripherals. */ |
||||
/* For the available peripheral interrupt handler names, */ |
||||
/* please refer to the startup file (startup_stm32l0xx.s). */ |
||||
/******************************************************************************/ |
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,13 @@ |
||||
#n |
||||
#t__HAL_RCC_SYSCFG_CLK_ENABLE(); |
||||
#t__HAL_RCC_PWR_CLK_ENABLE(); |
||||
#n |
||||
#t/* System interrupt init*/ |
||||
#t/* SVC_IRQn interrupt configuration */ |
||||
#tNVIC_SetPriority(SVC_IRQn, 0); |
||||
#t/* PendSV_IRQn interrupt configuration */ |
||||
#tNVIC_SetPriority(PendSV_IRQn, 0); |
||||
#t/* SysTick_IRQn interrupt configuration */ |
||||
#tNVIC_SetPriority(SysTick_IRQn, 0); |
||||
#n |
||||
#n |
||||
@ -0,0 +1,285 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file system_stm32l0xx.c |
||||
* @author MCD Application Team |
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. |
||||
* |
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application: |
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside |
||||
* the "startup_stm32l0xx.s" file. |
||||
* |
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters. |
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
||||
* be called whenever the core clock is changed |
||||
* during program execution. |
||||
* |
||||
* |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup stm32l0xx_system
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @addtogroup STM32L0xx_System_Private_Includes
|
||||
* @{ |
||||
*/ |
||||
|
||||
#include "stm32l0xx.h" |
||||
|
||||
#if !defined (HSE_VALUE) |
||||
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ |
||||
#endif /* HSE_VALUE */ |
||||
|
||||
#if !defined (MSI_VALUE) |
||||
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/ |
||||
#endif /* MSI_VALUE */ |
||||
|
||||
#if !defined (HSI_VALUE) |
||||
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ |
||||
#endif /* HSI_VALUE */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Private_Defines
|
||||
* @{ |
||||
*/ |
||||
/************************* Miscellaneous Configuration ************************/ |
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */ |
||||
/* #define VECT_TAB_SRAM */ |
||||
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. |
||||
This value must be a multiple of 0x200. */ |
||||
/******************************************************************************/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Private_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Private_Variables
|
||||
* @{ |
||||
*/ |
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate() |
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there |
||||
is no need to call the 2 first functions listed above, since SystemCoreClock |
||||
variable is updated automatically. |
||||
*/ |
||||
uint32_t SystemCoreClock = 2000000U; |
||||
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; |
||||
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; |
||||
const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Private_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system. |
||||
* @param None |
||||
* @retval None |
||||
*/ |
||||
void SystemInit (void) |
||||
{
|
||||
/*!< Set MSION bit */ |
||||
RCC->CR |= (uint32_t)0x00000100U; |
||||
|
||||
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ |
||||
RCC->CFGR &= (uint32_t) 0x88FF400CU; |
||||
|
||||
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ |
||||
RCC->CR &= (uint32_t)0xFEF6FFF6U; |
||||
|
||||
/*!< Reset HSI48ON bit */ |
||||
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; |
||||
|
||||
/*!< Reset HSEBYP bit */ |
||||
RCC->CR &= (uint32_t)0xFFFBFFFFU; |
||||
|
||||
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ |
||||
RCC->CFGR &= (uint32_t)0xFF02FFFFU; |
||||
|
||||
/*!< Disable all interrupts */ |
||||
RCC->CIER = 0x00000000U; |
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/ |
||||
#ifdef VECT_TAB_SRAM |
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
||||
#else |
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
||||
#endif |
||||
} |
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock according to Clock Register Values |
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can |
||||
* be used by the user application to setup the SysTick timer or configure |
||||
* other parameters. |
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called |
||||
* to update SystemCoreClock variable value. Otherwise, any configuration |
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source: |
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
|
||||
* value as defined by the MSI range. |
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors. |
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value |
||||
* 16 MHz) but the real value may vary depending on the variations |
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value |
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real |
||||
* frequency of the crystal used. Otherwise, this function may |
||||
* have wrong result. |
||||
*
|
||||
* - The result of this function could be not correct when using fractional |
||||
* value for HSE crystal. |
||||
* @param None |
||||
* @retval None |
||||
*/ |
||||
void SystemCoreClockUpdate (void) |
||||
{ |
||||
uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; |
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/ |
||||
tmp = RCC->CFGR & RCC_CFGR_SWS; |
||||
|
||||
switch (tmp) |
||||
{ |
||||
case 0x00U: /* MSI used as system clock */ |
||||
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; |
||||
SystemCoreClock = (32768U * (1U << (msirange + 1U))); |
||||
break; |
||||
case 0x04U: /* HSI used as system clock */ |
||||
SystemCoreClock = HSI_VALUE; |
||||
break; |
||||
case 0x08U: /* HSE used as system clock */ |
||||
SystemCoreClock = HSE_VALUE; |
||||
break; |
||||
case 0x0CU: /* PLL used as system clock */ |
||||
/* Get PLL clock source and multiplication factor ----------------------*/ |
||||
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; |
||||
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; |
||||
pllmul = PLLMulTable[(pllmul >> 18U)]; |
||||
plldiv = (plldiv >> 22U) + 1U; |
||||
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
||||
|
||||
if (pllsource == 0x00U) |
||||
{ |
||||
/* HSI oscillator clock selected as PLL clock entry */ |
||||
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); |
||||
} |
||||
else |
||||
{ |
||||
/* HSE selected as PLL clock entry */ |
||||
SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); |
||||
} |
||||
break; |
||||
default: /* MSI used as system clock */ |
||||
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; |
||||
SystemCoreClock = (32768U * (1U << (msirange + 1U))); |
||||
break; |
||||
} |
||||
/* Compute HCLK clock frequency --------------------------------------------*/ |
||||
/* Get HCLK prescaler */ |
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; |
||||
/* HCLK clock frequency */ |
||||
SystemCoreClock >>= tmp; |
||||
} |
||||
|
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,200 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* File Name : USART.c |
||||
* Description : This file provides code for the configuration |
||||
* of the USART instances. |
||||
****************************************************************************** |
||||
** This notice applies to any and all portions of this file |
||||
* that are not between comment pairs USER CODE BEGIN and |
||||
* USER CODE END. Other portions of this file, whether
|
||||
* inserted by the user or by software development tools |
||||
* are owned by their respective copyright owners. |
||||
* |
||||
* COPYRIGHT(c) 2017 STMicroelectronics |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "usart.h" |
||||
|
||||
#include "gpio.h" |
||||
|
||||
/* USER CODE BEGIN 0 */ |
||||
|
||||
/* USER CODE END 0 */ |
||||
|
||||
UART_HandleTypeDef huart1; |
||||
UART_HandleTypeDef huart2; |
||||
|
||||
/* USART1 init function */ |
||||
|
||||
void MX_USART1_UART_Init(void) |
||||
{ |
||||
|
||||
huart1.Instance = USART1; |
||||
huart1.Init.BaudRate = 115200; |
||||
huart1.Init.WordLength = UART_WORDLENGTH_7B; |
||||
huart1.Init.StopBits = UART_STOPBITS_1; |
||||
huart1.Init.Parity = UART_PARITY_NONE; |
||||
huart1.Init.Mode = UART_MODE_TX_RX; |
||||
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; |
||||
huart1.Init.OverSampling = UART_OVERSAMPLING_16; |
||||
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; |
||||
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; |
||||
if (HAL_UART_Init(&huart1) != HAL_OK) |
||||
{ |
||||
_Error_Handler(__FILE__, __LINE__); |
||||
} |
||||
|
||||
} |
||||
/* USART2 init function */ |
||||
|
||||
void MX_USART2_UART_Init(void) |
||||
{ |
||||
|
||||
huart2.Instance = USART2; |
||||
huart2.Init.BaudRate = 115200; |
||||
huart2.Init.WordLength = UART_WORDLENGTH_7B; |
||||
huart2.Init.StopBits = UART_STOPBITS_1; |
||||
huart2.Init.Parity = UART_PARITY_NONE; |
||||
huart2.Init.Mode = UART_MODE_TX_RX; |
||||
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; |
||||
huart2.Init.OverSampling = UART_OVERSAMPLING_16; |
||||
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; |
||||
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; |
||||
if (HAL_UART_Init(&huart2) != HAL_OK) |
||||
{ |
||||
_Error_Handler(__FILE__, __LINE__); |
||||
} |
||||
|
||||
} |
||||
|
||||
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) |
||||
{ |
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct; |
||||
if(uartHandle->Instance==USART1) |
||||
{ |
||||
/* USER CODE BEGIN USART1_MspInit 0 */ |
||||
|
||||
/* USER CODE END USART1_MspInit 0 */ |
||||
/* USART1 clock enable */ |
||||
__HAL_RCC_USART1_CLK_ENABLE(); |
||||
|
||||
/**USART1 GPIO Configuration
|
||||
PA9 ------> USART1_TX |
||||
PA10 ------> USART1_RX
|
||||
*/ |
||||
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
||||
GPIO_InitStruct.Pull = GPIO_PULLUP; |
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
||||
GPIO_InitStruct.Alternate = GPIO_AF4_USART1; |
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); |
||||
|
||||
/* USER CODE BEGIN USART1_MspInit 1 */ |
||||
|
||||
/* USER CODE END USART1_MspInit 1 */ |
||||
} |
||||
else if(uartHandle->Instance==USART2) |
||||
{ |
||||
/* USER CODE BEGIN USART2_MspInit 0 */ |
||||
|
||||
/* USER CODE END USART2_MspInit 0 */ |
||||
/* USART2 clock enable */ |
||||
__HAL_RCC_USART2_CLK_ENABLE(); |
||||
|
||||
/**USART2 GPIO Configuration
|
||||
PA2 ------> USART2_TX |
||||
PA3 ------> USART2_RX
|
||||
*/ |
||||
GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; |
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
||||
GPIO_InitStruct.Pull = GPIO_PULLUP; |
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
||||
GPIO_InitStruct.Alternate = GPIO_AF4_USART2; |
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); |
||||
|
||||
/* USER CODE BEGIN USART2_MspInit 1 */ |
||||
|
||||
/* USER CODE END USART2_MspInit 1 */ |
||||
} |
||||
} |
||||
|
||||
void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) |
||||
{ |
||||
|
||||
if(uartHandle->Instance==USART1) |
||||
{ |
||||
/* USER CODE BEGIN USART1_MspDeInit 0 */ |
||||
|
||||
/* USER CODE END USART1_MspDeInit 0 */ |
||||
/* Peripheral clock disable */ |
||||
__HAL_RCC_USART1_CLK_DISABLE(); |
||||
|
||||
/**USART1 GPIO Configuration
|
||||
PA9 ------> USART1_TX |
||||
PA10 ------> USART1_RX
|
||||
*/ |
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); |
||||
|
||||
/* USER CODE BEGIN USART1_MspDeInit 1 */ |
||||
|
||||
/* USER CODE END USART1_MspDeInit 1 */ |
||||
} |
||||
else if(uartHandle->Instance==USART2) |
||||
{ |
||||
/* USER CODE BEGIN USART2_MspDeInit 0 */ |
||||
|
||||
/* USER CODE END USART2_MspDeInit 0 */ |
||||
/* Peripheral clock disable */ |
||||
__HAL_RCC_USART2_CLK_DISABLE(); |
||||
|
||||
/**USART2 GPIO Configuration
|
||||
PA2 ------> USART2_TX |
||||
PA3 ------> USART2_RX
|
||||
*/ |
||||
HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); |
||||
|
||||
/* USER CODE BEGIN USART2_MspDeInit 1 */ |
||||
|
||||
/* USER CODE END USART2_MspDeInit 1 */ |
||||
} |
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */ |
||||
|
||||
/* USER CODE END 1 */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,87 @@ |
||||
<?xml version="1.0" encoding="UTF-8"?> |
||||
<Project> |
||||
<ProjectName>/home/ondra/spd/cubeproject/nortos/proj/\proj</ProjectName> |
||||
<CMSIS>../Drivers/CMSIS</CMSIS> |
||||
<HAL_Driver>/home/ondra/STM32Cube/Repository//STM32Cube_FW_L0_V1.10.0/Drivers/CMSIS</HAL_Driver> |
||||
|
||||
<Toolchain>SW4STM32</Toolchain> |
||||
<Version>0</Version> |
||||
|
||||
<filestoremove> |
||||
<file> |
||||
</file> |
||||
</filestoremove> |
||||
|
||||
<inctoremove> |
||||
<Aincludes> |
||||
<include></include> |
||||
</Aincludes> |
||||
<Cincludes> |
||||
</Cincludes> |
||||
</inctoremove> |
||||
|
||||
<configs> |
||||
<config> |
||||
<name>proj</name> |
||||
<device>STM32L073RZTx</device> |
||||
<heapSize>0x200</heapSize> |
||||
<stackSize>0x400</stackSize> |
||||
|
||||
<board>NUCLEO-L073RZ</board> |
||||
|
||||
<usedDebug>true</usedDebug> |
||||
<debugprobe></debugprobe> |
||||
<optimization>6</optimization> |
||||
<icfloc>1</icfloc> |
||||
<Adefines> |
||||
<define></define> |
||||
</Adefines> |
||||
|
||||
<UsedFreeRTOS></UsedFreeRTOS> |
||||
<Aincludes> |
||||
|
||||
|
||||
<include></include> |
||||
</Aincludes> |
||||
<Cdefines> |
||||
<define>__weak="__attribute__((weak))"</define> |
||||
<define>__packed="__attribute__((__packed__))"</define> |
||||
</Cdefines> |
||||
<definestoremove> |
||||
<Adefines> |
||||
<define></define> |
||||
</Adefines> |
||||
<Cdefines> |
||||
<define>USE_FULL_LL_DRIVER</define> |
||||
<define>MBEDTLS_CONFIG_FILE="mbedtls_config.h"</define> |
||||
<define>_TIMEVAL_DEFINED</define> |
||||
<define>_SYS_TIME_H_</define> |
||||
</Cdefines> |
||||
</definestoremove> |
||||
|
||||
<Cincludes> |
||||
<include>../Inc</include> |
||||
<include>../Drivers/STM32L0xx_HAL_Driver/Inc</include> |
||||
<include>../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy</include> |
||||
<include>../Drivers/CMSIS/Device/ST/STM32L0xx/Include</include> |
||||
<include>../Drivers/CMSIS/Include</include> |
||||
|
||||
</Cincludes> |
||||
</config> |
||||
</configs> |
||||
|
||||
<underRoot>true</underRoot> |
||||
<copyAsReference>false</copyAsReference> |
||||
<sourceEntries> |
||||
<sourceEntry> |
||||
<name>Inc</name> |
||||
</sourceEntry> |
||||
<sourceEntry> |
||||
<name>Src</name> |
||||
</sourceEntry> |
||||
<sourceEntry> |
||||
<name>Drivers</name> |
||||
</sourceEntry> |
||||
</sourceEntries> |
||||
|
||||
</Project> |
||||
@ -0,0 +1,28 @@ |
||||
# This is an NUCLEO-L073RZ board with a single STM32L073RZTx chip |
||||
# |
||||
# Generated by System Workbench for STM32 |
||||
# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s) |
||||
|
||||
source [find interface/stlink.cfg] |
||||
|
||||
set WORKAREASIZE 0x5000 |
||||
|
||||
transport select "hla_swd" |
||||
|
||||
set CHIPNAME STM32L073RZTx |
||||
|
||||
# Enable debug when in low power modes |
||||
set ENABLE_LOW_POWER 1 |
||||
|
||||
# Stop Watchdog counters when halt |
||||
set STOP_WATCHDOG 1 |
||||
|
||||
# STlink Debug clock frequency |
||||
set CLOCK_FREQ 4000 |
||||
|
||||
# use hardware reset, connect under reset |
||||
# connect_assert_srst needed if low power mode application running (WFI...) |
||||
reset_config srst_only srst_nogate connect_assert_srst |
||||
set CONNECT_UNDER_RESET 1 |
||||
|
||||
source [find target/stm32l0x.cfg] |
||||
@ -0,0 +1,184 @@ |
||||
#MicroXplorer Configuration settings - do not modify |
||||
File.Version=6 |
||||
I2C1.IPParameters=Timing |
||||
I2C1.Timing=0x00506682 |
||||
KeepUserPlacement=true |
||||
Mcu.Family=STM32L0 |
||||
Mcu.IP0=I2C1 |
||||
Mcu.IP1=NVIC |
||||
Mcu.IP2=RCC |
||||
Mcu.IP3=RTC |
||||
Mcu.IP4=SPI1 |
||||
Mcu.IP5=SYS |
||||
Mcu.IP6=USART1 |
||||
Mcu.IP7=USART2 |
||||
Mcu.IPNb=8 |
||||
Mcu.Name=STM32L073R(B-Z)Tx |
||||
Mcu.Package=LQFP64 |
||||
Mcu.Pin0=PC13 |
||||
Mcu.Pin1=PC14-OSC32_IN |
||||
Mcu.Pin10=PA9 |
||||
Mcu.Pin11=PA10 |
||||
Mcu.Pin12=PA13 |
||||
Mcu.Pin13=PA14 |
||||
Mcu.Pin14=PB8 |
||||
Mcu.Pin15=PB9 |
||||
Mcu.Pin16=VP_RTC_VS_RTC_Activate |
||||
Mcu.Pin17=VP_SYS_VS_Systick |
||||
Mcu.Pin2=PC15-OSC32_OUT |
||||
Mcu.Pin3=PH0-OSC_IN |
||||
Mcu.Pin4=PA2 |
||||
Mcu.Pin5=PA3 |
||||
Mcu.Pin6=PA4 |
||||
Mcu.Pin7=PA5 |
||||
Mcu.Pin8=PA6 |
||||
Mcu.Pin9=PA7 |
||||
Mcu.PinsNb=18 |
||||
Mcu.UserConstants= |
||||
Mcu.UserName=STM32L073RZTx |
||||
MxCube.Version=4.23.0 |
||||
MxDb.Version=DB.4.0.230 |
||||
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:false |
||||
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:false |
||||
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false |
||||
NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false |
||||
NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:true |
||||
PA10.Mode=Asynchronous |
||||
PA10.Signal=USART1_RX |
||||
PA13.GPIOParameters=GPIO_Label |
||||
PA13.GPIO_Label=TMS |
||||
PA13.Locked=true |
||||
PA13.Signal=SYS_SWDIO |
||||
PA14.GPIOParameters=GPIO_Label |
||||
PA14.GPIO_Label=TCK |
||||
PA14.Locked=true |
||||
PA14.Signal=SYS_SWCLK |
||||
PA2.GPIOParameters=GPIO_Label |
||||
PA2.GPIO_Label=USART_TX |
||||
PA2.Locked=true |
||||
PA2.Mode=Asynchronous |
||||
PA2.Signal=USART2_TX |
||||
PA3.GPIOParameters=GPIO_Label |
||||
PA3.GPIO_Label=USART_RX |
||||
PA3.Locked=true |
||||
PA3.Mode=Asynchronous |
||||
PA3.Signal=USART2_RX |
||||
PA4.Mode=NSS_Signal_Hard_Output |
||||
PA4.Signal=SPI1_NSS |
||||
PA5.Locked=true |
||||
PA5.Mode=Full_Duplex_Master |
||||
PA5.Signal=SPI1_SCK |
||||
PA6.Mode=Full_Duplex_Master |
||||
PA6.Signal=SPI1_MISO |
||||
PA7.Mode=Full_Duplex_Master |
||||
PA7.Signal=SPI1_MOSI |
||||
PA9.Mode=Asynchronous |
||||
PA9.Signal=USART1_TX |
||||
PB8.Locked=true |
||||
PB8.Mode=I2C |
||||
PB8.Signal=I2C1_SCL |
||||
PB9.Locked=true |
||||
PB9.Mode=I2C |
||||
PB9.Signal=I2C1_SDA |
||||
PC13.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI |
||||
PC13.GPIO_Label=B1 [Blue PushButton] |
||||
PC13.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING |
||||
PC13.Locked=true |
||||
PC13.Signal=GPXTI13 |
||||
PC14-OSC32_IN.Locked=true |
||||
PC14-OSC32_IN.Mode=LSE-External-Oscillator |
||||
PC14-OSC32_IN.Signal=RCC_OSC32_IN |
||||
PC15-OSC32_OUT.Locked=true |
||||
PC15-OSC32_OUT.Mode=LSE-External-Oscillator |
||||
PC15-OSC32_OUT.Signal=RCC_OSC32_OUT |
||||
PCC.Checker=true |
||||
PCC.Line=STM32L0x3 |
||||
PCC.MCU=STM32L073R(B-Z)Tx |
||||
PCC.PartNumber=STM32L073RZTx |
||||
PCC.Seq0=0 |
||||
PCC.Series=STM32L0 |
||||
PCC.Temperature=25 |
||||
PCC.Vdd=3.0 |
||||
PH0-OSC_IN.GPIOParameters=GPIO_Label |
||||
PH0-OSC_IN.GPIO_Label=MCO |
||||
PH0-OSC_IN.Locked=true |
||||
PH0-OSC_IN.Mode=HSE-External-Clock-Source |
||||
PH0-OSC_IN.Signal=RCC_OSC_IN |
||||
PinOutPanel.RotationAngle=0 |
||||
ProjectManager.AskForMigrate=true |
||||
ProjectManager.BackupPrevious=false |
||||
ProjectManager.CompilerOptimize=2 |
||||
ProjectManager.ComputerToolchain=false |
||||
ProjectManager.CoupleFile=true |
||||
ProjectManager.CustomerFirmwarePackage=/home/ondra/STM32Cube/Repository/STM32Cube_FW_L0_V1.10.0 |
||||
ProjectManager.DefaultFWLocation=true |
||||
ProjectManager.DeletePrevious=true |
||||
ProjectManager.DeviceId=STM32L073RZTx |
||||
ProjectManager.FirmwarePackage=STM32Cube FW_L0 V1.10.0 |
||||
ProjectManager.FreePins=true |
||||
ProjectManager.HalAssertFull=false |
||||
ProjectManager.HeapSize=0x200 |
||||
ProjectManager.KeepUserCode=true |
||||
ProjectManager.LastFirmware=true |
||||
ProjectManager.LibraryCopy=1 |
||||
ProjectManager.PreviousToolchain=SW4STM32 |
||||
ProjectManager.ProjectBuild=false |
||||
ProjectManager.ProjectFileName=proj.ioc |
||||
ProjectManager.ProjectName=proj |
||||
ProjectManager.StackSize=0x400 |
||||
ProjectManager.TargetToolchain=SW4STM32 |
||||
ProjectManager.ToolChainLocation= |
||||
ProjectManager.UnderRoot=true |
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL,2-SystemClock_Config-RCC-false-HAL,3-MX_I2C1_Init-I2C1-false-HAL,4-MX_SPI1_Init-SPI1-false-HAL,5-MX_USART1_UART_Init-USART1-false-HAL,6-MX_USART2_UART_Init-USART2-false-HAL,7-MX_RTC_Init-RTC-false-HAL |
||||
RCC.48CLKFreq_Value=24000000 |
||||
RCC.AHBFreq_Value=24000000 |
||||
RCC.APB1Freq_Value=24000000 |
||||
RCC.APB1TimFreq_Value=24000000 |
||||
RCC.APB2Freq_Value=24000000 |
||||
RCC.APB2TimFreq_Value=24000000 |
||||
RCC.FCLKCortexFreq_Value=24000000 |
||||
RCC.FamilyName=M |
||||
RCC.HCLKFreq_Value=24000000 |
||||
RCC.HSE_VALUE=8000000 |
||||
RCC.HSI16_VALUE=16000000 |
||||
RCC.HSI48_VALUE=48000000 |
||||
RCC.HSI_VALUE=16000000 |
||||
RCC.I2C1Freq_Value=24000000 |
||||
RCC.I2C3Freq_Value=24000000 |
||||
RCC.IPParameters=48CLKFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI16_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,USART1Freq_Value,USART2Freq_Value,VCOOutputFreq_Value,WatchDogFreq_Value |
||||
RCC.LCDFreq_Value=37000 |
||||
RCC.LPTIMFreq_Value=24000000 |
||||
RCC.LPUARTFreq_Value=24000000 |
||||
RCC.LSI_VALUE=37000 |
||||
RCC.MCOPinFreq_Value=24000000 |
||||
RCC.MSI_VALUE=2097000 |
||||
RCC.PLLCLKFreq_Value=24000000 |
||||
RCC.PWRFreq_Value=24000000 |
||||
RCC.RTCFreq_Value=37000 |
||||
RCC.RTCHSEDivFreq_Value=4000000 |
||||
RCC.SYSCLKFreq_VALUE=24000000 |
||||
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK |
||||
RCC.TIMFreq_Value=24000000 |
||||
RCC.TimerFreq_Value=24000000 |
||||
RCC.USART1Freq_Value=24000000 |
||||
RCC.USART2Freq_Value=24000000 |
||||
RCC.VCOOutputFreq_Value=48000000 |
||||
RCC.WatchDogFreq_Value=37000 |
||||
SH.GPXTI13.0=GPIO_EXTI13 |
||||
SH.GPXTI13.ConfNb=1 |
||||
SPI1.CalculateBaudRate=12.0 MBits/s |
||||
SPI1.Direction=SPI_DIRECTION_2LINES |
||||
SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS |
||||
SPI1.Mode=SPI_MODE_MASTER |
||||
SPI1.VirtualNSS=VM_NSSHARD |
||||
SPI1.VirtualType=VM_MASTER |
||||
USART1.IPParameters=VirtualMode-Asynchronous |
||||
USART1.VirtualMode-Asynchronous=VM_ASYNC |
||||
USART2.IPParameters=VirtualMode-Asynchronous |
||||
USART2.VirtualMode-Asynchronous=VM_ASYNC |
||||
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled |
||||
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate |
||||
VP_SYS_VS_Systick.Mode=SysTick |
||||
VP_SYS_VS_Systick.Signal=SYS_VS_Systick |
||||
board=NUCLEO-L073RZ |
||||
boardIOC=true |
||||
@ -0,0 +1,305 @@ |
||||
/** |
||||
****************************************************************************** |
||||
* @file startup_stm32l073xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32L073xx Devices vector table for Atollic TrueSTUDIO toolchain.
|
||||
* This module performs: |
||||
* - Set the initial SP |
||||
* - Set the initial PC == Reset_Handler, |
||||
* - Set the vector table entries with the exceptions ISR address |
||||
* - Branches to main in the C library (which eventually |
||||
* calls main()). |
||||
* After Reset the Cortex-M0+ processor is in Thread mode, |
||||
* priority is Privileged, and the Stack is set to Main. |
||||
****************************************************************************** |
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m0plus |
||||
.fpu softvfp
|
||||
.thumb |
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section. |
||||
defined in linker script */ |
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */ |
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */ |
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */ |
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */ |
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler |
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function |
||||
Reset_Handler:
|
||||
ldr r0, =_estack |
||||
mov sp, r0 /* set stack pointer */ |
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */ |
||||
movs r1, #0 |
||||
b LoopCopyDataInit |
||||
|
||||
CopyDataInit: |
||||
ldr r3, =_sidata |
||||
ldr r3, [r3, r1] |
||||
str r3, [r0, r1] |
||||
adds r1, r1, #4 |
||||
|
||||
LoopCopyDataInit: |
||||
ldr r0, =_sdata |
||||
ldr r3, =_edata |
||||
adds r2, r0, r1 |
||||
cmp r2, r3 |
||||
bcc CopyDataInit |
||||
ldr r2, =_sbss |
||||
b LoopFillZerobss |
||||
/* Zero fill the bss segment. */ |
||||
FillZerobss: |
||||
movs r3, #0 |
||||
str r3, [r2] |
||||
adds r2, r2, #4 |
||||
|
||||
|
||||
LoopFillZerobss: |
||||
ldr r3, = _ebss |
||||
cmp r2, r3 |
||||
bcc FillZerobss |
||||
|
||||
/* Call the clock system intitialization function.*/ |
||||
bl SystemInit |
||||
/* Call static constructors */ |
||||
bl __libc_init_array |
||||
/* Call the application's entry point.*/ |
||||
bl main |
||||
|
||||
LoopForever: |
||||
b LoopForever |
||||
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler |
||||
|
||||
/** |
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving |
||||
* the system state for examination by a debugger. |
||||
* |
||||
* @param None
|
||||
* @retval : None
|
||||
*/ |
||||
.section .text.Default_Handler,"ax",%progbits |
||||
Default_Handler: |
||||
Infinite_Loop: |
||||
b Infinite_Loop |
||||
.size Default_Handler, .-Default_Handler |
||||
/****************************************************************************** |
||||
* |
||||
* The minimal vector table for a Cortex M0. Note that the proper constructs |
||||
* must be placed on this to ensure that it ends up at physical address |
||||
* 0x0000.0000. |
||||
* |
||||
******************************************************************************/ |
||||
.section .isr_vector,"a",%progbits |
||||
.type g_pfnVectors, %object |
||||
.size g_pfnVectors, .-g_pfnVectors |
||||
|
||||
|
||||
g_pfnVectors: |
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler /* Window WatchDog */ |
||||
.word PVD_IRQHandler /* PVD through EXTI Line detection */ |
||||
.word RTC_IRQHandler /* RTC through the EXTI line */ |
||||
.word FLASH_IRQHandler /* FLASH */ |
||||
.word RCC_CRS_IRQHandler /* RCC and CRS */ |
||||
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ |
||||
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ |
||||
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ |
||||
.word TSC_IRQHandler /* TSC */ |
||||
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ |
||||
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ |
||||
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/ |
||||
.word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ |
||||
.word LPTIM1_IRQHandler /* LPTIM1 */ |
||||
.word USART4_5_IRQHandler /* USART4 and USART 5 */ |
||||
.word TIM2_IRQHandler /* TIM2 */ |
||||
.word TIM3_IRQHandler /* TIM3 */ |
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC */ |
||||
.word TIM7_IRQHandler /* TIM7 */ |
||||
.word 0 /* Reserved */ |
||||
.word TIM21_IRQHandler /* TIM21 */ |
||||
.word I2C3_IRQHandler /* I2C3 */ |
||||
.word TIM22_IRQHandler /* TIM22 */ |
||||
.word I2C1_IRQHandler /* I2C1 */ |
||||
.word I2C2_IRQHandler /* I2C2 */ |
||||
.word SPI1_IRQHandler /* SPI1 */ |
||||
.word SPI2_IRQHandler /* SPI2 */ |
||||
.word USART1_IRQHandler /* USART1 */ |
||||
.word USART2_IRQHandler /* USART2 */ |
||||
.word RNG_LPUART1_IRQHandler /* RNG and LPUART1 */ |
||||
.word LCD_IRQHandler /* LCD */ |
||||
.word USB_IRQHandler /* USB */ |
||||
|
||||
/******************************************************************************* |
||||
* |
||||
* Provide weak aliases for each Exception handler to the Default_Handler. |
||||
* As they are weak aliases, any function with the same name will override |
||||
* this definition. |
||||
* |
||||
*******************************************************************************/ |
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler |
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler |
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler |
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler |
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler |
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler |
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler |
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler |
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler |
||||
|
||||
.weak RCC_CRS_IRQHandler
|
||||
.thumb_set RCC_CRS_IRQHandler,Default_Handler |
||||
|
||||
.weak EXTI0_1_IRQHandler
|
||||
.thumb_set EXTI0_1_IRQHandler,Default_Handler |
||||
|
||||
.weak EXTI2_3_IRQHandler
|
||||
.thumb_set EXTI2_3_IRQHandler,Default_Handler |
||||
|
||||
.weak EXTI4_15_IRQHandler
|
||||
.thumb_set EXTI4_15_IRQHandler,Default_Handler |
||||
|
||||
.weak TSC_IRQHandler
|
||||
.thumb_set TSC_IRQHandler,Default_Handler |
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler |
||||
|
||||
.weak DMA1_Channel2_3_IRQHandler
|
||||
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler |
||||
|
||||
.weak DMA1_Channel4_5_6_7_IRQHandler
|
||||
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler |
||||
|
||||
.weak ADC1_COMP_IRQHandler
|
||||
.thumb_set ADC1_COMP_IRQHandler,Default_Handler |
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler |
||||
|
||||
.weak USART4_5_IRQHandler
|
||||
.thumb_set USART4_5_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM21_IRQHandler
|
||||
.thumb_set TIM21_IRQHandler,Default_Handler |
||||
|
||||
.weak I2C3_IRQHandler
|
||||
.thumb_set I2C3_IRQHandler,Default_Handler |
||||
|
||||
.weak TIM22_IRQHandler
|
||||
.thumb_set TIM22_IRQHandler,Default_Handler |
||||
|
||||
.weak I2C1_IRQHandler
|
||||
.thumb_set I2C1_IRQHandler,Default_Handler |
||||
|
||||
.weak I2C2_IRQHandler
|
||||
.thumb_set I2C2_IRQHandler,Default_Handler |
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler |
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler |
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler |
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler |
||||
|
||||
.weak RNG_LPUART1_IRQHandler
|
||||
.thumb_set RNG_LPUART1_IRQHandler,Default_Handler |
||||
|
||||
.weak LCD_IRQHandler
|
||||
.thumb_set LCD_IRQHandler,Default_Handler |
||||
|
||||
.weak USB_IRQHandler
|
||||
.thumb_set USB_IRQHandler,Default_Handler |
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
Loading…
Reference in new issue