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@ -0,0 +1,14 @@ |
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[PreviousGenFiles] |
||||
HeaderPath=/home/ondra/spd/cubeproject/nortos/proj/Inc |
||||
HeaderFiles=gpio.h;i2c.h;rtc.h;spi.h;usart.h;stm32l0xx_it.h;stm32l0xx_hal_conf.h;main.h; |
||||
SourcePath=/home/ondra/spd/cubeproject/nortos/proj/Src |
||||
SourceFiles=gpio.c;i2c.c;rtc.c;spi.c;usart.c;stm32l0xx_it.c;stm32l0xx_hal_msp.c;main.c; |
||||
|
||||
[PreviousLibFiles] |
||||
LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/arm_common_tables.h; |
||||
|
||||
[PreviousUsedSW4STM32Files] |
||||
SourceFiles=../Src/main.c;../Src/gpio.c;../Src/i2c.c;../Src/rtc.c;../Src/spi.c;../Src/usart.c;../Src/stm32l0xx_it.c;../Src/stm32l0xx_hal_msp.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;../Src/system_stm32l0xx.c;../Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;../Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l073xx.s; |
||||
HeaderPath=../Drivers/STM32L0xx_HAL_Driver/Inc;../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32L0xx/Include;../Drivers/CMSIS/Include;../Inc; |
||||
CDefines=__weak:"__attribute__((weak))";__packed:"__attribute__((__packed__))"; |
||||
|
||||
@ -0,0 +1,30 @@ |
||||
<?xml version="1.0" encoding="UTF-8"?> |
||||
<projectDescription> |
||||
<name>proj</name> |
||||
<comment /> |
||||
<projects> |
||||
</projects> |
||||
<buildSpec> |
||||
<buildCommand> |
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> |
||||
<triggers>clean,full,incremental,</triggers> |
||||
<arguments> |
||||
</arguments> |
||||
</buildCommand> |
||||
<buildCommand> |
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> |
||||
<triggers>full,incremental,</triggers> |
||||
<arguments> |
||||
</arguments> |
||||
</buildCommand> |
||||
</buildSpec> |
||||
<natures> |
||||
<nature>org.eclipse.cdt.core.cnature</nature> |
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> |
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> |
||||
<nature>fr.ac6.mcu.ide.core.MCUProjectNature</nature> |
||||
</natures> |
||||
<linkedResources> |
||||
|
||||
</linkedResources> |
||||
</projectDescription> |
||||
@ -0,0 +1,27 @@ |
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?> |
||||
<project> |
||||
<configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1636346117" name="Debug"> |
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> |
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> |
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> |
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> |
||||
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/> |
||||
<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1176636128779449975" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> |
||||
<language-scope id="org.eclipse.cdt.core.gcc"/> |
||||
<language-scope id="org.eclipse.cdt.core.g++"/> |
||||
</provider> |
||||
</extension> |
||||
</configuration> |
||||
<configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.release.2060462303" name="Release"> |
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> |
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/> |
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/> |
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> |
||||
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/> |
||||
<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1176636128779449975" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true"> |
||||
<language-scope id="org.eclipse.cdt.core.gcc"/> |
||||
<language-scope id="org.eclipse.cdt.core.g++"/> |
||||
</provider> |
||||
</extension> |
||||
</configuration> |
||||
</project> |
||||
@ -0,0 +1,73 @@ |
||||
eclipse.preferences.version=1 |
||||
fr.ac6.mcu.ide.source.checker.libnano.problem=Error |
||||
fr.ac6.mcu.ide.source.checker.libnano.problem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Float formatting support\\")"} |
||||
org.eclipse.cdt.codan.checkers.errnoreturn=Warning |
||||
org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} |
||||
org.eclipse.cdt.codan.checkers.errreturnvalue=Error |
||||
org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} |
||||
org.eclipse.cdt.codan.checkers.nocommentinside=-Error |
||||
org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} |
||||
org.eclipse.cdt.codan.checkers.nolinecomment=-Error |
||||
org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} |
||||
org.eclipse.cdt.codan.checkers.noreturn=Error |
||||
org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} |
||||
org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error |
||||
org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false} |
||||
org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()} |
||||
org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true} |
||||
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error |
||||
org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info |
||||
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} |
||||
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning |
||||
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning |
||||
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()} |
||||
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false} |
||||
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false} |
||||
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"} |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning |
||||
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} |
||||
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error |
||||
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} |
||||
@ -0,0 +1,93 @@ |
||||
cmake_minimum_required(VERSION 3.9) |
||||
project(proj) |
||||
|
||||
set(CMAKE_CXX_STANDARD 11) |
||||
|
||||
set(SOURCE_FILES |
||||
Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h |
||||
Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h |
||||
Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h |
||||
Drivers/CMSIS/Include/arm_common_tables.h |
||||
Drivers/CMSIS/Include/arm_const_structs.h |
||||
Drivers/CMSIS/Include/arm_math.h |
||||
Drivers/CMSIS/Include/cmsis_armcc.h |
||||
Drivers/CMSIS/Include/cmsis_armcc_V6.h |
||||
Drivers/CMSIS/Include/cmsis_gcc.h |
||||
Drivers/CMSIS/Include/core_cm0.h |
||||
Drivers/CMSIS/Include/core_cm0plus.h |
||||
Drivers/CMSIS/Include/core_cm3.h |
||||
Drivers/CMSIS/Include/core_cm4.h |
||||
Drivers/CMSIS/Include/core_cm7.h |
||||
Drivers/CMSIS/Include/core_cmFunc.h |
||||
Drivers/CMSIS/Include/core_cmInstr.h |
||||
Drivers/CMSIS/Include/core_cmSimd.h |
||||
Drivers/CMSIS/Include/core_sc000.h |
||||
Drivers/CMSIS/Include/core_sc300.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h |
||||
Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c |
||||
Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c |
||||
Inc/gpio.h |
||||
Inc/i2c.h |
||||
Inc/main.h |
||||
Inc/rtc.h |
||||
Inc/spi.h |
||||
Inc/stm32l0xx_hal_conf.h |
||||
Inc/stm32l0xx_it.h |
||||
Inc/usart.h |
||||
Src/gpio.c |
||||
Src/i2c.c |
||||
Src/main.c |
||||
Src/rtc.c |
||||
Src/spi.c |
||||
Src/stm32l0xx_hal_msp.c |
||||
Src/stm32l0xx_it.c |
||||
Src/system_stm32l0xx.c |
||||
Src/usart.c) |
||||
|
||||
include_directories(Drivers/CMSIS/Device/ST/STM32L0xx/Include) |
||||
include_directories(Drivers/CMSIS/Include) |
||||
include_directories(Drivers/STM32L0xx_HAL_Driver/Inc) |
||||
include_directories(Drivers/STM32L0xx_HAL_Driver/Inc/Legacy) |
||||
include_directories(Inc) |
||||
|
||||
add_executable(proj ${SOURCE_FILES}) |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,241 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx.h |
||||
* @author MCD Application Team |
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for STM32L0xx devices.
|
||||
*
|
||||
* The file is the unique include file that the application programmer |
||||
* is using in the C source code, usually in main.c. This file contains: |
||||
* - Configuration section that allows to select: |
||||
* - The device used in the target application |
||||
* - To use or not the peripheral's drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral's registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER" |
||||
*
|
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup stm32l0xx
|
||||
* @{ |
||||
*/ |
||||
|
||||
#ifndef __STM32L0xx_H |
||||
#define __STM32L0xx_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif /* __cplusplus */ |
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @brief STM32 Family |
||||
*/ |
||||
#if !defined (STM32L0) |
||||
#define STM32L0 |
||||
#endif /* STM32L0 */ |
||||
|
||||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/ |
||||
|
||||
#if !defined (STM32L011xx) && !defined (STM32L021xx) && \ |
||||
!defined (STM32L031xx) && !defined (STM32L041xx) && \
|
||||
!defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
|
||||
!defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \
|
||||
!defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
|
||||
!defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \
|
||||
/* #define STM32L011xx */ |
||||
/* #define STM32L021xx */ |
||||
/* #define STM32L031xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */ |
||||
/* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */ |
||||
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */ |
||||
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */ |
||||
/* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */ |
||||
/* #define STM32L061xx */ /*!< */ |
||||
/* #define STM32L062xx */ /*!< STM32L062K8 */ |
||||
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
|
||||
/* #define STM32L071xx */ /*!< */ |
||||
/* #define STM32L072xx */ /*!< */ |
||||
/* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */ |
||||
/* #define STM32L081xx */ /*!< */ |
||||
/* #define STM32L082xx */ /*!< */ |
||||
/* #define STM32L083xx */ /*!< */
|
||||
#endif |
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor. |
||||
*/ |
||||
#if !defined (USE_HAL_DRIVER) |
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers. |
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/ |
||||
/*#define USE_HAL_DRIVER */ |
||||
#endif /* USE_HAL_DRIVER */ |
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.7.1 |
||||
*/ |
||||
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ |
||||
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ |
||||
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ |
||||
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ |
||||
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\ |
||||
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__STM32L0xx_CMSIS_VERSION_RC)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{ |
||||
*/ |
||||
#if defined(STM32L011xx) |
||||
#include "stm32l011xx.h" |
||||
#elif defined(STM32L021xx) |
||||
#include "stm32l021xx.h" |
||||
#elif defined(STM32L031xx) |
||||
#include "stm32l031xx.h" |
||||
#elif defined(STM32L041xx) |
||||
#include "stm32l041xx.h" |
||||
#elif defined(STM32L051xx) |
||||
#include "stm32l051xx.h" |
||||
#elif defined(STM32L052xx) |
||||
#include "stm32l052xx.h" |
||||
#elif defined(STM32L053xx) |
||||
#include "stm32l053xx.h" |
||||
#elif defined(STM32L062xx) |
||||
#include "stm32l062xx.h" |
||||
#elif defined(STM32L063xx) |
||||
#include "stm32l063xx.h" |
||||
#elif defined(STM32L061xx) |
||||
#include "stm32l061xx.h" |
||||
#elif defined(STM32L071xx) |
||||
#include "stm32l071xx.h" |
||||
#elif defined(STM32L072xx) |
||||
#include "stm32l072xx.h" |
||||
#elif defined(STM32L073xx) |
||||
#include "stm32l073xx.h" |
||||
#elif defined(STM32L082xx) |
||||
#include "stm32l082xx.h" |
||||
#elif defined(STM32L083xx) |
||||
#include "stm32l083xx.h" |
||||
#elif defined(STM32L081xx) |
||||
#include "stm32l081xx.h" |
||||
#else |
||||
#error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)" |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{ |
||||
*/
|
||||
typedef enum
|
||||
{ |
||||
RESET = 0,
|
||||
SET = !RESET |
||||
} FlagStatus, ITStatus; |
||||
|
||||
typedef enum
|
||||
{ |
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE |
||||
} FunctionalState; |
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) |
||||
|
||||
typedef enum
|
||||
{ |
||||
ERROR = 0,
|
||||
SUCCESS = !ERROR |
||||
} ErrorStatus; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{ |
||||
*/ |
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) |
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT)) |
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0)) |
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) |
||||
|
||||
#define READ_REG(REG) ((REG)) |
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined (USE_HAL_DRIVER) |
||||
#include "stm32l0xx_hal.h" |
||||
#endif /* USE_HAL_DRIVER */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif /* __cplusplus */ |
||||
|
||||
#endif /* __STM32L0xx_H */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,125 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file system_stm32l0xx.h |
||||
* @author MCD Application Team |
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup stm32l0xx_system
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion |
||||
*/ |
||||
#ifndef __SYSTEM_STM32L0XX_H |
||||
#define __SYSTEM_STM32L0XX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/** @addtogroup STM32L0xx_System_Includes
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/** @addtogroup STM32L0xx_System_Exported_types
|
||||
* @{ |
||||
*/ |
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate() |
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq() |
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there |
||||
is no need to call the 2 first functions listed above, since SystemCoreClock |
||||
variable is updated automatically. |
||||
*/ |
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ |
||||
/*
|
||||
*/ |
||||
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ |
||||
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ |
||||
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Exported_Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Exported_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup STM32L0xx_System_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
extern void SystemInit(void); |
||||
extern void SystemCoreClockUpdate(void); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /*__SYSTEM_STM32L0XX_H */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
@ -0,0 +1,136 @@ |
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
||||
* |
||||
* $Date: 19. October 2015 |
||||
* $Revision: V.1.4.5 a |
||||
* |
||||
* Project: CMSIS DSP Library |
||||
* Title: arm_common_tables.h |
||||
* |
||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions |
||||
* |
||||
* Target Processor: Cortex-M4/Cortex-M3 |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without |
||||
* modification, are permitted provided that the following conditions |
||||
* are met: |
||||
* - Redistributions of source code must retain the above copyright |
||||
* notice, this list of conditions and the following disclaimer. |
||||
* - Redistributions in binary form must reproduce the above copyright |
||||
* notice, this list of conditions and the following disclaimer in |
||||
* the documentation and/or other materials provided with the |
||||
* distribution. |
||||
* - Neither the name of ARM LIMITED nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this |
||||
* software without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
* POSSIBILITY OF SUCH DAMAGE. |
||||
* -------------------------------------------------------------------- */ |
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H |
||||
#define _ARM_COMMON_TABLES_H |
||||
|
||||
#include "arm_math.h" |
||||
|
||||
extern const uint16_t armBitRevTable[1024]; |
||||
extern const q15_t armRecipTableQ15[64]; |
||||
extern const q31_t armRecipTableQ31[64]; |
||||
/* extern const q31_t realCoefAQ31[1024]; */ |
||||
/* extern const q31_t realCoefBQ31[1024]; */ |
||||
extern const float32_t twiddleCoef_16[32]; |
||||
extern const float32_t twiddleCoef_32[64]; |
||||
extern const float32_t twiddleCoef_64[128]; |
||||
extern const float32_t twiddleCoef_128[256]; |
||||
extern const float32_t twiddleCoef_256[512]; |
||||
extern const float32_t twiddleCoef_512[1024]; |
||||
extern const float32_t twiddleCoef_1024[2048]; |
||||
extern const float32_t twiddleCoef_2048[4096]; |
||||
extern const float32_t twiddleCoef_4096[8192]; |
||||
#define twiddleCoef twiddleCoef_4096 |
||||
extern const q31_t twiddleCoef_16_q31[24]; |
||||
extern const q31_t twiddleCoef_32_q31[48]; |
||||
extern const q31_t twiddleCoef_64_q31[96]; |
||||
extern const q31_t twiddleCoef_128_q31[192]; |
||||
extern const q31_t twiddleCoef_256_q31[384]; |
||||
extern const q31_t twiddleCoef_512_q31[768]; |
||||
extern const q31_t twiddleCoef_1024_q31[1536]; |
||||
extern const q31_t twiddleCoef_2048_q31[3072]; |
||||
extern const q31_t twiddleCoef_4096_q31[6144]; |
||||
extern const q15_t twiddleCoef_16_q15[24]; |
||||
extern const q15_t twiddleCoef_32_q15[48]; |
||||
extern const q15_t twiddleCoef_64_q15[96]; |
||||
extern const q15_t twiddleCoef_128_q15[192]; |
||||
extern const q15_t twiddleCoef_256_q15[384]; |
||||
extern const q15_t twiddleCoef_512_q15[768]; |
||||
extern const q15_t twiddleCoef_1024_q15[1536]; |
||||
extern const q15_t twiddleCoef_2048_q15[3072]; |
||||
extern const q15_t twiddleCoef_4096_q15[6144]; |
||||
extern const float32_t twiddleCoef_rfft_32[32]; |
||||
extern const float32_t twiddleCoef_rfft_64[64]; |
||||
extern const float32_t twiddleCoef_rfft_128[128]; |
||||
extern const float32_t twiddleCoef_rfft_256[256]; |
||||
extern const float32_t twiddleCoef_rfft_512[512]; |
||||
extern const float32_t twiddleCoef_rfft_1024[1024]; |
||||
extern const float32_t twiddleCoef_rfft_2048[2048]; |
||||
extern const float32_t twiddleCoef_rfft_4096[4096]; |
||||
|
||||
|
||||
/* floating-point bit reversal tables */ |
||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) |
||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) |
||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) |
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) |
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) |
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) |
||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) |
||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) |
||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) |
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; |
||||
|
||||
/* fixed-point bit reversal tables */ |
||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) |
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) |
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) |
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; |
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; |
||||
|
||||
/* Tables for Fast Math Sine and Cosine */ |
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; |
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; |
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; |
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */ |
||||
@ -0,0 +1,79 @@ |
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved. |
||||
* |
||||
* $Date: 19. March 2015 |
||||
* $Revision: V.1.4.5 |
||||
* |
||||
* Project: CMSIS DSP Library |
||||
* Title: arm_const_structs.h |
||||
* |
||||
* Description: This file has constant structs that are initialized for |
||||
* user convenience. For example, some can be given as |
||||
* arguments to the arm_cfft_f32() function. |
||||
* |
||||
* Target Processor: Cortex-M4/Cortex-M3 |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without |
||||
* modification, are permitted provided that the following conditions |
||||
* are met: |
||||
* - Redistributions of source code must retain the above copyright |
||||
* notice, this list of conditions and the following disclaimer. |
||||
* - Redistributions in binary form must reproduce the above copyright |
||||
* notice, this list of conditions and the following disclaimer in |
||||
* the documentation and/or other materials provided with the |
||||
* distribution. |
||||
* - Neither the name of ARM LIMITED nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this |
||||
* software without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
* POSSIBILITY OF SUCH DAMAGE. |
||||
* -------------------------------------------------------------------- */ |
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H |
||||
#define _ARM_CONST_STRUCTS_H |
||||
|
||||
#include "arm_math.h" |
||||
#include "arm_common_tables.h" |
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; |
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; |
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; |
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; |
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; |
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; |
||||
|
||||
#endif |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,734 @@ |
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h |
||||
* @brief CMSIS Cortex-M Core Function/Instruction Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H |
||||
#define __CMSIS_ARMCC_H |
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) |
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
||||
#endif |
||||
|
||||
/* ########################### Core Function Access ########################### */ |
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
||||
@{ |
||||
*/ |
||||
|
||||
/* intrinsic void __enable_irq(); */ |
||||
/* intrinsic void __disable_irq(); */ |
||||
|
||||
/**
|
||||
\brief Get Control Register |
||||
\details Returns the content of the Control Register. |
||||
\return Control Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_CONTROL(void) |
||||
{ |
||||
register uint32_t __regControl __ASM("control"); |
||||
return(__regControl); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register |
||||
\details Writes the given value to the Control Register. |
||||
\param [in] control Control Register value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control) |
||||
{ |
||||
register uint32_t __regControl __ASM("control"); |
||||
__regControl = control; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register |
||||
\details Returns the content of the IPSR Register. |
||||
\return IPSR Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_IPSR(void) |
||||
{ |
||||
register uint32_t __regIPSR __ASM("ipsr"); |
||||
return(__regIPSR); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register |
||||
\details Returns the content of the APSR Register. |
||||
\return APSR Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_APSR(void) |
||||
{ |
||||
register uint32_t __regAPSR __ASM("apsr"); |
||||
return(__regAPSR); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register |
||||
\details Returns the content of the xPSR Register. |
||||
\return xPSR Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_xPSR(void) |
||||
{ |
||||
register uint32_t __regXPSR __ASM("xpsr"); |
||||
return(__regXPSR); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer |
||||
\details Returns the current value of the Process Stack Pointer (PSP). |
||||
\return PSP Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_PSP(void) |
||||
{ |
||||
register uint32_t __regProcessStackPointer __ASM("psp"); |
||||
return(__regProcessStackPointer); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer |
||||
\details Assigns the given value to the Process Stack Pointer (PSP). |
||||
\param [in] topOfProcStack Process Stack Pointer value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
||||
{ |
||||
register uint32_t __regProcessStackPointer __ASM("psp"); |
||||
__regProcessStackPointer = topOfProcStack; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer |
||||
\details Returns the current value of the Main Stack Pointer (MSP). |
||||
\return MSP Register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_MSP(void) |
||||
{ |
||||
register uint32_t __regMainStackPointer __ASM("msp"); |
||||
return(__regMainStackPointer); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer |
||||
\details Assigns the given value to the Main Stack Pointer (MSP). |
||||
\param [in] topOfMainStack Main Stack Pointer value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
||||
{ |
||||
register uint32_t __regMainStackPointer __ASM("msp"); |
||||
__regMainStackPointer = topOfMainStack; |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask |
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register. |
||||
\return Priority Mask value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void) |
||||
{ |
||||
register uint32_t __regPriMask __ASM("primask"); |
||||
return(__regPriMask); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask |
||||
\details Assigns the given value to the Priority Mask Register. |
||||
\param [in] priMask Priority Mask |
||||
*/ |
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
||||
{ |
||||
register uint32_t __regPriMask __ASM("primask"); |
||||
__regPriMask = (priMask); |
||||
} |
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) |
||||
|
||||
/**
|
||||
\brief Enable FIQ |
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR. |
||||
Can only be executed in Privileged modes. |
||||
*/ |
||||
#define __enable_fault_irq __enable_fiq |
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ |
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR. |
||||
Can only be executed in Privileged modes. |
||||
*/ |
||||
#define __disable_fault_irq __disable_fiq |
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority |
||||
\details Returns the current value of the Base Priority register. |
||||
\return Base Priority register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void) |
||||
{ |
||||
register uint32_t __regBasePri __ASM("basepri"); |
||||
return(__regBasePri); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority |
||||
\details Assigns the given value to the Base Priority register. |
||||
\param [in] basePri Base Priority value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) |
||||
{ |
||||
register uint32_t __regBasePri __ASM("basepri"); |
||||
__regBasePri = (basePri & 0xFFU); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition |
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, |
||||
or the new value increases the BASEPRI priority level. |
||||
\param [in] basePri Base Priority value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) |
||||
{ |
||||
register uint32_t __regBasePriMax __ASM("basepri_max"); |
||||
__regBasePriMax = (basePri & 0xFFU); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask |
||||
\details Returns the current value of the Fault Mask register. |
||||
\return Fault Mask register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void) |
||||
{ |
||||
register uint32_t __regFaultMask __ASM("faultmask"); |
||||
return(__regFaultMask); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask |
||||
\details Assigns the given value to the Fault Mask register. |
||||
\param [in] faultMask Fault Mask value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
||||
{ |
||||
register uint32_t __regFaultMask __ASM("faultmask"); |
||||
__regFaultMask = (faultMask & (uint32_t)1); |
||||
} |
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ |
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) |
||||
|
||||
/**
|
||||
\brief Get FPSCR |
||||
\details Returns the current value of the Floating Point Status/Control register. |
||||
\return Floating Point Status/Control register value |
||||
*/ |
||||
__STATIC_INLINE uint32_t __get_FPSCR(void) |
||||
{ |
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) |
||||
register uint32_t __regfpscr __ASM("fpscr"); |
||||
return(__regfpscr); |
||||
#else |
||||
return(0U); |
||||
#endif |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR |
||||
\details Assigns the given value to the Floating Point Status/Control register. |
||||
\param [in] fpscr Floating Point Status/Control value to set |
||||
*/ |
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
||||
{ |
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) |
||||
register uint32_t __regfpscr __ASM("fpscr"); |
||||
__regfpscr = (fpscr); |
||||
#endif |
||||
} |
||||
|
||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ |
||||
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */ |
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */ |
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief No Operation |
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes. |
||||
*/ |
||||
#define __NOP __nop |
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt |
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. |
||||
*/ |
||||
#define __WFI __wfi |
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event |
||||
\details Wait For Event is a hint instruction that permits the processor to enter |
||||
a low-power state until one of a number of events occurs. |
||||
*/ |
||||
#define __WFE __wfe |
||||
|
||||
|
||||
/**
|
||||
\brief Send Event |
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
||||
*/ |
||||
#define __SEV __sev |
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier |
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor, |
||||
so that all instructions following the ISB are fetched from cache or memory, |
||||
after the instruction has been completed. |
||||
*/ |
||||
#define __ISB() do {\ |
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U) |
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier |
||||
\details Acts as a special kind of Data Memory Barrier. |
||||
It completes when all explicit memory accesses before this instruction complete. |
||||
*/ |
||||
#define __DSB() do {\ |
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U) |
||||
|
||||
/**
|
||||
\brief Data Memory Barrier |
||||
\details Ensures the apparent order of the explicit memory operations before |
||||
and after the instruction, without ensuring their completion. |
||||
*/ |
||||
#define __DMB() do {\ |
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U) |
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit) |
||||
\details Reverses the byte order in integer value. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#define __REV __rev |
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit) |
||||
\details Reverses the byte order in two unsigned short values. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#ifndef __NO_EMBEDDED_ASM |
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) |
||||
{ |
||||
rev16 r0, r0 |
||||
bx lr |
||||
} |
||||
#endif |
||||
|
||||
/**
|
||||
\brief Reverse byte order in signed short value |
||||
\details Reverses the byte order in a signed short value with sign extension to integer. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#ifndef __NO_EMBEDDED_ASM |
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) |
||||
{ |
||||
revsh r0, r0 |
||||
bx lr |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit) |
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
||||
\param [in] value Value to rotate |
||||
\param [in] value Number of Bits to rotate |
||||
\return Rotated value |
||||
*/ |
||||
#define __ROR __ror |
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint |
||||
\details Causes the processor to enter Debug state. |
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached. |
||||
\param [in] value is ignored by the processor. |
||||
If required, a debugger can use it to store additional information about the breakpoint. |
||||
*/ |
||||
#define __BKPT(value) __breakpoint(value) |
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value |
||||
\details Reverses the bit order of the given value. |
||||
\param [in] value Value to reverse |
||||
\return Reversed value |
||||
*/ |
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) |
||||
#define __RBIT __rbit |
||||
#else |
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) |
||||
{ |
||||
uint32_t result; |
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ |
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */ |
||||
for (value >>= 1U; value; value >>= 1U) |
||||
{ |
||||
result <<= 1U; |
||||
result |= value & 1U; |
||||
s--; |
||||
} |
||||
result <<= s; /* shift when v's highest bits are zero */ |
||||
return(result); |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros |
||||
\details Counts the number of leading zeros of a data value. |
||||
\param [in] value Value to count the leading zeros |
||||
\return number of leading zeros in value |
||||
*/ |
||||
#define __CLZ __clz |
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) |
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit) |
||||
\details Executes a exclusive LDR instruction for 8 bit value. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint8_t at (*ptr) |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) |
||||
#else |
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit) |
||||
\details Executes a exclusive LDR instruction for 16 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint16_t at (*ptr) |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) |
||||
#else |
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit) |
||||
\details Executes a exclusive LDR instruction for 32 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint32_t at (*ptr) |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) |
||||
#else |
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit) |
||||
\details Executes a exclusive STR instruction for 8 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
\return 0 Function succeeded |
||||
\return 1 Function failed |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __STREXB(value, ptr) __strex(value, ptr) |
||||
#else |
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit) |
||||
\details Executes a exclusive STR instruction for 16 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
\return 0 Function succeeded |
||||
\return 1 Function failed |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __STREXH(value, ptr) __strex(value, ptr) |
||||
#else |
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit) |
||||
\details Executes a exclusive STR instruction for 32 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
\return 0 Function succeeded |
||||
\return 1 Function failed |
||||
*/ |
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) |
||||
#define __STREXW(value, ptr) __strex(value, ptr) |
||||
#else |
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock |
||||
\details Removes the exclusive lock which is created by LDREX. |
||||
*/ |
||||
#define __CLREX __clrex |
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate |
||||
\details Saturates a signed value. |
||||
\param [in] value Value to be saturated |
||||
\param [in] sat Bit position to saturate to (1..32) |
||||
\return Saturated value |
||||
*/ |
||||
#define __SSAT __ssat |
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate |
||||
\details Saturates an unsigned value. |
||||
\param [in] value Value to be saturated |
||||
\param [in] sat Bit position to saturate to (0..31) |
||||
\return Saturated value |
||||
*/ |
||||
#define __USAT __usat |
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit) |
||||
\details Moves each bit of a bitstring right by one bit. |
||||
The carry input is shifted in at the left end of the bitstring. |
||||
\param [in] value Value to rotate |
||||
\return Rotated value |
||||
*/ |
||||
#ifndef __NO_EMBEDDED_ASM |
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) |
||||
{ |
||||
rrx r0, r0 |
||||
bx lr |
||||
} |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit) |
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint8_t at (*ptr) |
||||
*/ |
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) |
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit) |
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint16_t at (*ptr) |
||||
*/ |
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) |
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit) |
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values. |
||||
\param [in] ptr Pointer to data |
||||
\return value of type uint32_t at (*ptr) |
||||
*/ |
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) |
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit) |
||||
\details Executes a Unprivileged STRT instruction for 8 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
*/ |
||||
#define __STRBT(value, ptr) __strt(value, ptr) |
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit) |
||||
\details Executes a Unprivileged STRT instruction for 16 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
*/ |
||||
#define __STRHT(value, ptr) __strt(value, ptr) |
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit) |
||||
\details Executes a Unprivileged STRT instruction for 32 bit values. |
||||
\param [in] value Value to store |
||||
\param [in] ptr Pointer to location |
||||
*/ |
||||
#define __STRT(value, ptr) __strt(value, ptr) |
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ |
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */ |
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions |
||||
@{ |
||||
*/ |
||||
|
||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ |
||||
|
||||
#define __SADD8 __sadd8 |
||||
#define __QADD8 __qadd8 |
||||
#define __SHADD8 __shadd8 |
||||
#define __UADD8 __uadd8 |
||||
#define __UQADD8 __uqadd8 |
||||
#define __UHADD8 __uhadd8 |
||||
#define __SSUB8 __ssub8 |
||||
#define __QSUB8 __qsub8 |
||||
#define __SHSUB8 __shsub8 |
||||
#define __USUB8 __usub8 |
||||
#define __UQSUB8 __uqsub8 |
||||
#define __UHSUB8 __uhsub8 |
||||
#define __SADD16 __sadd16 |
||||
#define __QADD16 __qadd16 |
||||
#define __SHADD16 __shadd16 |
||||
#define __UADD16 __uadd16 |
||||
#define __UQADD16 __uqadd16 |
||||
#define __UHADD16 __uhadd16 |
||||
#define __SSUB16 __ssub16 |
||||
#define __QSUB16 __qsub16 |
||||
#define __SHSUB16 __shsub16 |
||||
#define __USUB16 __usub16 |
||||
#define __UQSUB16 __uqsub16 |
||||
#define __UHSUB16 __uhsub16 |
||||
#define __SASX __sasx |
||||
#define __QASX __qasx |
||||
#define __SHASX __shasx |
||||
#define __UASX __uasx |
||||
#define __UQASX __uqasx |
||||
#define __UHASX __uhasx |
||||
#define __SSAX __ssax |
||||
#define __QSAX __qsax |
||||
#define __SHSAX __shsax |
||||
#define __USAX __usax |
||||
#define __UQSAX __uqsax |
||||
#define __UHSAX __uhsax |
||||
#define __USAD8 __usad8 |
||||
#define __USADA8 __usada8 |
||||
#define __SSAT16 __ssat16 |
||||
#define __USAT16 __usat16 |
||||
#define __UXTB16 __uxtb16 |
||||
#define __UXTAB16 __uxtab16 |
||||
#define __SXTB16 __sxtb16 |
||||
#define __SXTAB16 __sxtab16 |
||||
#define __SMUAD __smuad |
||||
#define __SMUADX __smuadx |
||||
#define __SMLAD __smlad |
||||
#define __SMLADX __smladx |
||||
#define __SMLALD __smlald |
||||
#define __SMLALDX __smlaldx |
||||
#define __SMUSD __smusd |
||||
#define __SMUSDX __smusdx |
||||
#define __SMLSD __smlsd |
||||
#define __SMLSDX __smlsdx |
||||
#define __SMLSLD __smlsld |
||||
#define __SMLSLDX __smlsldx |
||||
#define __SEL __sel |
||||
#define __QADD __qadd |
||||
#define __QSUB __qsub |
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ |
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) |
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ |
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) |
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ |
||||
((int64_t)(ARG3) << 32U) ) >> 32U)) |
||||
|
||||
#endif /* (__CORTEX_M >= 0x04) */ |
||||
/*@} end of group CMSIS_SIMD_intrinsics */ |
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,798 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h |
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC |
||||
#define __CORE_CM0_H_GENERIC |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
||||
CMSIS violates the following MISRA-C:2004 rules: |
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br> |
||||
Function definitions in header files are used to allow 'inlining'. |
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
||||
Unions are used for effective representation of core registers. |
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br> |
||||
Function-like macros are used to allow more efficient code. |
||||
*/ |
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions |
||||
******************************************************************************/ |
||||
/**
|
||||
\ingroup Cortex_M0 |
||||
@{ |
||||
*/ |
||||
|
||||
/* CMSIS CM0 definitions */ |
||||
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ |
||||
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ |
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ |
||||
|
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#define __packed |
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#else |
||||
#error Unknown compiler |
||||
#endif |
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all |
||||
*/ |
||||
#define __FPU_USED 0U |
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#if defined __TARGET_FPU_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#if defined __ARM_PCS_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#if defined __ARMVFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#if defined __TI_VFP_SUPPORT__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#if defined __FPU_VFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#if ( __CSMC__ & 0x400U) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */ |
||||
#include "core_cmFunc.h" /* Core Function Access */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */ |
||||
|
||||
#ifndef __CMSIS_GENERIC |
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT |
||||
#define __CORE_CM0_H_DEPENDANT |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* check device defines and use defaults */ |
||||
#if defined __CHECK_DEVICE_DEFINES |
||||
#ifndef __CM0_REV |
||||
#define __CM0_REV 0x0000U |
||||
#warning "__CM0_REV not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __NVIC_PRIO_BITS |
||||
#define __NVIC_PRIO_BITS 2U |
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __Vendor_SysTickConfig |
||||
#define __Vendor_SysTickConfig 0U |
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
||||
#endif |
||||
#endif |
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */ |
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines |
||||
|
||||
<strong>IO Type Qualifiers</strong> are used |
||||
\li to specify the access to peripheral variables. |
||||
\li for automatic generation of peripheral register debug information. |
||||
*/ |
||||
#ifdef __cplusplus |
||||
#define __I volatile /*!< Defines 'read only' permissions */ |
||||
#else |
||||
#define __I volatile const /*!< Defines 'read only' permissions */ |
||||
#endif |
||||
#define __O volatile /*!< Defines 'write only' permissions */ |
||||
#define __IO volatile /*!< Defines 'read / write' permissions */ |
||||
|
||||
/* following defines should be used for structure members */ |
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */ |
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */ |
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
||||
|
||||
/*@} end of group Cortex_M0 */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction |
||||
Core Register contain: |
||||
- Core Register |
||||
- Core NVIC Register |
||||
- Core SCB Register |
||||
- Core SysTick Register |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions |
||||
\brief Type definitions and defines for Cortex-M processor based devices. |
||||
*/ |
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CORE Status and Control Registers |
||||
\brief Core Register type definitions. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} APSR_Type; |
||||
|
||||
/* APSR Register Definitions */ |
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */ |
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */ |
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */ |
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} IPSR_Type; |
||||
|
||||
/* IPSR Register Definitions */ |
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} xPSR_Type; |
||||
|
||||
/* xPSR Register Definitions */ |
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} CONTROL_Type; |
||||
|
||||
/* CONTROL Register Definitions */ |
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
||||
|
||||
/*@} end of group CMSIS_CORE */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
||||
\brief Type definitions for the NVIC Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
||||
uint32_t RESERVED0[31U]; |
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
||||
uint32_t RSERVED1[31U]; |
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
||||
uint32_t RESERVED2[31U]; |
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
||||
uint32_t RESERVED3[31U]; |
||||
uint32_t RESERVED4[64U]; |
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
||||
} NVIC_Type; |
||||
|
||||
/*@} end of group CMSIS_NVIC */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCB System Control Block (SCB) |
||||
\brief Type definitions for the System Control Block Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
||||
uint32_t RESERVED0; |
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
||||
uint32_t RESERVED1; |
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
||||
} SCB_Type; |
||||
|
||||
/* SCB CPUID Register Definitions */ |
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */ |
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||||
|
||||
/* SCB System Control Register Definitions */ |
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||||
|
||||
/* SCB Configuration Control Register Definitions */ |
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||||
|
||||
/* SCB System Handler Control and State Register Definitions */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||||
\brief Type definitions for the System Timer Registers. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||||
} SysTick_Type; |
||||
|
||||
/* SysTick Control / Status Register Definitions */ |
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||||
|
||||
/* SysTick Reload Register Definitions */ |
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||||
|
||||
/* SysTick Current Register Definitions */ |
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||||
|
||||
/* SysTick Calibration Register Definitions */ |
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||||
|
||||
/*@} end of group CMSIS_SysTick */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
||||
Therefore they are not covered by the Cortex-M0 header file. |
||||
@{ |
||||
*/ |
||||
/*@} end of group CMSIS_CoreDebug */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_bitfield Core register bit field macros |
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of the bit field. |
||||
\return Masked and shifted value. |
||||
*/ |
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) |
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of register. |
||||
\return Masked and shifted bit field value. |
||||
*/ |
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) |
||||
|
||||
/*@} end of group CMSIS_core_bitfield */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_base Core Definitions |
||||
\brief Definitions for base addresses, unions, and structures. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Memory mapping of Cortex-M0 Hardware */ |
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||||
|
||||
|
||||
/*@} */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer |
||||
Core Function Interface contains: |
||||
- Core NVIC Functions |
||||
- Core SysTick Functions |
||||
- Core Register Access Functions |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||||
*/ |
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||||
\brief Functions that manage interrupts and exceptions via the NVIC. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */ |
||||
/* The following MACROS handle generation of the register offset and byte masks */ |
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt |
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt |
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt |
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return 0 Interrupt status is not pending. |
||||
\return 1 Interrupt status is pending. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt |
||||
\details Sets the pending bit of an external interrupt. |
||||
\param [in] IRQn Interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt |
||||
\details Clears the pending bit of an external interrupt. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority |
||||
\details Sets the priority of an interrupt. |
||||
\note The priority cannot be set for every core interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\param [in] priority Priority to set. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||||
{ |
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
else |
||||
{ |
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority |
||||
\details Reads the priority of an interrupt. |
||||
The interrupt number can be positive to specify an external (device specific) interrupt, |
||||
or negative to specify an internal (core) interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Interrupt Priority. |
||||
Value is aligned automatically to the implemented priority bits of the microcontroller. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
||||
{ |
||||
|
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
else |
||||
{ |
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief System Reset |
||||
\details Initiates a system reset request to reset the MCU. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SystemReset(void) |
||||
{ |
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */ |
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||||
SCB_AIRCR_SYSRESETREQ_Msk); |
||||
__DSB(); /* Ensure completion of memory access */ |
||||
|
||||
for(;;) /* wait until reset */ |
||||
{ |
||||
__NOP(); |
||||
} |
||||
} |
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */ |
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||||
\brief Functions that configure the System. |
||||
@{ |
||||
*/ |
||||
|
||||
#if (__Vendor_SysTickConfig == 0U) |
||||
|
||||
/**
|
||||
\brief System Tick Configuration |
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
Counter is in free running mode to generate periodic interrupts. |
||||
\param [in] ticks Number of ticks between two interrupts. |
||||
\return 0 Function succeeded. |
||||
\return 1 Function failed. |
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||||
must contain a vendor-specific implementation of this function. |
||||
*/ |
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||||
{ |
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||||
{ |
||||
return (1UL); /* Reload value impossible */ |
||||
} |
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||||
SysTick_CTRL_TICKINT_Msk | |
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||||
return (0UL); /* Function successful */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */ |
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */ |
||||
|
||||
#endif /* __CMSIS_GENERIC */ |
||||
@ -0,0 +1,914 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cm0plus.h |
||||
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CM0PLUS_H_GENERIC |
||||
#define __CORE_CM0PLUS_H_GENERIC |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
||||
CMSIS violates the following MISRA-C:2004 rules: |
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br> |
||||
Function definitions in header files are used to allow 'inlining'. |
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
||||
Unions are used for effective representation of core registers. |
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br> |
||||
Function-like macros are used to allow more efficient code. |
||||
*/ |
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions |
||||
******************************************************************************/ |
||||
/**
|
||||
\ingroup Cortex-M0+ |
||||
@{ |
||||
*/ |
||||
|
||||
/* CMSIS CM0+ definitions */ |
||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ |
||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ |
||||
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ |
||||
|
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#define __packed |
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#else |
||||
#error Unknown compiler |
||||
#endif |
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all |
||||
*/ |
||||
#define __FPU_USED 0U |
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#if defined __TARGET_FPU_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#if defined __ARM_PCS_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#if defined __ARMVFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#if defined __TI_VFP_SUPPORT__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#if defined __FPU_VFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#if ( __CSMC__ & 0x400U) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */ |
||||
#include "core_cmFunc.h" /* Core Function Access */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM0PLUS_H_GENERIC */ |
||||
|
||||
#ifndef __CMSIS_GENERIC |
||||
|
||||
#ifndef __CORE_CM0PLUS_H_DEPENDANT |
||||
#define __CORE_CM0PLUS_H_DEPENDANT |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* check device defines and use defaults */ |
||||
#if defined __CHECK_DEVICE_DEFINES |
||||
#ifndef __CM0PLUS_REV |
||||
#define __CM0PLUS_REV 0x0000U |
||||
#warning "__CM0PLUS_REV not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __MPU_PRESENT |
||||
#define __MPU_PRESENT 0U |
||||
#warning "__MPU_PRESENT not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __VTOR_PRESENT |
||||
#define __VTOR_PRESENT 0U |
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __NVIC_PRIO_BITS |
||||
#define __NVIC_PRIO_BITS 2U |
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __Vendor_SysTickConfig |
||||
#define __Vendor_SysTickConfig 0U |
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
||||
#endif |
||||
#endif |
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */ |
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines |
||||
|
||||
<strong>IO Type Qualifiers</strong> are used |
||||
\li to specify the access to peripheral variables. |
||||
\li for automatic generation of peripheral register debug information. |
||||
*/ |
||||
#ifdef __cplusplus |
||||
#define __I volatile /*!< Defines 'read only' permissions */ |
||||
#else |
||||
#define __I volatile const /*!< Defines 'read only' permissions */ |
||||
#endif |
||||
#define __O volatile /*!< Defines 'write only' permissions */ |
||||
#define __IO volatile /*!< Defines 'read / write' permissions */ |
||||
|
||||
/* following defines should be used for structure members */ |
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */ |
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */ |
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
||||
|
||||
/*@} end of group Cortex-M0+ */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction |
||||
Core Register contain: |
||||
- Core Register |
||||
- Core NVIC Register |
||||
- Core SCB Register |
||||
- Core SysTick Register |
||||
- Core MPU Register |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions |
||||
\brief Type definitions and defines for Cortex-M processor based devices. |
||||
*/ |
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CORE Status and Control Registers |
||||
\brief Core Register type definitions. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} APSR_Type; |
||||
|
||||
/* APSR Register Definitions */ |
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */ |
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */ |
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */ |
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} IPSR_Type; |
||||
|
||||
/* IPSR Register Definitions */ |
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} xPSR_Type; |
||||
|
||||
/* xPSR Register Definitions */ |
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} CONTROL_Type; |
||||
|
||||
/* CONTROL Register Definitions */ |
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
||||
|
||||
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
||||
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
||||
|
||||
/*@} end of group CMSIS_CORE */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
||||
\brief Type definitions for the NVIC Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
||||
uint32_t RESERVED0[31U]; |
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
||||
uint32_t RSERVED1[31U]; |
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
||||
uint32_t RESERVED2[31U]; |
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
||||
uint32_t RESERVED3[31U]; |
||||
uint32_t RESERVED4[64U]; |
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
||||
} NVIC_Type; |
||||
|
||||
/*@} end of group CMSIS_NVIC */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCB System Control Block (SCB) |
||||
\brief Type definitions for the System Control Block Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
||||
#if (__VTOR_PRESENT == 1U) |
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
||||
#else |
||||
uint32_t RESERVED0; |
||||
#endif |
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
||||
uint32_t RESERVED1; |
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
||||
} SCB_Type; |
||||
|
||||
/* SCB CPUID Register Definitions */ |
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||||
|
||||
#if (__VTOR_PRESENT == 1U) |
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ |
||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
||||
#endif |
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */ |
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||||
|
||||
/* SCB System Control Register Definitions */ |
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||||
|
||||
/* SCB Configuration Control Register Definitions */ |
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||||
|
||||
/* SCB System Handler Control and State Register Definitions */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||||
\brief Type definitions for the System Timer Registers. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||||
} SysTick_Type; |
||||
|
||||
/* SysTick Control / Status Register Definitions */ |
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||||
|
||||
/* SysTick Reload Register Definitions */ |
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||||
|
||||
/* SysTick Current Register Definitions */ |
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||||
|
||||
/* SysTick Calibration Register Definitions */ |
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||||
|
||||
/*@} end of group CMSIS_SysTick */ |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU) |
||||
\brief Type definitions for the Memory Protection Unit (MPU) |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
||||
} MPU_Type; |
||||
|
||||
/* MPU Type Register Definitions */ |
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
||||
|
||||
/* MPU Control Register Definitions */ |
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
||||
|
||||
/* MPU Region Number Register Definitions */ |
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
||||
|
||||
/* MPU Region Base Address Register Definitions */ |
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ |
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */ |
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
||||
|
||||
/*@} end of group CMSIS_MPU */ |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||||
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
||||
Therefore they are not covered by the Cortex-M0+ header file. |
||||
@{ |
||||
*/ |
||||
/*@} end of group CMSIS_CoreDebug */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_bitfield Core register bit field macros |
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of the bit field. |
||||
\return Masked and shifted value. |
||||
*/ |
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) |
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of register. |
||||
\return Masked and shifted bit field value. |
||||
*/ |
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) |
||||
|
||||
/*@} end of group CMSIS_core_bitfield */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_base Core Definitions |
||||
\brief Definitions for base addresses, unions, and structures. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Memory mapping of Cortex-M0+ Hardware */ |
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
||||
#endif |
||||
|
||||
/*@} */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer |
||||
Core Function Interface contains: |
||||
- Core NVIC Functions |
||||
- Core SysTick Functions |
||||
- Core Register Access Functions |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||||
*/ |
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||||
\brief Functions that manage interrupts and exceptions via the NVIC. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */ |
||||
/* The following MACROS handle generation of the register offset and byte masks */ |
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt |
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt |
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt |
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return 0 Interrupt status is not pending. |
||||
\return 1 Interrupt status is pending. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt |
||||
\details Sets the pending bit of an external interrupt. |
||||
\param [in] IRQn Interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt |
||||
\details Clears the pending bit of an external interrupt. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority |
||||
\details Sets the priority of an interrupt. |
||||
\note The priority cannot be set for every core interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\param [in] priority Priority to set. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||||
{ |
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
else |
||||
{ |
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority |
||||
\details Reads the priority of an interrupt. |
||||
The interrupt number can be positive to specify an external (device specific) interrupt, |
||||
or negative to specify an internal (core) interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Interrupt Priority. |
||||
Value is aligned automatically to the implemented priority bits of the microcontroller. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
||||
{ |
||||
|
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
else |
||||
{ |
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief System Reset |
||||
\details Initiates a system reset request to reset the MCU. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SystemReset(void) |
||||
{ |
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */ |
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||||
SCB_AIRCR_SYSRESETREQ_Msk); |
||||
__DSB(); /* Ensure completion of memory access */ |
||||
|
||||
for(;;) /* wait until reset */ |
||||
{ |
||||
__NOP(); |
||||
} |
||||
} |
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */ |
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||||
\brief Functions that configure the System. |
||||
@{ |
||||
*/ |
||||
|
||||
#if (__Vendor_SysTickConfig == 0U) |
||||
|
||||
/**
|
||||
\brief System Tick Configuration |
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
Counter is in free running mode to generate periodic interrupts. |
||||
\param [in] ticks Number of ticks between two interrupts. |
||||
\return 0 Function succeeded. |
||||
\return 1 Function failed. |
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||||
must contain a vendor-specific implementation of this function. |
||||
*/ |
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||||
{ |
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||||
{ |
||||
return (1UL); /* Reload value impossible */ |
||||
} |
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||||
SysTick_CTRL_TICKINT_Msk | |
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||||
return (0UL); /* Function successful */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */ |
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CM0PLUS_H_DEPENDANT */ |
||||
|
||||
#endif /* __CMSIS_GENERIC */ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,87 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h |
||||
* @brief CMSIS Cortex-M Core Function Access Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CMFUNC_H |
||||
#define __CORE_CMFUNC_H |
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */ |
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
||||
@{ |
||||
*/ |
||||
|
||||
/*------------------ RealView Compiler -----------------*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armcc_V6.h" |
||||
|
||||
/*------------------ GNU Compiler ----------------------*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
/*------------------ ICC Compiler ----------------------*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iar.h> |
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/ |
||||
#elif defined ( __TMS470__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
/*------------------ TASKING Compiler ------------------*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */ |
||||
|
||||
#endif /* __CORE_CMFUNC_H */ |
||||
@ -0,0 +1,87 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h |
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CMINSTR_H |
||||
#define __CORE_CMINSTR_H |
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */ |
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions |
||||
@{ |
||||
*/ |
||||
|
||||
/*------------------ RealView Compiler -----------------*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armcc_V6.h" |
||||
|
||||
/*------------------ GNU Compiler ----------------------*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
/*------------------ ICC Compiler ----------------------*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iar.h> |
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/ |
||||
#elif defined ( __TMS470__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
/*------------------ TASKING Compiler ------------------*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#endif |
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
||||
|
||||
#endif /* __CORE_CMINSTR_H */ |
||||
@ -0,0 +1,96 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h |
||||
* @brief CMSIS Cortex-M SIMD Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_CMSIMD_H |
||||
#define __CORE_CMSIMD_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */ |
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions |
||||
@{ |
||||
*/ |
||||
|
||||
/*------------------ RealView Compiler -----------------*/ |
||||
#if defined ( __CC_ARM ) |
||||
#include "cmsis_armcc.h" |
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#include "cmsis_armcc_V6.h" |
||||
|
||||
/*------------------ GNU Compiler ----------------------*/ |
||||
#elif defined ( __GNUC__ ) |
||||
#include "cmsis_gcc.h" |
||||
|
||||
/*------------------ ICC Compiler ----------------------*/ |
||||
#elif defined ( __ICCARM__ ) |
||||
#include <cmsis_iar.h> |
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/ |
||||
#elif defined ( __TMS470__ ) |
||||
#include <cmsis_ccs.h> |
||||
|
||||
/*------------------ TASKING Compiler ------------------*/ |
||||
#elif defined ( __TASKING__ ) |
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler. |
||||
* Please use "carm -?i" to get an up to date list of all intrinsics, |
||||
* Including the CMSIS ones. |
||||
*/ |
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/ |
||||
#elif defined ( __CSMC__ ) |
||||
#include <cmsis_csm.h> |
||||
|
||||
#endif |
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */ |
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_CMSIMD_H */ |
||||
@ -0,0 +1,926 @@ |
||||
/**************************************************************************//**
|
||||
* @file core_sc000.h |
||||
* @brief CMSIS SC000 Core Peripheral Access Layer Header File |
||||
* @version V4.30 |
||||
* @date 20. October 2015 |
||||
******************************************************************************/ |
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved. |
||||
Redistribution and use in source and binary forms, with or without |
||||
modification, are permitted provided that the following conditions are met: |
||||
- Redistributions of source code must retain the above copyright |
||||
notice, this list of conditions and the following disclaimer. |
||||
- Redistributions in binary form must reproduce the above copyright |
||||
notice, this list of conditions and the following disclaimer in the |
||||
documentation and/or other materials provided with the distribution. |
||||
- Neither the name of ARM nor the names of its contributors may be used |
||||
to endorse or promote products derived from this software without |
||||
specific prior written permission. |
||||
* |
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
||||
POSSIBILITY OF SUCH DAMAGE. |
||||
---------------------------------------------------------------------------*/ |
||||
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#pragma system_include /* treat file as system include file for MISRA check */ |
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#pragma clang system_header /* treat file as system include file */ |
||||
#endif |
||||
|
||||
#ifndef __CORE_SC000_H_GENERIC |
||||
#define __CORE_SC000_H_GENERIC |
||||
|
||||
#include <stdint.h> |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
||||
CMSIS violates the following MISRA-C:2004 rules: |
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br> |
||||
Function definitions in header files are used to allow 'inlining'. |
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
||||
Unions are used for effective representation of core registers. |
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br> |
||||
Function-like macros are used to allow more efficient code. |
||||
*/ |
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions |
||||
******************************************************************************/ |
||||
/**
|
||||
\ingroup SC000 |
||||
@{ |
||||
*/ |
||||
|
||||
/* CMSIS SC000 definitions */ |
||||
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ |
||||
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ |
||||
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ |
||||
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
||||
|
||||
#define __CORTEX_SC (000U) /*!< Cortex secure core */ |
||||
|
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||||
#define __STATIC_INLINE static __inline |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#define __packed |
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ |
||||
#define __STATIC_INLINE static inline |
||||
|
||||
#else |
||||
#error Unknown compiler |
||||
#endif |
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all |
||||
*/ |
||||
#define __FPU_USED 0U |
||||
|
||||
#if defined ( __CC_ARM ) |
||||
#if defined __TARGET_FPU_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
||||
#if defined __ARM_PCS_VFP |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
#if defined __ARMVFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TMS470__ ) |
||||
#if defined __TI_VFP_SUPPORT__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __TASKING__ ) |
||||
#if defined __FPU_VFP__ |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#elif defined ( __CSMC__ ) |
||||
#if ( __CSMC__ & 0x400U) |
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */ |
||||
#include "core_cmFunc.h" /* Core Function Access */ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_SC000_H_GENERIC */ |
||||
|
||||
#ifndef __CMSIS_GENERIC |
||||
|
||||
#ifndef __CORE_SC000_H_DEPENDANT |
||||
#define __CORE_SC000_H_DEPENDANT |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* check device defines and use defaults */ |
||||
#if defined __CHECK_DEVICE_DEFINES |
||||
#ifndef __SC000_REV |
||||
#define __SC000_REV 0x0000U |
||||
#warning "__SC000_REV not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __MPU_PRESENT |
||||
#define __MPU_PRESENT 0U |
||||
#warning "__MPU_PRESENT not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __NVIC_PRIO_BITS |
||||
#define __NVIC_PRIO_BITS 2U |
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
||||
#endif |
||||
|
||||
#ifndef __Vendor_SysTickConfig |
||||
#define __Vendor_SysTickConfig 0U |
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
||||
#endif |
||||
#endif |
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */ |
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines |
||||
|
||||
<strong>IO Type Qualifiers</strong> are used |
||||
\li to specify the access to peripheral variables. |
||||
\li for automatic generation of peripheral register debug information. |
||||
*/ |
||||
#ifdef __cplusplus |
||||
#define __I volatile /*!< Defines 'read only' permissions */ |
||||
#else |
||||
#define __I volatile const /*!< Defines 'read only' permissions */ |
||||
#endif |
||||
#define __O volatile /*!< Defines 'write only' permissions */ |
||||
#define __IO volatile /*!< Defines 'read / write' permissions */ |
||||
|
||||
/* following defines should be used for structure members */ |
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */ |
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */ |
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
||||
|
||||
/*@} end of group SC000 */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction |
||||
Core Register contain: |
||||
- Core Register |
||||
- Core NVIC Register |
||||
- Core SCB Register |
||||
- Core SysTick Register |
||||
- Core MPU Register |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions |
||||
\brief Type definitions and defines for Cortex-M processor based devices. |
||||
*/ |
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CORE Status and Control Registers |
||||
\brief Core Register type definitions. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} APSR_Type; |
||||
|
||||
/* APSR Register Definitions */ |
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */ |
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */ |
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */ |
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} IPSR_Type; |
||||
|
||||
/* IPSR Register Definitions */ |
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} xPSR_Type; |
||||
|
||||
/* xPSR Register Definitions */ |
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL). |
||||
*/ |
||||
typedef union |
||||
{ |
||||
struct |
||||
{ |
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
||||
} b; /*!< Structure used for bit access */ |
||||
uint32_t w; /*!< Type used for word access */ |
||||
} CONTROL_Type; |
||||
|
||||
/* CONTROL Register Definitions */ |
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
||||
|
||||
/*@} end of group CMSIS_CORE */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
||||
\brief Type definitions for the NVIC Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
||||
uint32_t RESERVED0[31U]; |
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
||||
uint32_t RSERVED1[31U]; |
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
||||
uint32_t RESERVED2[31U]; |
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
||||
uint32_t RESERVED3[31U]; |
||||
uint32_t RESERVED4[64U]; |
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
||||
} NVIC_Type; |
||||
|
||||
/*@} end of group CMSIS_NVIC */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCB System Control Block (SCB) |
||||
\brief Type definitions for the System Control Block Registers |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
||||
uint32_t RESERVED0[1U]; |
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
||||
uint32_t RESERVED1[154U]; |
||||
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ |
||||
} SCB_Type; |
||||
|
||||
/* SCB CPUID Register Definitions */ |
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||||
|
||||
/* SCB Interrupt Control State Register Definitions */ |
||||
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ |
||||
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */ |
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||||
|
||||
/* SCB System Control Register Definitions */ |
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||||
|
||||
/* SCB Configuration Control Register Definitions */ |
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||||
|
||||
/* SCB System Handler Control and State Register Definitions */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
||||
\brief Type definitions for the System Control and ID Register not in the SCB |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB. |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t RESERVED0[2U]; |
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
||||
} SCnSCB_Type; |
||||
|
||||
/* Auxiliary Control Register Definitions */ |
||||
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ |
||||
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ |
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||||
\brief Type definitions for the System Timer Registers. |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||||
} SysTick_Type; |
||||
|
||||
/* SysTick Control / Status Register Definitions */ |
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||||
|
||||
/* SysTick Reload Register Definitions */ |
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||||
|
||||
/* SysTick Current Register Definitions */ |
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||||
|
||||
/* SysTick Calibration Register Definitions */ |
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||||
|
||||
/*@} end of group CMSIS_SysTick */ |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU) |
||||
\brief Type definitions for the Memory Protection Unit (MPU) |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU). |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
||||
} MPU_Type; |
||||
|
||||
/* MPU Type Register Definitions */ |
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
||||
|
||||
/* MPU Control Register Definitions */ |
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
||||
|
||||
/* MPU Region Number Register Definitions */ |
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
||||
|
||||
/* MPU Region Base Address Register Definitions */ |
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ |
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */ |
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
||||
|
||||
/*@} end of group CMSIS_MPU */ |
||||
#endif |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||||
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
||||
Therefore they are not covered by the SC000 header file. |
||||
@{ |
||||
*/ |
||||
/*@} end of group CMSIS_CoreDebug */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_bitfield Core register bit field macros |
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||||
@{ |
||||
*/ |
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of the bit field. |
||||
\return Masked and shifted value. |
||||
*/ |
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) |
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value. |
||||
\param[in] field Name of the register bit field. |
||||
\param[in] value Value of register. |
||||
\return Masked and shifted bit field value. |
||||
*/ |
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) |
||||
|
||||
/*@} end of group CMSIS_core_bitfield */ |
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register |
||||
\defgroup CMSIS_core_base Core Definitions |
||||
\brief Definitions for base addresses, unions, and structures. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Memory mapping of SC000 Hardware */ |
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||||
|
||||
#if (__MPU_PRESENT == 1U) |
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
||||
#endif |
||||
|
||||
/*@} */ |
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer |
||||
Core Function Interface contains: |
||||
- Core NVIC Functions |
||||
- Core SysTick Functions |
||||
- Core Register Access Functions |
||||
******************************************************************************/ |
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||||
*/ |
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||||
\brief Functions that manage interrupts and exceptions via the NVIC. |
||||
@{ |
||||
*/ |
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */ |
||||
/* The following MACROS handle generation of the register offset and byte masks */ |
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt |
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt |
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt |
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return 0 Interrupt status is not pending. |
||||
\return 1 Interrupt status is pending. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt |
||||
\details Sets the pending bit of an external interrupt. |
||||
\param [in] IRQn Interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt |
||||
\details Clears the pending bit of an external interrupt. |
||||
\param [in] IRQn External interrupt number. Value cannot be negative. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||||
{ |
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority |
||||
\details Sets the priority of an interrupt. |
||||
\note The priority cannot be set for every core interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\param [in] priority Priority to set. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||||
{ |
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
else |
||||
{ |
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority |
||||
\details Reads the priority of an interrupt. |
||||
The interrupt number can be positive to specify an external (device specific) interrupt, |
||||
or negative to specify an internal (core) interrupt. |
||||
\param [in] IRQn Interrupt number. |
||||
\return Interrupt Priority. |
||||
Value is aligned automatically to the implemented priority bits of the microcontroller. |
||||
*/ |
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
||||
{ |
||||
|
||||
if ((int32_t)(IRQn) < 0) |
||||
{ |
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
else |
||||
{ |
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||||
} |
||||
} |
||||
|
||||
|
||||
/**
|
||||
\brief System Reset |
||||
\details Initiates a system reset request to reset the MCU. |
||||
*/ |
||||
__STATIC_INLINE void NVIC_SystemReset(void) |
||||
{ |
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */ |
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||||
SCB_AIRCR_SYSRESETREQ_Msk); |
||||
__DSB(); /* Ensure completion of memory access */ |
||||
|
||||
for(;;) /* wait until reset */ |
||||
{ |
||||
__NOP(); |
||||
} |
||||
} |
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */ |
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */ |
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface |
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||||
\brief Functions that configure the System. |
||||
@{ |
||||
*/ |
||||
|
||||
#if (__Vendor_SysTickConfig == 0U) |
||||
|
||||
/**
|
||||
\brief System Tick Configuration |
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||||
Counter is in free running mode to generate periodic interrupts. |
||||
\param [in] ticks Number of ticks between two interrupts. |
||||
\return 0 Function succeeded. |
||||
\return 1 Function failed. |
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||||
must contain a vendor-specific implementation of this function. |
||||
*/ |
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||||
{ |
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||||
{ |
||||
return (1UL); /* Reload value impossible */ |
||||
} |
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||||
SysTick_CTRL_TICKINT_Msk | |
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||||
return (0UL); /* Function successful */ |
||||
} |
||||
|
||||
#endif |
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */ |
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __CORE_SC000_H_DEPENDANT */ |
||||
|
||||
#endif /* __CMSIS_GENERIC */ |
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,444 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal.h |
||||
* @author MCD Application Team |
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_H |
||||
#define __STM32L0xx_HAL_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
|
||||
// added
|
||||
#include <stm32l073xx.h> |
||||
|
||||
#include "stm32l0xx_hal_conf.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup HAL HAL
|
||||
* @{ |
||||
*/
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_BootMode Boot Mode
|
||||
* @{ |
||||
*/ |
||||
#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000U) |
||||
#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0) |
||||
#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration
|
||||
* @{ |
||||
*/ |
||||
#define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP |
||||
#define DBGMCU_STOP DBGMCU_CR_DBG_STOP |
||||
#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY |
||||
#define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U)) |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if defined (LCD_BASE) /* STM32L0x3xx only */ |
||||
/** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors
|
||||
* @{ |
||||
*/ |
||||
#define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */ |
||||
#define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */ |
||||
#define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */ |
||||
#define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */ |
||||
#if defined (SYSCFG_CFGR2_CAPA_3) |
||||
#define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */ |
||||
#endif |
||||
#if defined (SYSCFG_CFGR2_CAPA_4) |
||||
#define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */ |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif |
||||
|
||||
/** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection
|
||||
* @{ |
||||
*/
|
||||
#define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000U) /* no pad connected */ |
||||
#define SYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */ |
||||
#define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */ |
||||
#define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */ |
||||
|
||||
#define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || \ |
||||
((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || \
|
||||
((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || \
|
||||
((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition
|
||||
* @{ |
||||
*/ |
||||
#define SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF |
||||
|
||||
#define IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO
|
||||
* @{ |
||||
*/
|
||||
/** @brief Fast mode Plus driving capability on a specific GPIO
|
||||
*/
|
||||
#if defined (SYSCFG_CFGR2_I2C_PB6_FMP) |
||||
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */ |
||||
#endif |
||||
#if defined (SYSCFG_CFGR2_I2C_PB7_FMP) |
||||
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */ |
||||
#endif |
||||
#if defined (SYSCFG_CFGR2_I2C_PB8_FMP) |
||||
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */ |
||||
#endif |
||||
#if defined (SYSCFG_CFGR2_I2C_PB9_FMP) |
||||
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */ |
||||
#endif |
||||
|
||||
#define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || \ |
||||
(((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || \
|
||||
(((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || \
|
||||
(((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) ) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/ |
||||
#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
||||
/**
|
||||
* @brief TIM2 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
||||
/**
|
||||
* @brief TIM3 Peripherals Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
||||
/**
|
||||
* @brief TIM6 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
||||
/**
|
||||
* @brief TIM7 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) |
||||
/**
|
||||
* @brief RTC Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
||||
/**
|
||||
* @brief WWDG Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
||||
/**
|
||||
* @brief IWDG Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP) |
||||
/**
|
||||
* @brief I2C1 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP) |
||||
/**
|
||||
* @brief I2C2 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP) |
||||
/**
|
||||
* @brief I2C3 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) |
||||
/**
|
||||
* @brief LPTIMER Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP) |
||||
/**
|
||||
* @brief TIM22 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) |
||||
#endif |
||||
|
||||
#if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP) |
||||
/**
|
||||
* @brief TIM21 Peripherals Debug mode
|
||||
*/ |
||||
#define __HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) |
||||
#define __HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) |
||||
#endif |
||||
|
||||
/** @brief Main Flash memory mapped at 0x00000000
|
||||
*/ |
||||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) |
||||
|
||||
/** @brief System Flash memory mapped at 0x00000000
|
||||
*/ |
||||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) |
||||
|
||||
|
||||
/** @brief Embedded SRAM mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1) |
||||
|
||||
/** @brief Configuration of the DBG Low Power mode.
|
||||
* @param __DBGLPMODE__: bit field to indicate in wich Low Power mode DBG is still active. |
||||
* This parameter can be a value of |
||||
* - DBGMCU_SLEEP |
||||
* - DBGMCU_STOP |
||||
* - DBGMCU_STANDBY |
||||
*/ |
||||
#define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \ |
||||
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \
|
||||
} while (0)
|
||||
|
||||
#if defined (LCD_BASE) /* STM32L0x3xx only */ |
||||
|
||||
/** @brief Macro to configure the VLCD Decoupling capacitance connection.
|
||||
* |
||||
* @param __SYSCFG_VLCD_CAPA__: specifies the decoupling of LCD capacitance for rails connection on GPIO. |
||||
* This parameter can be a combination of following values (when available): |
||||
* @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2
|
||||
* @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 |
||||
* @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 |
||||
* @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 |
||||
* @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
|
||||
* @retval None |
||||
*/ |
||||
#define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \ |
||||
MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__)) |
||||
|
||||
/**
|
||||
* @brief Returns the decoupling of LCD capacitance configured by user. |
||||
* @retval The LCD capacitance connection as configured by user. The returned can be a combination of : |
||||
* SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2
|
||||
* SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 |
||||
* SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 |
||||
* SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 |
||||
* SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
|
||||
*/ |
||||
#define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA) |
||||
|
||||
#endif |
||||
|
||||
/**
|
||||
* @brief Returns the boot mode as configured by user. |
||||
* @retval The boot mode as configured by user. The returned can be a value of : |
||||
* - SYSCFG_BOOT_MAINFLASH |
||||
* - SYSCFG_BOOT_SYSTEMFLASH |
||||
* - SYSCFG_BOOT_SRAM |
||||
*/ |
||||
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE) |
||||
|
||||
|
||||
/** @brief Check whether the specified SYSCFG flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check. |
||||
* The only parameter supported is SYSCFG_FLAG_VREFINT_READY |
||||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
||||
*/ |
||||
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__)) |
||||
|
||||
/** @brief Fast mode Plus driving capability enable macro
|
||||
* @param __FASTMODEPLUS__: This parameter can be a value of :
|
||||
* @arg SYSCFG_FASTMODEPLUS_PB6 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB7 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB8 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB9 |
||||
*/ |
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ |
||||
SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
|
||||
}while(0) |
||||
/** @brief Fast mode Plus driving capability disable macro
|
||||
* @param __FASTMODEPLUS__: This parameter can be a value of :
|
||||
* @arg SYSCFG_FASTMODEPLUS_PB6 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB7 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB8 |
||||
* @arg SYSCFG_FASTMODEPLUS_PB9 |
||||
*/ |
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ |
||||
CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
|
||||
}while(0) |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{ |
||||
*/ |
||||
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions |
||||
* @{ |
||||
*/ |
||||
HAL_StatusTypeDef HAL_Init(void); |
||||
HAL_StatusTypeDef HAL_DeInit(void); |
||||
void HAL_MspInit(void); |
||||
void HAL_MspDeInit(void); |
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Peripheral Control functions |
||||
* @{ |
||||
*/ |
||||
void HAL_IncTick(void); |
||||
void HAL_Delay(__IO uint32_t Delay); |
||||
uint32_t HAL_GetTick(void); |
||||
void HAL_SuspendTick(void); |
||||
void HAL_ResumeTick(void); |
||||
uint32_t HAL_GetHalVersion(void); |
||||
uint32_t HAL_GetREVID(void); |
||||
uint32_t HAL_GetDEVID(void); |
||||
void HAL_DBGMCU_EnableDBGSleepMode(void); |
||||
void HAL_DBGMCU_DisableDBGSleepMode(void); |
||||
void HAL_DBGMCU_EnableDBGStopMode(void); |
||||
void HAL_DBGMCU_DisableDBGStopMode(void); |
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void); |
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void); |
||||
void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph); |
||||
void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph); |
||||
uint32_t HAL_SYSCFG_GetBootMode(void); |
||||
void HAL_SYSCFG_Enable_Lock_VREFINT(void); |
||||
void HAL_SYSCFG_Disable_Lock_VREFINT(void); |
||||
void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Define the private group ***********************************/ |
||||
/**************************************************************/ |
||||
/** @defgroup HAL_Private HAL Private
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**************************************************************/ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,416 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_cortex.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of CORTEX HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_CORTEX_H |
||||
#define __STM32L0xx_HAL_CORTEX_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @{ |
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
|
||||
* @{ |
||||
*/ |
||||
|
||||
#if (__MPU_PRESENT == 1) |
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @{ |
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
||||
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
||||
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
||||
uint8_t TypeExtField; /*!< This parameter is NOT used but is kept to keep API unified through all families*/ |
||||
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
||||
}MPU_Region_InitTypeDef; |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4U) |
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0) |
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source
|
||||
* @{ |
||||
*/ |
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) |
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) |
||||
#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ |
||||
((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#if (__MPU_PRESENT == 1) |
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
|
||||
* @{ |
||||
*/ |
||||
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) |
||||
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) |
||||
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) |
||||
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01U) |
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{ |
||||
*/ |
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) |
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) |
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) |
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{ |
||||
*/ |
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) |
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) |
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) |
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) |
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) |
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) |
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) |
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) |
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) |
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) |
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) |
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) |
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) |
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) |
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) |
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) |
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) |
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) |
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) |
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) |
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) |
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) |
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) |
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) |
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) |
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) |
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) |
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) |
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) |
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) |
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) |
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) |
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) |
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{ |
||||
*/ |
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) |
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) |
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) |
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) |
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) |
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) |
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) |
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions |
||||
* @{ |
||||
*/ |
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_SystemReset(void); |
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
||||
#if (__MPU_PRESENT == 1) |
||||
/**
|
||||
* @brief Disable the MPU. |
||||
* @retval None |
||||
*/ |
||||
__STATIC_INLINE void HAL_MPU_Disable(void) |
||||
{ |
||||
|
||||
/*Data Memory Barrier setup */ |
||||
__DMB(); |
||||
/* Disable the MPU */ |
||||
MPU->CTRL = 0; |
||||
} |
||||
|
||||
/**
|
||||
* @brief Enable the MPU. |
||||
* @param MPU_Control: Specifies the control mode of the MPU during hard fault, |
||||
* NMI, FAULTMASK and privileged access to the default memory |
||||
* This parameter can be one of the following values: |
||||
* @arg MPU_HFNMI_PRIVDEF_NONE |
||||
* @arg MPU_HARDFAULT_NMI |
||||
* @arg MPU_PRIVILEGED_DEFAULT |
||||
* @arg MPU_HFNMI_PRIVDEF |
||||
* @retval None |
||||
*/ |
||||
|
||||
__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) |
||||
{ |
||||
/* Enable the MPU */ |
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
||||
/* Data Synchronization Barrier setup */ |
||||
__DSB(); |
||||
/* Instruction Synchronization Barrier setup */ |
||||
__ISB(); |
||||
|
||||
} |
||||
#endif /* __MPU_PRESENT */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions |
||||
* @{ |
||||
*/ |
||||
|
||||
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); |
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
||||
void HAL_SYSTICK_IRQHandler(void); |
||||
void HAL_SYSTICK_Callback(void); |
||||
#if (__MPU_PRESENT == 1) |
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
||||
#endif /* __MPU_PRESENT */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private types -------------------------------------------------------------*/ |
||||
/* Private variables ---------------------------------------------------------*/ |
||||
/* Private constants ---------------------------------------------------------*/ |
||||
/* Private macros ------------------------------------------------------------*/ |
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
#if (__MPU_PRESENT == 1) |
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
||||
((STATE) == MPU_REGION_DISABLE)) |
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO)) |
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7)) |
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ |
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB)) |
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) |
||||
#endif /* __MPU_PRESENT */ |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_CORTEX_H */ |
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,208 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_def.h |
||||
* @author MCD Application Team |
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_DEF |
||||
#define __STM32L0xx_HAL_DEF |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx.h" |
||||
#include "Legacy/stm32_hal_legacy.h" |
||||
#include <stdio.h> |
||||
#include <stdint.h> |
||||
#include <stdbool.h> |
||||
|
||||
/* Exported types ------------------------------------------------------------*/ |
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{ |
||||
HAL_OK = 0x00U, |
||||
HAL_ERROR = 0x01U, |
||||
HAL_BUSY = 0x02U, |
||||
HAL_TIMEOUT = 0x03U |
||||
} HAL_StatusTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/ |
||||
typedef enum
|
||||
{ |
||||
HAL_UNLOCKED = 0x00U, |
||||
HAL_LOCKED = 0x01U
|
||||
} HAL_LockTypeDef; |
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
|
||||
#define UNUSED(x) ((void)(x)) |
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU |
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) |
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) |
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ |
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0) |
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle. |
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter |
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field. |
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed |
||||
* (i.e. HAL_PPP_MspInit() will not be executed). |
||||
* - When there is a need to reconfigure the low level hardware: instead of calling |
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). |
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function |
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware. |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) |
||||
|
||||
#if (USE_RTOS == 1) |
||||
|
||||
/* Reserved for future use */ |
||||
#error "USE_RTOS should be 0 in the current HAL release" |
||||
|
||||
#else |
||||
#define __HAL_LOCK(__HANDLE__) \ |
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0) |
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \ |
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0) |
||||
#endif /* USE_RTOS */ |
||||
|
||||
#if defined ( __GNUC__ ) |
||||
#ifndef __weak |
||||
#define __weak __attribute__((weak)) |
||||
#endif /* __weak */ |
||||
#ifndef __packed |
||||
#define __packed __attribute__((__packed__)) |
||||
#endif /* __packed */ |
||||
|
||||
#define __NOINLINE __attribute__ ( (noinline) ) |
||||
|
||||
#endif /* __GNUC__ */ |
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ |
||||
#if defined (__GNUC__) /* GNU Compiler */ |
||||
#ifndef __ALIGN_END |
||||
#define __ALIGN_END __attribute__ ((aligned (4))) |
||||
#endif /* __ALIGN_END */ |
||||
#ifndef __ALIGN_BEGIN |
||||
#define __ALIGN_BEGIN |
||||
#endif /* __ALIGN_BEGIN */ |
||||
#else |
||||
#ifndef __ALIGN_END |
||||
#define __ALIGN_END |
||||
#endif /* __ALIGN_END */ |
||||
#ifndef __ALIGN_BEGIN |
||||
#if defined (__CC_ARM) /* ARM Compiler */ |
||||
#define __ALIGN_BEGIN __align(4) |
||||
#elif defined (__ICCARM__) /* IAR Compiler */ |
||||
#define __ALIGN_BEGIN |
||||
#endif /* __CC_ARM */ |
||||
#endif /* __ALIGN_BEGIN */ |
||||
#endif /* __GNUC__ */ |
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition |
||||
*/
|
||||
#if defined ( __CC_ARM ) |
||||
/* ARM Compiler
|
||||
------------ |
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module. |
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM. |
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target' |
||||
dialog.
|
||||
*/ |
||||
#define __RAM_FUNC HAL_StatusTypeDef |
||||
|
||||
#define __NOINLINE __attribute__ ( (noinline) ) |
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) |
||||
/* ICCARM Compiler
|
||||
--------------- |
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/ |
||||
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef |
||||
|
||||
#define __NOINLINE _Pragma("optimize = no_inline") |
||||
|
||||
#elif defined ( __GNUC__ ) |
||||
/* GNU Compiler
|
||||
------------ |
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))". |
||||
*/ |
||||
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) |
||||
|
||||
#endif |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* ___STM32L0xx_HAL_DEF */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,694 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_dma.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of DMA HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
****************************************************************************** |
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_DMA_H |
||||
#define __STM32L0xx_HAL_DMA_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMA DMA
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @{ |
||||
*/ |
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/ |
||||
typedef struct |
||||
{ |
||||
uint32_t Request; /*!< Specifies the request selected for the specified channel.
|
||||
This parameter can be a value of @ref DMA_request */ |
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory. |
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */ |
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
When Memory to Memory transfer is used, this is the Source Increment mode |
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
When Memory to Memory transfer is used, this is the Destination Increment mode |
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
When Memory to Memory transfer is used, this is the Source Alignment format |
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
When Memory to Memory transfer is used, this is the Destination Alignment format |
||||
This parameter can be a value of @ref DMA_Memory_data_size */ |
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular).
|
||||
This parameter can be a value of @ref DMA_mode |
||||
@note The circular buffer mode cannot be used if the memory-to-memory |
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */ |
||||
} DMA_InitTypeDef; |
||||
|
||||
/**
|
||||
* @brief DMA Configuration enumeration values definition
|
||||
*/
|
||||
typedef enum
|
||||
{ |
||||
DMA_MODE = 0U, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ |
||||
DMA_PRIORITY = 1U, /*!< Control related priority level Parameter in DMA_InitTypeDef */ |
||||
|
||||
} DMA_ControlTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum |
||||
{ |
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA process success and ready for use */ |
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||
HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ |
||||
HAL_DMA_STATE_READY_HALF = 0x05U, /*!< DMA Half process success */ |
||||
}HAL_DMA_StateTypeDef; |
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum |
||||
{ |
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
||||
HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ |
||||
|
||||
}HAL_DMA_LevelCompleteTypeDef; |
||||
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef |
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */ |
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
||||
|
||||
void *Parent; /*!< Parent object state */ |
||||
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
||||
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
||||
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
||||
|
||||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */ |
||||
|
||||
} DMA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Codes
|
||||
* @{ |
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
||||
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ |
||||
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< no ongoing transfer */ |
||||
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ |
||||
|
||||
#if defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
||||
((INSTANCE) == DMA1_Channel2) || \
|
||||
((INSTANCE) == DMA1_Channel3) || \
|
||||
((INSTANCE) == DMA1_Channel4) || \
|
||||
((INSTANCE) == DMA1_Channel5)) |
||||
#else |
||||
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
||||
((INSTANCE) == DMA1_Channel2) || \
|
||||
((INSTANCE) == DMA1_Channel3) || \
|
||||
((INSTANCE) == DMA1_Channel4) || \
|
||||
((INSTANCE) == DMA1_Channel5) || \
|
||||
((INSTANCE) == DMA1_Channel6) || \
|
||||
((INSTANCE) == DMA1_Channel7))
|
||||
|
||||
#endif |
||||
#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_request DMA request defintiions
|
||||
* @{ |
||||
*/
|
||||
|
||||
#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
||||
|
||||
#define DMA_REQUEST_0 ((uint32_t)0x00000000U) |
||||
#define DMA_REQUEST_1 ((uint32_t)0x00000001U) |
||||
#define DMA_REQUEST_2 ((uint32_t)0x00000002U) |
||||
#define DMA_REQUEST_3 ((uint32_t)0x00000003U) |
||||
#define DMA_REQUEST_4 ((uint32_t)0x00000004U) |
||||
#define DMA_REQUEST_5 ((uint32_t)0x00000005U) |
||||
#define DMA_REQUEST_6 ((uint32_t)0x00000006U) |
||||
#define DMA_REQUEST_7 ((uint32_t)0x00000007U) |
||||
#define DMA_REQUEST_8 ((uint32_t)0x00000008U) |
||||
#define DMA_REQUEST_9 ((uint32_t)0x00000009U) |
||||
#define DMA_REQUEST_10 ((uint32_t)0x0000000AU) |
||||
#define DMA_REQUEST_11 ((uint32_t)0x0000000BU) |
||||
#define DMA_REQUEST_12 ((uint32_t)0x0000000CU) |
||||
#define DMA_REQUEST_13 ((uint32_t)0x0000000DU) |
||||
#define DMA_REQUEST_14 ((uint32_t)0x0000000EU) |
||||
#define DMA_REQUEST_15 ((uint32_t)0x0000000FU) |
||||
|
||||
#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
||||
((REQUEST) == DMA_REQUEST_1) || \
|
||||
((REQUEST) == DMA_REQUEST_2) || \
|
||||
((REQUEST) == DMA_REQUEST_3) || \
|
||||
((REQUEST) == DMA_REQUEST_4) || \
|
||||
((REQUEST) == DMA_REQUEST_5) || \
|
||||
((REQUEST) == DMA_REQUEST_6) || \
|
||||
((REQUEST) == DMA_REQUEST_7) || \
|
||||
((REQUEST) == DMA_REQUEST_8) || \
|
||||
((REQUEST) == DMA_REQUEST_9) || \
|
||||
((REQUEST) == DMA_REQUEST_10) || \
|
||||
((REQUEST) == DMA_REQUEST_11) || \
|
||||
((REQUEST) == DMA_REQUEST_12) || \
|
||||
((REQUEST) == DMA_REQUEST_13) || \
|
||||
((REQUEST) == DMA_REQUEST_14) || \
|
||||
((REQUEST) == DMA_REQUEST_15)) |
||||
|
||||
#else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ |
||||
|
||||
#define DMA_REQUEST_0 ((uint32_t)0x00000000U) |
||||
#define DMA_REQUEST_1 ((uint32_t)0x00000001U) |
||||
#define DMA_REQUEST_2 ((uint32_t)0x00000002U) |
||||
#define DMA_REQUEST_3 ((uint32_t)0x00000003U) |
||||
#define DMA_REQUEST_4 ((uint32_t)0x00000004U) |
||||
#define DMA_REQUEST_5 ((uint32_t)0x00000005U) |
||||
#define DMA_REQUEST_6 ((uint32_t)0x00000006U) |
||||
#define DMA_REQUEST_7 ((uint32_t)0x00000007U) |
||||
#define DMA_REQUEST_8 ((uint32_t)0x00000008U) |
||||
#define DMA_REQUEST_9 ((uint32_t)0x00000009U) |
||||
#define DMA_REQUEST_11 ((uint32_t)0x0000000BU) |
||||
|
||||
#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ |
||||
((REQUEST) == DMA_REQUEST_1) || \
|
||||
((REQUEST) == DMA_REQUEST_2) || \
|
||||
((REQUEST) == DMA_REQUEST_3) || \
|
||||
((REQUEST) == DMA_REQUEST_4) || \
|
||||
((REQUEST) == DMA_REQUEST_5) || \
|
||||
((REQUEST) == DMA_REQUEST_6) || \
|
||||
((REQUEST) == DMA_REQUEST_7) || \
|
||||
((REQUEST) == DMA_REQUEST_8) || \
|
||||
((REQUEST) == DMA_REQUEST_9) || \
|
||||
((REQUEST) == DMA_REQUEST_11)) |
||||
#endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
|
||||
* @{ |
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ |
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ |
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Data_buffer_size DMA Data Buffer Size Check
|
||||
* @{ |
||||
*/
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral Incremented Mode
|
||||
* @{ |
||||
*/
|
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
||||
#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */ |
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
||||
((STATE) == DMA_PINC_DISABLE)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory Incremented Mode
|
||||
* @{ |
||||
*/
|
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
||||
#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */ |
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
||||
((STATE) == DMA_MINC_DISABLE)) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral Data Size Alignment
|
||||
* @{ |
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */ |
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD)) |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory Data Size Alignment
|
||||
* @{
|
||||
*/ |
||||
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */ |
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD )) |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_mode DMA Mode
|
||||
* @{ |
||||
*/
|
||||
#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */ |
||||
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ |
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
||||
((MODE) == DMA_CIRCULAR))
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority Level
|
||||
* @{ |
||||
*/ |
||||
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */ |
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA Interrupt Definitions
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
||||
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
||||
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_flag_definitions DMA Flag Definitions
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define DMA_FLAG_GL1 ((uint32_t)0x00000001U) |
||||
#define DMA_FLAG_TC1 ((uint32_t)0x00000002U) |
||||
#define DMA_FLAG_HT1 ((uint32_t)0x00000004U) |
||||
#define DMA_FLAG_TE1 ((uint32_t)0x00000008U) |
||||
#define DMA_FLAG_GL2 ((uint32_t)0x00000010U) |
||||
#define DMA_FLAG_TC2 ((uint32_t)0x00000020U) |
||||
#define DMA_FLAG_HT2 ((uint32_t)0x00000040U) |
||||
#define DMA_FLAG_TE2 ((uint32_t)0x00000080U) |
||||
#define DMA_FLAG_GL3 ((uint32_t)0x00000100U) |
||||
#define DMA_FLAG_TC3 ((uint32_t)0x00000200U) |
||||
#define DMA_FLAG_HT3 ((uint32_t)0x00000400U) |
||||
#define DMA_FLAG_TE3 ((uint32_t)0x00000800U) |
||||
#define DMA_FLAG_GL4 ((uint32_t)0x00001000U) |
||||
#define DMA_FLAG_TC4 ((uint32_t)0x00002000U) |
||||
#define DMA_FLAG_HT4 ((uint32_t)0x00004000U) |
||||
#define DMA_FLAG_TE4 ((uint32_t)0x00008000U) |
||||
#define DMA_FLAG_GL5 ((uint32_t)0x00010000U) |
||||
#define DMA_FLAG_TC5 ((uint32_t)0x00020000U) |
||||
#define DMA_FLAG_HT5 ((uint32_t)0x00040000U) |
||||
#define DMA_FLAG_TE5 ((uint32_t)0x00080000U) |
||||
#define DMA_FLAG_GL6 ((uint32_t)0x00100000U) |
||||
#define DMA_FLAG_TC6 ((uint32_t)0x00200000U) |
||||
#define DMA_FLAG_HT6 ((uint32_t)0x00400000U) |
||||
#define DMA_FLAG_TE6 ((uint32_t)0x00800000U) |
||||
#define DMA_FLAG_GL7 ((uint32_t)0x01000000U) |
||||
#define DMA_FLAG_TC7 ((uint32_t)0x02000000U) |
||||
#define DMA_FLAG_HT7 ((uint32_t)0x04000000U) |
||||
#define DMA_FLAG_TE7 ((uint32_t)0x08000000U) |
||||
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @brief Reset DMA handle state
|
||||
* @param __HANDLE__: DMA handle |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) |
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval None. |
||||
*/ |
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) |
||||
|
||||
|
||||
/* Interrupt & Flag management */ |
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer complete flag index. |
||||
*/ |
||||
|
||||
#if defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5) |
||||
#else |
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7)
|
||||
#endif |
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified half transfer complete flag index. |
||||
*/ |
||||
#if defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5) |
||||
#else |
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7) |
||||
#endif |
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer error flag index. |
||||
*/ |
||||
#if defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5) |
||||
#else |
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7) |
||||
#endif |
||||
/**
|
||||
* @brief Returns the current DMA Channel Global interrupt flag. |
||||
* @param __HANDLE__: DMA handle |
||||
* @retval The specified transfer error flag index. |
||||
*/ |
||||
#if defined (STM32L011xx) || defined (STM32L021xx) |
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||||
DMA_ISR_GIF5) |
||||
#else |
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
|
||||
DMA_ISR_GIF7) |
||||
#endif |
||||
/**
|
||||
* @brief Get the DMA Channel pending flags. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __FLAG__: Get the specified flag. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag |
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag |
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag |
||||
* @arg DMA_ISR_GIFx: Global interrupt flag |
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET). |
||||
*/ |
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __FLAG__: specifies the flag to clear. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag |
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag |
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag |
||||
* @arg DMA_ISR_GIFx: Global interrupt flag |
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
||||
|
||||
/**
|
||||
* @brief Enables the specified DMA Channel interrupts. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Disables the specified DMA Channel interrupts. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
||||
* @retval None |
||||
*/ |
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMA Channel interrupt is enabled or not. |
||||
* @param __HANDLE__: DMA handle |
||||
* @param __INTERRUPT__: specifies the DMA interrupt source to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask |
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask |
||||
* @arg DMA_IT_TE: Transfer error interrupt mask |
||||
* @retval The state of DMA_IT (SET or RESET). |
||||
*/ |
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) |
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer. |
||||
* @param __HANDLE__: DMA handle |
||||
* |
||||
* @retval The number of remaining data units in the current DMA Channel transfer. |
||||
*/ |
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Initialization and de-initialization functions *****************************/ |
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* IO operation functions *****************************************************/ |
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/* Peripheral State and Error functions ***************************************/ |
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
/* Define the private group ***********************************/ |
||||
/**************************************************************/ |
||||
/** @defgroup DMA_Private DMA Private
|
||||
* @{ |
||||
*/ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
/**************************************************************/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* __STM32L0xx_HAL_DMA_H */ |
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||||
|
||||
@ -0,0 +1,386 @@ |
||||
/**
|
||||
****************************************************************************** |
||||
* @file stm32l0xx_hal_flash.h |
||||
* @author MCD Application Team |
||||
* @brief Header file of Flash HAL module. |
||||
****************************************************************************** |
||||
* @attention |
||||
* |
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without modification, |
||||
* are permitted provided that the following conditions are met: |
||||
* 1. Redistributions of source code must retain the above copyright notice, |
||||
* this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, |
||||
* this list of conditions and the following disclaimer in the documentation |
||||
* and/or other materials provided with the distribution. |
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
******************************************************************************
|
||||
*/ |
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/ |
||||
#ifndef __STM32L0xx_HAL_FLASH_H |
||||
#define __STM32L0xx_HAL_FLASH_H |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
/* Includes ------------------------------------------------------------------*/ |
||||
#include "stm32l0xx_hal_def.h" |
||||
|
||||
/** @addtogroup STM32L0xx_HAL_Driver
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Private_Constants
|
||||
* @{ |
||||
*/ |
||||
#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ |
||||
#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Private_Macros
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(_VALUE_) ((_VALUE_) == FLASH_TYPEPROGRAM_WORD) |
||||
|
||||
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ |
||||
((__LATENCY__) == FLASH_LATENCY_1)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition |
||||
*/ |
||||
typedef enum
|
||||
{ |
||||
FLASH_PROC_NONE = 0,
|
||||
FLASH_PROC_PAGEERASE = 1, |
||||
FLASH_PROC_PROGRAM = 2, |
||||
} FLASH_ProcedureTypeDef; |
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/ |
||||
typedef struct |
||||
{ |
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ |
||||
|
||||
__IO uint32_t NbPagesToErase; /*!< Internal variable to save the remaining sectors to erase in IT context*/ |
||||
|
||||
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ |
||||
|
||||
__IO uint32_t Page; /*!< Internal variable to define the current page which is erasing */ |
||||
|
||||
HAL_LockTypeDef Lock; /*!< FLASH locking object */ |
||||
|
||||
__IO uint32_t ErrorCode; /*!< FLASH error code
|
||||
This parameter can be a value of @ref FLASH_Error_Codes */ |
||||
} FLASH_ProcessTypeDef; |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Exported constants --------------------------------------------------------*/ |
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{ |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error_Codes FLASH Error Codes
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ |
||||
#define HAL_FLASH_ERROR_PGA 0x01U /*!< Programming alignment error */ |
||||
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ |
||||
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ |
||||
#define HAL_FLASH_ERROR_SIZE 0x08U /*!< */ |
||||
#define HAL_FLASH_ERROR_RD 0x10U /*!< Read protected error */ |
||||
#define HAL_FLASH_ERROR_FWWERR 0x20U /*!< FLASH Write or Erase operation aborted */ |
||||
#define HAL_FLASH_ERROR_NOTZERO 0x40U /*!< FLASH Write operation is done in a not-erased region */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Page_Size FLASH size information
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFF) * 1024U) |
||||
#define FLASH_PAGE_SIZE ((uint32_t)128U) /*!< FLASH Page Size in bytes */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{ |
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{ |
||||
*/
|
||||
#define FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */ |
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @defgroup FLASH_Interrupts FLASH Interrupts
|
||||
* @{ |
||||
*/ |
||||
|
||||
#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */ |
||||
#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */ |
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags FLASH Flags
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ |
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ |
||||
#define FLASH_FLAG_ENDHV FLASH_SR_HVOFF /*!< FLASH End of High Voltage flag */ |
||||
#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */ |
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ |
||||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ |
||||
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ |
||||
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */ |
||||
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protected error flag */ |
||||
#define FLASH_FLAG_FWWERR FLASH_SR_FWWERR /*!< FLASH Write or Errase operation aborted */ |
||||
#define FLASH_FLAG_NOTZEROERR FLASH_SR_NOTZEROERR /*!< FLASH Read protected error flag */ |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys FLASH Keys
|
||||
* @{ |
||||
*/
|
||||
|
||||
#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */ |
||||
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 |
||||
to unlock the RUN_PD bit in FLASH_ACR */ |
||||
|
||||
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEFU) /*!< Flash program erase key1 */ |
||||
#define FLASH_PEKEY2 ((uint32_t)0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2 |
||||
to unlock the write access to the FLASH_PECR register and |
||||
data EEPROM */ |
||||
|
||||
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBFU) /*!< Flash program memory key1 */ |
||||
#define FLASH_PRGKEY2 ((uint32_t)0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2 |
||||
to unlock the program memory */ |
||||
|
||||
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8U) /*!< Flash option key1 */ |
||||
#define FLASH_OPTKEY2 ((uint32_t)0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to |
||||
unlock the write access to the option byte block */ |
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* CMSIS_Legacy */
|
||||
|
||||
#if defined ( __ICCARM__ ) |
||||
#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk |
||||
#endif |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/ |
||||
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{ |
||||
*/ |
||||
|
||||
|
||||
/** @defgroup FLASH_Interrupt FLASH Interrupts
|
||||
* @brief macros to handle FLASH interrupts |
||||
* @{ |
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt. |
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt |
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->PECR), (__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt. |
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt |
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none |
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__)) |
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__ specifies the FLASH flag to check. |
||||
* This parameter can be one of the following values: |
||||
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag |
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag |
||||
* @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode |
||||
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag |
||||
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag |
||||
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx) |
||||
* @arg @ref FLASH_FLAG_RDERR FLASH Read protected error flag |
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_FWWERR FLASH Fetch While Write Error flag |
||||
* @arg @ref FLASH_FLAG_NOTZEROERR Not Zero area error flag
|
||||
* @retval The new state of __FLAG__ (SET or RESET). |
||||
*/ |
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) |
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag. |
||||
* @param __FLAG__ specifies the FLASH flags to clear. |
||||
* This parameter can be any combination of the following values: |
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag |
||||
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag |
||||
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx) |
||||
* @arg @ref FLASH_FLAG_RDERR FLASH Read protected error flag |
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_FWWERR FLASH Fetch While Write Error flag |
||||
* @arg @ref FLASH_FLAG_NOTZEROERR Not Zero area error flag
|
||||
* @retval none |
||||
*/ |
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) |
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/**
|
||||
* @} |
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extended module */ |
||||
#include "stm32l0xx_hal_flash_ex.h" |
||||
#include "stm32l0xx_hal_flash_ramfunc.h" |
||||
|
||||
/* Exported functions --------------------------------------------------------*/ |
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{ |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{ |
||||
*/ |
||||
/* IO operation functions *****************************************************/ |
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); |
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data); |
||||
|
||||
/* FLASH IRQ handler function */ |
||||
void HAL_FLASH_IRQHandler(void); |
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); |
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral Control functions ***********************************************/ |
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); |
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{ |
||||
*/ |
||||
/* Peripheral State and Error functions ***************************************/ |
||||
uint32_t HAL_FLASH_GetError(void); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/* Private function -------------------------------------------------*/ |
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{ |
||||
*/ |
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||
|
||||
/**
|
||||
* @} |
||||
*/ |
||||