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114 lines
6.9 KiB
114 lines
6.9 KiB
#pragma once
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#include "common.h"
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// AUTHOR : Ondrej Hruska
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// DATE : 12/2015
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// DESCR : Control registers and bit masks for FLASH control
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//
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// FLASH, DATA EEPROM and Option Bytes Registers
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//****************************************************************************
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//*
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//* REGISTERS
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//*
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//****************************************************************************
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// FLASH registers
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#define FLASH_ACR MMIO32(FLASH_CTRL + 0x00) // Access control register,
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#define FLASH_PECR MMIO32(FLASH_CTRL + 0x04) // Program/erase control register,
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#define FLASH_PDKEYR MMIO32(FLASH_CTRL + 0x08) // Power down key register,
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#define FLASH_PEKEYR MMIO32(FLASH_CTRL + 0x0c) // Program/erase key register,
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#define FLASH_PRGKEYR MMIO32(FLASH_CTRL + 0x10) // Program memory key register,
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#define FLASH_OPTKEYR MMIO32(FLASH_CTRL + 0x14) // Option byte key register,
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#define FLASH_SR MMIO32(FLASH_CTRL + 0x18) // Status register,
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#define FLASH_OBR MMIO32(FLASH_CTRL + 0x1c) // Option byte register,
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#define FLASH_WRPR MMIO32(FLASH_CTRL + 0x20) // Write protection register,
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#define FLASH_WRPR1 MMIO32(FLASH_CTRL + 0x28) // Write protection register 1,
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#define FLASH_WRPR2 MMIO32(FLASH_CTRL + 0x2C) // Write protection register 2,
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// FLASH option bytes (maybe incorrect, not tested)
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#define OB_RDP MMIO32(OB_CTRL + 0x00) // Read protection register,
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#define OB_USER MMIO32(OB_CTRL + 0x04) // user register,
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#define OB_WRP01 MMIO32(OB_CTRL + 0x08) // write protection register 0 1,
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#define OB_WRP23 MMIO32(OB_CTRL + 0x0C) // write protection register 2 3,
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#define OB_WRP45 MMIO32(OB_CTRL + 0x10) // write protection register 4 5,
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#define OB_WRP67 MMIO32(OB_CTRL + 0x14) // write protection register 6 7,
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#define OB_WRP89 MMIO32(OB_CTRL + 0x18) // write protection register 8 9,
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#define OB_WRP1011 MMIO32(OB_CTRL + 0x1C) // write protection register 10 11,
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//****************************************************************************
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//*
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//* BIT MASKS AND DEFINITIONS
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//*
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//****************************************************************************
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//****************** Bit definition for FLASH_ACR register *****************
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#define FLASH_ACR_LATENCY 0x00000001 // Latency
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#define FLASH_ACR_PRFTEN 0x00000002 // Prefetch Buffer Enable
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#define FLASH_ACR_ACC64 0x00000004 // Access 64 bits
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#define FLASH_ACR_SLEEP_PD 0x00000008 // Flash mode during sleep mode
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#define FLASH_ACR_RUN_PD 0x00000010 // Flash mode during RUN mode
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//****************** Bit definition for FLASH_PECR register *****************
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#define FLASH_PECR_PELOCK 0x00000001 // FLASH_PECR and Flash data Lock
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#define FLASH_PECR_PRGLOCK 0x00000002 // Program matrix Lock
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#define FLASH_PECR_OPTLOCK 0x00000004 // Option byte matrix Lock
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#define FLASH_PECR_PROG 0x00000008 // Program matrix selection
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#define FLASH_PECR_DATA 0x00000010 // Data matrix selection
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#define FLASH_PECR_FTDW 0x00000100 // Fixed Time Data write for Word/Half Word/Byte programming
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#define FLASH_PECR_ERASE 0x00000200 // Page erasing mode
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#define FLASH_PECR_FPRG 0x00000400 // Fast Page/Half Page programming mode
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#define FLASH_PECR_PARALLBANK 0x00008000 // Parallel Bank mode
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#define FLASH_PECR_EOPIE 0x00010000 // End of programming interrupt
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#define FLASH_PECR_ERRIE 0x00020000 // Error interrupt
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#define FLASH_PECR_OBL_LAUNCH 0x00040000 // Launch the option byte loading
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//***************** Bit definition for FLASH_PDKEYR register *****************
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#define FLASH_PDKEYR_PDKEYR 0xFFFFFFFF // FLASH_PEC and data matrix Key
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//***************** Bit definition for FLASH_PEKEYR register *****************
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#define FLASH_PEKEYR_PEKEYR 0xFFFFFFFF // FLASH_PEC and data matrix Key
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//***************** Bit definition for FLASH_PRGKEYR register *****************
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#define FLASH_PRGKEYR_PRGKEYR 0xFFFFFFFF // Program matrix Key
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//***************** Bit definition for FLASH_OPTKEYR register *****************
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#define FLASH_OPTKEYR_OPTKEYR 0xFFFFFFFF // Option bytes matrix Key
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//***************** Bit definition for FLASH_SR register ******************
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#define FLASH_SR_BSY 0x00000001 // Busy
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#define FLASH_SR_EOP 0x00000002 // End Of Programming
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#define FLASH_SR_ENHV 0x00000004 // End of high voltage
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#define FLASH_SR_READY 0x00000008 // Flash ready after low power mode
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#define FLASH_SR_WRPERR 0x00000100 // Write protected error
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#define FLASH_SR_PGAERR 0x00000200 // Programming Alignment Error
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#define FLASH_SR_SIZERR 0x00000400 // Size error
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#define FLASH_SR_OPTVERR 0x00000800 // Option validity error
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#define FLASH_SR_OPTVERRUSR 0x00001000 // Option User validity error
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#define FLASH_SR_RDERR 0x00002000 // Read protected error
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//***************** Bit definition for FLASH_OBR register ******************
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#define FLASH_OBR_RDPRT 0x000000AA // Read Protection
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#define FLASH_OBR_SPRMOD 0x00000100 // Selection of protection mode of WPRi bits (available only in STM32L1xx Medium-density Plus devices)
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#define FLASH_OBR_BOR_LEV 0x000F0000 // BOR_LEV[3:0] Brown Out Reset Threshold Level
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#define FLASH_OBR_IWDG_SW 0x00100000 // IWDG_SW
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#define FLASH_OBR_nRST_STOP 0x00200000 // nRST_STOP
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#define FLASH_OBR_nRST_STDBY 0x00400000 // nRST_STDBY
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#define FLASH_OBR_BFB2 0x00800000 // BFB2(available only in STM32L1xx High-density devices)
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//***************** Bit definition for FLASH_WRPR register *****************
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#define FLASH_WRPR_WRP 0xFFFFFFFF // Write Protection bits
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//***************** Bit definition for FLASH_WRPR1 register ****************
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#define FLASH_WRPR1_WRP 0xFFFFFFFF // Write Protection bits (available only in STM32L1xx Medium-density Plus and High-density devices)
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//***************** Bit definition for FLASH_WRPR2 register ****************
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#define FLASH_WRPR2_WRP 0xFFFFFFFF // Write Protection bits (available only in STM32L1xx High-density devices)
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