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					@ -61,7 +61,10 @@ void init_usart(void) | 
				
			
			
		
	
		
			
				
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					void init_systick(void) | 
				
			
			
		
	
		
			
				
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					{ | 
				
			
			
		
	
		
			
				
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						SysTick_CSR = (SysTick_CSR & ~SysTick_CSR_CLKSOURCE) | SysTick_CSR_CLKSOURCE_CORE; | 
				
			
			
		
	
		
			
				
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						//SysTick_CSR = (SysTick_CSR & ~SysTick_CSR_CLKSOURCE) | (1 << __CTZ(SysTick_CSR_CLKSOURCE));
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						patch_register(SysTick_CSR, SysTick_CSR_CLKSOURCE, 1); // 1 - core, 0 - div 8
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						SysTick_RELOAD = 16000; // 1ms interrupt @ 16MHz core clock
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						SysTick_CSR |= SysTick_CSR_TICKINT | SysTick_CSR_ENABLE; | 
				
			
			
		
	
		
			
				
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					} | 
				
			
			
		
	
	
		
			
				
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					@ -103,6 +106,8 @@ void init_dac(void) | 
				
			
			
		
	
		
			
				
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						gpio_set_mode(GPIOA, BIT4, MODER_ANALOG); // PA4 - DAC CH1 out
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						DAC_CR |= DAC_CR_EN1; // enable first channel
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						DAC_DHR12R1 = 0; // reset value
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					} | 
				
			
			
		
	
		
			
				
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					@ -114,14 +119,14 @@ void init_pwm1(void) | 
				
			
			
		
	
		
			
				
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						// using timer 3, channel 1
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						gpio_set_af(GPIOA, BIT6, AF2); | 
				
			
			
		
	
		
			
				
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						patch_register(&TIM3_CCMR1, TIM_CCMR1_OC1M, TIM_OCM_PWM1); // set PWM1 mode
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						patch_register(TIM3_CCMR1, TIM_CCMR1_OC1M, TIM_OCM_PWM1); // set PWM1 mode
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						TIM3_CCMR1 |= TIM_CCMR1_OC1PE; // preload enable
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						TIM3_CR1 |= TIM_CR1_ARPE; // auto reload is buffered
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						TIM3_CCER |= TIM_CCER_CC1E; // enable output compare (PWM output)
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						patch_register(&TIM3_CR1, TIM_CR1_CMS, TIM_CMS_EDGE); // centering mode
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						patch_register(&TIM3_CR1, TIM_CR1_DIR, 0); // count upwards only
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						patch_register(TIM3_CR1, TIM_CR1_CMS, TIM_CMS_EDGE); // centering mode
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						patch_register(TIM3_CR1, TIM_CR1_DIR, 0); // count upwards only
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						// frequency set to 16 kHz
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