MightyPork 3999c51eb7 implement a more readable bit mask syntax, add (ldXX Wr Rd Rd) with separate dest and both sources

2020-10-17 14:54:51 +02:00

..

src

implement a more readable bit mask syntax, add (ldXX Wr Rd Rd) with separate dest and both sources

2020-10-17 14:54:51 +02:00

Cargo.toml

Add ld{32,16,8},sw{32,16,8},clz{,32,16,8},clo{,32,16,8},rng,rev,rbit; rename swap->xch

2020-10-11 22:01:12 +02:00