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@ -448,10 +448,15 @@ static int r82xx_set_pll(struct r82xx_priv *priv, uint32_t freq) |
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return rc; |
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return rc; |
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/* set VCO current = 100 RTL-SDRBLOG MOD: MAX CURRENT*/ |
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/* set VCO current = 100 RTL-SDRBLOG MOD: MAX CURRENT*/ |
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rc = r82xx_write_reg_mask(priv, 0x12, 0x00, 0xe0); |
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rc = r82xx_write_reg_mask(priv, 0x12, 0x06, 0xff); |
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if (rc < 0) |
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if (rc < 0) |
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return rc; |
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return rc; |
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// Test turning tracking filter off
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//rc = r82xx_write_reg_mask(priv, 0x1a, 0x40, 0xC0);
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/* Calculate divider */ |
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/* Calculate divider */ |
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while (mix_div <= 64) { |
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while (mix_div <= 64) { |
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if (((freq_khz * mix_div) >= vco_min) && |
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if (((freq_khz * mix_div) >= vco_min) && |
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@ -540,7 +545,7 @@ static int r82xx_set_pll(struct r82xx_priv *priv, uint32_t freq) |
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if (!i) { |
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if (!i) { |
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/* Didn't lock. Increase VCO current */ |
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/* Didn't lock. Increase VCO current */ |
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rc = r82xx_write_reg_mask(priv, 0x12, 0x00, 0xe0); |
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rc = r82xx_write_reg_mask(priv, 0x12, 0x06, 0xff); |
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if (rc < 0) |
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if (rc < 0) |
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return rc; |
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return rc; |
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} |
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} |
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@ -663,6 +668,9 @@ static int r82xx_sysfreq_sel(struct r82xx_priv *priv, uint32_t freq, |
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rc = r82xx_write_reg_mask(priv, 0x11, cp_cur, 0x38); |
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rc = r82xx_write_reg_mask(priv, 0x11, cp_cur, 0x38); |
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if (rc < 0) |
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if (rc < 0) |
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return rc; |
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return rc; |
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// RTLSDRBLOG. Improve L-band performance by setting PLL drop out to 2.0v
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div_buf_cur = 0xa0; |
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rc = r82xx_write_reg_mask(priv, 0x17, div_buf_cur, 0x30); |
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rc = r82xx_write_reg_mask(priv, 0x17, div_buf_cur, 0x30); |
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if (rc < 0) |
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if (rc < 0) |
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return rc; |
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return rc; |
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@ -968,7 +976,7 @@ int r82xx_set_gain(struct r82xx_priv *priv, int set_manual_gain, int gain) |
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return rc; |
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return rc; |
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/* set fixed VGA gain for now (16.3 dB) */ |
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/* set fixed VGA gain for now (16.3 dB) */ |
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rc = r82xx_write_reg_mask(priv, 0x0c, 0x08, 0x9f); |
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rc = r82xx_write_reg_mask(priv, 0x0c, 0x08, 0x9f); //init val 0x08 0x0c works well at 1.7
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if (rc < 0) |
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if (rc < 0) |
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return rc; |
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return rc; |
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