@ -206,7 +206,6 @@ int fc0012_set_params(void *dev, uint32_t freq, uint32_t bandwidth)
vco_select = 1 ;
vco_select = 1 ;
}
}
if ( freq > = 45000000 ) {
/* From divided value (XDIV) determined the FA and FP value */
/* From divided value (XDIV) determined the FA and FP value */
xdiv = ( uint16_t ) ( f_vco / xtal_freq_div_2 ) ;
xdiv = ( uint16_t ) ( f_vco / xtal_freq_div_2 ) ;
if ( ( f_vco - xdiv * xtal_freq_div_2 ) > = ( xtal_freq_div_2 / 2 ) )
if ( ( f_vco - xdiv * xtal_freq_div_2 ) > = ( xtal_freq_div_2 / 2 ) )
@ -228,16 +227,11 @@ int fc0012_set_params(void *dev, uint32_t freq, uint32_t bandwidth)
reg [ 2 ] = pm ;
reg [ 2 ] = pm ;
}
}
if ( reg [ 1 ] > 15 ) {
if ( ( reg [ 1 ] > 15 ) | | ( reg [ 2 ] < 0x0b ) ) {
fprintf ( stderr , " [FC0012] no valid PLL combination "
fprintf ( stderr , " [FC0012] no valid PLL combination "
" found for %u Hz! \n " , freq ) ;
" found for %u Hz! \n " , freq ) ;
return - 1 ;
return - 1 ;
}
}
} else {
/* fix for frequency less than 45 MHz */
reg [ 1 ] = 0x06 ;
reg [ 2 ] = 0x11 ;
}
/* fix clock out */
/* fix clock out */
reg [ 6 ] | = 0x20 ;
reg [ 6 ] | = 0x20 ;