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@ -139,9 +139,6 @@ static uint8_t spi(uint8_t tx) { |
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RD_CONFIG_EN_CRC | \
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RD_CONFIG_CRCO) |
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#define CEHIGH CE(1) |
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#define CELOW CE(0) |
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static inline uint8_t CS(uint8_t hl) |
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{ |
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if (hl == 1) { |
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@ -169,7 +166,19 @@ static uint8_t NRF_WriteRegister(uint8_t reg, uint8_t value) |
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status = spi(CMD_WRITE_REG | reg); |
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spi(value); |
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} |
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dbg("Wr[0x%02x] := 0x%02x", (int)reg, (int) value); |
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dbg_nrf("Wr[0x%02x] := 0x%02x", (int)reg, (int) value); |
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uint8_t reg_val = 0; |
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CHIPSELECT { |
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spi(CMD_READ_REG | reg); |
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reg_val = spi(0); |
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} |
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dbg_nrf(" verify 0x%02x", (int)reg_val); |
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if (reg_val != value) |
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dbg_nrf(" !!!"); |
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else |
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dbg_nrf(" OK"); |
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return status; |
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} |
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@ -180,7 +189,7 @@ static uint8_t NRF_ReadRegister(uint8_t reg) |
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spi(CMD_READ_REG | reg); |
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reg_val = spi(0); |
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} |
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dbg("Rd[0x%02x] = 0x%02x", (int)reg, (int) reg_val); |
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dbg_nrf("Rd[0x%02x] = 0x%02x", (int)reg, (int) reg_val); |
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return reg_val; |
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} |
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@ -226,7 +235,7 @@ void NRF_SetBaseAddress(const uint8_t *Bytes4) |
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void NRF_SetRxAddress(uint8_t pipenum, uint8_t AddrByte) |
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{ |
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if (pipenum > 5) { |
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dbg("!! bad pipe %d", pipenum); |
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dbg_nrf("!! bad pipe %d", pipenum); |
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return; |
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} |
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@ -234,13 +243,13 @@ void NRF_SetRxAddress(uint8_t pipenum, uint8_t AddrByte) |
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nrf_pipe_addr[pipenum] = AddrByte; |
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dbg("Set Rx addr (pipe %d) = 0x%02x", (int)pipenum, AddrByte); |
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dbg_nrf("Set Rx addr (pipe %d) = 0x%02x", (int)pipenum, AddrByte); |
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if (pipenum == 0) { |
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dbg("W ADDR_PA0: %02X-%02X-%02X-%02X-%02X", nrf_base_address[0], nrf_base_address[1], nrf_base_address[2], nrf_base_address[3], nrf_base_address[4]); |
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dbg_nrf("W ADDR_PA0: %02X-%02X-%02X-%02X-%02X", nrf_base_address[0], nrf_base_address[1], nrf_base_address[2], nrf_base_address[3], nrf_base_address[4]); |
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NRF_WriteBuffer(RG_RX_ADDR_P0, nrf_base_address, 5); |
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} |
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else if (pipenum == 1) { |
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dbg("W ADDR_PA1: %02X-%02X-%02X-%02X-%02X", nrf_base_address[0], nrf_base_address[1], nrf_base_address[2], nrf_base_address[3], nrf_base_address[4]); |
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dbg_nrf("W ADDR_PA1: %02X-%02X-%02X-%02X-%02X", nrf_base_address[0], nrf_base_address[1], nrf_base_address[2], nrf_base_address[3], nrf_base_address[4]); |
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NRF_WriteBuffer(RG_RX_ADDR_P1, nrf_base_address, 5); |
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} |
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else { |
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@ -278,6 +287,7 @@ uint8_t NRF_Addr2PipeNum(uint8_t addr) |
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void NRF_EnablePipe(uint8_t pipenum) |
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{ |
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dbg_nrf("Enable pipe num %d", (int)pipenum); |
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uint8_t enabled = NRF_ReadRegister(RG_EN_RXADDR); |
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enabled |= 1 << pipenum; |
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NRF_WriteRegister(RG_EN_RXADDR, enabled); |
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@ -298,34 +308,39 @@ static void NRF_SetTxAddress(uint8_t SendTo) |
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{ |
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nrf_base_address[4] = SendTo; |
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dbg("W Tx_ADDR + Rx0: %02X-%02X-%02X-%02X-%02X", nrf_base_address[0], nrf_base_address[1], nrf_base_address[2], nrf_base_address[3], nrf_base_address[4]); |
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dbg_nrf("W Tx_ADDR + Rx0: %02X-%02X-%02X-%02X-%02X", |
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nrf_base_address[0], nrf_base_address[1], nrf_base_address[2], nrf_base_address[3], nrf_base_address[4]); |
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NRF_WriteBuffer(RG_TX_ADDR, nrf_base_address, 5); |
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NRF_WriteBuffer(RG_RX_ADDR_P0, nrf_base_address, 5); // the ACK will come to pipe 0
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} |
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void NRF_PowerDown(void) |
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{ |
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dbg("PDn"); |
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CELOW; |
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dbg_nrf("PDn"); |
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CE(0); |
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NRF_WriteRegister(RG_CONFIG, ModeBits); |
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} |
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void NRF_ModeTX(void) |
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{ |
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dbg("Tx Mode"); |
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dbg_nrf("Tx Mode"); |
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CELOW; |
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CE(0); |
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uint8_t m = NRF_ReadRegister(RG_CONFIG); |
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NRF_WriteRegister(RG_CONFIG, ModeBits | RD_CONFIG_PWR_UP); |
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if ((m & RD_CONFIG_PWR_UP) == 0) LL_mDelay(5); |
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if ((m & RD_CONFIG_PWR_UP) == 0) { |
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// switching on
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LL_mDelay(5); |
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} |
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} |
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void NRF_ModeRX(void) |
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{ |
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dbg("Rx Mode"); |
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dbg_nrf("Rx Mode"); |
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NRF_WriteRegister(RG_CONFIG, ModeBits | RD_CONFIG_PWR_UP | RD_CONFIG_PRIM_RX); |
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NRF_SetRxAddress(0, nrf_pipe_addr[0]); // set the P0 address - it was changed during Rx for ACK reception
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CEHIGH; |
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CE(1); |
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//if ((m&2)==0) LL_mDelay()(5); You don't need to wait. Just nothing will come for 5ms or more
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} |
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@ -363,7 +378,9 @@ uint8_t NRF_ReceivePacket(uint8_t *Packet, uint8_t *PipeNum) |
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uint8_t pw = 0, status; |
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if (!NRF_IsRxPacket()) return 0; |
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CELOW; |
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const uint8_t orig_conf = NRF_ReadRegister(RG_CONFIG); |
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CE(0); // quit Rx mode - go idle
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CHIPSELECT { |
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status = spi(CMD_RD_RX_PL_WIDTH); |
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pw = spi(0); |
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@ -373,19 +390,25 @@ uint8_t NRF_ReceivePacket(uint8_t *Packet, uint8_t *PipeNum) |
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CHIPSELECT { |
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spi(CMD_FLUSH_RX); |
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} |
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NRF_WriteRegister(RG_STATUS, RD_STATUS_RX_DR); |
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return 0; |
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pw = 0; |
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} else { |
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// Read the reception pipe number
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*PipeNum = ((status & RD_STATUS_RX_PNO) >> 1); |
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CHIPSELECT { |
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spi(CMD_RD_RX_PLD); |
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for (uint8_t i = 0; i < pw; i++) Packet[i] = spi(0); |
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} |
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} |
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NRF_WriteRegister(RG_STATUS, RD_STATUS_RX_DR); // Clear the RX_DR interrupt
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// Read the reception pipe number
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*PipeNum = (status & RD_STATUS_RX_PNO) >> 1; |
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CHIPSELECT { |
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spi(CMD_RD_RX_PLD); |
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for (uint8_t i = 0; i < pw; i++) Packet[i] = spi(0); |
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if ((orig_conf & RD_CONFIG_PWR_UP) == 0) { |
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dbg_nrf("going back PwrDn"); |
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NRF_PowerDown(); |
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} |
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else if ((orig_conf & RD_CONFIG_PRIM_RX) == RD_CONFIG_PRIM_RX) { |
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dbg_nrf("going back PwrUp+Rx"); |
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NRF_ModeRX(); |
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} |
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NRF_WriteRegister(RG_STATUS, RD_STATUS_RX_DR); // Clear the RX_DR interrupt
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CEHIGH; |
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return pw; |
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} |
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@ -398,14 +421,14 @@ bool NRF_IsRxPacket(void) |
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bool NRF_SendPacket(uint8_t PipeNum, const uint8_t *Packet, uint8_t Length) |
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{ |
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if (!nrf_pipe_enabled[PipeNum]) { |
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dbg("!! Pipe %d not enabled", PipeNum); |
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dbg_nrf("!! Pipe %d not enabled", PipeNum); |
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return 0; |
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} |
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const uint8_t orig_conf = NRF_ReadRegister(RG_CONFIG); |
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CELOW; |
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CE(0); |
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NRF_ModeTX(); // Make sure in TX mode
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NRF_SetTxAddress(nrf_pipe_addr[PipeNum]); |
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NRF_SetTxAddress(nrf_pipe_addr[PipeNum]); // this sets the Tx addr and also pipe 0 addr for ACK
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CHIPSELECT { |
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spi(CMD_FLUSH_TX); |
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@ -416,25 +439,27 @@ bool NRF_SendPacket(uint8_t PipeNum, const uint8_t *Packet, uint8_t Length) |
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for (uint8_t i = 0; i < Length; i++) spi(Packet[i]); |
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}; |
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CEHIGH; |
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_delay_us(15); // At least 10 us
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CELOW; |
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// CE pulse
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CE(1); |
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_delay_us(20); // At least 10 us
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CE(0); |
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uint8_t st = 0; |
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while ((st & (RD_STATUS_MAX_RT|RD_STATUS_TX_DS)) == 0) { |
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st = NRF_ReadStatus(); // Packet acked or timed out
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} |
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dbg("Send status: MAX_RT %d, SENT %d", (st&RD_STATUS_MAX_RT) != 0, (st&RD_STATUS_TX_DS) != 0); |
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dbg_nrf("Send status: 0x%02x - MAX_RT %d, SENT %d", (int)st, |
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(st&RD_STATUS_MAX_RT) != 0, (st&RD_STATUS_TX_DS) != 0); |
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NRF_WriteRegister(RG_STATUS, st & (RD_STATUS_MAX_RT|RD_STATUS_TX_DS)); // Clear the bit
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if ((orig_conf & RD_CONFIG_PWR_UP) == 0) { |
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dbg("going back PwrDn"); |
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dbg_nrf("going back PwrDn"); |
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NRF_PowerDown(); |
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} |
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else if ((orig_conf & RD_CONFIG_PRIM_RX) == RD_CONFIG_PRIM_RX) { |
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dbg("going back PwrUp+Rx"); |
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dbg_nrf("going back PwrUp+Rx"); |
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NRF_ModeRX(); |
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} |
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@ -455,27 +480,35 @@ void NRF_Init(uint8_t pSpeed) |
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{ |
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// Set the required output pins
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NSS(1); |
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CELOW; |
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CE(0); |
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LL_mDelay(200); |
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for (int i = 0; i < 6; i++) { |
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nrf_pipe_addr[i] = 0; |
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nrf_pipe_enabled[i] = 0; |
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} |
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// clear flags etc
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NRF_PowerDown(); |
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CHIPSELECT { spi(CMD_FLUSH_RX); } |
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CHIPSELECT { spi(CMD_FLUSH_TX); } |
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NRF_WriteRegister(RG_STATUS, 0x70); |
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NRF_WriteRegister(RG_CONFIG, ModeBits); |
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NRF_WriteRegister(RG_SETUP_AW, 0b11); // 5 byte addresses
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// default
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// NRF_EnablePipe(0);
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NRF_WriteRegister(RG_EN_RXADDR, 0x00); // disable all
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NRF_WriteRegister(RG_SETUP_RETR, 0x18); // 8 retries
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NRF_WriteRegister(RG_RF_CH, 2); // channel 2 NO HIGHER THAN 83 in USA!
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NRF_WriteRegister(RG_SETUP_RETR, 0x18); // 8 retries, 500 ms
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NRF_WriteRegister(RG_RF_CH, 7); // channel 2 NO HIGHER THAN 83 in USA!
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NRF_WriteRegister(RG_RF_SETUP, pSpeed); |
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NRF_WriteRegister(RG_DYNPD, 0b111111); // Dynamic packet length
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NRF_WriteRegister(RG_FEATURE, 0b100); // Enable dynamic payload, and no payload in the ack.
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for (int i = 0; i < 6; i++) { |
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NRF_WriteRegister(RG_RX_PW_P0+i, 32); // Receive 32 byte packets - XXX this is probably not needed with dynamic length
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} |
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//NRFModePowerDown(); // Already in power down mode, dummy
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// for (int i = 0; i < 6; i++) {
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// NRF_WriteRegister(RG_RX_PW_P0+i, 32); // Receive 32 byte packets - XXX this is probably not needed with dynamic length
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// }
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} |
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