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517 lines
20 KiB
517 lines
20 KiB
7 years ago
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/**
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******************************************************************************
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* @file stm32f1xx_hal_cec.h
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* @author MCD Application Team
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* @brief Header file of CEC HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F1xx_HAL_CEC_H
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#define __STM32F1xx_HAL_CEC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(STM32F100xB) || defined(STM32F100xE)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal_def.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @addtogroup CEC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup CEC_Exported_Types CEC Exported Types
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* @{
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*/
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/**
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* @brief CEC Init Structure definition
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*/
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typedef struct
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{
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uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode.
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This parameter can be a value of @ref CEC_BitTimingErrorMode */
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uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode.
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This parameter can be a value of @ref CEC_BitPeriodErrorMode */
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uint16_t OwnAddress; /*!< Own addresses configuration
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This parameter can be a value of @ref CEC_OWN_ADDRESS */
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uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
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}CEC_InitTypeDef;
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/**
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* @brief HAL CEC State structures definition
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* @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
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* - gState contains CEC state information related to global Handle management
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* and also information related to Tx operations.
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* gState value coding follow below described bitmap :
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* b7 (not used)
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* x : Should be set to 0
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* b6 Error information
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* 0 : No Error
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* 1 : Error
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* b5 IP initilisation status
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* 0 : Reset (IP not initialized)
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* 1 : Init done (IP initialized. HAL CEC Init function already called)
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* b4-b3 (not used)
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* xx : Should be set to 00
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* b2 Intrinsic process state
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* 0 : Ready
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* 1 : Busy (IP busy with some configuration or internal operations)
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* b1 (not used)
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* x : Should be set to 0
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* b0 Tx state
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* 0 : Ready (no Tx operation ongoing)
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* 1 : Busy (Tx operation ongoing)
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* - RxState contains information related to Rx operations.
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* RxState value coding follow below described bitmap :
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* b7-b6 (not used)
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* xx : Should be set to 00
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* b5 IP initilisation status
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* 0 : Reset (IP not initialized)
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* 1 : Init done (IP initialized)
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* b4-b2 (not used)
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* xxx : Should be set to 000
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* b1 Rx state
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* 0 : Ready (no Rx operation ongoing)
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* 1 : Busy (Rx operation ongoing)
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* b0 (not used)
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* x : Should be set to 0.
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*/
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typedef enum
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{
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HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
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Value is allowed for gState and RxState */
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HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
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Value is allowed for gState and RxState */
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HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
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Value is allowed for gState only */
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HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
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Value is allowed for RxState only */
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HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
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Value is allowed for gState only */
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HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
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Value is allowed for gState only */
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HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
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}HAL_CEC_StateTypeDef;
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/**
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* @brief CEC handle Structure definition
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*/
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typedef struct
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{
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CEC_TypeDef *Instance; /*!< CEC registers base address */
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CEC_InitTypeDef Init; /*!< CEC communication parameters */
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uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
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uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
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uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
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HAL_LockTypeDef Lock; /*!< Locking object */
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HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
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and also related to Tx operations.
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This parameter can be a value of @ref HAL_CEC_StateTypeDef */
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HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
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This parameter can be a value of @ref HAL_CEC_StateTypeDef */
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uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
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in case error is reported */
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}CEC_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CEC_Exported_Constants CEC Exported Constants
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* @{
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*/
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/** @defgroup CEC_Error_Code CEC Error Code
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* @{
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*/
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#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
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#define HAL_CEC_ERROR_BTE CEC_ESR_BTE /*!< Bit Timing Error */
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#define HAL_CEC_ERROR_BPE CEC_ESR_BPE /*!< Bit Period Error */
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#define HAL_CEC_ERROR_RBTFE CEC_ESR_RBTFE /*!< Rx Block Transfer Finished Error */
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#define HAL_CEC_ERROR_SBE CEC_ESR_SBE /*!< Start Bit Error */
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#define HAL_CEC_ERROR_ACKE CEC_ESR_ACKE /*!< Block Acknowledge Error */
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#define HAL_CEC_ERROR_LINE CEC_ESR_LINE /*!< Line Error */
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#define HAL_CEC_ERROR_TBTFE CEC_ESR_TBTFE /*!< Tx Block Transfer Finished Error */
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/**
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* @}
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*/
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/** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
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* @{
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*/
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#define CEC_BIT_TIMING_ERROR_MODE_STANDARD 0x00000000U /*!< Bit timing error Standard Mode */
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#define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
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/**
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* @}
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*/
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/** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
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* @{
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*/
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#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U /*!< Bit period error Standard Mode */
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#define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
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/**
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* @}
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*/
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/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
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* @{
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*/
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#define CEC_INITIATOR_LSB_POS 4U
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/**
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* @}
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*/
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/** @defgroup CEC_OWN_ADDRESS CEC Own Address
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* @{
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*/
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#define CEC_OWN_ADDRESS_NONE CEC_OWN_ADDRESS_0 /* Reset value */
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#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0000U) /* Logical Address 0 */
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#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0001U) /* Logical Address 1 */
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#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0002U) /* Logical Address 2 */
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#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0003U) /* Logical Address 3 */
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#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0004U) /* Logical Address 4 */
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#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0005U) /* Logical Address 5 */
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#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0006U) /* Logical Address 6 */
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#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0007U) /* Logical Address 7 */
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#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0008U) /* Logical Address 8 */
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#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0009U) /* Logical Address 9 */
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#define CEC_OWN_ADDRESS_10 ((uint16_t)0x000AU) /* Logical Address 10 */
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#define CEC_OWN_ADDRESS_11 ((uint16_t)0x000BU) /* Logical Address 11 */
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#define CEC_OWN_ADDRESS_12 ((uint16_t)0x000CU) /* Logical Address 12 */
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#define CEC_OWN_ADDRESS_13 ((uint16_t)0x000DU) /* Logical Address 13 */
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#define CEC_OWN_ADDRESS_14 ((uint16_t)0x000EU) /* Logical Address 14 */
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#define CEC_OWN_ADDRESS_15 ((uint16_t)0x000FU) /* Logical Address 15 */
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/**
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* @}
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*/
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/** @defgroup CEC_Interrupts_Definitions Interrupts definition
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* @{
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*/
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#define CEC_IT_IE CEC_CFGR_IE
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/**
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* @}
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*/
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/** @defgroup CEC_Flags_Definitions Flags definition
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* @{
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*/
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#define CEC_FLAG_TSOM CEC_CSR_TSOM
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#define CEC_FLAG_TEOM CEC_CSR_TEOM
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#define CEC_FLAG_TERR CEC_CSR_TERR
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#define CEC_FLAG_TBTRF CEC_CSR_TBTRF
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#define CEC_FLAG_RSOM CEC_CSR_RSOM
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#define CEC_FLAG_REOM CEC_CSR_REOM
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#define CEC_FLAG_RERR CEC_CSR_RERR
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#define CEC_FLAG_RBTF CEC_CSR_RBTF
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macros -----------------------------------------------------------*/
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/** @defgroup CEC_Exported_Macros CEC Exported Macros
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* @{
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*/
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/** @brief Reset CEC handle gstate & RxState
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* @param __HANDLE__: CEC handle.
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* @retval None
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*/
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#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
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(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
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(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
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} while(0U)
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/** @brief Checks whether or not the specified CEC interrupt flag is set.
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* @param __HANDLE__: specifies the CEC Handle.
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* @param __FLAG__: specifies the flag to check.
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* @arg CEC_FLAG_TERR: Tx Error
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* @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished
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* @arg CEC_FLAG_RERR: Rx Error
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* @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
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* @retval ITStatus
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*/
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#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__))
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/** @brief Clears the CEC's pending flags.
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* @param __HANDLE__: specifies the CEC Handle.
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* @param __FLAG__: specifies the flag to clear.
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* This parameter can be any combination of the following values:
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* @arg CEC_CSR_TERR: Tx Error
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* @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished
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* @arg CEC_CSR_RERR: Rx Error
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* @arg CEC_CSR_RBTF: Rx Block Transfer Finished
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* @retval none
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*/
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#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
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do { \
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uint32_t tmp = 0x0U; \
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tmp = (__HANDLE__)->Instance->CSR & 0x00000002U; \
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(__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\
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} while(0U)
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/** @brief Enables the specified CEC interrupt.
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* @param __HANDLE__: specifies the CEC Handle.
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* @param __INTERRUPT__: specifies the CEC interrupt to enable.
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* This parameter can be:
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* @arg CEC_IT_IE : Interrupt Enable.
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* @retval none
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*/
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#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
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/** @brief Disables the specified CEC interrupt.
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* @param __HANDLE__: specifies the CEC Handle.
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* @param __INTERRUPT__: specifies the CEC interrupt to disable.
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* This parameter can be:
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* @arg CEC_IT_IE : Interrupt Enable
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* @retval none
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*/
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#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
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/** @brief Checks whether or not the specified CEC interrupt is enabled.
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* @param __HANDLE__: specifies the CEC Handle.
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* @param __INTERRUPT__: specifies the CEC interrupt to check.
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* This parameter can be:
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* @arg CEC_IT_IE : Interrupt Enable
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* @retval FlagStatus
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*/
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#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
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/** @brief Enables the CEC device
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* @param __HANDLE__: specifies the CEC Handle.
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* @retval none
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*/
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#define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
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/** @brief Disables the CEC device
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* @param __HANDLE__: specifies the CEC Handle.
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* @retval none
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*/
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#define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
|
||
|
|
|
||
|
|
/** @brief Set Transmission Start flag
|
||
|
|
* @param __HANDLE__: specifies the CEC Handle.
|
||
|
|
* @retval none
|
||
|
|
*/
|
||
|
|
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
|
||
|
|
|
||
|
|
/** @brief Set Transmission End flag
|
||
|
|
* @param __HANDLE__: specifies the CEC Handle.
|
||
|
|
* @retval none
|
||
|
|
*/
|
||
|
|
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
|
||
|
|
|
||
|
|
/** @brief Get Transmission Start flag
|
||
|
|
* @param __HANDLE__: specifies the CEC Handle.
|
||
|
|
* @retval FlagStatus
|
||
|
|
*/
|
||
|
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#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
|
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|
|
|
||
|
|
/** @brief Get Transmission End flag
|
||
|
|
* @param __HANDLE__: specifies the CEC Handle.
|
||
|
|
* @retval FlagStatus
|
||
|
|
*/
|
||
|
|
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
|
||
|
|
|
||
|
|
/** @brief Clear OAR register
|
||
|
|
* @param __HANDLE__: specifies the CEC Handle.
|
||
|
|
* @retval none
|
||
|
|
*/
|
||
|
|
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
|
||
|
|
|
||
|
|
/** @brief Set OAR register
|
||
|
|
* @param __HANDLE__: specifies the CEC Handle.
|
||
|
|
* @param __ADDRESS__: Own Address value.
|
||
|
|
* @retval none
|
||
|
|
*/
|
||
|
|
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Exported functions --------------------------------------------------------*/
|
||
|
|
/** @addtogroup CEC_Exported_Functions CEC Exported Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||
|
|
* @brief Initialization and Configuration functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Initialization and de-initialization functions ****************************/
|
||
|
|
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
|
||
|
|
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
|
||
|
|
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
|
||
|
|
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
|
||
|
|
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
|
||
|
|
* @brief CEC Transmit/Receive functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* I/O operation functions ***************************************************/
|
||
|
|
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
|
||
|
|
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
|
||
|
|
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
|
||
|
|
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||
|
|
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||
|
|
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
|
||
|
|
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
|
||
|
|
* @brief CEC control functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Peripheral State and Error functions ***************************************/
|
||
|
|
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
|
||
|
|
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private types -------------------------------------------------------------*/
|
||
|
|
/** @defgroup CEC_Private_Types CEC Private Types
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private variables ---------------------------------------------------------*/
|
||
|
|
/** @defgroup CEC_Private_Variables CEC Private Variables
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private constants ---------------------------------------------------------*/
|
||
|
|
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private macros ------------------------------------------------------------*/
|
||
|
|
/** @defgroup CEC_Private_Macros CEC Private Macros
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
|
||
|
|
((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
|
||
|
|
|
||
|
|
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
|
||
|
|
((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
|
||
|
|
|
||
|
|
/** @brief Check CEC message size.
|
||
|
|
* The message size is the payload size: without counting the header,
|
||
|
|
* it varies from 0 byte (ping operation, one header only, no payload) to
|
||
|
|
* 15 bytes (1 opcode and up to 14 operands following the header).
|
||
|
|
* @param __SIZE__: CEC message size.
|
||
|
|
* @retval Test result (TRUE or FALSE).
|
||
|
|
*/
|
||
|
|
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
|
||
|
|
/** @brief Check CEC device Own Address Register (OAR) setting.
|
||
|
|
* @param __ADDRESS__: CEC own address.
|
||
|
|
* @retval Test result (TRUE or FALSE).
|
||
|
|
*/
|
||
|
|
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
|
||
|
|
|
||
|
|
/** @brief Check CEC initiator or destination logical address setting.
|
||
|
|
* Initiator and destination addresses are coded over 4 bits.
|
||
|
|
* @param __ADDRESS__: CEC initiator or logical address.
|
||
|
|
* @retval Test result (TRUE or FALSE).
|
||
|
|
*/
|
||
|
|
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/* Private functions ---------------------------------------------------------*/
|
||
|
|
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#endif /* defined(STM32F100xB) || defined(STM32F100xE) */
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __STM32F1xx_HAL_CEC_H */
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|