gex/gex-f072
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fixes for oscillator fallback

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MightyPork
2018-03-15 23:23:11 +01:00
parent 0657a11e48
commit 9954995fa3
2 changed files with 8 additions and 3 deletions
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Src/main.c
+7 -2
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@@ -50,6 +50,7 @@
#include "main.h" #include "main.h"
#include "stm32f0xx_hal.h" #include "stm32f0xx_hal.h"
#include "cmsis_os.h" #include "cmsis_os.h"
#include <stdbool.h>
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
#include "gex_hooks.h" #include "gex_hooks.h"
@@ -164,7 +165,9 @@ void SystemClock_Config(void)
counter++; counter++;
} }
bool has_pll = 0;
if (LL_RCC_HSE_IsReady() == 0) { if (LL_RCC_HSE_IsReady() == 0) {
// Looks like HSE xtal doesn't work - use HSI48 // Looks like HSE xtal doesn't work - use HSI48
LL_RCC_HSI48_Enable(); LL_RCC_HSI48_Enable();
while(LL_RCC_HSI48_IsReady() != 1) {} while(LL_RCC_HSI48_IsReady() != 1) {}
@@ -173,7 +176,7 @@ void SystemClock_Config(void)
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI48); LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI48);
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {} while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI48) {}
} else { } else {
// external 8 MHz xtal // external 8 MHz xtal
@@ -188,6 +191,8 @@ void SystemClock_Config(void)
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {} while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}
has_pll = true;
} }
/* Set APB1 prescaler */ /* Set APB1 prescaler */
@@ -202,7 +207,7 @@ void SystemClock_Config(void)
/**Initializes the CPU, AHB and APB busses clocks /**Initializes the CPU, AHB and APB busses clocks
*/ */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.SYSCLKSource = has_pll ? RCC_SYSCLKSOURCE_PLLCLK : RCC_SYSCLKSOURCE_HSI48;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
User
+1 -1
Submodule User updated: ffec192a27...f9200fcc7d