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221 lines
6.9 KiB
221 lines
6.9 KiB
7 years ago
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
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*
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* $Date: 19. March 2015
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* $Revision: V.1.4.5
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*
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* Project: CMSIS DSP Library
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* Title: arm_shift_q7.c
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*
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* Description: Processing function for the Q7 Shifting
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*
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* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of ARM LIMITED nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* -------------------------------------------------------------------- */
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#include "arm_math.h"
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/**
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* @ingroup groupMath
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*/
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/**
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* @addtogroup shift
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* @{
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*/
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/**
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* @brief Shifts the elements of a Q7 vector a specified number of bits.
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* @param[in] *pSrc points to the input vector
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* @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
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* @param[out] *pDst points to the output vector
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* @param[in] blockSize number of samples in the vector
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* @return none.
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*
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* \par Conditions for optimum performance
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* Input and output buffers should be aligned by 32-bit
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*
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*
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* <b>Scaling and Overflow Behavior:</b>
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* \par
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* The function uses saturating arithmetic.
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* Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.
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*/
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void arm_shift_q7(
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q7_t * pSrc,
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int8_t shiftBits,
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q7_t * pDst,
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uint32_t blockSize)
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{
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uint32_t blkCnt; /* loop counter */
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uint8_t sign; /* Sign of shiftBits */
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#ifndef ARM_MATH_CM0_FAMILY
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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q7_t in1; /* Input value1 */
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q7_t in2; /* Input value2 */
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q7_t in3; /* Input value3 */
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q7_t in4; /* Input value4 */
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/*loop Unrolling */
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blkCnt = blockSize >> 2u;
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/* Getting the sign of shiftBits */
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sign = (shiftBits & 0x80);
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/* If the shift value is positive then do right shift else left shift */
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if(sign == 0u)
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{
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/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
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** a second loop below computes the remaining 1 to 3 samples. */
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while(blkCnt > 0u)
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{
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/* C = A << shiftBits */
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/* Read 4 inputs */
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in1 = *pSrc;
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in2 = *(pSrc + 1);
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in3 = *(pSrc + 2);
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in4 = *(pSrc + 3);
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/* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
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*__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
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__SSAT((in2 << shiftBits), 8),
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__SSAT((in3 << shiftBits), 8),
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__SSAT((in4 << shiftBits), 8));
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/* Update source pointer to process next sampels */
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pSrc += 4u;
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/* Decrement the loop counter */
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blkCnt--;
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}
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/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
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** No loop unrolling is used. */
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blkCnt = blockSize % 0x4u;
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while(blkCnt > 0u)
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{
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/* C = A << shiftBits */
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/* Shift the input and then store the result in the destination buffer. */
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*pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
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/* Decrement the loop counter */
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blkCnt--;
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}
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}
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else
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{
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shiftBits = -shiftBits;
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/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
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** a second loop below computes the remaining 1 to 3 samples. */
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while(blkCnt > 0u)
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{
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/* C = A >> shiftBits */
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/* Read 4 inputs */
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in1 = *pSrc;
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in2 = *(pSrc + 1);
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in3 = *(pSrc + 2);
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in4 = *(pSrc + 3);
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/* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
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*__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),
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(in3 >> shiftBits), (in4 >> shiftBits));
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pSrc += 4u;
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/* Decrement the loop counter */
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blkCnt--;
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}
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/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
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** No loop unrolling is used. */
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blkCnt = blockSize % 0x4u;
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while(blkCnt > 0u)
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{
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/* C = A >> shiftBits */
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/* Shift the input and then store the result in the destination buffer. */
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in1 = *pSrc++;
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*pDst++ = (in1 >> shiftBits);
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/* Decrement the loop counter */
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blkCnt--;
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}
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}
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#else
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/* Run the below code for Cortex-M0 */
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/* Getting the sign of shiftBits */
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sign = (shiftBits & 0x80);
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/* If the shift value is positive then do right shift else left shift */
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if(sign == 0u)
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{
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/* Initialize blkCnt with number of samples */
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blkCnt = blockSize;
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while(blkCnt > 0u)
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{
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/* C = A << shiftBits */
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/* Shift the input and then store the result in the destination buffer. */
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*pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
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/* Decrement the loop counter */
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blkCnt--;
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}
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}
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else
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{
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/* Initialize blkCnt with number of samples */
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blkCnt = blockSize;
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while(blkCnt > 0u)
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{
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/* C = A >> shiftBits */
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/* Shift the input and then store the result in the destination buffer. */
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*pDst++ = (*pSrc++ >> -shiftBits);
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/* Decrement the loop counter */
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blkCnt--;
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}
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}
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#endif /* #ifndef ARM_MATH_CM0_FAMILY */
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}
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/**
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* @} end of shift group
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*/
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