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344 lines
11 KiB
344 lines
11 KiB
//
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// Created by MightyPork on 2018/01/14.
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//
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#include "platform.h"
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#include "unit_base.h"
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#define UUSART_INTERNAL
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#include "_usart_internal.h"
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extern error_t UUSART_ClaimDMAs(Unit *unit);
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extern error_t UUSART_SetupDMAs(Unit *unit);
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extern void UUSART_DeInitDMAs(Unit *unit);
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/** Allocate data structure and set defaults */
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error_t UUSART_preInit(Unit *unit)
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{
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struct priv *priv = unit->data = calloc_ck(1, sizeof(struct priv));
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if (priv == NULL) return E_OUT_OF_MEM;
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// some defaults
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priv->periph_num = 1;
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priv->remap = 0;
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priv->baudrate = 115200;
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priv->parity = 0; //!< 0-none, 1-odd, 2-even
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priv->stopbits = 1; //!< 0-half, 1-one, 2-1.5, 3-two
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priv->direction = UUSART_DIRECTION_RXTX; // RXTX
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priv->hw_flow_control = false;
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priv->clock_output = false;
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priv->cpol = 0;
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priv->cpha = 0;
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priv->lsb_first = true; // LSB first is default for UART
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priv->width = 8;
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priv->data_inv = false;
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priv->rx_inv = false;
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priv->tx_inv = false;
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priv->de_output = false;
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priv->de_polarity = 1; // active high
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// this should equal to a half-byte length when oversampling by 16 is used (default)
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priv->de_assert_time = 8;
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priv->de_clear_time = 8;
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return E_SUCCESS;
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}
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/** Claim the peripheral and assign priv->periph */
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static inline error_t UUSART_claimPeriph(Unit *unit)
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{
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struct priv *priv = unit->data;
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if (!(priv->periph_num >= 1 && priv->periph_num <= 5)) {
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dbg("!! Bad USART periph");
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return E_BAD_CONFIG;
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}
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// assign and claim the peripheral
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if (priv->periph_num == 1) {
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TRY(rsc_claim(unit, R_USART1));
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priv->periph = USART1;
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}
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else if (priv->periph_num == 2) {
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TRY(rsc_claim(unit, R_USART2));
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priv->periph = USART2;
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}
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else if (priv->periph_num == 3) {
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TRY(rsc_claim(unit, R_USART3));
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priv->periph = USART3;
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}
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#if defined(USART4)
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else if (priv->periph_num == 4) {
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TRY(rsc_claim(unit, R_USART4));
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priv->periph = USART4;
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}
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#endif
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#if defined(USART5)
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else if (priv->periph_num == 5) {
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TRY(rsc_claim(unit, R_USART5));
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priv->periph = USART5;
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}
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#endif
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else return E_BAD_CONFIG;
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TRY(UUSART_ClaimDMAs(unit));
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return E_SUCCESS;
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}
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/** Claim and configure GPIOs used */
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static inline error_t UUSART_configPins(Unit *unit)
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{
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struct priv *priv = unit->data;
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// This is written for F072, other platforms will need adjustments
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// Configure UART pins (AF)
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#define want_ck_pin(priv) ((priv)->clock_output)
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#define want_tx_pin(priv) (bool)((priv)->direction & 2)
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#define want_rx_pin(priv) (bool)((priv)->direction & 1)
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#define want_cts_pin(priv) ((priv)->hw_flow_control==2 || (priv)->hw_flow_control==3)
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#define want_rts_pin(priv) ((priv)->de_output || (priv)->hw_flow_control==1 || (priv)->hw_flow_control==3)
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/* List of required pins based on the user config */
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bool pins_wanted[5] = {
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want_ck_pin(priv),
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want_tx_pin(priv),
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want_rx_pin(priv),
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want_cts_pin(priv),
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want_rts_pin(priv)
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};
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#if GEX_PLAT_F072_DISCOVERY
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const struct PinAF *mappings = NULL;
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// TODO adjust this, possibly remove / split to individual pin config for ..
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// the final board
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const struct PinAF mapping_1_0[5] = {
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{'A', 8, LL_GPIO_AF_1}, // CK
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{'A', 9, LL_GPIO_AF_1}, // TX
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{'A', 10, LL_GPIO_AF_1}, // RX
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{'A', 11, LL_GPIO_AF_1}, // CTS - collides with USB
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{'A', 12, LL_GPIO_AF_1}, // RTS - collides with USB
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};
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const struct PinAF mapping_1_1[5] = {
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{'A', 8, LL_GPIO_AF_1}, // CK*
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{'B', 6, LL_GPIO_AF_1}, // TX
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{'B', 7, LL_GPIO_AF_1}, // RX
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{'A', 11, LL_GPIO_AF_1}, // CTS* - collides with USB
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{'A', 12, LL_GPIO_AF_1}, // RTS* - collides with USB
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};
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const struct PinAF mapping_2_0[5] = {
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{'A', 4, LL_GPIO_AF_1}, // CK
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{'A', 2, LL_GPIO_AF_1}, // TX
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{'A', 3, LL_GPIO_AF_1}, // RX
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{'A', 0, LL_GPIO_AF_1}, // CTS
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{'A', 1, LL_GPIO_AF_1}, // RTS
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};
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const struct PinAF mapping_2_1[5] = {
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{'A', 4, LL_GPIO_AF_1}, // CK*
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{'A', 14, LL_GPIO_AF_1}, // TX
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{'A', 15, LL_GPIO_AF_1}, // RX
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{'A', 0, LL_GPIO_AF_1}, // CTS*
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{'A', 1, LL_GPIO_AF_1}, // RTS*
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};
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const struct PinAF mapping_3_0[5] = {
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{'B', 12, LL_GPIO_AF_4}, // CK
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{'B', 10, LL_GPIO_AF_4}, // TX
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{'B', 11, LL_GPIO_AF_4}, // RX
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{'B', 13, LL_GPIO_AF_4}, // CTS
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{'B', 14, LL_GPIO_AF_4}, // RTS
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};
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const struct PinAF mapping_4_0[5] = {
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{'C', 12, LL_GPIO_AF_0}, // CK
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{'A', 0, LL_GPIO_AF_4}, // TX
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{'A', 1, LL_GPIO_AF_4}, // RX
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{'B', 7, LL_GPIO_AF_4}, // CTS
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{'A', 15, LL_GPIO_AF_4}, // RTS
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};
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const struct PinAF mapping_4_1[5] = {
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{'C', 12, LL_GPIO_AF_0}, // CK*
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{'C', 10, LL_GPIO_AF_0}, // TX
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{'C', 11, LL_GPIO_AF_0}, // RX
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{'B', 7, LL_GPIO_AF_4}, // CTS*
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{'A', 15, LL_GPIO_AF_4}, // RTS*
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};
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if (priv->periph_num == 1) {
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// USART1
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if (priv->remap == 0) mappings = &mapping_1_0[0];
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else if (priv->remap == 1) mappings = &mapping_1_1[0];
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else return E_BAD_CONFIG;
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}
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else if (priv->periph_num == 2) {
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// USART2
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if (priv->remap == 0) mappings = &mapping_2_0[0];
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else if (priv->remap == 1) mappings = &mapping_2_1[0];
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else return E_BAD_CONFIG;
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}
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else if (priv->periph_num == 3) {
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// USART3
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if (priv->remap == 0) mappings = &mapping_3_0[0];
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else return E_BAD_CONFIG;
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}
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else if (priv->periph_num == 4) {
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// USART3
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if (priv->remap == 0) mappings = &mapping_4_0[0];
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else if (priv->remap == 1) mappings = &mapping_4_1[0];
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else return E_BAD_CONFIG;
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}
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else return E_BAD_CONFIG;
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// Apply mappings based on the 'wanted' table
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for (int i = 0; i < 5; i++) {
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if (pins_wanted[i]) {
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if (mappings[i].port == 0) return E_BAD_CONFIG;
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TRY(rsc_claim_pin(unit, mappings[i].port, mappings[i].pin));
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TRY(hw_configure_gpio_af(mappings[i].port, mappings[i].pin, mappings[i].af));
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}
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}
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#elif GEX_PLAT_F103_BLUEPILL
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#error "NO IMPL"
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#elif GEX_PLAT_F303_DISCOVERY
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#error "NO IMPL"
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#elif GEX_PLAT_F407_DISCOVERY
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#error "NO IMPL"
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#else
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#error "BAD PLATFORM!"
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#endif
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return E_SUCCESS;
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}
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/** Finalize unit set-up */
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error_t UUSART_init(Unit *unit)
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{
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struct priv *priv = unit->data;
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TRY(UUSART_claimPeriph(unit));
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TRY(UUSART_configPins(unit));
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// --- Configure the peripheral ---
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// Enable clock for the peripheral used
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hw_periph_clock_enable(priv->periph);
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LL_USART_Disable(priv->periph);
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{
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LL_USART_DeInit(priv->periph);
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LL_USART_SetBaudRate(priv->periph, PLAT_APB1_HZ, LL_USART_OVERSAMPLING_16, priv->baudrate);
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LL_USART_SetParity(priv->periph,
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priv->parity == 0 ? LL_USART_PARITY_NONE :
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priv->parity == 1 ? LL_USART_PARITY_ODD
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: LL_USART_PARITY_EVEN);
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LL_USART_SetStopBitsLength(priv->periph,
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priv->stopbits == 0 ? LL_USART_STOPBITS_0_5 :
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priv->stopbits == 1 ? LL_USART_STOPBITS_1 :
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priv->stopbits == 2 ? LL_USART_STOPBITS_1_5
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: LL_USART_STOPBITS_2);
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LL_USART_SetTransferDirection(priv->periph,
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(priv->direction == UUSART_DIRECTION_RX) ? LL_USART_DIRECTION_RX :
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(priv->direction == UUSART_DIRECTION_TX) ? LL_USART_DIRECTION_TX
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: LL_USART_DIRECTION_TX_RX);
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LL_USART_SetHWFlowCtrl(priv->periph,
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priv->hw_flow_control == 0 ? LL_USART_HWCONTROL_NONE :
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priv->hw_flow_control == 1 ? LL_USART_HWCONTROL_RTS :
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priv->hw_flow_control == 2 ? LL_USART_HWCONTROL_CTS
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: LL_USART_HWCONTROL_RTS_CTS);
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LL_USART_ConfigClock(priv->periph,
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priv->cpha ? LL_USART_PHASE_2EDGE : LL_USART_PHASE_1EDGE,
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priv->cpol ? LL_USART_POLARITY_HIGH : LL_USART_POLARITY_LOW,
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true); // clock on last bit - TODO configurable?
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if (priv->clock_output)
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LL_USART_EnableSCLKOutput(priv->periph);
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else
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LL_USART_DisableSCLKOutput(priv->periph);
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LL_USART_SetTransferBitOrder(priv->periph,
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priv->lsb_first ? LL_USART_BITORDER_LSBFIRST
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: LL_USART_BITORDER_MSBFIRST);
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LL_USART_SetDataWidth(priv->periph,
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priv->width == 7 ? LL_USART_DATAWIDTH_7B :
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priv->width == 8 ? LL_USART_DATAWIDTH_8B
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: LL_USART_DATAWIDTH_9B);
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LL_USART_SetBinaryDataLogic(priv->periph,
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priv->data_inv ? LL_USART_BINARY_LOGIC_NEGATIVE
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: LL_USART_BINARY_LOGIC_POSITIVE);
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LL_USART_SetRXPinLevel(priv->periph, priv->rx_inv ? LL_USART_RXPIN_LEVEL_INVERTED
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: LL_USART_RXPIN_LEVEL_STANDARD);
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LL_USART_SetTXPinLevel(priv->periph, priv->tx_inv ? LL_USART_TXPIN_LEVEL_INVERTED
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: LL_USART_TXPIN_LEVEL_STANDARD);
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if (priv->de_output)
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LL_USART_EnableDEMode(priv->periph);
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else
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LL_USART_DisableDEMode(priv->periph);
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LL_USART_SetDESignalPolarity(priv->periph,
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priv->de_polarity ? LL_USART_DE_POLARITY_HIGH
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: LL_USART_DE_POLARITY_LOW);
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LL_USART_SetDEAssertionTime(priv->periph, priv->de_assert_time);
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LL_USART_SetDEDeassertionTime(priv->periph, priv->de_clear_time);
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// Prepare for DMA
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LL_USART_ClearFlag_TC(priv->periph);
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LL_USART_EnableDMAReq_RX(priv->periph);
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LL_USART_EnableDMAReq_TX(priv->periph);
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}
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LL_USART_Enable(priv->periph);
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// modifies some usart registers that can't be modified when enabled
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TRY(UUSART_SetupDMAs(unit));
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// timeout based on the baudrate
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unit->tick_interval = (uint16_t) ((50 * 1000) / priv->baudrate); // receive timeout (ms)
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if (unit->tick_interval < 5) unit->tick_interval = 5;
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return E_SUCCESS;
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}
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/** Tear down the unit */
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void UUSART_deInit(Unit *unit)
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{
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struct priv *priv = unit->data;
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// de-init the pins & peripheral only if inited correctly
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if (unit->status == E_SUCCESS) {
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assert_param(priv->periph);
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LL_USART_DeInit(priv->periph);
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// Disable clock
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hw_periph_clock_disable(priv->periph);
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UUSART_DeInitDMAs(unit);
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}
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// Release all resources
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rsc_teardown(unit);
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// Free memory
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free_ck(unit->data);
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unit->data = NULL;
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}
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