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268 lines
8.6 KiB
268 lines
8.6 KiB
//
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// Created by MightyPork on 2018/02/03.
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//
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#include "platform.h"
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#include "unit_base.h"
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#define ADC_INTERNAL
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#include "_adc_internal.h"
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const uint32_t LL_ADC_SAMPLETIMES[] = {
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LL_ADC_SAMPLINGTIME_1CYCLE_5,
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LL_ADC_SAMPLINGTIME_7CYCLES_5,
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LL_ADC_SAMPLINGTIME_13CYCLES_5,
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LL_ADC_SAMPLINGTIME_28CYCLES_5,
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LL_ADC_SAMPLINGTIME_41CYCLES_5,
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LL_ADC_SAMPLINGTIME_55CYCLES_5,
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LL_ADC_SAMPLINGTIME_71CYCLES_5,
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LL_ADC_SAMPLINGTIME_239CYCLES_5,
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};
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/** Allocate data structure and set defaults */
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error_t UADC_preInit(Unit *unit)
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{
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struct priv *priv = unit->data = calloc_ck(1, sizeof(struct priv));
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if (priv == NULL) return E_OUT_OF_MEM;
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priv->channels = 1; // PA0
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priv->enable_tsense = false;
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priv->enable_vref = false;
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priv->sample_time = 0b010; // 13.5c
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priv->frequency = 4; //1000
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return E_SUCCESS;
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}
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static void UADC_DMA_Handler(void *arg)
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{
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Unit *unit = arg;
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dbg("ADC DMA ISR hit");
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assert_param(unit);
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struct priv *priv = unit->data;
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assert_param(priv);
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const uint32_t isrsnapshot = priv->DMAx->ISR;
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if (LL_DMA_IsActiveFlag_G(isrsnapshot, priv->dma_chnum)) {
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bool tc = LL_DMA_IsActiveFlag_TC(isrsnapshot, priv->dma_chnum);
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bool ht = LL_DMA_IsActiveFlag_HT(isrsnapshot, priv->dma_chnum);
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// Here we have to either copy it somewhere else, or notify another thread (queue?)
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// that the data is ready for reading
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if (ht) {
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uint16_t start = 0;
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uint16_t end = (uint16_t) (priv->dma_buffer_size / 2);
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// TODO handle first half
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LL_DMA_ClearFlag_HT(priv->DMAx, priv->dma_chnum);
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}
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if (tc) {
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uint16_t start = (uint16_t) (priv->dma_buffer_size / 2);
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uint16_t end = (uint16_t) priv->dma_buffer_size;
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// TODO handle second half
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LL_DMA_ClearFlag_TC(priv->DMAx, priv->dma_chnum);
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}
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if (LL_DMA_IsActiveFlag_TE(isrsnapshot, priv->dma_chnum)) {
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// this shouldn't happen - error
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dbg("ADC DMA TE!");
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LL_DMA_ClearFlag_TE(priv->DMAx, priv->dma_chnum);
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}
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}
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}
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/** Finalize unit set-up */
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error_t UADC_init(Unit *unit)
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{
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bool suc = true;
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struct priv *priv = unit->data;
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// Written for F072 which has only one ADC
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TRY(rsc_claim(unit, R_ADC1));
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TRY(rsc_claim(unit, R_DMA1_1));
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TRY(rsc_claim(unit, R_TIM15));
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priv->DMAx = DMA1;
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priv->DMA_CHx = DMA1_Channel1;
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priv->dma_chnum = 1;
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priv->ADCx = ADC1;
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priv->ADCx_Common = ADC1_COMMON;
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priv->TIMx = TIM15;
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// ----------------------- CONFIGURE PINS --------------------------
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{
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// Claim and configure all analog pins
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priv->nb_channels = 0;
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for (uint8_t i = 0; i < 16; i++) {
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if (priv->channels & (1 << i)) {
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char c;
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uint8_t num;
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if (i <= 7) {
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c = 'A';
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num = i;
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}
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else if (i <= 9) {
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c = 'B';
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num = (uint8_t) (i - 8);
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}
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else {
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c = 'C';
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num = (uint8_t) (i - 10);
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}
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TRY(rsc_claim_pin(unit, c, num));
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uint32_t ll_pin = hw_pin2ll(num, &suc);
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GPIO_TypeDef *port = hw_port2periph(c, &suc);
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assert_param(suc);
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LL_GPIO_SetPinPull(port, ll_pin, LL_GPIO_PULL_NO);
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LL_GPIO_SetPinMode(port, ll_pin, LL_GPIO_MODE_ANALOG);
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priv->nb_channels++;
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}
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}
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if (priv->enable_tsense) priv->nb_channels++;
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if (priv->enable_vref) priv->nb_channels++;
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if (priv->nb_channels == 0) {
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dbg("!! Need at least 1 channel");
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return E_BAD_CONFIG;
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}
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}
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// ------------------- ENABLE CLOCKS --------------------------
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{
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// enable peripherals clock
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hw_periph_clock_enable(priv->ADCx);
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hw_periph_clock_enable(priv->TIMx);
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}
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// ------------------- CONFIGURE THE TIMER --------------------------
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dbg("Setting up TIMER");
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{
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// Find suitable timer values
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uint16_t presc;
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uint32_t count;
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float real_freq;
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if (!solve_timer(PLAT_APB1_HZ, priv->frequency, true, &presc, &count,
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&real_freq)) {
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dbg("Failed to resolve timer params.");
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return E_BAD_VALUE;
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}
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dbg("Frequency error %d ppm, presc %d, count %d",
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(int) lrintf(1000000.0f * ((real_freq - priv->frequency) / (float)priv->frequency)), (int) presc, (int) count);
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LL_TIM_SetPrescaler(priv->TIMx, (uint32_t) (presc - 1));
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LL_TIM_SetAutoReload(priv->TIMx, count - 1);
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LL_TIM_EnableARRPreload(priv->TIMx);
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LL_TIM_EnableUpdateEvent(priv->TIMx);
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LL_TIM_GenerateEvent_UPDATE(priv->TIMx); // load the prescaller value
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}
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// --------------------- CONFIGURE THE ADC ---------------------------
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dbg("Setting up ADC");
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{
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// Calibrate the ADC
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dbg("Wait for calib");
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LL_ADC_StartCalibration(priv->ADCx);
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while (LL_ADC_IsCalibrationOnGoing(priv->ADCx)) {}
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dbg("ADC calibrated.");
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uint32_t mask = 0;
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if (priv->enable_vref) mask |= LL_ADC_PATH_INTERNAL_VREFINT;
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if (priv->enable_tsense) mask |= LL_ADC_PATH_INTERNAL_TEMPSENSOR;
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LL_ADC_SetCommonPathInternalCh(priv->ADCx_Common, mask);
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LL_ADC_SetDataAlignment(priv->ADCx, LL_ADC_DATA_ALIGN_RIGHT);
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LL_ADC_SetResolution(priv->ADCx, LL_ADC_RESOLUTION_12B);
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LL_ADC_REG_SetDMATransfer(priv->ADCx, LL_ADC_REG_DMA_TRANSFER_UNLIMITED);
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// configure channels
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LL_ADC_REG_SetSequencerChannels(priv->ADCx, priv->channels);
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if (priv->enable_tsense) LL_ADC_REG_SetSequencerChAdd(priv->ADCx, LL_ADC_CHANNEL_TEMPSENSOR);
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if (priv->enable_vref) LL_ADC_REG_SetSequencerChAdd(priv->ADCx, LL_ADC_CHANNEL_VREFINT);
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LL_ADC_REG_SetTriggerSource(priv->ADCx, LL_ADC_REG_TRIG_EXT_TIM15_TRGO);
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LL_ADC_SetSamplingTimeCommonChannels(priv->ADCx, LL_ADC_SAMPLETIMES[priv->sample_time]);
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LL_ADC_Enable(priv->ADCx);
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}
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// --------------------- CONFIGURE DMA -------------------------------
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dbg("Setting up DMA");
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{
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// The length must be a 2*multiple of the number of channels
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// this is a horrible way to do it but will work
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uint16_t itemcount = (uint16_t) (priv->nb_channels * (uint16_t) (UADC_DMA_MAX_BUF_LEN / (2 * priv->nb_channels)));
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priv->dma_buffer_size = (uint16_t) (itemcount * 2);
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dbg("DMA item count is %d (%d bytes)", itemcount, priv->dma_buffer_size);
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priv->dma_buffer = malloc_ck(priv->dma_buffer_size);
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if (NULL == priv->dma_buffer) return E_OUT_OF_MEM;
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assert_param(((uint32_t) priv->dma_buffer & 3) == 0); // must be aligned
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{
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LL_DMA_InitTypeDef init;
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LL_DMA_StructInit(&init);
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init.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
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init.Mode = LL_DMA_MODE_CIRCULAR;
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init.NbData = itemcount;
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init.PeriphOrM2MSrcAddress = (uint32_t) &priv->ADCx->DR;
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init.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_HALFWORD;
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init.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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init.MemoryOrM2MDstAddress = (uint32_t) priv->dma_buffer;
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init.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_HALFWORD;
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init.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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assert_param(SUCCESS == LL_DMA_Init(priv->DMAx, priv->dma_chnum, &init));
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irqd_attach(priv->DMA_CHx, UADC_DMA_Handler, unit);
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// Interrupt on transfer 1/2 and complete
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// We will capture the first and second half and send it while the other half is being filled.
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LL_DMA_EnableIT_HT(priv->DMAx, priv->dma_chnum);
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LL_DMA_EnableIT_TC(priv->DMAx, priv->dma_chnum);
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}
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LL_DMA_EnableChannel(priv->DMAx, priv->dma_chnum);
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}
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dbg("ADC inited, starting the timer ...");
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// FIXME - temporary demo - counter start...
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LL_TIM_EnableCounter(priv->TIMx);
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return E_SUCCESS;
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}
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/** Tear down the unit */
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void UADC_deInit(Unit *unit)
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{
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struct priv *priv = unit->data;
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// de-init peripherals
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if (unit->status == E_SUCCESS ) {
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//LL_ADC_DeInit(priv->ADCx);
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LL_ADC_CommonDeInit(priv->ADCx_Common);
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LL_TIM_DeInit(priv->TIMx);
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irqd_detach(priv->DMAx, UADC_DMA_Handler);
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LL_DMA_DeInit(priv->DMAx, priv->dma_chnum);
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free_ck(priv->dma_buffer);
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}
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// Release all resources, deinit pins
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rsc_teardown(unit);
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// Free memory
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free_ck(unit->data);
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}
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