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56 lines
1.6 KiB
56 lines
1.6 KiB
//
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// Created by MightyPork on 2018/01/14.
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//
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#ifndef GEX_F072_UUSART_INTERNAL_H
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#define GEX_F072_UUSART_INTERNAL_H
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#ifndef UUSART_INTERNAL
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#error "Bad include"
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#endif
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#include "platform.h"
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#define UUSART_RXBUF_LEN 128
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#define UUSART_TXBUF_LEN 128
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/** Private data structure */
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struct priv {
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uint8_t periph_num; //!< 1-6
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uint8_t remap; //!< UART remap option
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uint32_t baudrate; //!< baud rate
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uint8_t parity; //!< 0-none, 1-odd, 2-even
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uint8_t stopbits; //!< 0-half, 1-one, 2-one-and-half, 3-two (halves - 1)
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uint8_t direction; //!< 1-RX, 2-TX, 3-RXTX
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uint8_t hw_flow_control; //!< HW flow control 0-none, 1-RTC, 2-CTS, 3-full
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bool clock_output; //!< Output serial clock
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bool cpol; //!< clock CPOL setting
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bool cpha; //!< clock CPHA setting
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bool lsb_first; //!< bit order
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uint8_t width; //!< word width - 7, 8, 9 (this includes parity)
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bool data_inv; //!< Invert data bytes
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bool rx_inv; //!< Invert the RX pin levels
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bool tx_inv; //!< Invert the TX pin levels
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bool de_output; //!< Generate the Driver Enable signal for RS485
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bool de_polarity; //!< DE active level
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uint8_t de_assert_time; //!< Time to assert the DE signal before transmit
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uint8_t de_clear_time; //!< Time to clear the DE signal after transmit
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USART_TypeDef *periph;
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DMA_TypeDef *dma;
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DMA_Channel_TypeDef *dma_rx;
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DMA_Channel_TypeDef *dma_tx;
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uint8_t dma_rx_chnum;
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uint8_t dma_tx_chnum;
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uint8_t *rx_buffer;
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uint8_t *tx_buffer;
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uint16_t rx_buf_readpos;
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};
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#endif //GEX_F072_UUSART_INTERNAL_H
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