nordic implemented, need testing and fixes
This commit is contained in:
@@ -0,0 +1,165 @@
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//
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// Created by MightyPork on 2018/04/06.
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//
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#include "iface_nordic.h"
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#include "nrf_pins.h"
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#include "resources.h"
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#include "hw_utils.h"
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#include "nrf.h"
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#include "unit_base.h"
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#include "system_settings.h"
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extern osSemaphoreId semVcomTxReadyHandle;
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#define RX_PIPE_NUM 1
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void iface_nordic_claim_resources(void)
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{
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, NRF_R_SPI));
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, NRF_R_CE));
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, NRF_R_NSS));
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, NRF_R_IRQ));
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, NRF_R_MISO));
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, NRF_R_MOSI));
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, NRF_R_SCK));
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, R_EXTI0+NRF_EXTI_LINENUM));
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}
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void iface_nordic_free_resources(void)
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{
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rsc_free(&UNIT_SYSTEM, NRF_R_SPI);
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rsc_free(&UNIT_SYSTEM, NRF_R_CE);
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rsc_free(&UNIT_SYSTEM, NRF_R_NSS);
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rsc_free(&UNIT_SYSTEM, NRF_R_IRQ);
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rsc_free(&UNIT_SYSTEM, NRF_R_MISO);
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rsc_free(&UNIT_SYSTEM, NRF_R_MOSI);
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rsc_free(&UNIT_SYSTEM, NRF_R_SCK);
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rsc_free(&UNIT_SYSTEM, R_EXTI0+NRF_EXTI_LINENUM);
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}
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static uint8_t rx_buffer[32];
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static void NrfIrqHandler(void *arg)
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{
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LL_EXTI_ClearFlag_0_31(LL_EXTI_LINES[NRF_EXTI_LINENUM]);
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uint8_t pipenum;
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uint8_t count = NRF_ReceivePacket(rx_buffer, &pipenum);
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if (count > 0) {
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dbg("NRF RX %d bytes", (int)count);
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rxQuePostMsg(rx_buffer, count);
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} else {
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dbg("IRQ but no Rx");
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}
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}
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bool iface_nordic_init(void)
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{
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dbg("Setting up Nordic...");
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hw_periph_clock_enable(NRF_SPI);
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// SPI pins
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assert_param(E_SUCCESS == hw_configure_gpiorsc_af(NRF_R_SCK, NRF_SPI_AF));
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assert_param(E_SUCCESS == hw_configure_gpiorsc_af(NRF_R_MOSI, NRF_SPI_AF));
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assert_param(E_SUCCESS == hw_configure_gpiorsc_af(NRF_R_MISO, NRF_SPI_AF));
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// Manual pins
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LL_GPIO_SetPinMode(NRF_NSS_GPIO_Port, NRF_NSS_Pin, LL_GPIO_MODE_OUTPUT);
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LL_GPIO_SetPinMode(NRF_CE_GPIO_Port, NRF_CE_Pin, LL_GPIO_MODE_OUTPUT);
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LL_GPIO_SetPinMode(NRF_IRQ_GPIO_Port, NRF_IRQ_Pin, LL_GPIO_MODE_INPUT);
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LL_SPI_Disable(NRF_SPI);
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{
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LL_SPI_SetBaudRatePrescaler(NRF_SPI, LL_SPI_BAUDRATEPRESCALER_DIV8);
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LL_SPI_SetClockPolarity(NRF_SPI, LL_SPI_POLARITY_LOW);
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LL_SPI_SetClockPhase(NRF_SPI, LL_SPI_PHASE_2EDGE);
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LL_SPI_SetTransferDirection(NRF_SPI, LL_SPI_FULL_DUPLEX);
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LL_SPI_SetTransferBitOrder(NRF_SPI, LL_SPI_MSB_FIRST);
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LL_SPI_SetNSSMode(NRF_SPI, LL_SPI_NSS_SOFT);
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LL_SPI_SetDataWidth(NRF_SPI, LL_SPI_DATAWIDTH_8BIT);
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LL_SPI_SetRxFIFOThreshold(NRF_SPI, LL_SPI_RX_FIFO_TH_QUARTER); // trigger RXNE on 1 byte
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LL_SPI_SetMode(NRF_SPI, LL_SPI_MODE_MASTER);
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}
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LL_SPI_Enable(NRF_SPI);
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dbg("configure nrf module");
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// Now configure the radio
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NRF_Init(NRF_SPEED_2M); // TODO configurable speed
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NRF_SetChannel(SystemSettings.nrf_channel);
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NRF_SetBaseAddress(SystemSettings.nrf_network);
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NRF_SetRxAddress(RX_PIPE_NUM, SystemSettings.nrf_address);
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NRF_ModeRX();
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dbg("enable exti");
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// EXTI
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LL_EXTI_EnableIT_0_31(LL_EXTI_LINES[NRF_EXTI_LINENUM]);
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LL_EXTI_EnableFallingTrig_0_31(LL_EXTI_LINES[NRF_EXTI_LINENUM]);
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LL_SYSCFG_SetEXTISource(NRF_SYSCFG_EXTI_PORT, LL_SYSCFG_EXTI_LINES[NRF_EXTI_LINENUM]);
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irqd_attach(EXTIS[NRF_EXTI_LINENUM], NrfIrqHandler, NULL);
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// TODO increase priority in NVIC?
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dbg("nrf setup done");
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return true;
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}
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void iface_nordic_deinit(void)
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{
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LL_EXTI_DisableIT_0_31(LL_EXTI_LINES[NRF_EXTI_LINENUM]);
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LL_EXTI_DisableFallingTrig_0_31(LL_EXTI_LINES[NRF_EXTI_LINENUM]);
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irqd_detach(EXTIS[NRF_EXTI_LINENUM], NrfIrqHandler);
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hw_periph_clock_disable(NRF_SPI);
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hw_deinit_pin_rsc(NRF_R_SCK);
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hw_deinit_pin_rsc(NRF_R_MOSI);
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hw_deinit_pin_rsc(NRF_R_MISO);
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hw_deinit_pin_rsc(NRF_R_NSS);
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hw_deinit_pin_rsc(NRF_R_CE);
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hw_deinit_pin_rsc(NRF_R_IRQ);
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}
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#define MAX_RETRY 8
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void iface_nordic_transmit(const uint8_t *buff, uint32_t len)
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{
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bool suc = false;
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while (len > 0) {
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uint8_t chunk = (uint8_t) MIN(32, len);
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uint16_t delay = 1;
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for (int i = 0; i < MAX_RETRY; i++) {
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suc = NRF_SendPacket(RX_PIPE_NUM, buff, chunk); // use the pipe to retrieve the address
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if (!suc) {
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vTaskDelay(delay);
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delay += 5; // longer delay next time
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} else {
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break;
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}
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}
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if (!suc) {
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break;
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}
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buff += chunk;
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len -= chunk;
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}
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if (suc) {
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dbg("+ NRF Tx OK!");
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} else {
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dbg("- NRF sending failed");
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}
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// give when it's done
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xSemaphoreGive(semVcomTxReadyHandle); // similar to how it's done in USB - this is called in the Tx Done handler
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}
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@@ -0,0 +1,20 @@
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//
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// Created by MightyPork on 2018/04/06.
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//
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#ifndef GEX_F072_IFACE_NORDIC_H
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#define GEX_F072_IFACE_NORDIC_H
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#include "platform.h"
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void iface_nordic_claim_resources(void);
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void iface_nordic_free_resources(void);
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void iface_nordic_deinit(void);
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bool iface_nordic_init(void);
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void iface_nordic_transmit(const uint8_t *buff, uint32_t len);
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#endif //GEX_F072_IFACE_NORDIC_H
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@@ -0,0 +1,105 @@
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//
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// Created by MightyPork on 2018/04/06.
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//
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#include "platform.h"
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#include "iface_uart.h"
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#include "resources.h"
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#include "hw_utils.h"
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#include "irq_dispatcher.h"
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#include "task_msg.h"
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#include "system_settings.h"
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extern osSemaphoreId semVcomTxReadyHandle;
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static uint32_t usart_rxi = 0;
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static uint8_t usart_rx_buffer[MSG_QUE_SLOT_SIZE];
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static uint32_t last_rx_time = 0;
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void iface_uart_claim_resources(void)
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{
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, R_USART2));
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, R_PA2));
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assert_param(E_SUCCESS == rsc_claim(&UNIT_SYSTEM, R_PA3));
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}
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void iface_uart_free_resources(void)
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{
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rsc_free(&UNIT_SYSTEM, R_USART2);
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rsc_free(&UNIT_SYSTEM, R_PA2);
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rsc_free(&UNIT_SYSTEM, R_PA3);
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}
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/** Handler for the USART transport */
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static void com_UsartIrqHandler(void *arg)
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{
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(void)arg;
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if (LL_USART_IsActiveFlag_RXNE(USART2)) {
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vPortEnterCritical();
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{
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usart_rx_buffer[usart_rxi++] = LL_USART_ReceiveData8(USART2);
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if (usart_rxi == MSG_QUE_SLOT_SIZE) {
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rxQuePostMsg(usart_rx_buffer, MSG_QUE_SLOT_SIZE); // avoid it happening in the irq
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usart_rxi = 0;
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}
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last_rx_time = HAL_GetTick();
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}
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vPortExitCritical();
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}
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}
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/** this is called from the hal tick irq */
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void com_iface_flush_buffer(void)
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{
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if (usart_rxi > 0 && (HAL_GetTick()-last_rx_time)>=2) {
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vPortEnterCritical();
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{
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rxQuePostMsg(usart_rx_buffer, usart_rxi);
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usart_rxi = 0;
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}
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vPortExitCritical();
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}
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}
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bool iface_uart_init(void)
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{
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dbg("Setting up UART transfer");
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assert_param(E_SUCCESS == hw_configure_gpiorsc_af(R_PA2, LL_GPIO_AF_1));
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assert_param(E_SUCCESS == hw_configure_gpiorsc_af(R_PA3, LL_GPIO_AF_1));
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__HAL_RCC_USART2_CLK_ENABLE();
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__HAL_RCC_USART2_FORCE_RESET();
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__HAL_RCC_USART2_RELEASE_RESET();
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LL_USART_Disable(USART2);
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LL_USART_SetBaudRate(USART2, PLAT_APB1_HZ, LL_USART_OVERSAMPLING_16, SystemSettings.comm_uart_baud);
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dbg("baud = %d", (int)SystemSettings.comm_uart_baud);
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irqd_attach(USART2, com_UsartIrqHandler, NULL);
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LL_USART_EnableIT_RXNE(USART2);
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LL_USART_SetTransferDirection(USART2, LL_USART_DIRECTION_TX_RX);
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LL_USART_Enable(USART2);
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return true; // always OK (TODO check voltage on Rx if it's 3V3 when idle?)
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}
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void iface_uart_deinit(void)
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{
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// this doesn't normally happen
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hw_deinit_pin_rsc(R_PA2);
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hw_deinit_pin_rsc(R_PA3);
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__HAL_RCC_USART2_CLK_DISABLE();
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irqd_detach(USART2, com_UsartIrqHandler);
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}
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void iface_uart_transmit(const uint8_t *buff, uint32_t len)
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{
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// TODO rewrite this to use DMA, then wait for the DMA
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for(uint32_t i=0;i<len;i++) {
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while(!LL_USART_IsActiveFlag_TXE(USART2));
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LL_USART_TransmitData8(USART2, buff[i]);
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}
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xSemaphoreGive(semVcomTxReadyHandle); // act as if we just finished it and this is perhaps the DMA irq
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}
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@@ -0,0 +1,20 @@
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//
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// Created by MightyPork on 2018/04/06.
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//
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#ifndef GEX_F072_IFACE_UART_H
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#define GEX_F072_IFACE_UART_H
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#include "platform.h"
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void com_iface_flush_buffer(void);
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void iface_uart_deinit(void);
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bool iface_uart_init(void);
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void iface_uart_free_resources(void);
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void iface_uart_claim_resources(void);
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void iface_uart_transmit(const uint8_t *buff, uint32_t len);
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#endif //GEX_F072_IFACE_UART_H
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@@ -0,0 +1,73 @@
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//
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// Created by MightyPork on 2018/04/06.
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//
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#include "iface_usb.h"
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#include "TinyFrame.h"
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#include "system_settings.h"
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#include "USB/usb_device.h"
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extern osSemaphoreId semVcomTxReadyHandle;
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extern osMutexId mutTinyFrameTxHandle;
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bool iface_usb_ready(void)
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{
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return 0 != (USB->DADDR & USB_DADDR_ADD);
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}
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/**
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* USB transmit implementation
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*
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* @param buff - buffer to send (can be longer than the buffers)
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* @param len - buffer size
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*/
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void iface_usb_transmit(const uint8_t *buff, uint32_t len)
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{
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#if 1
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const uint32_t real_size = len;
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// Padding to a multiple of 64 bytes - this is supposed to maximize the bulk transfer speed
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if ((len&0x3F) && !SystemSettings.visible_vcom) { // this corrupts VCOM on Linux for some reason
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uint32_t pad = (64 - (len&0x3F));
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memset((void *) (buff + len), 0, pad);
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len += pad; // padding to a multiple of 64 (size of the endpoint)
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}
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// We bypass the USBD driver library's overhead by using the HAL function directly
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assert_param(HAL_OK == HAL_PCD_EP_Transmit(hUsbDeviceFS.pData, CDC_IN_EP, (uint8_t *) buff, len));
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// The buffer is the TF transmit buffer, we can't leave it to work asynchronously because
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// the next call could modify it before it's been transmitted (in the case of a chunked / multi-part frame)
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// If this is not the last chunk (assuming all but the last use full 512 bytes of the TF buffer), wait now for completion
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if (real_size == TF_SENDBUF_LEN) {
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// TODO this seems wrong - investigate
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if (pdTRUE != xSemaphoreTake(semVcomTxReadyHandle, 100)) {
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TF_Error("Tx stalled in WriteImpl");
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return;
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}
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}
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#else
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(void) tf;
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#define CHUNK 64 // size of the USB packet
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int32_t total = (int32_t) len;
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while (total > 0) {
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const int32_t mxStatus = osSemaphoreWait(semVcomTxReadyHandle, 100);
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if (mxStatus != osOK) {
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TF_Error("Tx stalled");
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return;
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}
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const uint16_t chunksize = (uint16_t) MIN(total, CHUNK);
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// this is an attempt to speed it up a little by removing a couple levels of indirection
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assert_param(HAL_OK == HAL_PCD_EP_Transmit(hUsbDeviceFS.pData, CDC_IN_EP, (uint8_t *) buff, chunksize));
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// USBD_LL_Transmit(&hUsbDeviceFS, CDC_IN_EP, (uint8_t *) buff, chunksize);
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// assert_param(USBD_OK == CDC_Transmit_FS((uint8_t *) buff, chunksize));
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buff += chunksize;
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total -= chunksize;
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}
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#endif
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}
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@@ -0,0 +1,20 @@
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//
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// Created by MightyPork on 2018/04/06.
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//
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#ifndef GEX_F072_IFACE_USB_H
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#define GEX_F072_IFACE_USB_H
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#include "platform.h"
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bool iface_usb_ready(void);
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/**
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* USB transmit implementation
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*
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* @param buff - buffer to send (can be longer than the buffers)
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* @param len - buffer size
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*/
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void iface_usb_transmit(const uint8_t *buff, uint32_t len);
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#endif //GEX_F072_IFACE_USB_H
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+27
-103
@@ -2,7 +2,6 @@
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// Created by MightyPork on 2018/03/23.
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//
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#include <stm32f072xb.h>
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#include "platform.h"
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#include "usbd_core.h"
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#include "USB/usb_device.h"
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@@ -12,6 +11,10 @@
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#include "framework/resources.h"
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#include "platform/hw_utils.h"
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#include "framework/unit_base.h"
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#include "nrf_pins.h"
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#include "iface_uart.h"
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#include "iface_usb.h"
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#include "iface_nordic.h"
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enum ComportSelection gActiveComport = COMPORT_USB; // start with USB so the handlers work correctly initially
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@@ -35,36 +38,31 @@ void com_switch_transfer_if_needed(void)
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// Check if USB is enumerated
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const uint32_t uadr = (USB->DADDR & USB_DADDR_ADD);
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if (0 == uadr) {
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if (!iface_usb_ready()) {
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dbg("Not enumerated, assuming USB is dead");
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// Fallback to radio or bare USART
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do {
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if (SystemSettings.use_comm_nordic) {
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if (configure_interface(COMPORT_NORDIC)) {
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break;
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}
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if (configure_interface(COMPORT_NORDIC)) break;
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}
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|
||||
#if 0
|
||||
if (SystemSettings.use_comm_lora) {
|
||||
if (configure_interface(COMPORT_LORA)) {
|
||||
break;
|
||||
}
|
||||
if (configure_interface(COMPORT_LORA)) break;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (SystemSettings.use_comm_uart) {
|
||||
// after nordic/lora
|
||||
if (configure_interface(COMPORT_USART)) {
|
||||
break;
|
||||
}
|
||||
if (configure_interface(COMPORT_USART)) break;
|
||||
}
|
||||
|
||||
dbg("No alternate com interface configured.");
|
||||
gActiveComport = COMPORT_NONE;
|
||||
} while (0);
|
||||
} else {
|
||||
dbg("USB got address 0x%02x - OK", (int)uadr);
|
||||
dbg("USB got address - OK");
|
||||
}
|
||||
|
||||
xfer_verify_done = true;
|
||||
@@ -76,24 +74,11 @@ void com_switch_transfer_if_needed(void)
|
||||
void com_claim_resources_for_alt_transfers(void)
|
||||
{
|
||||
if (SystemSettings.use_comm_uart) {
|
||||
do {
|
||||
if (E_SUCCESS != rsc_claim(&UNIT_SYSTEM, R_USART2)) {
|
||||
SystemSettings.use_comm_uart = false;
|
||||
break;
|
||||
}
|
||||
iface_uart_claim_resources();
|
||||
}
|
||||
|
||||
if (E_SUCCESS != rsc_claim(&UNIT_SYSTEM, R_PA2)) {
|
||||
SystemSettings.use_comm_uart = false;
|
||||
rsc_free(&UNIT_SYSTEM, R_USART2);
|
||||
break;
|
||||
}
|
||||
if (E_SUCCESS != rsc_claim(&UNIT_SYSTEM, R_PA3)) {
|
||||
SystemSettings.use_comm_uart = false;
|
||||
rsc_free(&UNIT_SYSTEM, R_USART2);
|
||||
rsc_free(&UNIT_SYSTEM, R_PA2);
|
||||
break;
|
||||
}
|
||||
} while (0);
|
||||
if (SystemSettings.use_comm_nordic) {
|
||||
iface_nordic_claim_resources();
|
||||
}
|
||||
}
|
||||
|
||||
@@ -101,46 +86,14 @@ void com_claim_resources_for_alt_transfers(void)
|
||||
void com_release_resources_for_alt_transfers(void)
|
||||
{
|
||||
if (SystemSettings.use_comm_uart) {
|
||||
rsc_free(&UNIT_SYSTEM, R_USART2);
|
||||
rsc_free(&UNIT_SYSTEM, R_PA2);
|
||||
rsc_free(&UNIT_SYSTEM, R_PA3);
|
||||
iface_uart_free_resources();
|
||||
}
|
||||
|
||||
if (SystemSettings.use_comm_nordic) {
|
||||
iface_nordic_free_resources();
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t usart_rxi = 0;
|
||||
static uint8_t usart_rx_buffer[MSG_QUE_SLOT_SIZE];
|
||||
static uint32_t last_rx_time = 0;
|
||||
|
||||
/** Handler for the USART transport */
|
||||
static void com_UsartIrqHandler(void *arg)
|
||||
{
|
||||
(void)arg;
|
||||
if (LL_USART_IsActiveFlag_RXNE(USART2)) {
|
||||
vPortEnterCritical();
|
||||
{
|
||||
usart_rx_buffer[usart_rxi++] = LL_USART_ReceiveData8(USART2);
|
||||
if (usart_rxi == MSG_QUE_SLOT_SIZE) {
|
||||
rxQuePostMsg(usart_rx_buffer, MSG_QUE_SLOT_SIZE); // avoid it happening in the irq
|
||||
usart_rxi = 0;
|
||||
}
|
||||
last_rx_time = HAL_GetTick();
|
||||
}
|
||||
vPortExitCritical();
|
||||
}
|
||||
}
|
||||
|
||||
/** this is called from the hal tick irq */
|
||||
void com_iface_flush_buffer(void)
|
||||
{
|
||||
if (usart_rxi > 0 && (HAL_GetTick()-last_rx_time)>=2) {
|
||||
vPortEnterCritical();
|
||||
{
|
||||
rxQuePostMsg(usart_rx_buffer, usart_rxi);
|
||||
usart_rxi = 0;
|
||||
}
|
||||
vPortExitCritical();
|
||||
}
|
||||
}
|
||||
|
||||
static bool configure_interface(enum ComportSelection iface)
|
||||
{
|
||||
@@ -151,14 +104,10 @@ static bool configure_interface(enum ComportSelection iface)
|
||||
__HAL_RCC_USB_CLK_DISABLE();
|
||||
}
|
||||
else if (gActiveComport == COMPORT_USART) {
|
||||
// this doesn't normally happen
|
||||
hw_deinit_pin_rsc(R_PA2);
|
||||
hw_deinit_pin_rsc(R_PA3);
|
||||
__HAL_RCC_USART2_CLK_DISABLE();
|
||||
irqd_detach(USART2, com_UsartIrqHandler);
|
||||
iface_uart_deinit();
|
||||
}
|
||||
else if (gActiveComport == COMPORT_NORDIC) {
|
||||
// TODO
|
||||
iface_nordic_deinit();
|
||||
}
|
||||
|
||||
|
||||
@@ -170,45 +119,20 @@ static bool configure_interface(enum ComportSelection iface)
|
||||
return false;
|
||||
}
|
||||
else if (iface == COMPORT_USART) {
|
||||
dbg("Setting up UART transfer");
|
||||
assert_param(E_SUCCESS == hw_configure_gpiorsc_af(R_PA2, LL_GPIO_AF_1));
|
||||
assert_param(E_SUCCESS == hw_configure_gpiorsc_af(R_PA3, LL_GPIO_AF_1));
|
||||
|
||||
__HAL_RCC_USART2_CLK_ENABLE();
|
||||
__HAL_RCC_USART2_FORCE_RESET();
|
||||
__HAL_RCC_USART2_RELEASE_RESET();
|
||||
|
||||
LL_USART_Disable(USART2);
|
||||
|
||||
LL_USART_SetBaudRate(USART2, PLAT_APB1_HZ, LL_USART_OVERSAMPLING_16, SystemSettings.comm_uart_baud);
|
||||
dbg("baud = %d", (int)SystemSettings.comm_uart_baud);
|
||||
|
||||
irqd_attach(USART2, com_UsartIrqHandler, NULL);
|
||||
LL_USART_EnableIT_RXNE(USART2);
|
||||
LL_USART_SetTransferDirection(USART2, LL_USART_DIRECTION_TX_RX);
|
||||
|
||||
LL_USART_Enable(USART2);
|
||||
|
||||
return true; // always OK (TODO check voltage on Rx if it's 3V3 when idle?)
|
||||
return iface_uart_init();
|
||||
}
|
||||
else if (iface == COMPORT_NORDIC) {
|
||||
// Try to configure nordic
|
||||
dbg("Setting up nRF transfer");
|
||||
|
||||
// TODO set up and check nRF transport
|
||||
|
||||
|
||||
// On failure, try setting up LoRa
|
||||
dbg("nRF failed to init");
|
||||
return false;
|
||||
return iface_nordic_init();
|
||||
}
|
||||
#if 0
|
||||
else if (iface == COMPORT_LORA) {
|
||||
// Try to configure nordic
|
||||
dbg("Setting up LoRa transfer");
|
||||
// TODO set up and check LoRa transport
|
||||
dbg("LoRa failed to init");
|
||||
dbg("LoRa not impl!");
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
else {
|
||||
trap("Bad iface %d", iface);
|
||||
}
|
||||
|
||||
+467
@@ -0,0 +1,467 @@
|
||||
//
|
||||
// Created by MightyPork on 2018/04/02.
|
||||
//
|
||||
|
||||
#include "platform.h"
|
||||
#include "nrf.h"
|
||||
|
||||
/**
|
||||
* Read a register
|
||||
*
|
||||
* @param reg - register number (max 83)
|
||||
* @return register value
|
||||
*/
|
||||
static uint8_t NRF_ReadRegister(uint8_t reg);
|
||||
|
||||
/**
|
||||
* Write a register
|
||||
*
|
||||
* @param reg - register number (max 83)
|
||||
* @param value - register value
|
||||
* @return status register value
|
||||
*/
|
||||
static uint8_t NRF_WriteRegister(uint8_t reg, uint8_t value);
|
||||
|
||||
// Internal use
|
||||
static uint8_t NRF_WriteBuffer(uint8_t reg, const uint8_t *pBuf, uint8_t bytes);
|
||||
|
||||
static uint8_t NRF_ReadBuffer(uint8_t reg, uint8_t *pBuf, uint8_t bytes);
|
||||
|
||||
/**
|
||||
* Set TX address for next frame
|
||||
*
|
||||
* @param SendTo - addr
|
||||
*/
|
||||
static void NRF_SetTxAddress(uint8_t ToAddr);
|
||||
|
||||
//----------------------------------------------------------
|
||||
|
||||
/** Tight asm loop */
|
||||
#define __asm_loop(cycles) \
|
||||
do { \
|
||||
register uint32_t _count asm ("r4") = cycles; \
|
||||
asm volatile( \
|
||||
".syntax unified\n" \
|
||||
".thumb\n" \
|
||||
"0:" \
|
||||
"subs %0, #1\n" \
|
||||
"bne 0b\n" \
|
||||
: "+r" (_count)); \
|
||||
} while(0)
|
||||
|
||||
// 12 for 72 MHz
|
||||
#define _delay_us(n) __asm_loop((n)*8)
|
||||
|
||||
static inline void CE(bool level) {
|
||||
if (level) LL_GPIO_SetOutputPin(NRF_CE_GPIO_Port, NRF_CE_Pin);
|
||||
else LL_GPIO_ResetOutputPin(NRF_CE_GPIO_Port, NRF_CE_Pin);
|
||||
}
|
||||
|
||||
static inline void NSS(bool level) {
|
||||
if (level) LL_GPIO_SetOutputPin(NRF_NSS_GPIO_Port, NRF_NSS_Pin);
|
||||
else LL_GPIO_ResetOutputPin(NRF_NSS_GPIO_Port, NRF_NSS_Pin);
|
||||
}
|
||||
|
||||
static uint8_t spi(uint8_t tx) {
|
||||
while (! LL_SPI_IsActiveFlag_TXE(NRF_SPI));
|
||||
LL_SPI_TransmitData8(NRF_SPI, tx);
|
||||
while (! LL_SPI_IsActiveFlag_RXNE(NRF_SPI));
|
||||
return LL_SPI_ReceiveData8(NRF_SPI);
|
||||
}
|
||||
|
||||
//-------
|
||||
|
||||
/*
|
||||
* from: http://barefootelectronics.com/NRF24L01.aspx
|
||||
*/
|
||||
|
||||
#define CMD_READ_REG 0x00 // Read command to register
|
||||
#define CMD_WRITE_REG 0x20 // Write command to register
|
||||
#define CMD_RD_RX_PLD 0x61 // Read RX payload register address
|
||||
#define CMD_WR_TX_PLD 0xA0 // Write TX payload register address
|
||||
#define CMD_FLUSH_TX 0xE1 // Flush TX register command
|
||||
#define CMD_FLUSH_RX 0xE2 // Flush RX register command
|
||||
#define CMD_REUSE_TX_PL 0xE3 // Reuse TX payload register command
|
||||
#define CMD_RD_RX_PL_WIDTH 0x60 // Read RX Payload Width
|
||||
#define CMD_WR_ACK_PLD 0xA8 // Write ACK payload for Pipe (Add pipe number 0-6)
|
||||
#define CMD_WR_TX_PLD_NK 0xB0 // Write ACK payload for not ack
|
||||
#define CMD_NOP 0xFF // No Operation, might be used to read status register
|
||||
|
||||
// SPI(nRF24L01) registers(addresses)
|
||||
#define RG_CONFIG 0x00 // 'Config' register address
|
||||
#define RG_EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
|
||||
#define RG_EN_RXADDR 0x02 // 'Enabled RX addresses' register address
|
||||
#define RG_SETUP_AW 0x03 // 'Setup address width' register address
|
||||
#define RG_SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
|
||||
#define RG_RF_CH 0x05 // 'RF channel' register address
|
||||
#define RG_RF_SETUP 0x06 // 'RF setup' register address
|
||||
#define RG_STATUS 0x07 // 'Status' register address
|
||||
#define RG_OBSERVE_TX 0x08 // 'Observe TX' register address
|
||||
#define RG_CD 0x09 // 'Carrier Detect' register address
|
||||
#define RG_RX_ADDR_P0 0x0A // 'RX address pipe0' register address
|
||||
#define RG_RX_ADDR_P1 0x0B // 'RX address pipe1' register address
|
||||
#define RG_RX_ADDR_P2 0x0C // 'RX address pipe2' register address
|
||||
#define RG_RX_ADDR_P3 0x0D // 'RX address pipe3' register address
|
||||
#define RG_RX_ADDR_P4 0x0E // 'RX address pipe4' register address
|
||||
#define RG_RX_ADDR_P5 0x0F // 'RX address pipe5' register address
|
||||
#define RG_TX_ADDR 0x10 // 'TX address' register address
|
||||
#define RG_RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
|
||||
#define RG_RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
|
||||
#define RG_RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
|
||||
#define RG_RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
|
||||
#define RG_RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
|
||||
#define RG_RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
|
||||
#define RG_FIFO_STATUS 0x17 // 'FIFO Status Register' register address
|
||||
#define RG_DYNPD 0x1C // 'Enable dynamic payload length
|
||||
#define RG_FEATURE 0x1D // 'Feature register
|
||||
|
||||
#define RD_STATUS_TX_FULL 0x01 // tx queue full
|
||||
#define RD_STATUS_RX_PNO 0x0E // pipe number of the received payload
|
||||
#define RD_STATUS_MAX_RT 0x10 // max retransmissions
|
||||
#define RD_STATUS_TX_DS 0x20 // data sent
|
||||
#define RD_STATUS_RX_DR 0x40 // data ready
|
||||
|
||||
#define RD_CONFIG_PRIM_RX 0x01 // is primary receiver
|
||||
#define RD_CONFIG_PWR_UP 0x02 // power up
|
||||
#define RD_CONFIG_CRCO 0x04 // 2-byte CRC
|
||||
#define RD_CONFIG_EN_CRC 0x08 // enable CRC
|
||||
#define RD_CONFIG_DISABLE_IRQ_MAX_RT 0x10
|
||||
#define RD_CONFIG_DISABLE_IRQ_TX_DS 0x20
|
||||
#define RD_CONFIG_DISABLE_IRQ_RX_DR 0x40
|
||||
|
||||
// Config register bits (excluding the bottom two that are changed dynamically)
|
||||
// enable only Rx IRQ
|
||||
#define ModeBits (RD_CONFIG_DISABLE_IRQ_MAX_RT | \
|
||||
RD_CONFIG_DISABLE_IRQ_TX_DS | \
|
||||
RD_CONFIG_EN_CRC | \
|
||||
RD_CONFIG_CRCO)
|
||||
|
||||
#define CEHIGH CE(1)
|
||||
#define CELOW CE(0)
|
||||
|
||||
static inline uint8_t CS(uint8_t hl)
|
||||
{
|
||||
if (hl == 1) {
|
||||
NSS(0);
|
||||
}
|
||||
else {
|
||||
NSS(1);
|
||||
}
|
||||
return hl;
|
||||
}
|
||||
|
||||
#define CHIPSELECT for (uint8_t cs = CS(1); cs==1; cs = CS(0))
|
||||
|
||||
// Base NRF address - byte 4 may be modified before writing to a pipe register,
|
||||
// the first 4 bytes are shared in the network. Master is always code 0.
|
||||
static uint8_t nrf_base_address[5];
|
||||
|
||||
static uint8_t nrf_pipe_addr[6];
|
||||
static bool nrf_pipe_enabled[6];
|
||||
|
||||
static uint8_t NRF_WriteRegister(uint8_t reg, uint8_t value)
|
||||
{
|
||||
uint8_t status = 0;
|
||||
CHIPSELECT {
|
||||
status = spi(CMD_WRITE_REG | reg);
|
||||
spi(value);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
static uint8_t NRF_ReadRegister(uint8_t reg)
|
||||
{
|
||||
uint8_t reg_val = 0;
|
||||
CHIPSELECT {
|
||||
spi(CMD_READ_REG | reg);
|
||||
reg_val = spi(0);
|
||||
}
|
||||
return reg_val;
|
||||
}
|
||||
|
||||
static uint8_t NRF_ReadStatus(void)
|
||||
{
|
||||
uint8_t reg_val = 0;
|
||||
CHIPSELECT {
|
||||
reg_val = spi(CMD_NOP);
|
||||
}
|
||||
return reg_val;
|
||||
}
|
||||
|
||||
static uint8_t NRF_WriteBuffer(uint8_t reg, const uint8_t *pBuf, uint8_t bytes)
|
||||
{
|
||||
uint8_t status = 0, i = 0;
|
||||
CHIPSELECT {
|
||||
status = spi(CMD_WRITE_REG | reg);
|
||||
for (i = 0; i < bytes; i++) {
|
||||
spi(*pBuf++);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
static uint8_t NRF_ReadBuffer(uint8_t reg, uint8_t *pBuf, uint8_t bytes)
|
||||
{
|
||||
uint8_t status = 0, i;
|
||||
CHIPSELECT {
|
||||
status = spi(CMD_READ_REG | reg);
|
||||
for (i = 0; i < bytes; i++) {
|
||||
pBuf[i] = spi(0);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void NRF_SetBaseAddress(const uint8_t *Bytes4)
|
||||
{
|
||||
memcpy(nrf_base_address, Bytes4, 4);
|
||||
nrf_base_address[4] = 0;
|
||||
}
|
||||
|
||||
void NRF_SetRxAddress(uint8_t pipenum, uint8_t AddrByte)
|
||||
{
|
||||
if (pipenum > 5) {
|
||||
dbg("!! bad pipe %d", pipenum);
|
||||
return;
|
||||
}
|
||||
|
||||
nrf_base_address[4] = AddrByte;
|
||||
|
||||
nrf_pipe_addr[pipenum] = AddrByte;
|
||||
|
||||
if (pipenum == 0) {
|
||||
NRF_WriteBuffer(RG_RX_ADDR_P0, nrf_base_address, 5);
|
||||
}
|
||||
else if (pipenum == 1) {
|
||||
NRF_WriteBuffer(RG_RX_ADDR_P1, nrf_base_address, 5);
|
||||
}
|
||||
else {
|
||||
NRF_WriteRegister(RG_RX_ADDR_P2 + (pipenum - 2), AddrByte);
|
||||
}
|
||||
}
|
||||
|
||||
bool NRF_AddPipe(uint8_t AddrByte, uint8_t *PipeNum)
|
||||
{
|
||||
for (uint8_t i = 0; i < 6; i++) {
|
||||
if(!nrf_pipe_enabled[i]) {
|
||||
NRF_SetRxAddress(i, AddrByte);
|
||||
*PipeNum = i;
|
||||
NRF_EnablePipe(i);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
uint8_t NRF_PipeNum2Addr(uint8_t pipe_num)
|
||||
{
|
||||
if (pipe_num > 5) return 0; // fail
|
||||
return nrf_pipe_addr[pipe_num];
|
||||
}
|
||||
|
||||
uint8_t NRF_Addr2PipeNum(uint8_t addr)
|
||||
{
|
||||
for (int i = 0; i < 6; i++) {
|
||||
if (nrf_pipe_addr[i] == addr) return (uint8_t) i;
|
||||
}
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
void NRF_EnablePipe(uint8_t pipenum)
|
||||
{
|
||||
uint8_t enabled = NRF_ReadRegister(RG_EN_RXADDR);
|
||||
enabled |= 1 << pipenum;
|
||||
NRF_WriteRegister(RG_EN_RXADDR, enabled);
|
||||
|
||||
nrf_pipe_enabled[pipenum] = 1;
|
||||
}
|
||||
|
||||
void NRF_DisablePipe(uint8_t pipenum)
|
||||
{
|
||||
uint8_t enabled = NRF_ReadRegister(RG_EN_RXADDR);
|
||||
enabled &= ~(1 << pipenum);
|
||||
NRF_WriteRegister(RG_EN_RXADDR, enabled);
|
||||
|
||||
nrf_pipe_enabled[pipenum] = 0;
|
||||
}
|
||||
|
||||
static void NRF_SetTxAddress(uint8_t SendTo)
|
||||
{
|
||||
nrf_base_address[4] = SendTo;
|
||||
NRF_WriteBuffer(RG_TX_ADDR, nrf_base_address, 5);
|
||||
NRF_WriteBuffer(RG_RX_ADDR_P0, nrf_base_address, 5); // the ACK will come to pipe 0
|
||||
}
|
||||
|
||||
void NRF_PowerDown(void)
|
||||
{
|
||||
CELOW;
|
||||
NRF_WriteRegister(RG_CONFIG, ModeBits);
|
||||
}
|
||||
|
||||
void NRF_ModeTX(void)
|
||||
{
|
||||
CELOW;
|
||||
uint8_t m = NRF_ReadRegister(RG_CONFIG);
|
||||
NRF_WriteRegister(RG_CONFIG, ModeBits | RD_CONFIG_PWR_UP);
|
||||
if ((m & RD_CONFIG_PWR_UP) == 0) LL_mDelay(5);
|
||||
}
|
||||
|
||||
void NRF_ModeRX(void)
|
||||
{
|
||||
NRF_WriteRegister(RG_CONFIG, ModeBits | RD_CONFIG_PWR_UP | RD_CONFIG_PRIM_RX);
|
||||
NRF_SetRxAddress(0, nrf_pipe_addr[0]); // set the P0 address - it was changed during Rx for ACK reception
|
||||
CEHIGH;
|
||||
|
||||
//if ((m&2)==0) LL_mDelay()(5); You don't need to wait. Just nothing will come for 5ms or more
|
||||
}
|
||||
|
||||
uint8_t NRF_IsModePowerDown(void)
|
||||
{
|
||||
uint8_t ret = 0;
|
||||
if ((NRF_ReadRegister(RG_CONFIG) & RD_CONFIG_PWR_UP) == 0) ret = 1;
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint8_t NRF_IsModeTX(void)
|
||||
{
|
||||
uint8_t m = NRF_ReadRegister(RG_CONFIG);
|
||||
if ((m & RD_CONFIG_PWR_UP) == 0) return 0; // OFF
|
||||
if ((m & RD_CONFIG_PRIM_RX) == 0) return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8_t NRF_IsModeRx(void)
|
||||
{
|
||||
uint8_t m = NRF_ReadRegister(RG_CONFIG);
|
||||
if ((m & RD_CONFIG_PWR_UP) == 0) return 0; // OFF
|
||||
if ((m & RD_CONFIG_PRIM_RX) == 0) return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
void NRF_SetChannel(uint8_t Ch)
|
||||
{
|
||||
NRF_WriteRegister(RG_RF_CH, Ch);
|
||||
}
|
||||
|
||||
uint8_t NRF_ReceivePacket(uint8_t *Packet, uint8_t *PipeNum)
|
||||
{
|
||||
uint8_t pw = 0, status;
|
||||
if (!NRF_IsRxPacket()) return 0;
|
||||
|
||||
CELOW;
|
||||
CHIPSELECT {
|
||||
status = spi(CMD_RD_RX_PL_WIDTH);
|
||||
pw = spi(0);
|
||||
}
|
||||
|
||||
if (pw > 32) {
|
||||
CHIPSELECT {
|
||||
spi(CMD_FLUSH_RX);
|
||||
}
|
||||
NRF_WriteRegister(RG_STATUS, RD_STATUS_RX_DR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Read the reception pipe number
|
||||
*PipeNum = (status & RD_STATUS_RX_PNO) >> 1;
|
||||
|
||||
CHIPSELECT {
|
||||
spi(CMD_RD_RX_PLD);
|
||||
for (uint8_t i = 0; i < pw; i++) Packet[i] = spi(0);
|
||||
}
|
||||
NRF_WriteRegister(RG_STATUS, RD_STATUS_RX_DR); // Clear the RX_DR interrupt
|
||||
CEHIGH;
|
||||
return pw;
|
||||
}
|
||||
|
||||
bool NRF_IsRxPacket(void)
|
||||
{
|
||||
uint8_t ret = NRF_ReadRegister(RG_STATUS) & RD_STATUS_RX_DR;
|
||||
return 0 != ret;
|
||||
}
|
||||
|
||||
bool NRF_SendPacket(uint8_t PipeNum, const uint8_t *Packet, uint8_t Length)
|
||||
{
|
||||
if (!nrf_pipe_enabled[PipeNum]) {
|
||||
dbg("!! Pipe %d not enabled", PipeNum);
|
||||
return 0;
|
||||
}
|
||||
|
||||
const uint8_t orig_conf = NRF_ReadRegister(RG_CONFIG);
|
||||
CELOW;
|
||||
NRF_ModeTX(); // Make sure in TX mode
|
||||
NRF_SetTxAddress(nrf_pipe_addr[PipeNum]);
|
||||
|
||||
CHIPSELECT {
|
||||
spi(CMD_FLUSH_TX);
|
||||
};
|
||||
|
||||
CHIPSELECT {
|
||||
spi(CMD_WR_TX_PLD);
|
||||
for (uint8_t i = 0; i < Length; i++) spi(Packet[i]);
|
||||
};
|
||||
|
||||
CEHIGH;
|
||||
_delay_us(15); // At least 10 us
|
||||
CELOW;
|
||||
|
||||
uint8_t st = 0;
|
||||
while ((st & (RD_STATUS_MAX_RT|RD_STATUS_TX_DS)) == 0) {
|
||||
st = NRF_ReadStatus(); // Packet acked or timed out
|
||||
}
|
||||
|
||||
NRF_WriteRegister(RG_STATUS, st & (RD_STATUS_MAX_RT|RD_STATUS_TX_DS)); // Clear the bit
|
||||
|
||||
if ((orig_conf & RD_CONFIG_PWR_UP) == 0) {
|
||||
NRF_PowerDown();
|
||||
}
|
||||
else if ((orig_conf & RD_CONFIG_PRIM_RX) == RD_CONFIG_PRIM_RX) {
|
||||
NRF_ModeRX();
|
||||
}
|
||||
|
||||
return 0 != (st & RD_STATUS_TX_DS); // success
|
||||
}
|
||||
|
||||
void NRF_Reset(void)
|
||||
{
|
||||
NSS(1);
|
||||
CELOW;
|
||||
NRF_PowerDown();
|
||||
|
||||
NRF_WriteRegister(RG_EN_RXADDR, 0); // disable all pipes
|
||||
|
||||
for (int i = 0; i < 6; i++) {
|
||||
nrf_pipe_addr[i] = 0;
|
||||
nrf_pipe_enabled[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void NRF_Init(uint8_t pSpeed)
|
||||
{
|
||||
// Set the required output pins
|
||||
NSS(1);
|
||||
CELOW;
|
||||
|
||||
LL_mDelay(200);
|
||||
|
||||
NRF_WriteRegister(RG_CONFIG, ModeBits);
|
||||
NRF_WriteRegister(RG_SETUP_AW, 0b11); // 5 byte addresses
|
||||
|
||||
// default
|
||||
// NRF_EnablePipe(0);
|
||||
|
||||
NRF_WriteRegister(RG_SETUP_RETR, 0x18); // 8 retries
|
||||
NRF_WriteRegister(RG_RF_CH, 2); // channel 2 NO HIGHER THAN 83 in USA!
|
||||
|
||||
NRF_WriteRegister(RG_RF_SETUP, pSpeed);
|
||||
|
||||
NRF_WriteRegister(RG_DYNPD, 0b111111); // Dynamic packet length
|
||||
NRF_WriteRegister(RG_FEATURE, 0b100); // Enable dynamic payload, and no payload in the ack.
|
||||
|
||||
for (int i = 0; i < 6; i++) {
|
||||
NRF_WriteRegister(RG_RX_PW_P0+i, 32); // Receive 32 byte packets - XXX this is probably not needed with dynamic length
|
||||
}
|
||||
|
||||
//NRFModePowerDown(); // Already in power down mode, dummy
|
||||
}
|
||||
+159
@@ -0,0 +1,159 @@
|
||||
//
|
||||
// Created by MightyPork on 2018/04/02.
|
||||
//
|
||||
|
||||
#ifndef GEX_NRF_NRF_H
|
||||
#define GEX_NRF_NRF_H
|
||||
|
||||
/*
|
||||
* nordic.h
|
||||
*
|
||||
* Created:12/16/2013 3:36:04 PM
|
||||
* Author: Tom
|
||||
*
|
||||
* NRF24L01+ Library II
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef NORDIC_H_
|
||||
#define NORDIC_H_
|
||||
|
||||
#include "platform.h"
|
||||
#include "resources.h"
|
||||
#include "nrf_pins.h"
|
||||
|
||||
// Initialize SPI and the Nordic
|
||||
|
||||
/**
|
||||
* Initialize the NRF module
|
||||
*
|
||||
* @param pSpeed
|
||||
*/
|
||||
void NRF_Init(uint8_t pSpeed);
|
||||
|
||||
#define NRF_SPEED_500k 0b00100110
|
||||
#define NRF_SPEED_2M 0b00001110
|
||||
#define NRF_SPEED_1M 0b00000110
|
||||
|
||||
/**
|
||||
* Set reception address
|
||||
* @param pipenum - pipe to set
|
||||
* @param AddrByte - byte 0
|
||||
*/
|
||||
void NRF_SetRxAddress(uint8_t pipenum, uint8_t AddrByte);
|
||||
|
||||
/**
|
||||
* Set communication channel
|
||||
*/
|
||||
void NRF_SetChannel(uint8_t Ch) ; // 0 through 83 only!
|
||||
|
||||
/**
|
||||
* Power down the transceiver
|
||||
*/
|
||||
void NRF_PowerDown(void);
|
||||
|
||||
/**
|
||||
* Selecr RX mode
|
||||
*/
|
||||
void NRF_ModeRX(void);
|
||||
|
||||
/**
|
||||
* Select TX mode
|
||||
*/
|
||||
void NRF_ModeTX(void);
|
||||
|
||||
/**
|
||||
* @return NRF is power down
|
||||
*/
|
||||
uint8_t NRF_IsModePowerDown(void);
|
||||
|
||||
/**
|
||||
* @return NRF in TX mode
|
||||
*/
|
||||
uint8_t NRF_IsModeTX(void);
|
||||
|
||||
/**
|
||||
* @return NRF in RX mode
|
||||
*/
|
||||
uint8_t NRF_IsModeRx(void);
|
||||
|
||||
/**
|
||||
* Add a pipe to the next free slot
|
||||
*
|
||||
* @param AddrByte - address byte of the peer
|
||||
* @param[out] PipeNum - pipe number is written here
|
||||
* @return success
|
||||
*/
|
||||
bool NRF_AddPipe(uint8_t AddrByte, uint8_t *PipeNum);
|
||||
|
||||
/**
|
||||
* Convert pipe number to address byte
|
||||
*
|
||||
* @param pipe_num - pipe number
|
||||
* @return address byte
|
||||
*/
|
||||
uint8_t NRF_PipeNum2Addr(uint8_t pipe_num);
|
||||
|
||||
/**
|
||||
* Convert address to a pipe number
|
||||
*
|
||||
* @param addr
|
||||
* @return
|
||||
*/
|
||||
uint8_t NRF_Addr2PipeNum(uint8_t addr);
|
||||
|
||||
/**
|
||||
* Reset as much as possible (incl. removing pipes)
|
||||
*/
|
||||
void NRF_Reset(void);
|
||||
|
||||
/**
|
||||
* Send a packet (takes care of mode switching etc)
|
||||
*
|
||||
* @param PipeNum - pipe number
|
||||
* @param Packet - packet bytes
|
||||
* @param Length - packet length
|
||||
* @return success (ACK'd)
|
||||
*/
|
||||
bool NRF_SendPacket(uint8_t PipeNum, const uint8_t *Packet, uint8_t Length);
|
||||
|
||||
/**
|
||||
* Receive a packet
|
||||
*
|
||||
* @param[out] Packet - the receiuved packet - buffer that is written
|
||||
* @param[out] PipeNum - pipe number that was received from
|
||||
* @return packet size, 0 on failure
|
||||
*/
|
||||
uint8_t NRF_ReceivePacket(uint8_t *Packet, uint8_t *PipeNum);
|
||||
|
||||
/**
|
||||
* Set base address
|
||||
* @param Bytes4
|
||||
*/
|
||||
void NRF_SetBaseAddress(const uint8_t *Bytes4);
|
||||
|
||||
/**
|
||||
* Check if there's a packet to be read
|
||||
*
|
||||
* @return 1 if any to read
|
||||
*/
|
||||
bool NRF_IsRxPacket(void);
|
||||
|
||||
/**
|
||||
* Enable a pipe
|
||||
*
|
||||
* @param pipenum - pipe number 0-5
|
||||
*/
|
||||
void NRF_EnablePipe(uint8_t pipenum);
|
||||
|
||||
/**
|
||||
* Disable a pipe
|
||||
*
|
||||
* @param pipenum - pipe number 0-5
|
||||
*/
|
||||
void NRF_DisablePipe(uint8_t pipenum);
|
||||
|
||||
#endif /* NORDIC_H_ */
|
||||
|
||||
#endif //GEX_NRF_NRF_H
|
||||
@@ -0,0 +1,33 @@
|
||||
//
|
||||
// Created by MightyPork on 2018/04/06.
|
||||
//
|
||||
|
||||
#ifndef GEX_F072_NRF_PINS_H
|
||||
#define GEX_F072_NRF_PINS_H
|
||||
|
||||
#include "platform.h"
|
||||
|
||||
// TODO move those to plat_compat?
|
||||
#define NRF_SPI SPI1
|
||||
#define NRF_R_SPI R_SPI1
|
||||
|
||||
#define NRF_IRQ_Pin LL_GPIO_PIN_10
|
||||
#define NRF_IRQ_GPIO_Port GPIOB
|
||||
#define NRF_R_IRQ R_PB10
|
||||
#define NRF_EXTI_LINENUM 10
|
||||
#define NRF_SYSCFG_EXTI_PORT LL_SYSCFG_EXTI_PORTB
|
||||
|
||||
#define NRF_NSS_Pin LL_GPIO_PIN_11
|
||||
#define NRF_NSS_GPIO_Port GPIOB
|
||||
#define NRF_R_NSS R_PB11
|
||||
|
||||
#define NRF_CE_Pin LL_GPIO_PIN_12
|
||||
#define NRF_CE_GPIO_Port GPIOB
|
||||
#define NRF_R_CE R_PB12
|
||||
|
||||
#define NRF_R_SCK R_PA5
|
||||
#define NRF_R_MISO R_PA6
|
||||
#define NRF_R_MOSI R_PA7
|
||||
#define NRF_SPI_AF LL_GPIO_AF_0
|
||||
|
||||
#endif //GEX_F072_NRF_PINS_H
|
||||
Reference in New Issue
Block a user