From 7793c72308bddfe3de1ab6e838a91f5b074228f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Hru=C5=A1ka?= Date: Sun, 18 Mar 2018 17:33:59 +0100 Subject: [PATCH] some fixes + semtech demo --- demo_lora.py | 213 +++++++++ gex/units/DOut.py | 6 +- loratest.txt | 78 ++++ sx_fsk.py | 1109 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 1403 insertions(+), 3 deletions(-) create mode 100644 demo_lora.py create mode 100644 loratest.txt create mode 100644 sx_fsk.py diff --git a/demo_lora.py b/demo_lora.py new file mode 100644 index 0000000..79f602c --- /dev/null +++ b/demo_lora.py @@ -0,0 +1,213 @@ +import time + +import gex +import sx_fsk as sx + + +# we're demonstrating the use of the QFSK mode of the SX1278 +# this is an example of how GEX can be used to control a peripheral module - in this case evaluating +# it for use in GEX remote + + +class LoRa: + def __init__(self, + rst: gex.DOut, + spi: gex.SPI, ssnum): + self.ss = ssnum + self.rst = rst + self.spi = spi + + def reset(self): + self.rst.pulse_us(100, active=False) + time.sleep(0.005) + + def rd(self, addr): + return self.spi.query(self.ss, [addr], 1)[0] + + def wr(self, addr, value): + self.spi.write(self.ss, [addr | 0x80, value]) + + def rds(self, start, count=1): + return self.spi.query(self.ss, [start], count) + + def wrs(self, start, values): + ba = bytearray() + ba.append(start | 0x80) + ba.extend(values) + self.spi.write(self.ss, ba) + + def rmw(self, addr, keep, set): + """ rmw, first and-ing the register with mask and then oring with set """ + val = self.rd(addr) + self.wr(addr, (val & keep) | set) + + def waitModeSwitch(self): + while 0 == (self.rd(sx.REG_IRQFLAGS1) & sx.RF_IRQFLAGS1_MODEREADY): + time.sleep(0.001) + + def waitSent(self): + while 0 == (self.rd(sx.REG_IRQFLAGS2) & sx.RF_IRQFLAGS2_PACKETSENT): + time.sleep(0.001) + + def fsk_set_defaults(self): + # Set default values (semtech patches: * in DS) + self.rmw(sx.REG_RXCONFIG, + sx.RF_RXCONFIG_RXTRIGER_MASK, + sx.RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT) + + self.wr(sx.REG_PREAMBLEDETECT, + sx.RF_PREAMBLEDETECT_DETECTOR_ON | + sx.RF_PREAMBLEDETECT_DETECTORSIZE_2 | + sx.RF_PREAMBLEDETECT_DETECTORTOL_10) + + self.rmw(sx.REG_OSC, sx.RF_OSC_CLKOUT_MASK, sx.RF_OSC_CLKOUT_OFF) + + self.rmw(sx.REG_FIFOTHRESH, + sx.RF_FIFOTHRESH_TXSTARTCONDITION_MASK, + sx.RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY) + + self.rmw(sx.REG_IMAGECAL, + sx.RF_IMAGECAL_AUTOIMAGECAL_MASK, + sx.RF_IMAGECAL_AUTOIMAGECAL_OFF) + + def configure_for_fsk(self, address): + self.rmw(sx.REG_OPMODE, + sx.RF_OPMODE_LONGRANGEMODE_MASK & sx.RF_OPMODE_MODULATIONTYPE_MASK & sx.RF_OPMODE_MASK, + sx.RF_OPMODE_LONGRANGEMODE_OFF | + sx.RF_OPMODE_MODULATIONTYPE_FSK | + sx.RF_OPMODE_STANDBY) + self.waitModeSwitch() + + self.fsk_set_defaults() + self.wr(sx.REG_NODEADRS, address) + self.wr(sx.REG_BROADCASTADRS, 0xFF) + # use whitening and force address matching + self.rmw(sx.REG_PACKETCONFIG1, + sx.RF_PACKETCONFIG1_DCFREE_MASK & sx.RF_PACKETCONFIG1_ADDRSFILTERING_MASK, + sx.RF_PACKETCONFIG1_DCFREE_WHITENING | + sx.RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST) + + self.wr(sx.REG_RXCONFIG, + sx.RF_RXCONFIG_AFCAUTO_ON | + sx.RF_RXCONFIG_AGCAUTO_ON | + sx.RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT) + + XTAL_FREQ = 32000000 + FREQ_STEP = 61.03515625 + FSK_FDEV = 60000 # Hz NOTE: originally: 25000, seems to help increasing + FSK_DATARATE = 200000 # bps - originally 50000 + + MAX_RFPOWER = 0 # 0-7 boost - this doesnt seem to have a huge impact + + FSK_PREAMBLE_LENGTH = 5 # Same for Tx and Rx + + fdev = round(FSK_FDEV / FREQ_STEP) + self.wr(sx.REG_FDEVMSB, fdev >> 8) + self.wr(sx.REG_FDEVLSB, fdev & 0xFF) + + datarate = round(XTAL_FREQ / FSK_DATARATE) + print("dr=%d"%datarate) + self.wr(sx.REG_BITRATEMSB, datarate >> 8) + self.wr(sx.REG_BITRATELSB, datarate & 0xFF) + + preamblelen = FSK_PREAMBLE_LENGTH + self.wr(sx.REG_PREAMBLEMSB, preamblelen >> 8) + self.wr(sx.REG_PREAMBLELSB, preamblelen & 0xFF) + + # bandwidths - 1 MHz + self.wr(sx.REG_RXBW, 0x0A) # FSK_BANDWIDTH + self.wr(sx.REG_AFCBW, 0x0A) # FSK_AFC_BANDWIDTH + + # max payload len to rx + self.wr(sx.REG_PAYLOADLENGTH, 0xFF) + + self.rmw(sx.REG_PARAMP, 0x9F, 0x40) # enable gauss 0.5 + + # pick the sync word size + self.rmw(sx.REG_SYNCCONFIG, + sx.RF_SYNCCONFIG_SYNCSIZE_MASK, + sx.RF_SYNCCONFIG_SYNCSIZE_3) + + # sync word (network ID) + self.wrs(sx.REG_SYNCVALUE1, [ + 0xe7, 0x3d, 0xfa, 0x01, 0x5e, 0xa1, 0xc9, 0x98 # something random + ]) + + # enable LNA boost (?) + self.rmw(sx.REG_LNA, + sx.RF_LNA_BOOST_MASK, + sx.RF_LNA_BOOST_ON) + + # experiments with the pa config + self.rmw(sx.REG_PACONFIG, + sx.RF_PACONFIG_PASELECT_MASK|0x8F, # max power mask + sx.RF_PACONFIG_PASELECT_PABOOST | MAX_RFPOWER<<4) + + # we could also possibly adjust the Tx power + + + +with gex.Client(gex.TrxRawUSB()) as client: + spi = gex.SPI(client, 'spi') + rst1 = gex.DOut(client, 'rst1') + rst2 = gex.DOut(client, 'rst2') + + a = LoRa(rst1, spi, 0) + b = LoRa(rst2, spi, 1) + + # reset the two transceivers to ensure they start in a defined state + a.reset() + b.reset() + + # go to sleep mode, select FSK + a.configure_for_fsk(0x33) + b.configure_for_fsk(0x44) + + print("Devices configured") + + for j in range(0, 240): + if(j>0 and j%60==0): + print() + + # --- Send a message from 1 to 2 --- + msg = [ + 51, # len + 0x44, # address + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 0, 1, 2, 3, 4, 5, 6, 7, 8, j + ] + + a.wrs(sx.REG_FIFO, msg) + + b.rmw(sx.REG_OPMODE, sx.RF_OPMODE_MASK, sx.RF_OPMODE_RECEIVER) + # time.sleep(0.005) + + # trigger A + a.rmw(sx.REG_OPMODE, sx.RF_OPMODE_MASK, sx.RF_OPMODE_TRANSMITTER) + a.waitModeSwitch() + a.waitSent() + # time.sleep(0.02) + + # print("a irq flags = ", ["0x%02x"%x for x in a.rds(sx.REG_IRQFLAGS1, 2)]) + # print("b irq flags = ", ["0x%02x"%x for x in b.rds(sx.REG_IRQFLAGS1, 2)]) + + rxd = [b.rd(sx.REG_FIFO) for x in range(0,len(msg))] + if rxd == msg: + print("\x1b[32;1m+\x1b[0m", end="", flush=True) + else: + print("\x1b[31m-\x1b[0m", end="", flush=True) + # + # for i in range(0,8): + # print("0x%02x" % rxd[i],end=" ") + # print() + # print() + print() + + # good night + a.rmw(sx.REG_OPMODE, sx.RF_OPMODE_MASK, sx.RF_OPMODE_SLEEP) + b.rmw(sx.REG_OPMODE, sx.RF_OPMODE_MASK, sx.RF_OPMODE_SLEEP) + + diff --git a/gex/units/DOut.py b/gex/units/DOut.py index f1656b6..da1bbd5 100644 --- a/gex/units/DOut.py +++ b/gex/units/DOut.py @@ -25,19 +25,19 @@ class DOut(gex.Unit): pb.u16(pins) self._send(CMD_WRITE, pb.close(), confirm=confirm) - def set(self, pins, confirm=True): + def set(self, pins=1, confirm=True): """ Set pins high - packed, int or list """ pb = gex.PayloadBuilder() pb.u16(self.pins2int(pins)) self._send(CMD_SET, pb.close(), confirm=confirm) - def clear(self, pins, confirm=True): + def clear(self, pins=1, confirm=True): """ Set pins low - packed, int or list """ pb = gex.PayloadBuilder() pb.u16(self.pins2int(pins)) self._send(CMD_CLEAR, pb.close(), confirm=confirm) - def toggle(self, pins, confirm=True): + def toggle(self, pins=1, confirm=True): """ Toggle pins - packed, int or list """ pb = gex.PayloadBuilder() pb.u16(self.pins2int(pins)) diff --git a/loratest.txt b/loratest.txt new file mode 100644 index 0000000..683c7c9 --- /dev/null +++ b/loratest.txt @@ -0,0 +1,78 @@ +## UNITS.INI +## GEX v0.0.1 on STM32F072-HUB +## built Mar 17 2018 at 17:53:15 + +[UNITS] +# Create units by adding their names next to a type (e.g. DO=A,B), +# remove the same way. Reload to update the unit sections below. + +# Digital output +DO=rst1,rst2 +# Digital input with triggers +DI= +# Neopixel RGB LED strip +NPX= +# I2C master +I2C= +# SPI master +SPI=spi +# Serial port +USART= +# 1-Wire master +1WIRE= +# Analog/digital converter +ADC= +# Shift register driver (595, 4094) +SIPO= +# Frequency and pulse measurement +FCAP= +# Capacitive touch sensing +TOUCH= +# Simple PWM output +PWMDIM= +# Two-channel analog output with waveforms +DAC= + +[DO:rst1@2] +# Port name +port=B +# Pins (comma separated, supports ranges) +pins=2 +# Initially high pins +initial=2 +# Open-drain pins +open-drain= + +[DO:rst2@3] +# Port name +port=B +# Pins (comma separated, supports ranges) +pins=6 +# Initially high pins +initial=6 +# Open-drain pins +open-drain= + +[SPI:spi@1] +# Peripheral number (SPIx) +device=1 +# Pin mappings (SCK,MISO,MOSI) +# SPI1: (0) A5,A6,A7 (1) B3,B4,B5 +# SPI2: (0) B13,B14,B15 +remap=1 + +# Prescaller: 2,4,8,...,256 +prescaller=64 +# Clock polarity: 0,1 (clock idle level) +cpol=0 +# Clock phase: 0,1 (active edge, 0-first, 1-second) +cpha=0 +# Transmit only, disable MISO +tx-only=N +# Bit order (LSB or MSB first) +first-bit=MSB + +# SS port name +port=B +# SS pins (comma separated, supports ranges) +pins=1-0 diff --git a/sx_fsk.py b/sx_fsk.py new file mode 100644 index 0000000..7cf39cd --- /dev/null +++ b/sx_fsk.py @@ -0,0 +1,1109 @@ +REG_FIFO = 0x00 +# Common settings +REG_OPMODE = 0x01 +REG_BITRATEMSB = 0x02 +REG_BITRATELSB = 0x03 +REG_FDEVMSB = 0x04 +REG_FDEVLSB = 0x05 +REG_FRFMSB = 0x06 +REG_FRFMID = 0x07 +REG_FRFLSB = 0x08 +# Tx settings +REG_PACONFIG = 0x09 +REG_PARAMP = 0x0A +REG_OCP = 0x0B +# Rx settings +REG_LNA = 0x0C +REG_RXCONFIG = 0x0D +REG_RSSICONFIG = 0x0E +REG_RSSICOLLISION = 0x0F +REG_RSSITHRESH = 0x10 +REG_RSSIVALUE = 0x11 +REG_RXBW = 0x12 +REG_AFCBW = 0x13 +REG_OOKPEAK = 0x14 +REG_OOKFIX = 0x15 +REG_OOKAVG = 0x16 +REG_RES17 = 0x17 +REG_RES18 = 0x18 +REG_RES19 = 0x19 +REG_AFCFEI = 0x1A +REG_AFCMSB = 0x1B +REG_AFCLSB = 0x1C +REG_FEIMSB = 0x1D +REG_FEILSB = 0x1E +REG_PREAMBLEDETECT = 0x1F +REG_RXTIMEOUT1 = 0x20 +REG_RXTIMEOUT2 = 0x21 +REG_RXTIMEOUT3 = 0x22 +REG_RXDELAY = 0x23 +# Oscillator settings +REG_OSC = 0x24 +# Packet handler settings +REG_PREAMBLEMSB = 0x25 +REG_PREAMBLELSB = 0x26 +REG_SYNCCONFIG = 0x27 +REG_SYNCVALUE1 = 0x28 +REG_SYNCVALUE2 = 0x29 +REG_SYNCVALUE3 = 0x2A +REG_SYNCVALUE4 = 0x2B +REG_SYNCVALUE5 = 0x2C +REG_SYNCVALUE6 = 0x2D +REG_SYNCVALUE7 = 0x2E +REG_SYNCVALUE8 = 0x2F +REG_PACKETCONFIG1 = 0x30 +REG_PACKETCONFIG2 = 0x31 +REG_PAYLOADLENGTH = 0x32 +REG_NODEADRS = 0x33 +REG_BROADCASTADRS = 0x34 +REG_FIFOTHRESH = 0x35 +# SM settings +REG_SEQCONFIG1 = 0x36 +REG_SEQCONFIG2 = 0x37 +REG_TIMERRESOL = 0x38 +REG_TIMER1COEF = 0x39 +REG_TIMER2COEF = 0x3A +# Service settings +REG_IMAGECAL = 0x3B +REG_TEMP = 0x3C +REG_LOWBAT = 0x3D +# Status +REG_IRQFLAGS1 = 0x3E +REG_IRQFLAGS2 = 0x3F +# I/O settings +REG_DIOMAPPING1 = 0x40 +REG_DIOMAPPING2 = 0x41 +# Version +REG_VERSION = 0x42 +# Additional settings +REG_AGCREF = 0x43 +REG_AGCTHRESH1 = 0x44 +REG_AGCTHRESH2 = 0x45 +REG_AGCTHRESH3 = 0x46 +REG_PLLHOP = 0x4B +REG_TCXO = 0x58 +REG_PADAC = 0x5A +REG_PLL = 0x5C +REG_PLLLOWPN = 0x5E +REG_FORMERTEMP = 0x6C +REG_BITRATEFRAC = 0x70 + +""" + * ============================================================================ + * SX1272 FSK bits control definition + * ============================================================================ +""" + +""" + * RegFifo +""" + +""" + * RegOpMode +""" +RF_OPMODE_LONGRANGEMODE_MASK = 0x7F +RF_OPMODE_LONGRANGEMODE_OFF = 0x00 +RF_OPMODE_LONGRANGEMODE_ON = 0x80 + +RF_OPMODE_MODULATIONTYPE_MASK = 0x9F +RF_OPMODE_MODULATIONTYPE_FSK = 0x00 # Default +RF_OPMODE_MODULATIONTYPE_OOK = 0x20 + +RF_OPMODE_MODULATIONSHAPING_MASK = 0xE7 +RF_OPMODE_MODULATIONSHAPING_00 = 0x00 # Default +RF_OPMODE_MODULATIONSHAPING_01 = 0x08 +RF_OPMODE_MODULATIONSHAPING_10 = 0x10 +RF_OPMODE_MODULATIONSHAPING_11 = 0x18 + +RF_OPMODE_MASK = 0xF8 +RF_OPMODE_SLEEP = 0x00 +RF_OPMODE_STANDBY = 0x01 # Default +RF_OPMODE_SYNTHESIZER_TX = 0x02 +RF_OPMODE_TRANSMITTER = 0x03 +RF_OPMODE_SYNTHESIZER_RX = 0x04 +RF_OPMODE_RECEIVER = 0x05 + +""" + * RegBitRate (bits/sec) +""" +RF_BITRATEMSB_1200_BPS = 0x68 +RF_BITRATELSB_1200_BPS = 0x2B +RF_BITRATEMSB_2400_BPS = 0x34 +RF_BITRATELSB_2400_BPS = 0x15 +RF_BITRATEMSB_4800_BPS = 0x1A # Default +RF_BITRATELSB_4800_BPS = 0x0B # Default +RF_BITRATEMSB_9600_BPS = 0x0D +RF_BITRATELSB_9600_BPS = 0x05 +RF_BITRATEMSB_15000_BPS = 0x08 +RF_BITRATELSB_15000_BPS = 0x55 +RF_BITRATEMSB_19200_BPS = 0x06 +RF_BITRATELSB_19200_BPS = 0x83 +RF_BITRATEMSB_38400_BPS = 0x03 +RF_BITRATELSB_38400_BPS = 0x41 +RF_BITRATEMSB_76800_BPS = 0x01 +RF_BITRATELSB_76800_BPS = 0xA1 +RF_BITRATEMSB_153600_BPS = 0x00 +RF_BITRATELSB_153600_BPS = 0xD0 +RF_BITRATEMSB_57600_BPS = 0x02 +RF_BITRATELSB_57600_BPS = 0x2C +RF_BITRATEMSB_115200_BPS = 0x01 +RF_BITRATELSB_115200_BPS = 0x16 +RF_BITRATEMSB_12500_BPS = 0x0A +RF_BITRATELSB_12500_BPS = 0x00 +RF_BITRATEMSB_25000_BPS = 0x05 +RF_BITRATELSB_25000_BPS = 0x00 +RF_BITRATEMSB_50000_BPS = 0x02 +RF_BITRATELSB_50000_BPS = 0x80 +RF_BITRATEMSB_100000_BPS = 0x01 +RF_BITRATELSB_100000_BPS = 0x40 +RF_BITRATEMSB_150000_BPS = 0x00 +RF_BITRATELSB_150000_BPS = 0xD5 +RF_BITRATEMSB_200000_BPS = 0x00 +RF_BITRATELSB_200000_BPS = 0xA0 +RF_BITRATEMSB_250000_BPS = 0x00 +RF_BITRATELSB_250000_BPS = 0x80 +RF_BITRATEMSB_32768_BPS = 0x03 +RF_BITRATELSB_32768_BPS = 0xD1 + +""" + * RegFdev (Hz) +""" +RF_FDEVMSB_2000_HZ = 0x00 +RF_FDEVLSB_2000_HZ = 0x21 +RF_FDEVMSB_5000_HZ = 0x00 # Default +RF_FDEVLSB_5000_HZ = 0x52 # Default +RF_FDEVMSB_10000_HZ = 0x00 +RF_FDEVLSB_10000_HZ = 0xA4 +RF_FDEVMSB_15000_HZ = 0x00 +RF_FDEVLSB_15000_HZ = 0xF6 +RF_FDEVMSB_20000_HZ = 0x01 +RF_FDEVLSB_20000_HZ = 0x48 +RF_FDEVMSB_25000_HZ = 0x01 +RF_FDEVLSB_25000_HZ = 0x9A +RF_FDEVMSB_30000_HZ = 0x01 +RF_FDEVLSB_30000_HZ = 0xEC +RF_FDEVMSB_35000_HZ = 0x02 +RF_FDEVLSB_35000_HZ = 0x3D +RF_FDEVMSB_40000_HZ = 0x02 +RF_FDEVLSB_40000_HZ = 0x8F +RF_FDEVMSB_45000_HZ = 0x02 +RF_FDEVLSB_45000_HZ = 0xE1 +RF_FDEVMSB_50000_HZ = 0x03 +RF_FDEVLSB_50000_HZ = 0x33 +RF_FDEVMSB_55000_HZ = 0x03 +RF_FDEVLSB_55000_HZ = 0x85 +RF_FDEVMSB_60000_HZ = 0x03 +RF_FDEVLSB_60000_HZ = 0xD7 +RF_FDEVMSB_65000_HZ = 0x04 +RF_FDEVLSB_65000_HZ = 0x29 +RF_FDEVMSB_70000_HZ = 0x04 +RF_FDEVLSB_70000_HZ = 0x7B +RF_FDEVMSB_75000_HZ = 0x04 +RF_FDEVLSB_75000_HZ = 0xCD +RF_FDEVMSB_80000_HZ = 0x05 +RF_FDEVLSB_80000_HZ = 0x1F +RF_FDEVMSB_85000_HZ = 0x05 +RF_FDEVLSB_85000_HZ = 0x71 +RF_FDEVMSB_90000_HZ = 0x05 +RF_FDEVLSB_90000_HZ = 0xC3 +RF_FDEVMSB_95000_HZ = 0x06 +RF_FDEVLSB_95000_HZ = 0x14 +RF_FDEVMSB_100000_HZ = 0x06 +RF_FDEVLSB_100000_HZ = 0x66 +RF_FDEVMSB_110000_HZ = 0x07 +RF_FDEVLSB_110000_HZ = 0x0A +RF_FDEVMSB_120000_HZ = 0x07 +RF_FDEVLSB_120000_HZ = 0xAE +RF_FDEVMSB_130000_HZ = 0x08 +RF_FDEVLSB_130000_HZ = 0x52 +RF_FDEVMSB_140000_HZ = 0x08 +RF_FDEVLSB_140000_HZ = 0xF6 +RF_FDEVMSB_150000_HZ = 0x09 +RF_FDEVLSB_150000_HZ = 0x9A +RF_FDEVMSB_160000_HZ = 0x0A +RF_FDEVLSB_160000_HZ = 0x3D +RF_FDEVMSB_170000_HZ = 0x0A +RF_FDEVLSB_170000_HZ = 0xE1 +RF_FDEVMSB_180000_HZ = 0x0B +RF_FDEVLSB_180000_HZ = 0x85 +RF_FDEVMSB_190000_HZ = 0x0C +RF_FDEVLSB_190000_HZ = 0x29 +RF_FDEVMSB_200000_HZ = 0x0C +RF_FDEVLSB_200000_HZ = 0xCD + +""" + * RegFrf (MHz) +""" +RF_FRFMSB_863_MHZ = 0xD7 +RF_FRFMID_863_MHZ = 0xC0 +RF_FRFLSB_863_MHZ = 0x00 +RF_FRFMSB_864_MHZ = 0xD8 +RF_FRFMID_864_MHZ = 0x00 +RF_FRFLSB_864_MHZ = 0x00 +RF_FRFMSB_865_MHZ = 0xD8 +RF_FRFMID_865_MHZ = 0x40 +RF_FRFLSB_865_MHZ = 0x00 +RF_FRFMSB_866_MHZ = 0xD8 +RF_FRFMID_866_MHZ = 0x80 +RF_FRFLSB_866_MHZ = 0x00 +RF_FRFMSB_867_MHZ = 0xD8 +RF_FRFMID_867_MHZ = 0xC0 +RF_FRFLSB_867_MHZ = 0x00 +RF_FRFMSB_868_MHZ = 0xD9 +RF_FRFMID_868_MHZ = 0x00 +RF_FRFLSB_868_MHZ = 0x00 +RF_FRFMSB_869_MHZ = 0xD9 +RF_FRFMID_869_MHZ = 0x40 +RF_FRFLSB_869_MHZ = 0x00 +RF_FRFMSB_870_MHZ = 0xD9 +RF_FRFMID_870_MHZ = 0x80 +RF_FRFLSB_870_MHZ = 0x00 + +RF_FRFMSB_902_MHZ = 0xE1 +RF_FRFMID_902_MHZ = 0x80 +RF_FRFLSB_902_MHZ = 0x00 +RF_FRFMSB_903_MHZ = 0xE1 +RF_FRFMID_903_MHZ = 0xC0 +RF_FRFLSB_903_MHZ = 0x00 +RF_FRFMSB_904_MHZ = 0xE2 +RF_FRFMID_904_MHZ = 0x00 +RF_FRFLSB_904_MHZ = 0x00 +RF_FRFMSB_905_MHZ = 0xE2 +RF_FRFMID_905_MHZ = 0x40 +RF_FRFLSB_905_MHZ = 0x00 +RF_FRFMSB_906_MHZ = 0xE2 +RF_FRFMID_906_MHZ = 0x80 +RF_FRFLSB_906_MHZ = 0x00 +RF_FRFMSB_907_MHZ = 0xE2 +RF_FRFMID_907_MHZ = 0xC0 +RF_FRFLSB_907_MHZ = 0x00 +RF_FRFMSB_908_MHZ = 0xE3 +RF_FRFMID_908_MHZ = 0x00 +RF_FRFLSB_908_MHZ = 0x00 +RF_FRFMSB_909_MHZ = 0xE3 +RF_FRFMID_909_MHZ = 0x40 +RF_FRFLSB_909_MHZ = 0x00 +RF_FRFMSB_910_MHZ = 0xE3 +RF_FRFMID_910_MHZ = 0x80 +RF_FRFLSB_910_MHZ = 0x00 +RF_FRFMSB_911_MHZ = 0xE3 +RF_FRFMID_911_MHZ = 0xC0 +RF_FRFLSB_911_MHZ = 0x00 +RF_FRFMSB_912_MHZ = 0xE4 +RF_FRFMID_912_MHZ = 0x00 +RF_FRFLSB_912_MHZ = 0x00 +RF_FRFMSB_913_MHZ = 0xE4 +RF_FRFMID_913_MHZ = 0x40 +RF_FRFLSB_913_MHZ = 0x00 +RF_FRFMSB_914_MHZ = 0xE4 +RF_FRFMID_914_MHZ = 0x80 +RF_FRFLSB_914_MHZ = 0x00 +RF_FRFMSB_915_MHZ = 0xE4 # Default +RF_FRFMID_915_MHZ = 0xC0 # Default +RF_FRFLSB_915_MHZ = 0x00 # Default +RF_FRFMSB_916_MHZ = 0xE5 +RF_FRFMID_916_MHZ = 0x00 +RF_FRFLSB_916_MHZ = 0x00 +RF_FRFMSB_917_MHZ = 0xE5 +RF_FRFMID_917_MHZ = 0x40 +RF_FRFLSB_917_MHZ = 0x00 +RF_FRFMSB_918_MHZ = 0xE5 +RF_FRFMID_918_MHZ = 0x80 +RF_FRFLSB_918_MHZ = 0x00 +RF_FRFMSB_919_MHZ = 0xE5 +RF_FRFMID_919_MHZ = 0xC0 +RF_FRFLSB_919_MHZ = 0x00 +RF_FRFMSB_920_MHZ = 0xE6 +RF_FRFMID_920_MHZ = 0x00 +RF_FRFLSB_920_MHZ = 0x00 +RF_FRFMSB_921_MHZ = 0xE6 +RF_FRFMID_921_MHZ = 0x40 +RF_FRFLSB_921_MHZ = 0x00 +RF_FRFMSB_922_MHZ = 0xE6 +RF_FRFMID_922_MHZ = 0x80 +RF_FRFLSB_922_MHZ = 0x00 +RF_FRFMSB_923_MHZ = 0xE6 +RF_FRFMID_923_MHZ = 0xC0 +RF_FRFLSB_923_MHZ = 0x00 +RF_FRFMSB_924_MHZ = 0xE7 +RF_FRFMID_924_MHZ = 0x00 +RF_FRFLSB_924_MHZ = 0x00 +RF_FRFMSB_925_MHZ = 0xE7 +RF_FRFMID_925_MHZ = 0x40 +RF_FRFLSB_925_MHZ = 0x00 +RF_FRFMSB_926_MHZ = 0xE7 +RF_FRFMID_926_MHZ = 0x80 +RF_FRFLSB_926_MHZ = 0x00 +RF_FRFMSB_927_MHZ = 0xE7 +RF_FRFMID_927_MHZ = 0xC0 +RF_FRFLSB_927_MHZ = 0x00 +RF_FRFMSB_928_MHZ = 0xE8 +RF_FRFMID_928_MHZ = 0x00 +RF_FRFLSB_928_MHZ = 0x00 + +""" + * RegPaConfig +""" +RF_PACONFIG_PASELECT_MASK = 0x7F +RF_PACONFIG_PASELECT_PABOOST = 0x80 +RF_PACONFIG_PASELECT_RFO = 0x00 # Default + +RF_PACONFIG_OUTPUTPOWER_MASK = 0xF0 + +""" + * RegPaRamp +""" +RF_PARAMP_LOWPNTXPLL_MASK = 0xEF +RF_PARAMP_LOWPNTXPLL_OFF = 0x10 # Default +RF_PARAMP_LOWPNTXPLL_ON = 0x00 + +RF_PARAMP_MASK = 0xF0 +RF_PARAMP_3400_US = 0x00 +RF_PARAMP_2000_US = 0x01 +RF_PARAMP_1000_US = 0x02 +RF_PARAMP_0500_US = 0x03 +RF_PARAMP_0250_US = 0x04 +RF_PARAMP_0125_US = 0x05 +RF_PARAMP_0100_US = 0x06 +RF_PARAMP_0062_US = 0x07 +RF_PARAMP_0050_US = 0x08 +RF_PARAMP_0040_US = 0x09 # Default +RF_PARAMP_0031_US = 0x0A +RF_PARAMP_0025_US = 0x0B +RF_PARAMP_0020_US = 0x0C +RF_PARAMP_0015_US = 0x0D +RF_PARAMP_0012_US = 0x0E +RF_PARAMP_0010_US = 0x0F + +""" + * RegOcp +""" +RF_OCP_MASK = 0xDF +RF_OCP_ON = 0x20 # Default +RF_OCP_OFF = 0x00 + +RF_OCP_TRIM_MASK = 0xE0 +RF_OCP_TRIM_045_MA = 0x00 +RF_OCP_TRIM_050_MA = 0x01 +RF_OCP_TRIM_055_MA = 0x02 +RF_OCP_TRIM_060_MA = 0x03 +RF_OCP_TRIM_065_MA = 0x04 +RF_OCP_TRIM_070_MA = 0x05 +RF_OCP_TRIM_075_MA = 0x06 +RF_OCP_TRIM_080_MA = 0x07 +RF_OCP_TRIM_085_MA = 0x08 +RF_OCP_TRIM_090_MA = 0x09 +RF_OCP_TRIM_095_MA = 0x0A +RF_OCP_TRIM_100_MA = 0x0B # Default +RF_OCP_TRIM_105_MA = 0x0C +RF_OCP_TRIM_110_MA = 0x0D +RF_OCP_TRIM_115_MA = 0x0E +RF_OCP_TRIM_120_MA = 0x0F +RF_OCP_TRIM_130_MA = 0x10 +RF_OCP_TRIM_140_MA = 0x11 +RF_OCP_TRIM_150_MA = 0x12 +RF_OCP_TRIM_160_MA = 0x13 +RF_OCP_TRIM_170_MA = 0x14 +RF_OCP_TRIM_180_MA = 0x15 +RF_OCP_TRIM_190_MA = 0x16 +RF_OCP_TRIM_200_MA = 0x17 +RF_OCP_TRIM_210_MA = 0x18 +RF_OCP_TRIM_220_MA = 0x19 +RF_OCP_TRIM_230_MA = 0x1A +RF_OCP_TRIM_240_MA = 0x1B + +""" + * RegLna +""" +RF_LNA_GAIN_MASK = 0x1F +RF_LNA_GAIN_G1 = 0x20 # Default +RF_LNA_GAIN_G2 = 0x40 +RF_LNA_GAIN_G3 = 0x60 +RF_LNA_GAIN_G4 = 0x80 +RF_LNA_GAIN_G5 = 0xA0 +RF_LNA_GAIN_G6 = 0xC0 + +RF_LNA_BOOST_MASK = 0xFC +RF_LNA_BOOST_OFF = 0x00 # Default +RF_LNA_BOOST_ON = 0x03 + +""" + * RegRxConfig +""" +RF_RXCONFIG_RESTARTRXONCOLLISION_MASK = 0x7F +RF_RXCONFIG_RESTARTRXONCOLLISION_ON = 0x80 +RF_RXCONFIG_RESTARTRXONCOLLISION_OFF = 0x00 # Default + +RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK = 0x40 # Write only + +RF_RXCONFIG_RESTARTRXWITHPLLLOCK = 0x20 # Write only + +RF_RXCONFIG_AFCAUTO_MASK = 0xEF +RF_RXCONFIG_AFCAUTO_ON = 0x10 +RF_RXCONFIG_AFCAUTO_OFF = 0x00 # Default + +RF_RXCONFIG_AGCAUTO_MASK = 0xF7 +RF_RXCONFIG_AGCAUTO_ON = 0x08 # Default +RF_RXCONFIG_AGCAUTO_OFF = 0x00 + +RF_RXCONFIG_RXTRIGER_MASK = 0xF8 +RF_RXCONFIG_RXTRIGER_OFF = 0x00 +RF_RXCONFIG_RXTRIGER_RSSI = 0x01 +RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT = 0x06 # Default +RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT = 0x07 + +""" + * RegRssiConfig +""" +RF_RSSICONFIG_OFFSET_MASK = 0x07 +RF_RSSICONFIG_OFFSET_P_00_DB = 0x00 # Default +RF_RSSICONFIG_OFFSET_P_01_DB = 0x08 +RF_RSSICONFIG_OFFSET_P_02_DB = 0x10 +RF_RSSICONFIG_OFFSET_P_03_DB = 0x18 +RF_RSSICONFIG_OFFSET_P_04_DB = 0x20 +RF_RSSICONFIG_OFFSET_P_05_DB = 0x28 +RF_RSSICONFIG_OFFSET_P_06_DB = 0x30 +RF_RSSICONFIG_OFFSET_P_07_DB = 0x38 +RF_RSSICONFIG_OFFSET_P_08_DB = 0x40 +RF_RSSICONFIG_OFFSET_P_09_DB = 0x48 +RF_RSSICONFIG_OFFSET_P_10_DB = 0x50 +RF_RSSICONFIG_OFFSET_P_11_DB = 0x58 +RF_RSSICONFIG_OFFSET_P_12_DB = 0x60 +RF_RSSICONFIG_OFFSET_P_13_DB = 0x68 +RF_RSSICONFIG_OFFSET_P_14_DB = 0x70 +RF_RSSICONFIG_OFFSET_P_15_DB = 0x78 +RF_RSSICONFIG_OFFSET_M_16_DB = 0x80 +RF_RSSICONFIG_OFFSET_M_15_DB = 0x88 +RF_RSSICONFIG_OFFSET_M_14_DB = 0x90 +RF_RSSICONFIG_OFFSET_M_13_DB = 0x98 +RF_RSSICONFIG_OFFSET_M_12_DB = 0xA0 +RF_RSSICONFIG_OFFSET_M_11_DB = 0xA8 +RF_RSSICONFIG_OFFSET_M_10_DB = 0xB0 +RF_RSSICONFIG_OFFSET_M_09_DB = 0xB8 +RF_RSSICONFIG_OFFSET_M_08_DB = 0xC0 +RF_RSSICONFIG_OFFSET_M_07_DB = 0xC8 +RF_RSSICONFIG_OFFSET_M_06_DB = 0xD0 +RF_RSSICONFIG_OFFSET_M_05_DB = 0xD8 +RF_RSSICONFIG_OFFSET_M_04_DB = 0xE0 +RF_RSSICONFIG_OFFSET_M_03_DB = 0xE8 +RF_RSSICONFIG_OFFSET_M_02_DB = 0xF0 +RF_RSSICONFIG_OFFSET_M_01_DB = 0xF8 + +RF_RSSICONFIG_SMOOTHING_MASK = 0xF8 +RF_RSSICONFIG_SMOOTHING_2 = 0x00 +RF_RSSICONFIG_SMOOTHING_4 = 0x01 +RF_RSSICONFIG_SMOOTHING_8 = 0x02 # Default +RF_RSSICONFIG_SMOOTHING_16 = 0x03 +RF_RSSICONFIG_SMOOTHING_32 = 0x04 +RF_RSSICONFIG_SMOOTHING_64 = 0x05 +RF_RSSICONFIG_SMOOTHING_128 = 0x06 +RF_RSSICONFIG_SMOOTHING_256 = 0x07 + +""" + * RegRssiCollision +""" +RF_RSSICOLISION_THRESHOLD = 0x0A # Default + +""" + * RegRssiThresh +""" +RF_RSSITHRESH_THRESHOLD = 0xFF # Default + +""" + * RegRssiValue (Read Only) +""" + +""" + * RegRxBw +""" +RF_RXBW_MANT_MASK = 0xE7 +RF_RXBW_MANT_16 = 0x00 +RF_RXBW_MANT_20 = 0x08 +RF_RXBW_MANT_24 = 0x10 # Default + +RF_RXBW_EXP_MASK = 0xF8 +RF_RXBW_EXP_0 = 0x00 +RF_RXBW_EXP_1 = 0x01 +RF_RXBW_EXP_2 = 0x02 +RF_RXBW_EXP_3 = 0x03 +RF_RXBW_EXP_4 = 0x04 +RF_RXBW_EXP_5 = 0x05 # Default +RF_RXBW_EXP_6 = 0x06 +RF_RXBW_EXP_7 = 0x07 + +""" + * RegAfcBw +""" +RF_AFCBW_MANTAFC_MASK = 0xE7 +RF_AFCBW_MANTAFC_16 = 0x00 +RF_AFCBW_MANTAFC_20 = 0x08 # Default +RF_AFCBW_MANTAFC_24 = 0x10 + +RF_AFCBW_EXPAFC_MASK = 0xF8 +RF_AFCBW_EXPAFC_0 = 0x00 +RF_AFCBW_EXPAFC_1 = 0x01 +RF_AFCBW_EXPAFC_2 = 0x02 +RF_AFCBW_EXPAFC_3 = 0x03 # Default +RF_AFCBW_EXPAFC_4 = 0x04 +RF_AFCBW_EXPAFC_5 = 0x05 +RF_AFCBW_EXPAFC_6 = 0x06 +RF_AFCBW_EXPAFC_7 = 0x07 + +""" + * RegOokPeak +""" +RF_OOKPEAK_BITSYNC_MASK = 0xDF # Default +RF_OOKPEAK_BITSYNC_ON = 0x20 # Default +RF_OOKPEAK_BITSYNC_OFF = 0x00 + +RF_OOKPEAK_OOKTHRESHTYPE_MASK = 0xE7 +RF_OOKPEAK_OOKTHRESHTYPE_FIXED = 0x00 +RF_OOKPEAK_OOKTHRESHTYPE_PEAK = 0x08 # Default +RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE = 0x10 + +RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK = 0xF8 +RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB = 0x00 # Default +RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB = 0x01 +RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB = 0x02 +RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB = 0x03 +RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB = 0x04 +RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB = 0x05 +RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB = 0x06 +RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB = 0x07 + +""" + * RegOokFix +""" +RF_OOKFIX_OOKFIXEDTHRESHOLD = 0x0C # Default + +""" + * RegOokAvg +""" +RF_OOKAVG_OOKPEAKTHRESHDEC_MASK = 0x1F +RF_OOKAVG_OOKPEAKTHRESHDEC_000 = 0x00 # Default +RF_OOKAVG_OOKPEAKTHRESHDEC_001 = 0x20 +RF_OOKAVG_OOKPEAKTHRESHDEC_010 = 0x40 +RF_OOKAVG_OOKPEAKTHRESHDEC_011 = 0x60 +RF_OOKAVG_OOKPEAKTHRESHDEC_100 = 0x80 +RF_OOKAVG_OOKPEAKTHRESHDEC_101 = 0xA0 +RF_OOKAVG_OOKPEAKTHRESHDEC_110 = 0xC0 +RF_OOKAVG_OOKPEAKTHRESHDEC_111 = 0xE0 + +RF_OOKAVG_AVERAGEOFFSET_MASK = 0xF3 +RF_OOKAVG_AVERAGEOFFSET_0_DB = 0x00 # Default +RF_OOKAVG_AVERAGEOFFSET_2_DB = 0x04 +RF_OOKAVG_AVERAGEOFFSET_4_DB = 0x08 +RF_OOKAVG_AVERAGEOFFSET_6_DB = 0x0C + +RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK = 0xFC +RF_OOKAVG_OOKAVERAGETHRESHFILT_00 = 0x00 +RF_OOKAVG_OOKAVERAGETHRESHFILT_01 = 0x01 +RF_OOKAVG_OOKAVERAGETHRESHFILT_10 = 0x02 # Default +RF_OOKAVG_OOKAVERAGETHRESHFILT_11 = 0x03 + +""" + * RegAfcFei +""" +RF_AFCFEI_AGCSTART = 0x10 + +RF_AFCFEI_AFCCLEAR = 0x02 + +RF_AFCFEI_AFCAUTOCLEAR_MASK = 0xFE +RF_AFCFEI_AFCAUTOCLEAR_ON = 0x01 +RF_AFCFEI_AFCAUTOCLEAR_OFF = 0x00 # Default + +""" + * RegAfcMsb (Read Only) +""" + +""" + * RegAfcLsb (Read Only) +""" + +""" + * RegFeiMsb (Read Only) +""" + +""" + * RegFeiLsb (Read Only) +""" + +""" + * RegPreambleDetect +""" +RF_PREAMBLEDETECT_DETECTOR_MASK = 0x7F +RF_PREAMBLEDETECT_DETECTOR_ON = 0x80 # Default +RF_PREAMBLEDETECT_DETECTOR_OFF = 0x00 + +RF_PREAMBLEDETECT_DETECTORSIZE_MASK = 0x9F +RF_PREAMBLEDETECT_DETECTORSIZE_1 = 0x00 +RF_PREAMBLEDETECT_DETECTORSIZE_2 = 0x20 # Default +RF_PREAMBLEDETECT_DETECTORSIZE_3 = 0x40 +RF_PREAMBLEDETECT_DETECTORSIZE_4 = 0x60 + +RF_PREAMBLEDETECT_DETECTORTOL_MASK = 0xE0 +RF_PREAMBLEDETECT_DETECTORTOL_0 = 0x00 +RF_PREAMBLEDETECT_DETECTORTOL_1 = 0x01 +RF_PREAMBLEDETECT_DETECTORTOL_2 = 0x02 +RF_PREAMBLEDETECT_DETECTORTOL_3 = 0x03 +RF_PREAMBLEDETECT_DETECTORTOL_4 = 0x04 +RF_PREAMBLEDETECT_DETECTORTOL_5 = 0x05 +RF_PREAMBLEDETECT_DETECTORTOL_6 = 0x06 +RF_PREAMBLEDETECT_DETECTORTOL_7 = 0x07 +RF_PREAMBLEDETECT_DETECTORTOL_8 = 0x08 +RF_PREAMBLEDETECT_DETECTORTOL_9 = 0x09 +RF_PREAMBLEDETECT_DETECTORTOL_10 = 0x0A # Default +RF_PREAMBLEDETECT_DETECTORTOL_11 = 0x0B +RF_PREAMBLEDETECT_DETECTORTOL_12 = 0x0C +RF_PREAMBLEDETECT_DETECTORTOL_13 = 0x0D +RF_PREAMBLEDETECT_DETECTORTOL_14 = 0x0E +RF_PREAMBLEDETECT_DETECTORTOL_15 = 0x0F +RF_PREAMBLEDETECT_DETECTORTOL_16 = 0x10 +RF_PREAMBLEDETECT_DETECTORTOL_17 = 0x11 +RF_PREAMBLEDETECT_DETECTORTOL_18 = 0x12 +RF_PREAMBLEDETECT_DETECTORTOL_19 = 0x13 +RF_PREAMBLEDETECT_DETECTORTOL_20 = 0x14 +RF_PREAMBLEDETECT_DETECTORTOL_21 = 0x15 +RF_PREAMBLEDETECT_DETECTORTOL_22 = 0x16 +RF_PREAMBLEDETECT_DETECTORTOL_23 = 0x17 +RF_PREAMBLEDETECT_DETECTORTOL_24 = 0x18 +RF_PREAMBLEDETECT_DETECTORTOL_25 = 0x19 +RF_PREAMBLEDETECT_DETECTORTOL_26 = 0x1A +RF_PREAMBLEDETECT_DETECTORTOL_27 = 0x1B +RF_PREAMBLEDETECT_DETECTORTOL_28 = 0x1C +RF_PREAMBLEDETECT_DETECTORTOL_29 = 0x1D +RF_PREAMBLEDETECT_DETECTORTOL_30 = 0x1E +RF_PREAMBLEDETECT_DETECTORTOL_31 = 0x1F + +""" + * RegRxTimeout1 +""" +RF_RXTIMEOUT1_TIMEOUTRXRSSI = 0x00 # Default + +""" + * RegRxTimeout2 +""" +RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE = 0x00 # Default + +""" + * RegRxTimeout3 +""" +RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC = 0x00 # Default + +""" + * RegRxDelay +""" +RF_RXDELAY_INTERPACKETRXDELAY = 0x00 # Default + +""" + * RegOsc +""" +RF_OSC_RCCALSTART = 0x08 + +RF_OSC_CLKOUT_MASK = 0xF8 +RF_OSC_CLKOUT_32_MHZ = 0x00 +RF_OSC_CLKOUT_16_MHZ = 0x01 +RF_OSC_CLKOUT_8_MHZ = 0x02 +RF_OSC_CLKOUT_4_MHZ = 0x03 +RF_OSC_CLKOUT_2_MHZ = 0x04 +RF_OSC_CLKOUT_1_MHZ = 0x05 +RF_OSC_CLKOUT_RC = 0x06 +RF_OSC_CLKOUT_OFF = 0x07 # Default + +""" + * RegPreambleMsb/RegPreambleLsb +""" +RF_PREAMBLEMSB_SIZE = 0x00 # Default +RF_PREAMBLELSB_SIZE = 0x03 # Default + +""" + * RegSyncConfig +""" +RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK = 0x3F +RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON = 0x80 # Default +RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF = 0x40 +RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF = 0x00 + +RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK = 0xDF +RF_SYNCCONFIG_PREAMBLEPOLARITY_55 = 0x20 +RF_SYNCCONFIG_PREAMBLEPOLARITY_AA = 0x00 # Default + +RF_SYNCCONFIG_SYNC_MASK = 0xEF +RF_SYNCCONFIG_SYNC_ON = 0x10 # Default +RF_SYNCCONFIG_SYNC_OFF = 0x00 + +RF_SYNCCONFIG_FIFOFILLCONDITION_MASK = 0xF7 +RF_SYNCCONFIG_FIFOFILLCONDITION_AUTO = 0x00 # Default +RF_SYNCCONFIG_FIFOFILLCONDITION_MANUAL = 0x08 + +RF_SYNCCONFIG_SYNCSIZE_MASK = 0xF8 +RF_SYNCCONFIG_SYNCSIZE_1 = 0x00 +RF_SYNCCONFIG_SYNCSIZE_2 = 0x01 +RF_SYNCCONFIG_SYNCSIZE_3 = 0x02 +RF_SYNCCONFIG_SYNCSIZE_4 = 0x03 # Default +RF_SYNCCONFIG_SYNCSIZE_5 = 0x04 +RF_SYNCCONFIG_SYNCSIZE_6 = 0x05 +RF_SYNCCONFIG_SYNCSIZE_7 = 0x06 +RF_SYNCCONFIG_SYNCSIZE_8 = 0x07 + +""" + * RegSyncValue1-8 +""" +RF_SYNCVALUE1_SYNCVALUE = 0x01 # Default +RF_SYNCVALUE2_SYNCVALUE = 0x01 # Default +RF_SYNCVALUE3_SYNCVALUE = 0x01 # Default +RF_SYNCVALUE4_SYNCVALUE = 0x01 # Default +RF_SYNCVALUE5_SYNCVALUE = 0x01 # Default +RF_SYNCVALUE6_SYNCVALUE = 0x01 # Default +RF_SYNCVALUE7_SYNCVALUE = 0x01 # Default +RF_SYNCVALUE8_SYNCVALUE = 0x01 # Default + +""" + * RegPacketConfig1 +""" +RF_PACKETCONFIG1_PACKETFORMAT_MASK = 0x7F +RF_PACKETCONFIG1_PACKETFORMAT_FIXED = 0x00 +RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE = 0x80 # Default + +RF_PACKETCONFIG1_DCFREE_MASK = 0x9F +RF_PACKETCONFIG1_DCFREE_OFF = 0x00 # Default +RF_PACKETCONFIG1_DCFREE_MANCHESTER = 0x20 +RF_PACKETCONFIG1_DCFREE_WHITENING = 0x40 + +RF_PACKETCONFIG1_CRC_MASK = 0xEF +RF_PACKETCONFIG1_CRC_ON = 0x10 # Default +RF_PACKETCONFIG1_CRC_OFF = 0x00 + +RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK = 0xF7 +RF_PACKETCONFIG1_CRCAUTOCLEAR_ON = 0x00 # Default +RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF = 0x08 + +RF_PACKETCONFIG1_ADDRSFILTERING_MASK = 0xF9 +RF_PACKETCONFIG1_ADDRSFILTERING_OFF = 0x00 # Default +RF_PACKETCONFIG1_ADDRSFILTERING_NODE = 0x02 +RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST = 0x04 + +RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK = 0xFE +RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT = 0x00 # Default +RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM = 0x01 + +""" + * RegPacketConfig2 +""" +RF_PACKETCONFIG2_DATAMODE_MASK = 0xBF +RF_PACKETCONFIG2_DATAMODE_CONTINUOUS = 0x00 +RF_PACKETCONFIG2_DATAMODE_PACKET = 0x40 # Default + +RF_PACKETCONFIG2_IOHOME_MASK = 0xDF +RF_PACKETCONFIG2_IOHOME_ON = 0x20 +RF_PACKETCONFIG2_IOHOME_OFF = 0x00 # Default + +RF_PACKETCONFIG2_BEACON_MASK = 0xF7 +RF_PACKETCONFIG2_BEACON_ON = 0x08 +RF_PACKETCONFIG2_BEACON_OFF = 0x00 # Default + +RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK = 0xF8 + +""" + * RegPayloadLength +""" +RF_PAYLOADLENGTH_LENGTH = 0x40 # Default + +""" + * RegNodeAdrs +""" +RF_NODEADDRESS_ADDRESS = 0x00 + +""" + * RegBroadcastAdrs +""" +RF_BROADCASTADDRESS_ADDRESS = 0x00 + +""" + * RegFifoThresh +""" +RF_FIFOTHRESH_TXSTARTCONDITION_MASK = 0x7F +RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH = 0x00 +RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY = 0x80 # Default + +RF_FIFOTHRESH_FIFOTHRESHOLD_MASK = 0xC0 +RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD = 0x0F # Default + +""" + * RegSeqConfig1 +""" +RF_SEQCONFIG1_SEQUENCER_START = 0x80 + +RF_SEQCONFIG1_SEQUENCER_STOP = 0x40 + +RF_SEQCONFIG1_IDLEMODE_MASK = 0xDF +RF_SEQCONFIG1_IDLEMODE_SLEEP = 0x20 +RF_SEQCONFIG1_IDLEMODE_STANDBY = 0x00 # Default + +RF_SEQCONFIG1_FROMSTART_MASK = 0xE7 +RF_SEQCONFIG1_FROMSTART_TOLPS = 0x00 # Default +RF_SEQCONFIG1_FROMSTART_TORX = 0x08 +RF_SEQCONFIG1_FROMSTART_TOTX = 0x10 +RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL = 0x18 + +RF_SEQCONFIG1_LPS_MASK = 0xFB +RF_SEQCONFIG1_LPS_SEQUENCER_OFF = 0x00 # Default +RF_SEQCONFIG1_LPS_IDLE = 0x04 + +RF_SEQCONFIG1_FROMIDLE_MASK = 0xFD +RF_SEQCONFIG1_FROMIDLE_TOTX = 0x00 # Default +RF_SEQCONFIG1_FROMIDLE_TORX = 0x02 + +RF_SEQCONFIG1_FROMTX_MASK = 0xFE +RF_SEQCONFIG1_FROMTX_TOLPS = 0x00 # Default +RF_SEQCONFIG1_FROMTX_TORX = 0x01 + +""" + * RegSeqConfig2 +""" +RF_SEQCONFIG2_FROMRX_MASK = 0x1F +RF_SEQCONFIG2_FROMRX_TOUNUSED_000 = 0x00 # Default +RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY = 0x20 +RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY = 0x40 +RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK = 0x60 +RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI = 0x80 +RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC = 0xA0 +RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE = 0xC0 +RF_SEQCONFIG2_FROMRX_TOUNUSED_111 = 0xE0 + +RF_SEQCONFIG2_FROMRXTIMEOUT_MASK = 0xE7 +RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART = 0x00 # Default +RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX = 0x08 +RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS = 0x10 +RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF = 0x18 + +RF_SEQCONFIG2_FROMRXPKT_MASK = 0xF8 +RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF = 0x00 # Default +RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY = 0x01 +RF_SEQCONFIG2_FROMRXPKT_TOLPS = 0x02 +RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX = 0x03 +RF_SEQCONFIG2_FROMRXPKT_TORX = 0x04 + +""" + * RegTimerResol +""" +RF_TIMERRESOL_TIMER1RESOL_MASK = 0xF3 +RF_TIMERRESOL_TIMER1RESOL_OFF = 0x00 # Default +RF_TIMERRESOL_TIMER1RESOL_000064_US = 0x04 +RF_TIMERRESOL_TIMER1RESOL_004100_US = 0x08 +RF_TIMERRESOL_TIMER1RESOL_262000_US = 0x0C + +RF_TIMERRESOL_TIMER2RESOL_MASK = 0xFC +RF_TIMERRESOL_TIMER2RESOL_OFF = 0x00 # Default +RF_TIMERRESOL_TIMER2RESOL_000064_US = 0x01 +RF_TIMERRESOL_TIMER2RESOL_004100_US = 0x02 +RF_TIMERRESOL_TIMER2RESOL_262000_US = 0x03 + +""" + * RegTimer1Coef +""" +RF_TIMER1COEF_TIMER1COEFFICIENT = 0xF5 # Default + +""" + * RegTimer2Coef +""" +RF_TIMER2COEF_TIMER2COEFFICIENT = 0x20 # Default + +""" + * RegImageCal +""" +RF_IMAGECAL_AUTOIMAGECAL_MASK = 0x7F +RF_IMAGECAL_AUTOIMAGECAL_ON = 0x80 +RF_IMAGECAL_AUTOIMAGECAL_OFF = 0x00 # Default + +RF_IMAGECAL_IMAGECAL_MASK = 0xBF +RF_IMAGECAL_IMAGECAL_START = 0x40 + +RF_IMAGECAL_IMAGECAL_RUNNING = 0x20 +RF_IMAGECAL_IMAGECAL_DONE = 0x00 # Default + +RF_IMAGECAL_TEMPCHANGE_HIGHER = 0x08 +RF_IMAGECAL_TEMPCHANGE_LOWER = 0x00 + +RF_IMAGECAL_TEMPTHRESHOLD_MASK = 0xF9 +RF_IMAGECAL_TEMPTHRESHOLD_05 = 0x00 +RF_IMAGECAL_TEMPTHRESHOLD_10 = 0x02 # Default +RF_IMAGECAL_TEMPTHRESHOLD_15 = 0x04 +RF_IMAGECAL_TEMPTHRESHOLD_20 = 0x06 + +RF_IMAGECAL_TEMPMONITOR_MASK = 0xFE +RF_IMAGECAL_TEMPMONITOR_ON = 0x00 # Default +RF_IMAGECAL_TEMPMONITOR_OFF = 0x01 + +""" + * RegTemp (Read Only) +""" + +""" + * RegLowBat +""" +RF_LOWBAT_MASK = 0xF7 +RF_LOWBAT_ON = 0x08 +RF_LOWBAT_OFF = 0x00 # Default + +RF_LOWBAT_TRIM_MASK = 0xF8 +RF_LOWBAT_TRIM_1695 = 0x00 +RF_LOWBAT_TRIM_1764 = 0x01 +RF_LOWBAT_TRIM_1835 = 0x02 # Default +RF_LOWBAT_TRIM_1905 = 0x03 +RF_LOWBAT_TRIM_1976 = 0x04 +RF_LOWBAT_TRIM_2045 = 0x05 +RF_LOWBAT_TRIM_2116 = 0x06 +RF_LOWBAT_TRIM_2185 = 0x07 + +""" + * RegIrqFlags1 +""" +RF_IRQFLAGS1_MODEREADY = 0x80 + +RF_IRQFLAGS1_RXREADY = 0x40 + +RF_IRQFLAGS1_TXREADY = 0x20 + +RF_IRQFLAGS1_PLLLOCK = 0x10 + +RF_IRQFLAGS1_RSSI = 0x08 + +RF_IRQFLAGS1_TIMEOUT = 0x04 + +RF_IRQFLAGS1_PREAMBLEDETECT = 0x02 + +RF_IRQFLAGS1_SYNCADDRESSMATCH = 0x01 + +""" + * RegIrqFlags2 +""" +RF_IRQFLAGS2_FIFOFULL = 0x80 + +RF_IRQFLAGS2_FIFOEMPTY = 0x40 + +RF_IRQFLAGS2_FIFOLEVEL = 0x20 + +RF_IRQFLAGS2_FIFOOVERRUN = 0x10 + +RF_IRQFLAGS2_PACKETSENT = 0x08 + +RF_IRQFLAGS2_PAYLOADREADY = 0x04 + +RF_IRQFLAGS2_CRCOK = 0x02 + +RF_IRQFLAGS2_LOWBAT = 0x01 + +""" + * RegDioMapping1 +""" +RF_DIOMAPPING1_DIO0_MASK = 0x3F +RF_DIOMAPPING1_DIO0_00 = 0x00 # Default +RF_DIOMAPPING1_DIO0_01 = 0x40 +RF_DIOMAPPING1_DIO0_10 = 0x80 +RF_DIOMAPPING1_DIO0_11 = 0xC0 + +RF_DIOMAPPING1_DIO1_MASK = 0xCF +RF_DIOMAPPING1_DIO1_00 = 0x00 # Default +RF_DIOMAPPING1_DIO1_01 = 0x10 +RF_DIOMAPPING1_DIO1_10 = 0x20 +RF_DIOMAPPING1_DIO1_11 = 0x30 + +RF_DIOMAPPING1_DIO2_MASK = 0xF3 +RF_DIOMAPPING1_DIO2_00 = 0x00 # Default +RF_DIOMAPPING1_DIO2_01 = 0x04 +RF_DIOMAPPING1_DIO2_10 = 0x08 +RF_DIOMAPPING1_DIO2_11 = 0x0C + +RF_DIOMAPPING1_DIO3_MASK = 0xFC +RF_DIOMAPPING1_DIO3_00 = 0x00 # Default +RF_DIOMAPPING1_DIO3_01 = 0x01 +RF_DIOMAPPING1_DIO3_10 = 0x02 +RF_DIOMAPPING1_DIO3_11 = 0x03 + +""" + * RegDioMapping2 +""" +RF_DIOMAPPING2_DIO4_MASK = 0x3F +RF_DIOMAPPING2_DIO4_00 = 0x00 # Default +RF_DIOMAPPING2_DIO4_01 = 0x40 +RF_DIOMAPPING2_DIO4_10 = 0x80 +RF_DIOMAPPING2_DIO4_11 = 0xC0 + +RF_DIOMAPPING2_DIO5_MASK = 0xCF +RF_DIOMAPPING2_DIO5_00 = 0x00 # Default +RF_DIOMAPPING2_DIO5_01 = 0x10 +RF_DIOMAPPING2_DIO5_10 = 0x20 +RF_DIOMAPPING2_DIO5_11 = 0x30 + +RF_DIOMAPPING2_MAP_MASK = 0xFE +RF_DIOMAPPING2_MAP_PREAMBLEDETECT = 0x01 +RF_DIOMAPPING2_MAP_RSSI = 0x00 # Default + +""" + * RegVersion (Read Only) +""" + +""" + * RegAgcRef +""" + +""" + * RegAgcThresh1 +""" + +""" + * RegAgcThresh2 +""" + +""" + * RegAgcThresh3 +""" + +""" + * RegPllHop +""" +RF_PLLHOP_FASTHOP_MASK = 0x7F +RF_PLLHOP_FASTHOP_ON = 0x80 +RF_PLLHOP_FASTHOP_OFF = 0x00 # Default + +""" + * RegTcxo +""" +RF_TCXO_TCXOINPUT_MASK = 0xEF +RF_TCXO_TCXOINPUT_ON = 0x10 +RF_TCXO_TCXOINPUT_OFF = 0x00 # Default + +""" + * RegPaDac +""" +RF_PADAC_20DBM_MASK = 0xF8 +RF_PADAC_20DBM_ON = 0x07 +RF_PADAC_20DBM_OFF = 0x04 # Default + +""" + * RegPll +""" +RF_PLL_BANDWIDTH_MASK = 0x3F +RF_PLL_BANDWIDTH_75 = 0x00 +RF_PLL_BANDWIDTH_150 = 0x40 +RF_PLL_BANDWIDTH_225 = 0x80 +RF_PLL_BANDWIDTH_300 = 0xC0 # Default + +""" + * RegPllLowPn +""" +RF_PLLLOWPN_BANDWIDTH_MASK = 0x3F +RF_PLLLOWPN_BANDWIDTH_75 = 0x00 +RF_PLLLOWPN_BANDWIDTH_150 = 0x40 +RF_PLLLOWPN_BANDWIDTH_225 = 0x80 +RF_PLLLOWPN_BANDWIDTH_300 = 0xC0 # Default + +""" + * RegFormerTemp +""" + +""" + * RegBitrateFrac +""" +RF_BITRATEFRAC_MASK = 0xF0