Added the (possibly modified) Espressif SDK to the project to avoid problems with building. This may not be OK license wise, but who cares
This commit is contained in:
@@ -0,0 +1,9 @@
|
||||
#ifndef __GPIO16_H__
|
||||
#define __GPIO16_H__
|
||||
|
||||
void gpio16_output_conf(void);
|
||||
void gpio16_output_set(uint8 value);
|
||||
void gpio16_input_conf(void);
|
||||
uint8 gpio16_input_get(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,57 @@
|
||||
#ifndef __I2C_MASTER_H__
|
||||
#define __I2C_MASTER_H__
|
||||
|
||||
#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U
|
||||
#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_MTMS_U
|
||||
#define I2C_MASTER_SDA_GPIO 2
|
||||
#define I2C_MASTER_SCL_GPIO 14
|
||||
#define I2C_MASTER_SDA_FUNC FUNC_GPIO2
|
||||
#define I2C_MASTER_SCL_FUNC FUNC_GPIO14
|
||||
|
||||
//#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U
|
||||
//#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO0_U
|
||||
//#define I2C_MASTER_SDA_GPIO 2
|
||||
//#define I2C_MASTER_SCL_GPIO 0
|
||||
//#define I2C_MASTER_SDA_FUNC FUNC_GPIO2
|
||||
//#define I2C_MASTER_SCL_FUNC FUNC_GPIO0
|
||||
|
||||
#if 0
|
||||
#define I2C_MASTER_GPIO_SET(pin) \
|
||||
gpio_output_set(1<<pin,0,1<<pin,0)
|
||||
|
||||
#define I2C_MASTER_GPIO_CLR(pin) \
|
||||
gpio_output_set(0,1<<pin,1<<pin,0)
|
||||
|
||||
#define I2C_MASTER_GPIO_OUT(pin,val) \
|
||||
if(val) I2C_MASTER_GPIO_SET(pin);\
|
||||
else I2C_MASTER_GPIO_CLR(pin)
|
||||
#endif
|
||||
|
||||
#define I2C_MASTER_SDA_HIGH_SCL_HIGH() \
|
||||
gpio_output_set(1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
|
||||
|
||||
#define I2C_MASTER_SDA_HIGH_SCL_LOW() \
|
||||
gpio_output_set(1<<I2C_MASTER_SDA_GPIO, 1<<I2C_MASTER_SCL_GPIO, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
|
||||
|
||||
#define I2C_MASTER_SDA_LOW_SCL_HIGH() \
|
||||
gpio_output_set(1<<I2C_MASTER_SCL_GPIO, 1<<I2C_MASTER_SDA_GPIO, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
|
||||
|
||||
#define I2C_MASTER_SDA_LOW_SCL_LOW() \
|
||||
gpio_output_set(0, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 1<<I2C_MASTER_SDA_GPIO | 1<<I2C_MASTER_SCL_GPIO, 0)
|
||||
|
||||
void i2c_master_gpio_init(void);
|
||||
void i2c_master_init(void);
|
||||
|
||||
#define i2c_master_wait os_delay_us
|
||||
void i2c_master_stop(void);
|
||||
void i2c_master_start(void);
|
||||
void i2c_master_setAck(uint8 level);
|
||||
uint8 i2c_master_getAck(void);
|
||||
uint8 i2c_master_readByte(void);
|
||||
void i2c_master_writeByte(uint8 wrdata);
|
||||
|
||||
bool i2c_master_checkAck(void);
|
||||
void i2c_master_send_ack(void);
|
||||
void i2c_master_send_nack(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,27 @@
|
||||
#ifndef __KEY_H__
|
||||
#define __KEY_H__
|
||||
|
||||
#include "gpio.h"
|
||||
|
||||
typedef void (* key_function)(void);
|
||||
|
||||
struct single_key_param {
|
||||
uint8 key_level;
|
||||
uint8 gpio_id;
|
||||
uint8 gpio_func;
|
||||
uint32 gpio_name;
|
||||
os_timer_t key_5s;
|
||||
os_timer_t key_50ms;
|
||||
key_function short_press;
|
||||
key_function long_press;
|
||||
};
|
||||
|
||||
struct keys_param {
|
||||
uint8 key_num;
|
||||
struct single_key_param **single_key;
|
||||
};
|
||||
|
||||
struct single_key_param *key_init_single(uint8 gpio_id, uint32 gpio_name, uint8 gpio_func, key_function long_press, key_function short_press);
|
||||
void key_init(struct keys_param *key);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,16 @@
|
||||
#ifndef __SDIO_SLAVE_H__
|
||||
#define __SDIO_SLAVE_H__
|
||||
#include "c_types.h"␍
|
||||
#include "user_interface.h"
|
||||
|
||||
#define RX_AVAILIBLE 2
|
||||
#define TX_AVAILIBLE 1
|
||||
#define INIT_STAGE 0
|
||||
|
||||
void sdio_slave_init(void);
|
||||
|
||||
int32 sdio_load_data(const uint8* data,uint32 len);
|
||||
typedef void (*sdio_recv_data_callback_t)(uint8* data,uint32 len);
|
||||
|
||||
bool sdio_register_recv_cb(sdio_recv_data_callback_t cb);
|
||||
#endif
|
||||
@@ -0,0 +1,280 @@
|
||||
//Generated at 2012-10-23 19:55:03
|
||||
/*
|
||||
* Copyright (c) 2010 - 2011 Espressif System
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SLC_REGISTER_H_
|
||||
#define SLC_REGISTER_H_
|
||||
|
||||
#define REG_SLC_BASE 0x60000B00
|
||||
//version value:32'h091700
|
||||
|
||||
#define SLC_CONF0 (REG_SLC_BASE + 0x0)
|
||||
#ifndef ESP_MAC_5
|
||||
#define SLC_MODE 0x00000003
|
||||
#define SLC_MODE_S 12
|
||||
#endif
|
||||
#define SLC_DATA_BURST_EN (BIT(9))
|
||||
#define SLC_DSCR_BURST_EN (BIT(8))
|
||||
#define SLC_RX_NO_RESTART_CLR (BIT(7))
|
||||
#define SLC_RX_AUTO_WRBACK (BIT(6))
|
||||
#define SLC_RX_LOOP_TEST (BIT(5))
|
||||
#define SLC_TX_LOOP_TEST (BIT(4))
|
||||
#define SLC_AHBM_RST (BIT(3))
|
||||
#define SLC_AHBM_FIFO_RST (BIT(2))
|
||||
#define SLC_RXLINK_RST (BIT(1))
|
||||
#define SLC_TXLINK_RST (BIT(0))
|
||||
|
||||
#define SLC_INT_RAW (REG_SLC_BASE + 0x4)
|
||||
#define SLC_TX_DSCR_EMPTY_INT_RAW (BIT(21))
|
||||
#define SLC_RX_DSCR_ERR_INT_RAW (BIT(20))
|
||||
#define SLC_TX_DSCR_ERR_INT_RAW (BIT(19))
|
||||
#define SLC_TOHOST_INT_RAW (BIT(18))
|
||||
#define SLC_RX_EOF_INT_RAW (BIT(17))
|
||||
#define SLC_RX_DONE_INT_RAW (BIT(16))
|
||||
#define SLC_TX_EOF_INT_RAW (BIT(15))
|
||||
#define SLC_TX_DONE_INT_RAW (BIT(14))
|
||||
#define SLC_TOKEN1_1TO0_INT_RAW (BIT(13))
|
||||
#define SLC_TOKEN0_1TO0_INT_RAW (BIT(12))
|
||||
#define SLC_TX_OVF_INT_RAW (BIT(11))
|
||||
#define SLC_RX_UDF_INT_RAW (BIT(10))
|
||||
#define SLC_TX_START_INT_RAW (BIT(9))
|
||||
#define SLC_RX_START_INT_RAW (BIT(8))
|
||||
#define SLC_FRHOST_BIT7_INT_RAW (BIT(7))
|
||||
#define SLC_FRHOST_BIT6_INT_RAW (BIT(6))
|
||||
#define SLC_FRHOST_BIT5_INT_RAW (BIT(5))
|
||||
#define SLC_FRHOST_BIT4_INT_RAW (BIT(4))
|
||||
#define SLC_FRHOST_BIT3_INT_RAW (BIT(3))
|
||||
#define SLC_FRHOST_BIT2_INT_RAW (BIT(2))
|
||||
#define SLC_FRHOST_BIT1_INT_RAW (BIT(1))
|
||||
#define SLC_FRHOST_BIT0_INT_RAW (BIT(0))
|
||||
|
||||
#define SLC_INT_STATUS (REG_SLC_BASE + 0x8)
|
||||
#define SLC_TX_DSCR_EMPTY_INT_ST (BIT(21))
|
||||
#define SLC_RX_DSCR_ERR_INT_ST (BIT(20))
|
||||
#define SLC_TX_DSCR_ERR_INT_ST (BIT(19))
|
||||
#define SLC_TOHOST_INT_ST (BIT(18))
|
||||
#define SLC_RX_EOF_INT_ST (BIT(17))
|
||||
#define SLC_RX_DONE_INT_ST (BIT(16))
|
||||
#define SLC_TX_EOF_INT_ST (BIT(15))
|
||||
#define SLC_TX_DONE_INT_ST (BIT(14))
|
||||
#define SLC_TOKEN1_1TO0_INT_ST (BIT(13))
|
||||
#define SLC_TOKEN0_1TO0_INT_ST (BIT(12))
|
||||
#define SLC_TX_OVF_INT_ST (BIT(11))
|
||||
#define SLC_RX_UDF_INT_ST (BIT(10))
|
||||
#define SLC_TX_START_INT_ST (BIT(9))
|
||||
#define SLC_RX_START_INT_ST (BIT(8))
|
||||
#define SLC_FRHOST_BIT7_INT_ST (BIT(7))
|
||||
#define SLC_FRHOST_BIT6_INT_ST (BIT(6))
|
||||
#define SLC_FRHOST_BIT5_INT_ST (BIT(5))
|
||||
#define SLC_FRHOST_BIT4_INT_ST (BIT(4))
|
||||
#define SLC_FRHOST_BIT3_INT_ST (BIT(3))
|
||||
#define SLC_FRHOST_BIT2_INT_ST (BIT(2))
|
||||
#define SLC_FRHOST_BIT1_INT_ST (BIT(1))
|
||||
#define SLC_FRHOST_BIT0_INT_ST (BIT(0))
|
||||
|
||||
#define SLC_INT_ENA (REG_SLC_BASE + 0xC)
|
||||
#define SLC_TX_DSCR_EMPTY_INT_ENA (BIT(21))
|
||||
#define SLC_RX_DSCR_ERR_INT_ENA (BIT(20))
|
||||
#define SLC_TX_DSCR_ERR_INT_ENA (BIT(19))
|
||||
#define SLC_TOHOST_INT_ENA (BIT(18))
|
||||
#define SLC_RX_EOF_INT_ENA (BIT(17))
|
||||
#define SLC_RX_DONE_INT_ENA (BIT(16))
|
||||
#define SLC_TX_EOF_INT_ENA (BIT(15))
|
||||
#define SLC_TX_DONE_INT_ENA (BIT(14))
|
||||
#define SLC_TOKEN1_1TO0_INT_ENA (BIT(13))
|
||||
#define SLC_TOKEN0_1TO0_INT_ENA (BIT(12))
|
||||
#define SLC_TX_OVF_INT_ENA (BIT(11))
|
||||
#define SLC_RX_UDF_INT_ENA (BIT(10))
|
||||
#define SLC_TX_START_INT_ENA (BIT(9))
|
||||
#define SLC_RX_START_INT_ENA (BIT(8))
|
||||
#define SLC_FRHOST_BIT7_INT_ENA (BIT(7))
|
||||
#define SLC_FRHOST_BIT6_INT_ENA (BIT(6))
|
||||
#define SLC_FRHOST_BIT5_INT_ENA (BIT(5))
|
||||
#define SLC_FRHOST_BIT4_INT_ENA (BIT(4))
|
||||
#define SLC_FRHOST_BIT3_INT_ENA (BIT(3))
|
||||
#define SLC_FRHOST_BIT2_INT_ENA (BIT(2))
|
||||
#define SLC_FRHOST_BIT1_INT_ENA (BIT(1))
|
||||
#define SLC_FRHOST_BIT0_INT_ENA (BIT(0))
|
||||
|
||||
#define SLC_FRHOST_BIT_INT_ENA_ALL 0xff
|
||||
|
||||
#define SLC_INT_CLR (REG_SLC_BASE + 0x10)
|
||||
#define SLC_TX_DSCR_EMPTY_INT_CLR (BIT(21))
|
||||
#define SLC_RX_DSCR_ERR_INT_CLR (BIT(20))
|
||||
#define SLC_TX_DSCR_ERR_INT_CLR (BIT(19))
|
||||
#define SLC_TOHOST_INT_CLR (BIT(18))
|
||||
#define SLC_RX_EOF_INT_CLR (BIT(17))
|
||||
#define SLC_RX_DONE_INT_CLR (BIT(16))
|
||||
#define SLC_TX_EOF_INT_CLR (BIT(15))
|
||||
#define SLC_TX_DONE_INT_CLR (BIT(14))
|
||||
#define SLC_TOKEN1_1TO0_INT_CLR (BIT(13))
|
||||
#define SLC_TOKEN0_1TO0_INT_CLR (BIT(12))
|
||||
#define SLC_TX_OVF_INT_CLR (BIT(11))
|
||||
#define SLC_RX_UDF_INT_CLR (BIT(10))
|
||||
#define SLC_TX_START_INT_CLR (BIT(9))
|
||||
#define SLC_RX_START_INT_CLR (BIT(8))
|
||||
#define SLC_FRHOST_BIT7_INT_CLR (BIT(7))
|
||||
#define SLC_FRHOST_BIT6_INT_CLR (BIT(6))
|
||||
#define SLC_FRHOST_BIT5_INT_CLR (BIT(5))
|
||||
#define SLC_FRHOST_BIT4_INT_CLR (BIT(4))
|
||||
#define SLC_FRHOST_BIT3_INT_CLR (BIT(3))
|
||||
#define SLC_FRHOST_BIT2_INT_CLR (BIT(2))
|
||||
#define SLC_FRHOST_BIT1_INT_CLR (BIT(1))
|
||||
#define SLC_FRHOST_BIT0_INT_CLR (BIT(0))
|
||||
|
||||
#define SLC_RX_STATUS (REG_SLC_BASE + 0x14)
|
||||
#define SLC_RX_EMPTY (BIT(1))
|
||||
#define SLC_RX_FULL (BIT(0))
|
||||
|
||||
#define SLC_RX_FIFO_PUSH (REG_SLC_BASE + 0x18)
|
||||
#define SLC_RXFIFO_PUSH (BIT(16))
|
||||
#define SLC_RXFIFO_WDATA 0x000001FF
|
||||
#define SLC_RXFIFO_WDATA_S 0
|
||||
|
||||
#define SLC_TX_STATUS (REG_SLC_BASE + 0x1C)
|
||||
#define SLC_TX_EMPTY (BIT(1))
|
||||
#define SLC_TX_FULL (BIT(0))
|
||||
|
||||
#define SLC_TX_FIFO_POP (REG_SLC_BASE + 0x20)
|
||||
#define SLC_TXFIFO_POP (BIT(16))
|
||||
#define SLC_TXFIFO_RDATA 0x000007FF
|
||||
#define SLC_TXFIFO_RDATA_S 0
|
||||
|
||||
#define SLC_RX_LINK (REG_SLC_BASE + 0x24)
|
||||
#define SLC_RXLINK_PARK (BIT(31))
|
||||
#define SLC_RXLINK_RESTART (BIT(30))
|
||||
#define SLC_RXLINK_START (BIT(29))
|
||||
#define SLC_RXLINK_STOP (BIT(28))
|
||||
#define SLC_RXLINK_DESCADDR_MASK 0x000FFFFF
|
||||
#define SLC_RXLINK_ADDR_S 0
|
||||
|
||||
#define SLC_TX_LINK (REG_SLC_BASE + 0x28)
|
||||
#define SLC_TXLINK_PARK (BIT(31))
|
||||
#define SLC_TXLINK_RESTART (BIT(30))
|
||||
#define SLC_TXLINK_START (BIT(29))
|
||||
#define SLC_TXLINK_STOP (BIT(28))
|
||||
#define SLC_TXLINK_DESCADDR_MASK 0x000FFFFF
|
||||
#define SLC_TXLINK_ADDR_S 0
|
||||
|
||||
#define SLC_INTVEC_TOHOST (REG_SLC_BASE + 0x2C)
|
||||
#define SLC_TOHOST_INTVEC 0x000000FF
|
||||
#define SLC_TOHOST_INTVEC_S 0
|
||||
|
||||
#define SLC_TOKEN0 (REG_SLC_BASE + 0x30)
|
||||
#define SLC_TOKEN0_MASK 0x00000FFF
|
||||
#define SLC_TOKEN0_S 16
|
||||
#define SLC_TOKEN0_LOCAL_INC_MORE (BIT(14))
|
||||
#define SLC_TOKEN0_LOCAL_INC (BIT(13))
|
||||
#define SLC_TOKEN0_LOCAL_WR (BIT(12))
|
||||
#define SLC_TOKEN0_LOCAL_WDATA_MASK 0x00000FFF
|
||||
#define SLC_TOKEN0_LOCAL_WDATA_S 0
|
||||
|
||||
#define SLC_TOKEN1 (REG_SLC_BASE + 0x34)
|
||||
#define SLC_TOKEN1_MASK 0x00000FFF
|
||||
#define SLC_TOKEN1_S 16
|
||||
#define SLC_TOKEN1_LOCAL_INC_MORE (BIT(14))
|
||||
#define SLC_TOKEN1_LOCAL_INC (BIT(13))
|
||||
#define SLC_TOKEN1_LOCAL_WR (BIT(12))
|
||||
#define SLC_TOKEN1_LOCAL_WDATA 0x00000FFF
|
||||
#define SLC_TOKEN1_LOCAL_WDATA_S 0
|
||||
|
||||
#define SLC_CONF1 (REG_SLC_BASE + 0x38)
|
||||
#define SLC_STATE0 (REG_SLC_BASE + 0x3C)
|
||||
#define SLC_STATE1 (REG_SLC_BASE + 0x40)
|
||||
|
||||
#define SLC_BRIDGE_CONF (REG_SLC_BASE + 0x44)
|
||||
#ifndef ESP_MAC_5
|
||||
#define SLC_TX_PUSH_IDLE_NUM 0x0000FFFF
|
||||
#define SLC_TX_PUSH_IDLE_NUM_S 16
|
||||
#define SLC_TX_DUMMY_MODE (BIT(12))
|
||||
#endif
|
||||
#define SLC_FIFO_MAP_ENA 0x0000000F
|
||||
#define SLC_FIFO_MAP_ENA_S 8
|
||||
#define SLC_TXEOF_ENA 0x0000003F
|
||||
#define SLC_TXEOF_ENA_S 0
|
||||
|
||||
#define SLC_RX_EOF_DES_ADDR (REG_SLC_BASE + 0x48)
|
||||
#define SLC_TX_EOF_DES_ADDR (REG_SLC_BASE + 0x4C)
|
||||
#define SLC_FROM_HOST_LAST_DESC SLC_TX_EOF_DES_ADDR
|
||||
#define SLC_TO_HOST_LAST_DESC SLC_RX_EOF_DES_ADDR
|
||||
|
||||
#define SLC_RX_EOF_BFR_DES_ADDR (REG_SLC_BASE + 0x50)
|
||||
#define SLC_AHB_TEST (REG_SLC_BASE + 0x54)
|
||||
#define SLC_AHB_TESTADDR 0x00000003
|
||||
#define SLC_AHB_TESTADDR_S 4
|
||||
#define SLC_AHB_TESTMODE 0x00000007
|
||||
#define SLC_AHB_TESTMODE_S 0
|
||||
|
||||
#define SLC_SDIO_ST (REG_SLC_BASE + 0x58)
|
||||
#define SLC_BUS_ST 0x00000007
|
||||
#define SLC_BUS_ST_S 12
|
||||
#define SLC_SDIO_WAKEUP (BIT(8))
|
||||
#define SLC_FUNC_ST 0x0000000F
|
||||
#define SLC_FUNC_ST_S 4
|
||||
#define SLC_CMD_ST 0x00000007
|
||||
#define SLC_CMD_ST_S 0
|
||||
|
||||
#define SLC_RX_DSCR_CONF (REG_SLC_BASE + 0x5C)
|
||||
#ifdef ESP_MAC_5
|
||||
#define SLC_INFOR_NO_REPLACE (BIT(9))
|
||||
#define SLC_TOKEN_NO_REPLACE (BIT(8))
|
||||
#define SLC_POP_IDLE_CNT 0x000000FF
|
||||
#else
|
||||
#define SLC_RX_FILL_EN (BIT(20))
|
||||
#define SLC_RX_EOF_MODE (BIT(19))
|
||||
#define SLC_RX_FILL_MODE (BIT(18))
|
||||
#define SLC_INFOR_NO_REPLACE (BIT(17))
|
||||
#define SLC_TOKEN_NO_REPLACE (BIT(16)) //
|
||||
#define SLC_POP_IDLE_CNT 0x0000FFFF
|
||||
#endif
|
||||
#define SLC_POP_IDLE_CNT_S 0
|
||||
|
||||
#define SLC_TXLINK_DSCR (REG_SLC_BASE + 0x60)
|
||||
#define SLC_TXLINK_DSCR_BF0 (REG_SLC_BASE + 0x64)
|
||||
#define SLC_TXLINK_DSCR_BF1 (REG_SLC_BASE + 0x68)
|
||||
#define SLC_RXLINK_DSCR (REG_SLC_BASE + 0x6C)
|
||||
#define SLC_RXLINK_DSCR_BF0 (REG_SLC_BASE + 0x70)
|
||||
#define SLC_RXLINK_DSCR_BF1 (REG_SLC_BASE + 0x74)
|
||||
#define SLC_DATE (REG_SLC_BASE + 0x78)
|
||||
#define SLC_ID (REG_SLC_BASE + 0x7C)
|
||||
|
||||
#define SLC_HOST_CONF_W0 (REG_SLC_BASE + 0x80 + 0x14)
|
||||
#define SLC_HOST_CONF_W1 (REG_SLC_BASE + 0x80 + 0x18)
|
||||
#define SLC_HOST_CONF_W2 (REG_SLC_BASE + 0x80 + 0x20)
|
||||
#define SLC_HOST_CONF_W3 (REG_SLC_BASE + 0x80 + 0x24)
|
||||
#define SLC_HOST_CONF_W4 (REG_SLC_BASE + 0x80 + 0x28)
|
||||
|
||||
#define SLC_HOST_INTR_ST (REG_SLC_BASE + 0x80 + 0x1c)
|
||||
#define SLC_HOST_INTR_CLR (REG_SLC_BASE + 0x80 + 0x30)
|
||||
#define SLC_HOST_INTR_SOF_BIT (BIT(12))
|
||||
|
||||
#define SLC_HOST_INTR_ENA (REG_SLC_BASE + 0x80 + 0x34)
|
||||
#define SLC_RX_NEW_PACKET_INT_ENA (BIT23)
|
||||
#define SLC_HOST_TOHOST_BIT0_INT_ENA (BIT0)
|
||||
#define SLC_HOST_CONF_W5 (REG_SLC_BASE + 0x80 + 0x3C)
|
||||
#define SLC_HOST_INTR_RAW (REG_SLC_BASE + 0x80 + 0x8)
|
||||
#define SLC_HOST_INTR_ENA_BIT (BIT(23))
|
||||
//[15:12]: 0x3ff9xxxx -- 0b01 from_host
|
||||
// 0x3ffaxxxx -- 0b10 general
|
||||
// 0x3ffbxxxx -- 0b11 to_host
|
||||
#define SLC_DATA_ADDR_CLEAR_MASK (~(0xf<<12))
|
||||
#define SLC_FROM_HOST_ADDR_MASK (0x1<<12)
|
||||
#define SLC_TO_HOST_ADDR_MASK (0x3<<12)
|
||||
|
||||
#define SLC_SET_FROM_HOST_ADDR_MASK(v) do { \
|
||||
(v) &= SLC_DATA_ADDR_CLEAR_MASK; \
|
||||
(v) |= SLC_FROM_HOST_ADDR_MASK; \
|
||||
} while(0);
|
||||
|
||||
#define SLC_SET_TO_HOST_ADDR_MASK(v) do { \
|
||||
(v) &= SLC_DATA_ADDR_CLEAR_MASK; \
|
||||
(v) |= SLC_TO_HOST_ADDR_MASK; \
|
||||
} while(0);
|
||||
|
||||
|
||||
#define SLC_TX_DESC_DEBUG_REG 0x3ff0002c //[15:0] set to 0xcccc
|
||||
|
||||
|
||||
#endif // SLC_REGISTER_H_INCLUDED
|
||||
@@ -0,0 +1,50 @@
|
||||
#ifndef SPI_APP_H
|
||||
#define SPI_APP_H
|
||||
|
||||
#include "spi_register.h"
|
||||
#include "ets_sys.h"
|
||||
#include "osapi.h"
|
||||
#include "uart.h"
|
||||
#include "os_type.h"
|
||||
#include "spi_flash.h"
|
||||
|
||||
#define SPI_FLASH_BYTES_LEN 24
|
||||
#define IODATA_START_ADDR BIT0
|
||||
#define SPI_BUFF_BYTE_NUM 32
|
||||
|
||||
/*SPI number define*/
|
||||
#define SPI 0
|
||||
#define HSPI 1
|
||||
|
||||
void cache_flush(void);
|
||||
//spi master init funtion
|
||||
void spi_master_init(uint8 spi_no);
|
||||
|
||||
//lcd drive function
|
||||
void spi_lcd_9bit_write(uint8 spi_no,uint8 high_bit,uint8 low_8bit);
|
||||
//use spi send 8bit data
|
||||
void spi_mast_byte_write(uint8 spi_no,uint8 data);
|
||||
|
||||
//transmit data to esp8266 slave buffer,which needs 16bit transmission ,
|
||||
//first byte is master command 0x04, second byte is master data
|
||||
void spi_byte_write_espslave(uint8 spi_no,uint8 data);
|
||||
//read data from esp8266 slave buffer,which needs 16bit transmission ,
|
||||
//first byte is master command 0x06, second byte is to read slave data
|
||||
void spi_byte_read_espslave(uint8 spi_no,uint8 *data);
|
||||
|
||||
//esp8266 slave mode initial
|
||||
void spi_slave_init(uint8 spi_no,uint8 data_len);
|
||||
//esp8266 slave isr handle funtion,tiggered when any transmission is finished.
|
||||
//the function is registered in spi_slave_init.
|
||||
void spi_slave_isr_handler(void *para);
|
||||
|
||||
|
||||
//hspi test function, used to test esp8266 spi slave
|
||||
void hspi_master_readwrite_repeat(void);
|
||||
|
||||
|
||||
void spi_test_init(void);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
#ifndef SPI_OVERLAP_APP_H
|
||||
#define SPI_OVERLAP_APP_H
|
||||
|
||||
#include "ets_sys.h"
|
||||
#include "spi_flash.h"
|
||||
#define HSPI_OVERLAP
|
||||
//#define NO_HSPI_DEVICE
|
||||
#define HOST_INF_SEL 0x3ff00028
|
||||
#define FUNC_SPI_CS2 1
|
||||
#define FUNC_SPI_CS1 1
|
||||
#define reg_cspi_overlap (BIT7)
|
||||
|
||||
#define SPI_FLASH_BYTES_LEN 24
|
||||
#define IODATA_START_ADDR BIT0
|
||||
#define SPI_BUFF_BYTE_NUM 32
|
||||
|
||||
#define PERIPHS_IO_MUX_BACKUP 0
|
||||
#define SPI_USER_BACKUP 1
|
||||
#define SPI_CTRL_BACKUP 2
|
||||
#define SPI_CLOCK_BACKUP 3
|
||||
#define SPI_USER1_BACKUP 4
|
||||
#define SPI_USER2_BACKUP 5
|
||||
#define SPI_CMD_BACKUP 6
|
||||
#define SPI_PIN_BACKUP 7
|
||||
#define SPI_SLAVE_BACKUP 8
|
||||
|
||||
#define HSPI_CS_DEV 0
|
||||
#define SPI_CS1_DEV 1
|
||||
#define SPI_CS2_DEV 2
|
||||
#define SPI_CS0_FLASH 3
|
||||
#define HSPI_IDLE 4
|
||||
|
||||
struct hspi_device_config{
|
||||
uint8 active:1;
|
||||
uint8 clk_polar:1;
|
||||
uint8 res:1;
|
||||
uint8 clk_div:5;
|
||||
};
|
||||
|
||||
struct hspi_device_register{
|
||||
uint32 hspi_flash_reg_backup[9];
|
||||
uint32 hspi_dev_reg_backup[9];
|
||||
struct hspi_device_config hspi_dev_conf[4];
|
||||
uint8 selected_dev_num:3;
|
||||
uint8 spi_io_80m:1;
|
||||
uint8 hspi_reg_backup_flag:1;
|
||||
uint8 res:3;
|
||||
};
|
||||
|
||||
void hspi_overlap_init(void);
|
||||
void hspi_overlap_deinit(void);
|
||||
void spi_reg_recover(uint8 spi_no,uint32* backup_mem);
|
||||
void spi_reg_backup(uint8 spi_no,uint32* backup_mem);
|
||||
|
||||
void hspi_master_dev_init(uint8 dev_no,uint8 clk_polar,uint8 clk_div);
|
||||
void hspi_dev_sel(uint8 dev_no);
|
||||
|
||||
void hspi_overlap_flash_init(void);
|
||||
SpiFlashOpResult hspi_overlap_read_flash_data(SpiFlashChip * spi, uint32 flash_addr, uint32 * addr_dest, uint32 byte_length);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,202 @@
|
||||
/*
|
||||
* Copyright (c) 2010 - 2011 Espressif System
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SPI_REGISTER_H_INCLUDED
|
||||
#define SPI_REGISTER_H_INCLUDED
|
||||
|
||||
#define REG_SPI_BASE(i) (0x60000200-i*0x100)
|
||||
#define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0)
|
||||
|
||||
#define SPI_FLASH_READ BIT31
|
||||
#define SPI_FLASH_WREN BIT30
|
||||
#define SPI_FLASH_WRDI BIT29
|
||||
#define SPI_FLASH_RDID BIT28
|
||||
#define SPI_FLASH_RDSR BIT27
|
||||
#define SPI_FLASH_WRSR BIT26
|
||||
#define SPI_FLASH_PP BIT25
|
||||
#define SPI_FLASH_SE BIT24
|
||||
#define SPI_FLASH_BE BIT23
|
||||
#define SPI_FLASH_CE BIT22
|
||||
#define SPI_FLASH_RES BIT20
|
||||
|
||||
#define SPI_USR (BIT(18))
|
||||
|
||||
#define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4)
|
||||
|
||||
#define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8)
|
||||
#define SPI_WR_BIT_ORDER (BIT(26))
|
||||
#define SPI_RD_BIT_ORDER (BIT(25))
|
||||
#define SPI_QIO_MODE (BIT(24))
|
||||
#define SPI_DIO_MODE (BIT(23))
|
||||
#define SPI_QOUT_MODE (BIT(20))
|
||||
#define SPI_DOUT_MODE (BIT(14))
|
||||
#define SPI_FASTRD_MODE (BIT(13))
|
||||
|
||||
#define SPI_CTRL1(i) (REG_SPI_BASE(i) + 0xc)
|
||||
#define SPI_CS_HOLD_DELAY 0xf
|
||||
#define SPI_CS_HOLD_DELAY_S 28
|
||||
#define SPI_CS_HOLD_DELAY_RES 0xfff
|
||||
#define SPI_CS_HOLD_DELAY_RES_S 16
|
||||
|
||||
|
||||
#define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10)
|
||||
|
||||
#define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
|
||||
|
||||
#define SPI_CS_DELAY_NUM 0x0000000F
|
||||
#define SPI_CS_DELAY_NUM_S 28
|
||||
#define SPI_CS_DELAY_MODE 0x00000003
|
||||
#define SPI_CS_DELAY_MODE_S 26
|
||||
#define SPI_MOSI_DELAY_NUM 0x00000007
|
||||
#define SPI_MOSI_DELAY_NUM_S 23
|
||||
#define SPI_MOSI_DELAY_MODE 0x00000003
|
||||
#define SPI_MOSI_DELAY_MODE_S 21
|
||||
#define SPI_MISO_DELAY_NUM 0x00000007
|
||||
#define SPI_MISO_DELAY_NUM_S 18
|
||||
#define SPI_MISO_DELAY_MODE 0x00000003
|
||||
#define SPI_MISO_DELAY_MODE_S 16
|
||||
#define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
|
||||
#define SPI_CLK_EQU_SYSCLK (BIT(31))
|
||||
#define SPI_CLKDIV_PRE 0x00001FFF
|
||||
#define SPI_CLKDIV_PRE_S 18
|
||||
#define SPI_CLKCNT_N 0x0000003F
|
||||
#define SPI_CLKCNT_N_S 12
|
||||
#define SPI_CLKCNT_H 0x0000003F
|
||||
#define SPI_CLKCNT_H_S 6
|
||||
#define SPI_CLKCNT_L 0x0000003F
|
||||
#define SPI_CLKCNT_L_S 0
|
||||
|
||||
#define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C)
|
||||
#define SPI_USR_COMMAND (BIT(31))
|
||||
#define SPI_USR_ADDR (BIT(30))
|
||||
#define SPI_USR_DUMMY (BIT(29))
|
||||
#define SPI_USR_MISO (BIT(28))
|
||||
#define SPI_USR_MOSI (BIT(27))
|
||||
|
||||
#define SPI_USR_MOSI_HIGHPART (BIT(25))
|
||||
#define SPI_USR_MISO_HIGHPART (BIT(24))
|
||||
|
||||
|
||||
#define SPI_SIO (BIT(16))
|
||||
#define SPI_FWRITE_QIO (BIT(15))
|
||||
#define SPI_FWRITE_DIO (BIT(14))
|
||||
#define SPI_FWRITE_QUAD (BIT(13))
|
||||
#define SPI_FWRITE_DUAL (BIT(12))
|
||||
#define SPI_WR_BYTE_ORDER (BIT(11))
|
||||
#define SPI_RD_BYTE_ORDER (BIT(10))
|
||||
#define SPI_CK_OUT_EDGE (BIT(7))
|
||||
#define SPI_CK_I_EDGE (BIT(6))
|
||||
#define SPI_CS_SETUP (BIT(5))
|
||||
#define SPI_CS_HOLD (BIT(4))
|
||||
#define SPI_FLASH_MODE (BIT(2))
|
||||
|
||||
#define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20)
|
||||
#define SPI_USR_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_USR_ADDR_BITLEN_S 26
|
||||
#define SPI_USR_MOSI_BITLEN 0x000001FF
|
||||
#define SPI_USR_MOSI_BITLEN_S 17
|
||||
#define SPI_USR_MISO_BITLEN 0x000001FF
|
||||
#define SPI_USR_MISO_BITLEN_S 8
|
||||
|
||||
#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_USR_DUMMY_CYCLELEN_S 0
|
||||
|
||||
#define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24)
|
||||
#define SPI_USR_COMMAND_BITLEN 0x0000000F
|
||||
#define SPI_USR_COMMAND_BITLEN_S 28
|
||||
#define SPI_USR_COMMAND_VALUE 0x0000FFFF
|
||||
#define SPI_USR_COMMAND_VALUE_S 0
|
||||
|
||||
#define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28)
|
||||
#define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C)
|
||||
#define SPI_CS2_DIS (BIT(2))
|
||||
#define SPI_CS1_DIS (BIT(1))
|
||||
#define SPI_CS0_DIS (BIT(0))
|
||||
|
||||
#define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
|
||||
#define SPI_SYNC_RESET (BIT(31))
|
||||
#define SPI_SLAVE_MODE (BIT(30))
|
||||
#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
|
||||
#define SPI_SLV_WR_RD_STA_EN (BIT(28))
|
||||
#define SPI_SLV_CMD_DEFINE (BIT(27))
|
||||
#define SPI_TRANS_CNT 0x0000000F
|
||||
#define SPI_TRANS_CNT_S 23
|
||||
#define SPI_TRANS_DONE_EN (BIT(9))
|
||||
#define SPI_SLV_WR_STA_DONE_EN (BIT(8))
|
||||
#define SPI_SLV_RD_STA_DONE_EN (BIT(7))
|
||||
#define SPI_SLV_WR_BUF_DONE_EN (BIT(6))
|
||||
#define SPI_SLV_RD_BUF_DONE_EN (BIT(5))
|
||||
|
||||
|
||||
|
||||
#define SLV_SPI_INT_EN 0x0000001f
|
||||
#define SLV_SPI_INT_EN_S 5
|
||||
|
||||
#define SPI_TRANS_DONE (BIT(4))
|
||||
#define SPI_SLV_WR_STA_DONE (BIT(3))
|
||||
#define SPI_SLV_RD_STA_DONE (BIT(2))
|
||||
#define SPI_SLV_WR_BUF_DONE (BIT(1))
|
||||
#define SPI_SLV_RD_BUF_DONE (BIT(0))
|
||||
|
||||
#define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
|
||||
#define SPI_SLV_STATUS_BITLEN 0x0000001F
|
||||
#define SPI_SLV_STATUS_BITLEN_S 27
|
||||
#define SPI_SLV_BUF_BITLEN 0x000001FF
|
||||
#define SPI_SLV_BUF_BITLEN_S 16
|
||||
#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SLV_RD_ADDR_BITLEN_S 10
|
||||
#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SLV_WR_ADDR_BITLEN_S 4
|
||||
|
||||
#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
|
||||
#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
|
||||
#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
|
||||
#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
|
||||
|
||||
|
||||
|
||||
#define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
|
||||
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0X000000FF
|
||||
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
|
||||
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0X000000FF
|
||||
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
|
||||
#define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0X000000FF
|
||||
#define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S 8
|
||||
#define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0
|
||||
|
||||
#define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
|
||||
#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_WRSTA_CMD_VALUE_S 24
|
||||
#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_RDSTA_CMD_VALUE_S 16
|
||||
#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_WRBUF_CMD_VALUE_S 8
|
||||
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
|
||||
|
||||
#define SPI_W0(i) (REG_SPI_BASE(i) +0x40)
|
||||
#define SPI_W1(i) (REG_SPI_BASE(i) +0x44)
|
||||
#define SPI_W2(i) (REG_SPI_BASE(i) +0x48)
|
||||
#define SPI_W3(i) (REG_SPI_BASE(i) +0x4C)
|
||||
#define SPI_W4(i) (REG_SPI_BASE(i) +0x50)
|
||||
#define SPI_W5(i) (REG_SPI_BASE(i) +0x54)
|
||||
#define SPI_W6(i) (REG_SPI_BASE(i) +0x58)
|
||||
#define SPI_W7(i) (REG_SPI_BASE(i) +0x5C)
|
||||
#define SPI_W8(i) (REG_SPI_BASE(i) +0x60)
|
||||
#define SPI_W9(i) (REG_SPI_BASE(i) +0x64)
|
||||
#define SPI_W10(i) (REG_SPI_BASE(i) +0x68)
|
||||
#define SPI_W11(i) (REG_SPI_BASE(i) +0x6C)
|
||||
#define SPI_W12(i) (REG_SPI_BASE(i) +0x70)
|
||||
#define SPI_W13(i) (REG_SPI_BASE(i) +0x74)
|
||||
#define SPI_W14(i) (REG_SPI_BASE(i) +0x78)
|
||||
#define SPI_W15(i) (REG_SPI_BASE(i) +0x7C)
|
||||
|
||||
#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
|
||||
|
||||
#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
|
||||
#define SPI_INT_HOLD_ENA 0x00000003
|
||||
#define SPI_INT_HOLD_ENA_S 0
|
||||
#endif // SPI_REGISTER_H_INCLUDED
|
||||
@@ -0,0 +1,221 @@
|
||||
/*
|
||||
* File : uart.h
|
||||
* Copyright (C) 2013 - 2016, Espressif Systems
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of version 3 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#ifndef UART_APP_H
|
||||
#define UART_APP_H
|
||||
|
||||
#include "uart_register.h"
|
||||
#include "eagle_soc.h"
|
||||
#include "c_types.h"
|
||||
|
||||
#define UART_TX_BUFFER_SIZE 256 //Ring buffer length of tx buffer
|
||||
#define UART_RX_BUFFER_SIZE 256 //Ring buffer length of rx buffer
|
||||
|
||||
#define UART_BUFF_EN 0 //use uart buffer , FOR UART0
|
||||
#define UART_SELFTEST 0 //set 1:enable the loop test demo for uart buffer, FOR UART0
|
||||
|
||||
#define UART_HW_RTS 0 //set 1: enable uart hw flow control RTS, PIN MTDO, FOR UART0
|
||||
#define UART_HW_CTS 0 //set1: enable uart hw flow contrl CTS , PIN MTCK, FOR UART0
|
||||
|
||||
|
||||
|
||||
|
||||
#define UART0 0
|
||||
#define UART1 1
|
||||
|
||||
|
||||
typedef enum {
|
||||
FIVE_BITS = 0x0,
|
||||
SIX_BITS = 0x1,
|
||||
SEVEN_BITS = 0x2,
|
||||
EIGHT_BITS = 0x3
|
||||
} UartBitsNum4Char;
|
||||
|
||||
typedef enum {
|
||||
ONE_STOP_BIT = 0x1,
|
||||
ONE_HALF_STOP_BIT = 0x2,
|
||||
TWO_STOP_BIT = 0x3
|
||||
} UartStopBitsNum;
|
||||
|
||||
typedef enum {
|
||||
NONE_BITS = 0x2,
|
||||
ODD_BITS = 1,
|
||||
EVEN_BITS = 0
|
||||
} UartParityMode;
|
||||
|
||||
typedef enum {
|
||||
STICK_PARITY_DIS = 0,
|
||||
STICK_PARITY_EN = 1
|
||||
} UartExistParity;
|
||||
|
||||
typedef enum {
|
||||
UART_None_Inverse = 0x0,
|
||||
UART_Rxd_Inverse = UART_RXD_INV,
|
||||
UART_CTS_Inverse = UART_CTS_INV,
|
||||
UART_Txd_Inverse = UART_TXD_INV,
|
||||
UART_RTS_Inverse = UART_RTS_INV,
|
||||
} UART_LineLevelInverse;
|
||||
|
||||
|
||||
typedef enum {
|
||||
BIT_RATE_300 = 300,
|
||||
BIT_RATE_600 = 600,
|
||||
BIT_RATE_1200 = 1200,
|
||||
BIT_RATE_2400 = 2400,
|
||||
BIT_RATE_4800 = 4800,
|
||||
BIT_RATE_9600 = 9600,
|
||||
BIT_RATE_19200 = 19200,
|
||||
BIT_RATE_38400 = 38400,
|
||||
BIT_RATE_57600 = 57600,
|
||||
BIT_RATE_74880 = 74880,
|
||||
BIT_RATE_115200 = 115200,
|
||||
BIT_RATE_230400 = 230400,
|
||||
BIT_RATE_460800 = 460800,
|
||||
BIT_RATE_921600 = 921600,
|
||||
BIT_RATE_1843200 = 1843200,
|
||||
BIT_RATE_3686400 = 3686400,
|
||||
} UartBautRate;
|
||||
|
||||
typedef enum {
|
||||
NONE_CTRL,
|
||||
HARDWARE_CTRL,
|
||||
XON_XOFF_CTRL
|
||||
} UartFlowCtrl;
|
||||
|
||||
typedef enum {
|
||||
USART_HardwareFlowControl_None = 0x0,
|
||||
USART_HardwareFlowControl_RTS = 0x1,
|
||||
USART_HardwareFlowControl_CTS = 0x2,
|
||||
USART_HardwareFlowControl_CTS_RTS = 0x3
|
||||
} UART_HwFlowCtrl;
|
||||
|
||||
typedef enum {
|
||||
EMPTY,
|
||||
UNDER_WRITE,
|
||||
WRITE_OVER
|
||||
} RcvMsgBuffState;
|
||||
|
||||
typedef struct {
|
||||
uint32 RcvBuffSize;
|
||||
uint8 *pRcvMsgBuff;
|
||||
uint8 *pWritePos;
|
||||
uint8 *pReadPos;
|
||||
uint8 TrigLvl; //JLU: may need to pad
|
||||
RcvMsgBuffState BuffState;
|
||||
} RcvMsgBuff;
|
||||
|
||||
typedef struct {
|
||||
uint32 TrxBuffSize;
|
||||
uint8 *pTrxBuff;
|
||||
} TrxMsgBuff;
|
||||
|
||||
typedef enum {
|
||||
BAUD_RATE_DET,
|
||||
WAIT_SYNC_FRM,
|
||||
SRCH_MSG_HEAD,
|
||||
RCV_MSG_BODY,
|
||||
RCV_ESC_CHAR,
|
||||
} RcvMsgState;
|
||||
|
||||
typedef struct {
|
||||
UartBautRate baut_rate;
|
||||
UartBitsNum4Char data_bits;
|
||||
UartExistParity exist_parity;
|
||||
UartParityMode parity;
|
||||
UartStopBitsNum stop_bits;
|
||||
UartFlowCtrl flow_ctrl;
|
||||
RcvMsgBuff rcv_buff;
|
||||
TrxMsgBuff trx_buff;
|
||||
RcvMsgState rcv_state;
|
||||
int received;
|
||||
int buff_uart_no; //indicate which uart use tx/rx buffer
|
||||
} UartDevice;
|
||||
|
||||
void uart_init(UartBautRate uart0_br, UartBautRate uart1_br);
|
||||
void uart0_sendStr(const char *str);
|
||||
|
||||
|
||||
///////////////////////////////////////
|
||||
#define UART_FIFO_LEN 128 //define the tx fifo length
|
||||
#define UART_TX_EMPTY_THRESH_VAL 0x10
|
||||
|
||||
|
||||
struct UartBuffer{
|
||||
uint32 UartBuffSize;
|
||||
uint8 *pUartBuff;
|
||||
uint8 *pInPos;
|
||||
uint8 *pOutPos;
|
||||
STATUS BuffState;
|
||||
uint16 Space; //remanent space of the buffer
|
||||
uint8 TcpControl;
|
||||
struct UartBuffer * nextBuff;
|
||||
};
|
||||
|
||||
struct UartRxBuff{
|
||||
uint32 UartRxBuffSize;
|
||||
uint8 *pUartRxBuff;
|
||||
uint8 *pWritePos;
|
||||
uint8 *pReadPos;
|
||||
STATUS RxBuffState;
|
||||
uint32 Space; //remanent space of the buffer
|
||||
} ;
|
||||
|
||||
typedef enum {
|
||||
RUN = 0,
|
||||
BLOCK = 1,
|
||||
} TCPState;
|
||||
|
||||
//void ICACHE_FLASH_ATTR uart_test_rx();
|
||||
STATUS uart_tx_one_char(uint8 uart, uint8 TxChar);
|
||||
STATUS uart_tx_one_char_no_wait(uint8 uart, uint8 TxChar);
|
||||
void uart1_sendStr_no_wait(const char *str);
|
||||
struct UartBuffer* Uart_Buf_Init();
|
||||
|
||||
|
||||
#if UART_BUFF_EN
|
||||
LOCAL void Uart_Buf_Cpy(struct UartBuffer* pCur, char* pdata , uint16 data_len);
|
||||
void uart_buf_free(struct UartBuffer* pBuff);
|
||||
void tx_buff_enq(char* pdata, uint16 data_len );
|
||||
LOCAL void tx_fifo_insert(struct UartBuffer* pTxBuff, uint8 data_len, uint8 uart_no);
|
||||
void tx_start_uart_buffer(uint8 uart_no);
|
||||
uint16 rx_buff_deq(char* pdata, uint16 data_len );
|
||||
void Uart_rx_buff_enq();
|
||||
#endif
|
||||
void uart_rx_intr_enable(uint8 uart_no);
|
||||
void uart_rx_intr_disable(uint8 uart_no);
|
||||
void uart0_tx_buffer(uint8 *buf, uint16 len);
|
||||
|
||||
//==============================================
|
||||
#define FUNC_UART0_CTS 4
|
||||
#define FUNC_U0CTS 4
|
||||
#define FUNC_U1TXD_BK 2
|
||||
#define UART_LINE_INV_MASK (0x3f<<19)
|
||||
void UART_SetWordLength(uint8 uart_no, UartBitsNum4Char len);
|
||||
void UART_SetStopBits(uint8 uart_no, UartStopBitsNum bit_num);
|
||||
void UART_SetLineInverse(uint8 uart_no, UART_LineLevelInverse inverse_mask);
|
||||
void UART_SetParity(uint8 uart_no, UartParityMode Parity_mode);
|
||||
void UART_SetBaudrate(uint8 uart_no,uint32 baud_rate);
|
||||
void UART_SetFlowCtrl(uint8 uart_no,UART_HwFlowCtrl flow_ctrl,uint8 rx_thresh);
|
||||
void UART_WaitTxFifoEmpty(uint8 uart_no , uint32 time_out_us); //do not use if tx flow control enabled
|
||||
void UART_ResetFifo(uint8 uart_no);
|
||||
void UART_ClearIntrStatus(uint8 uart_no,uint32 clr_mask);
|
||||
void UART_SetIntrEna(uint8 uart_no,uint32 ena_mask);
|
||||
void UART_SetPrintPort(uint8 uart_no);
|
||||
bool UART_CheckOutputFinished(uint8 uart_no, uint32 time_out_us);
|
||||
//==============================================
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,156 @@
|
||||
/*
|
||||
* File : uart_register.h
|
||||
* Copyright (C) 2013 - 2016, Espressif Systems
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of version 3 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
/*
|
||||
* Copyright (c) 2010 - 2011 Espressif System
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef UART_REGISTER_H_
|
||||
#define UART_REGISTER_H_
|
||||
|
||||
#define REG_UART_BASE(i) (0x60000000 + (i)*0xf00)
|
||||
//version value:32'h062000
|
||||
|
||||
#define UART_FIFO(i) (REG_UART_BASE(i) + 0x0)
|
||||
#define UART_RXFIFO_RD_BYTE 0x000000FF
|
||||
#define UART_RXFIFO_RD_BYTE_S 0
|
||||
|
||||
#define UART_INT_RAW(i) (REG_UART_BASE(i) + 0x4)
|
||||
#define UART_RXFIFO_TOUT_INT_RAW (BIT(8))
|
||||
#define UART_BRK_DET_INT_RAW (BIT(7))
|
||||
#define UART_CTS_CHG_INT_RAW (BIT(6))
|
||||
#define UART_DSR_CHG_INT_RAW (BIT(5))
|
||||
#define UART_RXFIFO_OVF_INT_RAW (BIT(4))
|
||||
#define UART_FRM_ERR_INT_RAW (BIT(3))
|
||||
#define UART_PARITY_ERR_INT_RAW (BIT(2))
|
||||
#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1))
|
||||
#define UART_RXFIFO_FULL_INT_RAW (BIT(0))
|
||||
|
||||
#define UART_INT_ST(i) (REG_UART_BASE(i) + 0x8)
|
||||
#define UART_RXFIFO_TOUT_INT_ST (BIT(8))
|
||||
#define UART_BRK_DET_INT_ST (BIT(7))
|
||||
#define UART_CTS_CHG_INT_ST (BIT(6))
|
||||
#define UART_DSR_CHG_INT_ST (BIT(5))
|
||||
#define UART_RXFIFO_OVF_INT_ST (BIT(4))
|
||||
#define UART_FRM_ERR_INT_ST (BIT(3))
|
||||
#define UART_PARITY_ERR_INT_ST (BIT(2))
|
||||
#define UART_TXFIFO_EMPTY_INT_ST (BIT(1))
|
||||
#define UART_RXFIFO_FULL_INT_ST (BIT(0))
|
||||
|
||||
#define UART_INT_ENA(i) (REG_UART_BASE(i) + 0xC)
|
||||
#define UART_RXFIFO_TOUT_INT_ENA (BIT(8))
|
||||
#define UART_BRK_DET_INT_ENA (BIT(7))
|
||||
#define UART_CTS_CHG_INT_ENA (BIT(6))
|
||||
#define UART_DSR_CHG_INT_ENA (BIT(5))
|
||||
#define UART_RXFIFO_OVF_INT_ENA (BIT(4))
|
||||
#define UART_FRM_ERR_INT_ENA (BIT(3))
|
||||
#define UART_PARITY_ERR_INT_ENA (BIT(2))
|
||||
#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1))
|
||||
#define UART_RXFIFO_FULL_INT_ENA (BIT(0))
|
||||
|
||||
#define UART_INT_CLR(i) (REG_UART_BASE(i) + 0x10)
|
||||
#define UART_RXFIFO_TOUT_INT_CLR (BIT(8))
|
||||
#define UART_BRK_DET_INT_CLR (BIT(7))
|
||||
#define UART_CTS_CHG_INT_CLR (BIT(6))
|
||||
#define UART_DSR_CHG_INT_CLR (BIT(5))
|
||||
#define UART_RXFIFO_OVF_INT_CLR (BIT(4))
|
||||
#define UART_FRM_ERR_INT_CLR (BIT(3))
|
||||
#define UART_PARITY_ERR_INT_CLR (BIT(2))
|
||||
#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1))
|
||||
#define UART_RXFIFO_FULL_INT_CLR (BIT(0))
|
||||
|
||||
#define UART_CLKDIV(i) (REG_UART_BASE(i) + 0x14)
|
||||
#define UART_CLKDIV_CNT 0x000FFFFF
|
||||
#define UART_CLKDIV_S 0
|
||||
|
||||
#define UART_AUTOBAUD(i) (REG_UART_BASE(i) + 0x18)
|
||||
#define UART_GLITCH_FILT 0x000000FF
|
||||
#define UART_GLITCH_FILT_S 8
|
||||
#define UART_AUTOBAUD_EN (BIT(0))
|
||||
|
||||
#define UART_STATUS(i) (REG_UART_BASE(i) + 0x1C)
|
||||
#define UART_TXD (BIT(31))
|
||||
#define UART_RTSN (BIT(30))
|
||||
#define UART_DTRN (BIT(29))
|
||||
#define UART_TXFIFO_CNT 0x000000FF
|
||||
#define UART_TXFIFO_CNT_S 16
|
||||
#define UART_RXD (BIT(15))
|
||||
#define UART_CTSN (BIT(14))
|
||||
#define UART_DSRN (BIT(13))
|
||||
#define UART_RXFIFO_CNT 0x000000FF
|
||||
#define UART_RXFIFO_CNT_S 0
|
||||
|
||||
#define UART_CONF0(i) (REG_UART_BASE(i) + 0x20)
|
||||
#define UART_DTR_INV (BIT(24))
|
||||
#define UART_RTS_INV (BIT(23))
|
||||
#define UART_TXD_INV (BIT(22))
|
||||
#define UART_DSR_INV (BIT(21))
|
||||
#define UART_CTS_INV (BIT(20))
|
||||
#define UART_RXD_INV (BIT(19))
|
||||
#define UART_TXFIFO_RST (BIT(18))
|
||||
#define UART_RXFIFO_RST (BIT(17))
|
||||
#define UART_IRDA_EN (BIT(16))
|
||||
#define UART_TX_FLOW_EN (BIT(15))
|
||||
#define UART_LOOPBACK (BIT(14))
|
||||
#define UART_IRDA_RX_INV (BIT(13))
|
||||
#define UART_IRDA_TX_INV (BIT(12))
|
||||
#define UART_IRDA_WCTL (BIT(11))
|
||||
#define UART_IRDA_TX_EN (BIT(10))
|
||||
#define UART_IRDA_DPLX (BIT(9))
|
||||
#define UART_TXD_BRK (BIT(8))
|
||||
#define UART_SW_DTR (BIT(7))
|
||||
#define UART_SW_RTS (BIT(6))
|
||||
#define UART_STOP_BIT_NUM 0x00000003
|
||||
#define UART_STOP_BIT_NUM_S 4
|
||||
#define UART_BIT_NUM 0x00000003
|
||||
#define UART_BIT_NUM_S 2
|
||||
#define UART_PARITY_EN (BIT(1))
|
||||
#define UART_PARITY_EN_M 0x00000001
|
||||
#define UART_PARITY_EN_S 1
|
||||
#define UART_PARITY (BIT(0))
|
||||
#define UART_PARITY_M 0x00000001
|
||||
#define UART_PARITY_S 0
|
||||
|
||||
#define UART_CONF1(i) (REG_UART_BASE(i) + 0x24)
|
||||
#define UART_RX_TOUT_EN (BIT(31))
|
||||
#define UART_RX_TOUT_THRHD 0x0000007F
|
||||
#define UART_RX_TOUT_THRHD_S 24
|
||||
#define UART_RX_FLOW_EN (BIT(23))
|
||||
#define UART_RX_FLOW_THRHD 0x0000007F
|
||||
#define UART_RX_FLOW_THRHD_S 16
|
||||
#define UART_TXFIFO_EMPTY_THRHD 0x0000007F
|
||||
#define UART_TXFIFO_EMPTY_THRHD_S 8
|
||||
#define UART_RXFIFO_FULL_THRHD 0x0000007F
|
||||
#define UART_RXFIFO_FULL_THRHD_S 0
|
||||
|
||||
#define UART_LOWPULSE(i) (REG_UART_BASE(i) + 0x28)
|
||||
#define UART_LOWPULSE_MIN_CNT 0x000FFFFF
|
||||
#define UART_LOWPULSE_MIN_CNT_S 0
|
||||
|
||||
#define UART_HIGHPULSE(i) (REG_UART_BASE(i) + 0x2C)
|
||||
#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF
|
||||
#define UART_HIGHPULSE_MIN_CNT_S 0
|
||||
|
||||
#define UART_PULSE_NUM(i) (REG_UART_BASE(i) + 0x30)
|
||||
#define UART_PULSE_NUM_CNT 0x0003FF
|
||||
#define UART_PULSE_NUM_CNT_S 0
|
||||
|
||||
#define UART_DATE(i) (REG_UART_BASE(i) + 0x78)
|
||||
#define UART_ID(i) (REG_UART_BASE(i) + 0x7C)
|
||||
|
||||
#endif // UART_REGISTER_H_INCLUDED
|
||||
|
||||
Reference in New Issue
Block a user