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899 lines
27 KiB
899 lines
27 KiB
/**
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******************************************************************************
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* @file stm32f1xx_hal_dma.c
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* @author MCD Application Team
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* @brief DMA HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Direct Memory Access (DMA) peripheral:
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* + Initialization and de-initialization functions
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* + IO operation functions
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* + Peripheral State and errors functions
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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(#) Enable and configure the peripheral to be connected to the DMA Channel
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(except for internal SRAM / FLASH memories: no initialization is
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necessary). Please refer to the Reference manual for connection between peripherals
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and DMA requests.
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(#) For a given Channel, program the required configuration through the following parameters:
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Channel request, Transfer Direction, Source and Destination data formats,
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Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
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using HAL_DMA_Init() function.
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(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
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detection.
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(#) Use HAL_DMA_Abort() function to abort the current transfer
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-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
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*** Polling mode IO operation ***
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=================================
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[..]
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(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
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address and destination address and the Length of data to be transferred
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(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
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case a fixed Timeout can be configured by User depending from his application.
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*** Interrupt mode IO operation ***
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===================================
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[..]
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(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
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(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
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(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
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Source address and destination address and the Length of data to be transferred.
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In this case the DMA interrupt is configured
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(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
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(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
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add his own function by customization of function pointer XferCpltCallback and
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XferErrorCallback (i.e. a member of DMA handle structure).
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*** DMA HAL driver macros list ***
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=============================================
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[..]
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Below the list of most used macros in DMA HAL driver.
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(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
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(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
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(+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
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(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
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(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
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(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
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(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
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[..]
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(@) You can refer to the DMA HAL driver header file for more useful macros
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @defgroup DMA DMA
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* @brief DMA HAL module driver
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* @{
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*/
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#ifdef HAL_DMA_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup DMA_Private_Functions DMA Private Functions
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* @{
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*/
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static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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/**
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* @}
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*/
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/* Exported functions ---------------------------------------------------------*/
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/** @defgroup DMA_Exported_Functions DMA Exported Functions
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* @{
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*/
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/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and de-initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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This section provides functions allowing to initialize the DMA Channel source
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and destination addresses, incrementation and data sizes, transfer direction,
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circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
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[..]
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The HAL_DMA_Init() function follows the DMA configuration procedures as described in
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reference manual.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initialize the DMA according to the specified
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* parameters in the DMA_InitTypeDef and initialize the associated handle.
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* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Channel.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
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{
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uint32_t tmp = 0U;
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/* Check the DMA handle allocation */
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if(hdma == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the parameters */
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assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
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assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
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assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
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assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
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assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
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assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
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assert_param(IS_DMA_MODE(hdma->Init.Mode));
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assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
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#if defined (DMA2)
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/* calculation of the channel index */
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if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
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{
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/* DMA1 */
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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hdma->DmaBaseAddress = DMA1;
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}
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else
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{
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/* DMA2 */
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
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hdma->DmaBaseAddress = DMA2;
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}
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#else
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/* DMA1 */
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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hdma->DmaBaseAddress = DMA1;
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#endif /* DMA2 */
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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/* Get the CR register value */
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tmp = hdma->Instance->CCR;
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/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
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tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
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DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
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DMA_CCR_DIR));
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/* Prepare the DMA Channel configuration */
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tmp |= hdma->Init.Direction |
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hdma->Init.PeriphInc | hdma->Init.MemInc |
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hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
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hdma->Init.Mode | hdma->Init.Priority;
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/* Write to DMA Channel CR register */
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hdma->Instance->CCR = tmp;
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/* Initialise the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Initialize the DMA state*/
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hdma->State = HAL_DMA_STATE_READY;
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/* Allocate lock resource and initialize it */
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hdma->Lock = HAL_UNLOCKED;
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return HAL_OK;
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}
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/**
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* @brief DeInitialize the DMA peripheral.
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* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Channel.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
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{
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/* Check the DMA handle allocation */
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if(hdma == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the parameters */
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assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
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/* Disable the selected DMA Channelx */
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__HAL_DMA_DISABLE(hdma);
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/* Reset DMA Channel control register */
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hdma->Instance->CCR = 0U;
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/* Reset DMA Channel Number of Data to Transfer register */
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hdma->Instance->CNDTR = 0U;
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/* Reset DMA Channel peripheral address register */
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hdma->Instance->CPAR = 0U;
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/* Reset DMA Channel memory address register */
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hdma->Instance->CMAR = 0U;
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#if defined (DMA2)
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/* calculation of the channel index */
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if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
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{
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/* DMA1 */
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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hdma->DmaBaseAddress = DMA1;
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}
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else
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{
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/* DMA2 */
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
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hdma->DmaBaseAddress = DMA2;
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}
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#else
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/* DMA1 */
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hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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hdma->DmaBaseAddress = DMA1;
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#endif /* DMA2 */
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/* Clear all flags */
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hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
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/* Clean all callbacks */
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hdma->XferCpltCallback = NULL;
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hdma->XferHalfCpltCallback = NULL;
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hdma->XferErrorCallback = NULL;
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hdma->XferAbortCallback = NULL;
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/* Reset the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Reset the DMA state */
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hdma->State = HAL_DMA_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hdma);
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return HAL_OK;
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}
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/**
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* @}
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*/
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/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
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* @brief Input and Output operation functions
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*
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@verbatim
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===============================================================================
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##### IO operation functions #####
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===============================================================================
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[..] This section provides functions allowing to:
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(+) Configure the source, destination address and data length and Start DMA transfer
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(+) Configure the source, destination address and data length and
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Start DMA transfer with interrupt
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(+) Abort DMA transfer
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(+) Poll for transfer complete
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(+) Handle DMA interrupt request
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@endverbatim
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* @{
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*/
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/**
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* @brief Start the DMA Transfer.
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* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Channel.
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* @param SrcAddress: The source memory Buffer address
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* @param DstAddress: The destination memory Buffer address
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* @param DataLength: The length of data to be transferred from source to destination
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
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{
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HAL_StatusTypeDef status = HAL_OK;
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/* Check the parameters */
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assert_param(IS_DMA_BUFFER_SIZE(DataLength));
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/* Process locked */
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__HAL_LOCK(hdma);
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if(HAL_DMA_STATE_READY == hdma->State)
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{
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Disable the peripheral */
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__HAL_DMA_DISABLE(hdma);
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/* Configure the source, destination address and the data length & clear flags*/
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DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
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/* Enable the Peripheral */
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__HAL_DMA_ENABLE(hdma);
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}
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else
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{
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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status = HAL_BUSY;
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}
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return status;
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}
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/**
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* @brief Start the DMA Transfer with interrupt enabled.
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* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Channel.
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* @param SrcAddress: The source memory Buffer address
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* @param DstAddress: The destination memory Buffer address
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* @param DataLength: The length of data to be transferred from source to destination
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
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{
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HAL_StatusTypeDef status = HAL_OK;
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/* Check the parameters */
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assert_param(IS_DMA_BUFFER_SIZE(DataLength));
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/* Process locked */
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__HAL_LOCK(hdma);
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if(HAL_DMA_STATE_READY == hdma->State)
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{
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Disable the peripheral */
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__HAL_DMA_DISABLE(hdma);
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/* Configure the source, destination address and the data length & clear flags*/
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DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
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/* Enable the transfer complete interrupt */
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/* Enable the transfer Error interrupt */
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if(NULL != hdma->XferHalfCpltCallback)
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{
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/* Enable the Half transfer complete interrupt as well */
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__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
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}
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else
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{
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__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
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__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
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}
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/* Enable the Peripheral */
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__HAL_DMA_ENABLE(hdma);
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}
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else
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{
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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/* Remain BUSY */
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status = HAL_BUSY;
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}
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return status;
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}
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/**
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* @brief Abort the DMA Transfer.
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* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Channel.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
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{
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HAL_StatusTypeDef status = HAL_OK;
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if(hdma->State != HAL_DMA_STATE_BUSY)
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{
|
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/* no transfer ongoing */
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hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
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|
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/* Process Unlocked */
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__HAL_UNLOCK(hdma);
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return HAL_ERROR;
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}
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else
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{
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/* Disable DMA IT */
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__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
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|
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/* Disable the channel */
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__HAL_DMA_DISABLE(hdma);
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|
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/* Clear all flags */
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hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
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}
|
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/* Change the DMA state */
|
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hdma->State = HAL_DMA_STATE_READY;
|
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|
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/* Process Unlocked */
|
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__HAL_UNLOCK(hdma);
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|
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return status;
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}
|
|
|
|
/**
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* @brief Aborts the DMA Transfer in Interrupt mode.
|
|
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
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* the configuration information for the specified DMA Channel.
|
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* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
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{
|
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HAL_StatusTypeDef status = HAL_OK;
|
|
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if(HAL_DMA_STATE_BUSY != hdma->State)
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{
|
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/* no transfer ongoing */
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hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
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status = HAL_ERROR;
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}
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|
else
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{
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/* Disable DMA IT */
|
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__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
|
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/* Clear all flags */
|
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__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
|
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|
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/* Change the DMA state */
|
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hdma->State = HAL_DMA_STATE_READY;
|
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|
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/* Process Unlocked */
|
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__HAL_UNLOCK(hdma);
|
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|
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/* Call User Abort callback */
|
|
if(hdma->XferAbortCallback != NULL)
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{
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hdma->XferAbortCallback(hdma);
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|
}
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|
}
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|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Polling for transfer complete.
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @param CompleteLevel: Specifies the DMA level complete.
|
|
* @param Timeout: Timeout duration.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
|
|
{
|
|
uint32_t temp;
|
|
uint32_t tickstart = 0U;
|
|
|
|
if(HAL_DMA_STATE_BUSY != hdma->State)
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
__HAL_UNLOCK(hdma);
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|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Polling mode not supported in circular mode */
|
|
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Get the level transfer complete flag */
|
|
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
|
|
{
|
|
/* Transfer Complete flag */
|
|
temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
|
|
}
|
|
else
|
|
{
|
|
/* Half Transfer Complete flag */
|
|
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
|
|
}
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
|
|
{
|
|
if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
|
|
{
|
|
/* When a DMA transfer error occurs */
|
|
/* A hardware clear of its EN bits is performed */
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
|
|
|
|
/* Update error code */
|
|
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
|
|
|
|
/* Change the DMA state */
|
|
hdma->State= HAL_DMA_STATE_READY;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
/* Check for the Timeout */
|
|
if(Timeout != HAL_MAX_DELAY)
|
|
{
|
|
if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
|
|
{
|
|
/* Update error code */
|
|
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
}
|
|
|
|
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
|
|
{
|
|
/* Clear the transfer complete flag */
|
|
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
|
|
|
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
|
all transfers are complete) */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
}
|
|
else
|
|
{
|
|
/* Clear the half transfer complete flag */
|
|
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Handles DMA interrupt request.
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval None
|
|
*/
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|
{
|
|
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
|
uint32_t source_it = hdma->Instance->CCR;
|
|
|
|
/* Half Transfer Complete Interrupt management ******************************/
|
|
if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
|
|
{
|
|
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
|
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
|
{
|
|
/* Disable the half transfer interrupt */
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
|
}
|
|
/* Clear the half transfer complete flag */
|
|
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
|
|
|
/* DMA peripheral state is not updated in Half Transfer */
|
|
/* but in Transfer Complete case */
|
|
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferHalfCpltCallback(hdma);
|
|
}
|
|
}
|
|
|
|
/* Transfer Complete Interrupt management ***********************************/
|
|
else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
|
|
{
|
|
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
|
{
|
|
/* Disable the transfer complete and error interrupt */
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
}
|
|
/* Clear the transfer complete flag */
|
|
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
if(hdma->XferCpltCallback != NULL)
|
|
{
|
|
/* Transfer complete callback */
|
|
hdma->XferCpltCallback(hdma);
|
|
}
|
|
}
|
|
|
|
/* Transfer Error Interrupt management **************************************/
|
|
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
|
|
{
|
|
/* When a DMA transfer error occurs */
|
|
/* A hardware clear of its EN bits is performed */
|
|
/* Disable ALL DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
if (hdma->XferErrorCallback != NULL)
|
|
{
|
|
/* Transfer error callback */
|
|
hdma->XferErrorCallback(hdma);
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
/**
|
|
* @brief Register callbacks
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @param CallbackID: User Callback identifer
|
|
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
|
* @param pCallback: pointer to private callbacsk function which has pointer to
|
|
* a DMA_HandleTypeDef structure as parameter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
|
|
if(HAL_DMA_STATE_READY == hdma->State)
|
|
{
|
|
switch (CallbackID)
|
|
{
|
|
case HAL_DMA_XFER_CPLT_CB_ID:
|
|
hdma->XferCpltCallback = pCallback;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
|
hdma->XferHalfCpltCallback = pCallback;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_ERROR_CB_ID:
|
|
hdma->XferErrorCallback = pCallback;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_ABORT_CB_ID:
|
|
hdma->XferAbortCallback = pCallback;
|
|
break;
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief UnRegister callbacks
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @param CallbackID: User Callback identifer
|
|
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
|
|
if(HAL_DMA_STATE_READY == hdma->State)
|
|
{
|
|
switch (CallbackID)
|
|
{
|
|
case HAL_DMA_XFER_CPLT_CB_ID:
|
|
hdma->XferCpltCallback = NULL;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
|
hdma->XferHalfCpltCallback = NULL;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_ERROR_CB_ID:
|
|
hdma->XferErrorCallback = NULL;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_ABORT_CB_ID:
|
|
hdma->XferAbortCallback = NULL;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_ALL_CB_ID:
|
|
hdma->XferCpltCallback = NULL;
|
|
hdma->XferHalfCpltCallback = NULL;
|
|
hdma->XferErrorCallback = NULL;
|
|
hdma->XferAbortCallback = NULL;
|
|
break;
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
|
|
* @brief Peripheral State and Errors functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Peripheral State and Errors functions #####
|
|
===============================================================================
|
|
[..]
|
|
This subsection provides functions allowing to
|
|
(+) Check the DMA state
|
|
(+) Get error code
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Return the DMA hande state.
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL state
|
|
*/
|
|
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
|
{
|
|
/* Return DMA handle state */
|
|
return hdma->State;
|
|
}
|
|
|
|
/**
|
|
* @brief Return the DMA error code.
|
|
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval DMA Error Code
|
|
*/
|
|
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
return hdma->ErrorCode;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup DMA_Private_Functions
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Sets the DMA Transfer parameter.
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @param SrcAddress: The source memory Buffer address
|
|
* @param DstAddress: The destination memory Buffer address
|
|
* @param DataLength: The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
|
|
|
|
/* Configure DMA Channel data length */
|
|
hdma->Instance->CNDTR = DataLength;
|
|
|
|
/* Memory to Peripheral */
|
|
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
{
|
|
/* Configure DMA Channel destination address */
|
|
hdma->Instance->CPAR = DstAddress;
|
|
|
|
/* Configure DMA Channel source address */
|
|
hdma->Instance->CMAR = SrcAddress;
|
|
}
|
|
/* Peripheral to Memory */
|
|
else
|
|
{
|
|
/* Configure DMA Channel source address */
|
|
hdma->Instance->CPAR = SrcAddress;
|
|
|
|
/* Configure DMA Channel destination address */
|
|
hdma->Instance->CMAR = DstAddress;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
|